KiCad PCB EDA Suite
DRC_TEST_PROVIDER_EDGE_CLEARANCE Class Reference
Inheritance diagram for DRC_TEST_PROVIDER_EDGE_CLEARANCE:
DRC_TEST_PROVIDER_CLEARANCE_BASE DRC_TEST_PROVIDER

Public Member Functions

 DRC_TEST_PROVIDER_EDGE_CLEARANCE ()
 
virtual ~DRC_TEST_PROVIDER_EDGE_CLEARANCE ()
 
virtual bool Run () override
 Run this provider against the given PCB with configured options (if any). More...
 
virtual const wxString GetName () const override
 
virtual const wxString GetDescription () const override
 
void SetDRCEngine (DRC_ENGINE *engine)
 

Static Public Member Functions

static void Init ()
 

Protected Member Functions

int forEachGeometryItem (const std::vector< KICAD_T > &aTypes, LSET aLayers, const std::function< bool(BOARD_ITEM *)> &aFunc)
 
virtual void reportAux (wxString fmt,...)
 
virtual void reportViolation (std::shared_ptr< DRC_ITEM > &item, const VECTOR2I &aMarkerPos, PCB_LAYER_ID aMarkerLayer)
 
virtual bool reportProgress (int aCount, int aSize, int aDelta)
 
virtual bool reportPhase (const wxString &aStageName)
 
virtual void reportRuleStatistics ()
 
virtual void accountCheck (const DRC_RULE *ruleToTest)
 
virtual void accountCheck (const DRC_CONSTRAINT &constraintToTest)
 
bool isInvisibleText (const BOARD_ITEM *aItem) const
 
EDA_UNITS userUnits () const
 

Protected Attributes

BOARDm_board
 
bool m_boardOutlineValid
 
DRC_ENGINEm_drcEngine
 
std::unordered_map< const DRC_RULE *, int > m_stats
 
bool m_isRuleDriven = true
 

Static Protected Attributes

static std::vector< KICAD_Ts_allBasicItems
 
static std::vector< KICAD_Ts_allBasicItemsButZones
 

Private Member Functions

bool testAgainstEdge (BOARD_ITEM *item, SHAPE *itemShape, BOARD_ITEM *other, DRC_CONSTRAINT_T aConstraintType, PCB_DRC_CODE aErrorCode)
 

Private Attributes

std::vector< PAD * > m_castellatedPads
 
int m_largestEdgeClearance
 

Detailed Description

Definition at line 49 of file drc_test_provider_edge_clearance.cpp.

Constructor & Destructor Documentation

◆ DRC_TEST_PROVIDER_EDGE_CLEARANCE()

DRC_TEST_PROVIDER_EDGE_CLEARANCE::DRC_TEST_PROVIDER_EDGE_CLEARANCE ( )
inline

◆ ~DRC_TEST_PROVIDER_EDGE_CLEARANCE()

virtual DRC_TEST_PROVIDER_EDGE_CLEARANCE::~DRC_TEST_PROVIDER_EDGE_CLEARANCE ( )
inlinevirtual

Definition at line 58 of file drc_test_provider_edge_clearance.cpp.

59 {
60 }

Member Function Documentation

◆ accountCheck() [1/2]

void DRC_TEST_PROVIDER::accountCheck ( const DRC_CONSTRAINT constraintToTest)
protectedvirtualinherited

Definition at line 132 of file drc_test_provider.cpp.

133{
134 accountCheck( constraintToTest.GetParentRule() );
135}
DRC_RULE * GetParentRule() const
Definition: drc_rule.h:143
virtual void accountCheck(const DRC_RULE *ruleToTest)

References DRC_TEST_PROVIDER::accountCheck(), and DRC_CONSTRAINT::GetParentRule().

◆ accountCheck() [2/2]

void DRC_TEST_PROVIDER::accountCheck ( const DRC_RULE ruleToTest)
protectedvirtualinherited

Definition at line 121 of file drc_test_provider.cpp.

122{
123 auto it = m_stats.find( ruleToTest );
124
125 if( it == m_stats.end() )
126 m_stats[ ruleToTest ] = 1;
127 else
128 m_stats[ ruleToTest ] += 1;
129}
std::unordered_map< const DRC_RULE *, int > m_stats

References DRC_TEST_PROVIDER::m_stats.

Referenced by DRC_TEST_PROVIDER::accountCheck(), and DRC_TEST_PROVIDER::reportViolation().

◆ forEachGeometryItem()

int DRC_TEST_PROVIDER::forEachGeometryItem ( const std::vector< KICAD_T > &  aTypes,
LSET  aLayers,
const std::function< bool(BOARD_ITEM *)> &  aFunc 
)
protectedinherited

Definition at line 157 of file drc_test_provider.cpp.

159{
160 BOARD *brd = m_drcEngine->GetBoard();
161 std::bitset<MAX_STRUCT_TYPE_ID> typeMask;
162 int n = 0;
163
164 if( aTypes.size() == 0 )
165 {
166 for( int i = 0; i < MAX_STRUCT_TYPE_ID; i++ )
167 typeMask[ i ] = true;
168 }
169 else
170 {
171 for( KICAD_T aType : aTypes )
172 typeMask[ aType ] = true;
173 }
174
175 for( PCB_TRACK* item : brd->Tracks() )
176 {
177 if( (item->GetLayerSet() & aLayers).any() )
178 {
179 if( typeMask[ PCB_TRACE_T ] && item->Type() == PCB_TRACE_T )
180 {
181 aFunc( item );
182 n++;
183 }
184 else if( typeMask[ PCB_VIA_T ] && item->Type() == PCB_VIA_T )
185 {
186 aFunc( item );
187 n++;
188 }
189 else if( typeMask[ PCB_ARC_T ] && item->Type() == PCB_ARC_T )
190 {
191 aFunc( item );
192 n++;
193 }
194 }
195 }
196
197 for( BOARD_ITEM* item : brd->Drawings() )
198 {
199 if( (item->GetLayerSet() & aLayers).any() )
200 {
201 if( typeMask[ PCB_DIMENSION_T ] && BaseType( item->Type() ) == PCB_DIMENSION_T )
202 {
203 if( !aFunc( item ) )
204 return n;
205
206 n++;
207 }
208 else if( typeMask[ PCB_SHAPE_T ] && item->Type() == PCB_SHAPE_T )
209 {
210 if( !aFunc( item ) )
211 return n;
212
213 n++;
214 }
215 else if( typeMask[ PCB_TEXT_T ] && item->Type() == PCB_TEXT_T )
216 {
217 if( !aFunc( item ) )
218 return n;
219
220 n++;
221 }
222 else if( typeMask[ PCB_TEXTBOX_T ] && item->Type() == PCB_TEXTBOX_T )
223 {
224 if( !aFunc( item ) )
225 return n;
226
227 n++;
228 }
229 else if( typeMask[ PCB_TARGET_T ] && item->Type() == PCB_TARGET_T )
230 {
231 if( !aFunc( item ) )
232 return n;
233
234 n++;
235 }
236 }
237 }
238
239 if( typeMask[ PCB_ZONE_T ] )
240 {
241 for( ZONE* item : brd->Zones() )
242 {
243 if( ( item->GetLayerSet() & aLayers ).any() )
244 {
245 if( !aFunc( item ) )
246 return n;
247
248 n++;
249 }
250 }
251 }
252
253 for( FOOTPRINT* footprint : brd->Footprints() )
254 {
255 if( typeMask[ PCB_FP_TEXT_T ] )
256 {
257 if( ( footprint->Reference().GetLayerSet() & aLayers ).any() )
258 {
259 if( !aFunc( &footprint->Reference() ) )
260 return n;
261
262 n++;
263 }
264
265 if( ( footprint->Value().GetLayerSet() & aLayers ).any() )
266 {
267 if( !aFunc( &footprint->Value() ) )
268 return n;
269
270 n++;
271 }
272 }
273
274 if( typeMask[ PCB_PAD_T ] )
275 {
276 for( PAD* pad : footprint->Pads() )
277 {
278 // Careful: if a pad has a hole then it pierces all layers
279 if( pad->HasHole() || ( pad->GetLayerSet() & aLayers ).any() )
280 {
281 if( !aFunc( pad ) )
282 return n;
283
284 n++;
285 }
286 }
287 }
288
289 for( BOARD_ITEM* dwg : footprint->GraphicalItems() )
290 {
291 if( (dwg->GetLayerSet() & aLayers).any() )
292 {
293 if( typeMask[ PCB_DIMENSION_T ] && BaseType( dwg->Type() ) == PCB_DIMENSION_T )
294 {
295 if( !aFunc( dwg ) )
296 return n;
297
298 n++;
299 }
300 else if( typeMask[ PCB_FP_TEXT_T ] && dwg->Type() == PCB_FP_TEXT_T )
301 {
302 if( !aFunc( dwg ) )
303 return n;
304
305 n++;
306 }
307 else if( typeMask[ PCB_FP_TEXTBOX_T ] && dwg->Type() == PCB_FP_TEXTBOX_T )
308 {
309 if( !aFunc( dwg ) )
310 return n;
311
312 n++;
313 }
314 else if( typeMask[ PCB_FP_SHAPE_T ] && dwg->Type() == PCB_FP_SHAPE_T )
315 {
316 if( !aFunc( dwg ) )
317 return n;
318
319 n++;
320 }
321 }
322 }
323
324 if( typeMask[ PCB_FP_ZONE_T ] )
325 {
326 for( ZONE* zone : footprint->Zones() )
327 {
328 if( (zone->GetLayerSet() & aLayers).any() )
329 {
330 if( !aFunc( zone ) )
331 return n;
332
333 n++;
334 }
335 }
336 }
337
338 if( typeMask[ PCB_FOOTPRINT_T ] )
339 {
340 if( !aFunc( footprint ) )
341 return n;
342
343 n++;
344 }
345 }
346
347 return n;
348}
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition: board_item.h:53
Information pertinent to a Pcbnew printed circuit board.
Definition: board.h:240
ZONES & Zones()
Definition: board.h:288
FOOTPRINTS & Footprints()
Definition: board.h:282
TRACKS & Tracks()
Definition: board.h:279
DRAWINGS & Drawings()
Definition: board.h:285
BOARD * GetBoard() const
Definition: drc_engine.h:88
DRC_ENGINE * m_drcEngine
Definition: pad.h:59
Handle a list of polygons defining a copper zone.
Definition: zone.h:58
constexpr KICAD_T BaseType(const KICAD_T aType)
Return the underlying type of the given type.
Definition: typeinfo.h:245
KICAD_T
The set of class identification values stored in EDA_ITEM::m_structType.
Definition: typeinfo.h:78
@ PCB_SHAPE_T
class PCB_SHAPE, a segment not on copper layers
Definition: typeinfo.h:90
@ PCB_FP_SHAPE_T
class FP_SHAPE, a footprint edge
Definition: typeinfo.h:96
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
Definition: typeinfo.h:104
@ MAX_STRUCT_TYPE_ID
Definition: typeinfo.h:233
@ PCB_FP_TEXTBOX_T
class FP_TEXTBOX, wrapped text in a footprint
Definition: typeinfo.h:95
@ PCB_TEXTBOX_T
class PCB_TEXTBOX, wrapped text on a layer
Definition: typeinfo.h:93
@ PCB_ZONE_T
class ZONE, a copper pour area
Definition: typeinfo.h:114
@ PCB_TEXT_T
class PCB_TEXT, text on a layer
Definition: typeinfo.h:92
@ PCB_TARGET_T
class PCB_TARGET, a target (graphic item)
Definition: typeinfo.h:113
@ PCB_FOOTPRINT_T
class FOOTPRINT, a footprint
Definition: typeinfo.h:88
@ PCB_FP_ZONE_T
class ZONE, managed by a footprint
Definition: typeinfo.h:102
@ PCB_PAD_T
class PAD, a pad in a footprint
Definition: typeinfo.h:89
@ PCB_FP_TEXT_T
class FP_TEXT, text in a footprint
Definition: typeinfo.h:94
@ PCB_ARC_T
class PCB_ARC, an arc track segment on a copper layer
Definition: typeinfo.h:105
@ PCB_DIMENSION_T
class PCB_DIMENSION_BASE: abstract dimension meta-type
Definition: typeinfo.h:107
@ PCB_TRACE_T
class PCB_TRACK, a track segment (segment on a copper layer)
Definition: typeinfo.h:103

References BaseType(), BOARD::Drawings(), BOARD::Footprints(), DRC_ENGINE::GetBoard(), DRC_TEST_PROVIDER::m_drcEngine, MAX_STRUCT_TYPE_ID, pad, PCB_ARC_T, PCB_DIMENSION_T, PCB_FOOTPRINT_T, PCB_FP_SHAPE_T, PCB_FP_TEXT_T, PCB_FP_TEXTBOX_T, PCB_FP_ZONE_T, PCB_PAD_T, PCB_SHAPE_T, PCB_TARGET_T, PCB_TEXT_T, PCB_TEXTBOX_T, PCB_TRACE_T, PCB_VIA_T, PCB_ZONE_T, BOARD::Tracks(), and BOARD::Zones().

Referenced by DRC_TEST_PROVIDER_SOLDER_MASK::buildRTrees(), DRC_CACHE_GENERATOR::Run(), test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING::Run(), DRC_TEST_PROVIDER_DISALLOW::Run(), Run(), DRC_TEST_PROVIDER_HOLE_TO_HOLE::Run(), DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::Run(), DRC_TEST_PROVIDER_SILK_CLEARANCE::Run(), DRC_TEST_PROVIDER_SLIVER_CHECKER::Run(), DRC_TEST_PROVIDER_TEXT_DIMS::Run(), DRC_TEST_PROVIDER_MATCHED_LENGTH::runInternal(), DRC_TEST_PROVIDER_MISC::testAssertions(), DRC_TEST_PROVIDER_MISC::testDisabledLayers(), DRC_TEST_PROVIDER_SOLDER_MASK::testMaskBridges(), DRC_TEST_PROVIDER_SOLDER_MASK::testSilkToMaskClearance(), and DRC_TEST_PROVIDER_MISC::testTextVars().

◆ GetDescription()

virtual const wxString DRC_TEST_PROVIDER_EDGE_CLEARANCE::GetDescription ( ) const
inlineoverridevirtual

Reimplemented from DRC_TEST_PROVIDER.

Definition at line 69 of file drc_test_provider_edge_clearance.cpp.

70 {
71 return wxT( "Tests items vs board edge clearance" );
72 }

◆ GetName()

virtual const wxString DRC_TEST_PROVIDER_EDGE_CLEARANCE::GetName ( void  ) const
inlineoverridevirtual

Reimplemented from DRC_TEST_PROVIDER.

Definition at line 64 of file drc_test_provider_edge_clearance.cpp.

65 {
66 return wxT( "edge_clearance" );
67 }

◆ Init()

void DRC_TEST_PROVIDER::Init ( )
staticinherited

Definition at line 52 of file drc_test_provider.cpp.

53{
54 if( s_allBasicItems.size() == 0 )
55 {
56 for( int i = 0; i < MAX_STRUCT_TYPE_ID; i++ )
57 {
58 if( i != PCB_FOOTPRINT_T && i != PCB_GROUP_T )
59 {
60 s_allBasicItems.push_back( (KICAD_T) i );
61
62 if( i != PCB_ZONE_T && i != PCB_FP_ZONE_T )
63 s_allBasicItemsButZones.push_back( (KICAD_T) i );
64 }
65 }
66 }
67}
static std::vector< KICAD_T > s_allBasicItemsButZones
static std::vector< KICAD_T > s_allBasicItems
@ PCB_GROUP_T
class PCB_GROUP, a set of BOARD_ITEMs
Definition: typeinfo.h:117

References MAX_STRUCT_TYPE_ID, PCB_FOOTPRINT_T, PCB_FP_ZONE_T, PCB_GROUP_T, PCB_ZONE_T, DRC_TEST_PROVIDER::s_allBasicItems, and DRC_TEST_PROVIDER::s_allBasicItemsButZones.

Referenced by DRC_ENGINE::RunTests().

◆ isInvisibleText()

bool DRC_TEST_PROVIDER::isInvisibleText ( const BOARD_ITEM aItem) const
protectedinherited

Definition at line 351 of file drc_test_provider.cpp.

352{
353
354 if( const FP_TEXT* text = dyn_cast<const FP_TEXT*>( aItem ) )
355 {
356 if( !text->IsVisible() )
357 return true;
358 }
359
360 if( const PCB_TEXT* text = dyn_cast<const PCB_TEXT*>( aItem ) )
361 {
362 if( !text->IsVisible() )
363 return true;
364 }
365
366 return false;
367}

References text.

Referenced by Run(), DRC_TEST_PROVIDER_SILK_CLEARANCE::Run(), and DRC_TEST_PROVIDER_SOLDER_MASK::testSilkToMaskClearance().

◆ reportAux()

◆ reportPhase()

bool DRC_TEST_PROVIDER::reportPhase ( const wxString &  aStageName)
protectedvirtualinherited

◆ reportProgress()

bool DRC_TEST_PROVIDER::reportProgress ( int  aCount,
int  aSize,
int  aDelta 
)
protectedvirtualinherited

Definition at line 85 of file drc_test_provider.cpp.

86{
87 if( ( aCount % aDelta ) == 0 || aCount == aSize - 1 )
88 {
89 if( !m_drcEngine->ReportProgress( (double) aCount / (double) aSize ) )
90 return false;
91 }
92
93 return true;
94}
bool ReportProgress(double aProgress)

References DRC_TEST_PROVIDER::m_drcEngine, and DRC_ENGINE::ReportProgress().

Referenced by DRC_TEST_PROVIDER_SOLDER_MASK::buildRTrees(), DRC_CACHE_GENERATOR::Run(), DRC_TEST_PROVIDER_ANNULAR_WIDTH::Run(), DRC_TEST_PROVIDER_CONNECTIVITY::Run(), DRC_TEST_PROVIDER_DISALLOW::Run(), Run(), DRC_TEST_PROVIDER_HOLE_TO_HOLE::Run(), DRC_TEST_PROVIDER_LIBRARY_PARITY::Run(), DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::Run(), DRC_TEST_PROVIDER_SILK_CLEARANCE::Run(), DRC_TEST_PROVIDER_TEXT_DIMS::Run(), DRC_TEST_PROVIDER_TRACK_WIDTH::Run(), DRC_TEST_PROVIDER_VIA_DIAMETER::Run(), DRC_TEST_PROVIDER_MATCHED_LENGTH::runInternal(), DRC_TEST_PROVIDER_MISC::testAssertions(), DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::testCourtyardClearances(), DRC_TEST_PROVIDER_MISC::testDisabledLayers(), DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::testFootprintCourtyardDefinitions(), DRC_TEST_PROVIDER_SOLDER_MASK::testMaskBridges(), DRC_TEST_PROVIDER_COPPER_CLEARANCE::testPadClearances(), DRC_TEST_PROVIDER_SOLDER_MASK::testSilkToMaskClearance(), DRC_TEST_PROVIDER_MISC::testTextVars(), DRC_TEST_PROVIDER_COPPER_CLEARANCE::testTrackClearances(), and DRC_TEST_PROVIDER_COPPER_CLEARANCE::testZonesToZones().

◆ reportRuleStatistics()

void DRC_TEST_PROVIDER::reportRuleStatistics ( )
protectedvirtualinherited

Definition at line 138 of file drc_test_provider.cpp.

139{
140 if( !m_isRuleDriven )
141 return;
142
143 m_drcEngine->ReportAux( wxT( "Rule hit statistics: " ) );
144
145 for( const std::pair<const DRC_RULE* const, int>& stat : m_stats )
146 {
147 if( stat.first )
148 {
149 m_drcEngine->ReportAux( wxString::Format( wxT( " - rule '%s': %d hits " ),
150 stat.first->m_Name,
151 stat.second ) );
152 }
153 }
154}
void Format(OUTPUTFORMATTER *out, int aNestLevel, int aCtl, const CPTREE &aTree)
Output a PTREE into s-expression format via an OUTPUTFORMATTER derivative.
Definition: ptree.cpp:200

References Format(), DRC_TEST_PROVIDER::m_drcEngine, DRC_TEST_PROVIDER::m_isRuleDriven, DRC_TEST_PROVIDER::m_stats, and DRC_ENGINE::ReportAux().

Referenced by DRC_TEST_PROVIDER_ANNULAR_WIDTH::Run(), DRC_TEST_PROVIDER_CONNECTIVITY::Run(), DRC_TEST_PROVIDER_COPPER_CLEARANCE::Run(), test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING::Run(), DRC_TEST_PROVIDER_DISALLOW::Run(), DRC_TEST_PROVIDER_HOLE_SIZE::Run(), DRC_TEST_PROVIDER_SCHEMATIC_PARITY::Run(), DRC_TEST_PROVIDER_SOLDER_MASK::Run(), DRC_TEST_PROVIDER_TEXT_DIMS::Run(), DRC_TEST_PROVIDER_TRACK_WIDTH::Run(), DRC_TEST_PROVIDER_VIA_DIAMETER::Run(), and DRC_TEST_PROVIDER_MATCHED_LENGTH::runInternal().

◆ reportViolation()

void DRC_TEST_PROVIDER::reportViolation ( std::shared_ptr< DRC_ITEM > &  item,
const VECTOR2I aMarkerPos,
PCB_LAYER_ID  aMarkerLayer 
)
protectedvirtualinherited

Definition at line 74 of file drc_test_provider.cpp.

76{
77 if( item->GetViolatingRule() )
78 accountCheck( item->GetViolatingRule() );
79
80 item->SetViolatingTest( this );
81 m_drcEngine->ReportViolation( item, aMarkerPos, aMarkerLayer );
82}
void ReportViolation(const std::shared_ptr< DRC_ITEM > &aItem, const VECTOR2I &aPos, PCB_LAYER_ID aMarkerLayer)

References DRC_TEST_PROVIDER::accountCheck(), DRC_TEST_PROVIDER::m_drcEngine, and DRC_ENGINE::ReportViolation().

Referenced by DRC_TEST_PROVIDER_MATCHED_LENGTH::checkLengths(), DRC_TEST_PROVIDER_HOLE_SIZE::checkPadHole(), DRC_TEST_PROVIDER_MATCHED_LENGTH::checkSkews(), DRC_TEST_PROVIDER_MATCHED_LENGTH::checkViaCounts(), DRC_TEST_PROVIDER_HOLE_SIZE::checkViaHole(), DRC_TEST_PROVIDER_ANNULAR_WIDTH::Run(), DRC_TEST_PROVIDER_CONNECTION_WIDTH::Run(), DRC_TEST_PROVIDER_CONNECTIVITY::Run(), test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING::Run(), DRC_TEST_PROVIDER_DISALLOW::Run(), DRC_TEST_PROVIDER_FOOTPRINT_CHECKS::Run(), DRC_TEST_PROVIDER_LIBRARY_PARITY::Run(), DRC_TEST_PROVIDER_SILK_CLEARANCE::Run(), DRC_TEST_PROVIDER_SLIVER_CHECKER::Run(), DRC_TEST_PROVIDER_TEXT_DIMS::Run(), DRC_TEST_PROVIDER_TRACK_WIDTH::Run(), DRC_TEST_PROVIDER_VIA_DIAMETER::Run(), testAgainstEdge(), DRC_TEST_PROVIDER_MISC::testAssertions(), DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::testCourtyardClearances(), DRC_TEST_PROVIDER_MISC::testDisabledLayers(), DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::testFootprintCourtyardDefinitions(), DRC_TEST_PROVIDER_HOLE_TO_HOLE::testHoleAgainstHole(), DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testItemAgainstItem(), DRC_TEST_PROVIDER_SOLDER_MASK::testItemAgainstItems(), DRC_TEST_PROVIDER_COPPER_CLEARANCE::testItemAgainstZone(), DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testItemAgainstZones(), DRC_TEST_PROVIDER_SOLDER_MASK::testMaskItemAgainstZones(), DRC_TEST_PROVIDER_SCHEMATIC_PARITY::testNetlist(), DRC_TEST_PROVIDER_MISC::testOutline(), DRC_TEST_PROVIDER_COPPER_CLEARANCE::testPadAgainstItem(), DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testShapeLineChain(), DRC_TEST_PROVIDER_MISC::testTextVars(), DRC_TEST_PROVIDER_COPPER_CLEARANCE::testTrackAgainstItem(), DRC_TEST_PROVIDER_ZONE_CONNECTIONS::testZoneLayer(), DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testZoneLayer(), and DRC_TEST_PROVIDER_COPPER_CLEARANCE::testZonesToZones().

◆ Run()

bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run ( )
overridevirtual

Run this provider against the given PCB with configured options (if any).

Implements DRC_TEST_PROVIDER.

Definition at line 142 of file drc_test_provider_edge_clearance.cpp.

143{
145 {
146 if( !reportPhase( _( "Checking copper to board edge clearances..." ) ) )
147 return false; // DRC cancelled
148 }
150 {
151 if( !reportPhase( _( "Checking silk to board edge clearances..." ) ) )
152 return false; // DRC cancelled
153 }
154 else
155 {
156 reportAux( wxT( "Edge clearance violations ignored. Tests not run." ) );
157 return true; // continue with other tests
158 }
159
161 m_castellatedPads.clear();
162
163 DRC_CONSTRAINT worstClearanceConstraint;
164
165 if( m_drcEngine->QueryWorstConstraint( EDGE_CLEARANCE_CONSTRAINT, worstClearanceConstraint ) )
166 m_largestEdgeClearance = worstClearanceConstraint.GetValue().Min();
167
168 reportAux( wxT( "Worst clearance : %d nm" ), m_largestEdgeClearance );
169
170 std::vector<std::unique_ptr<PCB_SHAPE>> edges;
171 DRC_RTREE edgesTree;
172
174 [&]( BOARD_ITEM *item ) -> bool
175 {
176 PCB_SHAPE* shape = static_cast<PCB_SHAPE*>( item );
177 STROKE_PARAMS stroke = shape->GetStroke();
178
179 if( item->IsOnLayer( Edge_Cuts ) )
180 stroke.SetWidth( 0 );
181
182 if( shape->GetShape() == SHAPE_T::RECT && !shape->IsFilled() )
183 {
184 // A single rectangle for the board would make the RTree useless, so convert
185 // to 4 edges
186 edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
187 edges.back()->SetShape( SHAPE_T::SEGMENT );
188 edges.back()->SetEndX( shape->GetStartX() );
189 edges.back()->SetStroke( stroke );
190 edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
191 edges.back()->SetShape( SHAPE_T::SEGMENT );
192 edges.back()->SetEndY( shape->GetStartY() );
193 edges.back()->SetStroke( stroke );
194 edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
195 edges.back()->SetShape( SHAPE_T::SEGMENT );
196 edges.back()->SetStartX( shape->GetEndX() );
197 edges.back()->SetStroke( stroke );
198 edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
199 edges.back()->SetShape( SHAPE_T::SEGMENT );
200 edges.back()->SetStartY( shape->GetEndY() );
201 edges.back()->SetStroke( stroke );
202 }
203 else if( shape->GetShape() == SHAPE_T::POLY && !shape->IsFilled() )
204 {
205 // A single polygon for the board would make the RTree useless, so convert
206 // to n edges.
207 SHAPE_LINE_CHAIN poly = shape->GetPolyShape().Outline( 0 );
208
209 for( size_t ii = 0; ii < poly.GetSegmentCount(); ++ii )
210 {
211 SEG seg = poly.CSegment( ii );
212 edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
213 edges.back()->SetShape( SHAPE_T::SEGMENT );
214 edges.back()->SetStart( seg.A );
215 edges.back()->SetEnd( seg.B );
216 edges.back()->SetStroke( stroke );
217 }
218 }
219 else
220 {
221 edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
222 edges.back()->SetStroke( stroke );
223 }
224
225 return true;
226 } );
227
228 for( const std::unique_ptr<PCB_SHAPE>& edge : edges )
229 {
230 for( PCB_LAYER_ID layer : { Edge_Cuts, Margin } )
231 {
232 if( edge->IsOnLayer( layer ) )
233 edgesTree.Insert( edge.get(), layer, m_largestEdgeClearance );
234 }
235 }
236
237 for( FOOTPRINT* footprint : m_board->Footprints() )
238 {
239 for( PAD* pad : footprint->Pads() )
240 {
241 if( pad->GetAttribute() == PAD_ATTRIB::NPTH )
243
244 if( pad->GetProperty() == PAD_PROP::CASTELLATED )
245 m_castellatedPads.push_back( pad );
246 }
247 }
248
249 const int progressDelta = 200;
250 int count = 0;
251 int ii = 0;
252
254 [&]( BOARD_ITEM *item ) -> bool
255 {
256 count++;
257 return true;
258 } );
259
261 [&]( BOARD_ITEM *item ) -> bool
262 {
265
266 if( !testCopper && !testSilk )
267 return false; // We're done
268
269 if( !reportProgress( ii++, count, progressDelta ) )
270 return false; // DRC cancelled; we're done
271
272 if( isInvisibleText( item ) )
273 return true; // Continue with other items
274
275 if( item->Type() == PCB_PAD_T
276 && static_cast<PAD*>( item )->GetProperty() == PAD_PROP::CASTELLATED )
277 {
278 return true;
279 }
280
281 const std::shared_ptr<SHAPE>& itemShape = item->GetEffectiveShape();
282
283 for( PCB_LAYER_ID testLayer : { Edge_Cuts, Margin } )
284 {
285 if( testCopper && item->IsOnCopperLayer() )
286 {
287 edgesTree.QueryColliding( item, UNDEFINED_LAYER, testLayer, nullptr,
288 [&]( BOARD_ITEM* edge ) -> bool
289 {
290 return testAgainstEdge( item, itemShape.get(), edge,
291 EDGE_CLEARANCE_CONSTRAINT,
292 DRCE_EDGE_CLEARANCE );
293 },
294 m_largestEdgeClearance );
295 }
296
297 if( testSilk && ( item->IsOnLayer( F_SilkS ) || item->IsOnLayer( B_SilkS ) ) )
298 {
299 if( edgesTree.QueryColliding( item, UNDEFINED_LAYER, testLayer, nullptr,
300 [&]( BOARD_ITEM* edge ) -> bool
301 {
302 return testAgainstEdge( item, itemShape.get(), edge,
303 SILK_CLEARANCE_CONSTRAINT,
304 DRCE_SILK_EDGE_CLEARANCE );
305 },
307 {
308 // violations reported during QueryColliding
309 }
310 else
311 {
312 // TODO: check postion being outside board boundary
313 }
314 }
315 }
316
317 return true;
318 } );
319
321
322 return !m_drcEngine->IsCancelled();
323}
virtual bool IsOnLayer(PCB_LAYER_ID aLayer) const
Test to see if this object is on the given layer.
Definition: board_item.h:229
virtual std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
Definition: board_item.cpp:197
const MINOPTMAX< int > & GetValue() const
Definition: drc_rule.h:139
bool IsErrorLimitExceeded(int error_code)
bool IsCancelled() const
bool QueryWorstConstraint(DRC_CONSTRAINT_T aRuleId, DRC_CONSTRAINT &aConstraint)
Implement an R-tree for fast spatial and layer indexing of connectable items.
Definition: drc_rtree.h:48
void Insert(BOARD_ITEM *aItem, PCB_LAYER_ID aLayer, int aWorstClearance=0)
Insert an item into the tree on a particular layer with an optional worst clearance.
Definition: drc_rtree.h:104
virtual bool reportPhase(const wxString &aStageName)
int forEachGeometryItem(const std::vector< KICAD_T > &aTypes, LSET aLayers, const std::function< bool(BOARD_ITEM *)> &aFunc)
virtual bool reportProgress(int aCount, int aSize, int aDelta)
bool isInvisibleText(const BOARD_ITEM *aItem) const
virtual void reportRuleStatistics()
KICAD_T Type() const
Returns the type of object.
Definition: eda_item.h:112
int GetStartY() const
Definition: eda_shape.h:116
int GetEndX() const
Definition: eda_shape.h:142
SHAPE_POLY_SET & GetPolyShape()
Definition: eda_shape.h:242
bool IsFilled() const
Definition: eda_shape.h:89
SHAPE_T GetShape() const
Definition: eda_shape.h:110
int GetEndY() const
Definition: eda_shape.h:141
int GetStartX() const
Definition: eda_shape.h:117
LSET is a set of PCB_LAYER_IDs.
Definition: layer_ids.h:529
static LSET AllLayersMask()
Definition: lset.cpp:808
T Min() const
Definition: minoptmax.h:33
PAD_PROP GetProperty() const
Definition: pad.h:381
STROKE_PARAMS GetStroke() const override
Definition: pcb_shape.h:83
virtual EDA_ITEM * Clone() const override
Create a duplicate of this item with linked list members set to NULL.
Definition: pcb_shape.cpp:240
Definition: seg.h:42
VECTOR2I A
Definition: seg.h:49
VECTOR2I B
Definition: seg.h:50
Represent a polyline containing arcs as well as line segments: A chain of connected line and/or arc s...
virtual size_t GetSegmentCount() const override
const SEG CSegment(int aIndex) const
Return a constant copy of the aIndex segment in the line chain.
SHAPE_LINE_CHAIN & Outline(int aIndex)
Simple container to manage line stroke parameters.
Definition: stroke_params.h:87
void SetWidth(int aWidth)
Definition: stroke_params.h:98
@ DRCE_SILK_EDGE_CLEARANCE
Definition: drc_item.h:90
@ DRCE_EDGE_CLEARANCE
Definition: drc_item.h:45
@ EDGE_CLEARANCE_CONSTRAINT
Definition: drc_rule.h:49
#define _(s)
PCB_LAYER_ID
A quick note on layer IDs:
Definition: layer_ids.h:59
@ Edge_Cuts
Definition: layer_ids.h:113
@ Margin
Definition: layer_ids.h:114
@ F_SilkS
Definition: layer_ids.h:104
@ B_SilkS
Definition: layer_ids.h:103
@ NPTH
like PAD_PTH, but not plated
@ CASTELLATED
a pad with a castellated through hole

References _, SEG::A, LSET::AllLayersMask(), SEG::B, B_SilkS, CASTELLATED, PCB_SHAPE::Clone(), SHAPE_LINE_CHAIN::CSegment(), DRCE_EDGE_CLEARANCE, DRCE_SILK_EDGE_CLEARANCE, EDGE_CLEARANCE_CONSTRAINT, Edge_Cuts, F_SilkS, BOARD::Footprints(), DRC_TEST_PROVIDER::forEachGeometryItem(), DRC_ENGINE::GetBoard(), BOARD_ITEM::GetEffectiveShape(), EDA_SHAPE::GetEndX(), EDA_SHAPE::GetEndY(), EDA_SHAPE::GetPolyShape(), PAD::GetProperty(), SHAPE_LINE_CHAIN::GetSegmentCount(), EDA_SHAPE::GetShape(), EDA_SHAPE::GetStartX(), EDA_SHAPE::GetStartY(), PCB_SHAPE::GetStroke(), DRC_CONSTRAINT::GetValue(), DRC_RTREE::Insert(), DRC_ENGINE::IsErrorLimitExceeded(), EDA_SHAPE::IsFilled(), DRC_TEST_PROVIDER::isInvisibleText(), BOARD_ITEM::IsOnLayer(), DRC_TEST_PROVIDER_CLEARANCE_BASE::m_board, m_castellatedPads, DRC_TEST_PROVIDER::m_drcEngine, m_largestEdgeClearance, Margin, MINOPTMAX< T >::Min(), NPTH, SHAPE_POLY_SET::Outline(), pad, PCB_FP_SHAPE_T, PCB_PAD_T, PCB_SHAPE_T, POLY, DRC_ENGINE::QueryWorstConstraint(), RECT, DRC_TEST_PROVIDER::reportAux(), DRC_TEST_PROVIDER::reportPhase(), DRC_TEST_PROVIDER::reportProgress(), DRC_TEST_PROVIDER::s_allBasicItemsButZones, SEGMENT, STROKE_PARAMS::SetWidth(), and EDA_ITEM::Type().

◆ SetDRCEngine()

void DRC_TEST_PROVIDER::SetDRCEngine ( DRC_ENGINE engine)
inlineinherited

Definition at line 80 of file drc_test_provider.h.

81 {
82 m_drcEngine = engine;
83 m_stats.clear();
84 }

References DRC_TEST_PROVIDER::m_drcEngine, and DRC_TEST_PROVIDER::m_stats.

Referenced by EDIT_TOOL::doMoveSelection(), and DRC_ENGINE::RunTests().

◆ testAgainstEdge()

bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::testAgainstEdge ( BOARD_ITEM item,
SHAPE itemShape,
BOARD_ITEM other,
DRC_CONSTRAINT_T  aConstraintType,
PCB_DRC_CODE  aErrorCode 
)
private

Definition at line 84 of file drc_test_provider_edge_clearance.cpp.

88{
89 std::shared_ptr<SHAPE> shape;
90
91 if( edge->Type() == PCB_PAD_T )
92 shape = edge->GetEffectiveHoleShape();
93 else
94 shape = edge->GetEffectiveShape( Edge_Cuts );
95
96 auto constraint = m_drcEngine->EvalRules( aConstraintType, edge, item, UNDEFINED_LAYER );
97 int minClearance = constraint.GetValue().Min();
98 int actual;
99 VECTOR2I pos;
100
101 if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && minClearance >= 0 )
102 {
103 if( itemShape->Collide( shape.get(), minClearance, &actual, &pos ) )
104 {
105 if( item->Type() == PCB_TRACE_T || item->Type() == PCB_ARC_T )
106 {
107 // Edge collisions are allowed inside the holes of castellated pads
108 for( PAD* castellatedPad : m_castellatedPads )
109 {
110 if( castellatedPad->GetEffectiveHoleShape()->Collide( pos ) )
111 return true;
112 }
113 }
114
115 std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( aErrorCode );
116
117 // Only report clearance info if there is any; otherwise it's just a straight collision
118 if( minClearance > 0 )
119 {
120 wxString msg;
121
122 msg.Printf( _( "(%s clearance %s; actual %s)" ),
123 constraint.GetName(),
124 MessageTextFromValue( userUnits(), minClearance ),
125 MessageTextFromValue( userUnits(), actual ) );
126
127 drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
128 }
129
130 drce->SetItems( edge->m_Uuid, item->m_Uuid );
131 drce->SetViolatingRule( constraint.GetParentRule() );
132
133 reportViolation( drce, pos, Edge_Cuts );
134 return false; // don't report violations with multiple edges; one is enough
135 }
136 }
137
138 return true;
139}
wxString MessageTextFromValue(EDA_UNITS aUnits, int aValue, bool aAddUnitLabel, EDA_DATA_TYPE aType)
Convert a value to a string using double notation.
Definition: base_units.cpp:103
DRC_CONSTRAINT EvalRules(DRC_CONSTRAINT_T aConstraintType, const BOARD_ITEM *a, const BOARD_ITEM *b, PCB_LAYER_ID aLayer, REPORTER *aReporter=nullptr)
Definition: drc_engine.cpp:646
static std::shared_ptr< DRC_ITEM > Create(int aErrorCode)
Constructs a DRC_ITEM for the given error code.
Definition: drc_item.cpp:324
virtual void reportViolation(std::shared_ptr< DRC_ITEM > &item, const VECTOR2I &aMarkerPos, PCB_LAYER_ID aMarkerLayer)
EDA_UNITS userUnits() const
const KIID m_Uuid
Definition: eda_item.h:494
virtual bool Collide(const VECTOR2I &aP, int aClearance=0, int *aActual=nullptr, VECTOR2I *aLocation=nullptr) const
Check if the boundary of shape (this) lies closer to the point aP than aClearance,...
Definition: shape.h:178
@ UNDEFINED_LAYER
Definition: layer_ids.h:60
@ RPT_SEVERITY_IGNORE

References _, SHAPE::Collide(), DRC_ITEM::Create(), Edge_Cuts, DRC_ENGINE::EvalRules(), BOARD_ITEM::GetEffectiveHoleShape(), BOARD_ITEM::GetEffectiveShape(), DRC_CONSTRAINT::GetValue(), m_castellatedPads, DRC_TEST_PROVIDER::m_drcEngine, EDA_ITEM::m_Uuid, MessageTextFromValue(), MINOPTMAX< T >::Min(), PCB_ARC_T, PCB_PAD_T, PCB_TRACE_T, DRC_TEST_PROVIDER::reportViolation(), RPT_SEVERITY_IGNORE, EDA_ITEM::Type(), UNDEFINED_LAYER, and DRC_TEST_PROVIDER::userUnits().

◆ userUnits()

Member Data Documentation

◆ m_board

◆ m_boardOutlineValid

bool DRC_TEST_PROVIDER_CLEARANCE_BASE::m_boardOutlineValid
protectedinherited

Definition at line 51 of file drc_test_provider_clearance_base.h.

◆ m_castellatedPads

std::vector<PAD*> DRC_TEST_PROVIDER_EDGE_CLEARANCE::m_castellatedPads
private

Definition at line 79 of file drc_test_provider_edge_clearance.cpp.

Referenced by Run(), and testAgainstEdge().

◆ m_drcEngine

DRC_ENGINE* DRC_TEST_PROVIDER::m_drcEngine
protectedinherited

Definition at line 117 of file drc_test_provider.h.

Referenced by DRC_TEST_PROVIDER_HOLE_SIZE::checkPadHole(), DRC_TEST_PROVIDER_HOLE_SIZE::checkViaHole(), DRC_TEST_PROVIDER::forEachGeometryItem(), DRC_TEST_PROVIDER_CONNECTION_WIDTH::layerDesc(), DRC_TEST_PROVIDER_SLIVER_CHECKER::layerDesc(), DRC_TEST_PROVIDER::reportAux(), DRC_TEST_PROVIDER::reportPhase(), DRC_TEST_PROVIDER::reportProgress(), DRC_TEST_PROVIDER::reportRuleStatistics(), DRC_TEST_PROVIDER::reportViolation(), DRC_CACHE_GENERATOR::Run(), DRC_TEST_PROVIDER_ANNULAR_WIDTH::Run(), DRC_TEST_PROVIDER_CONNECTION_WIDTH::Run(), DRC_TEST_PROVIDER_CONNECTIVITY::Run(), DRC_TEST_PROVIDER_COPPER_CLEARANCE::Run(), DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::Run(), test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING::Run(), DRC_TEST_PROVIDER_DISALLOW::Run(), Run(), DRC_TEST_PROVIDER_FOOTPRINT_CHECKS::Run(), DRC_TEST_PROVIDER_HOLE_SIZE::Run(), DRC_TEST_PROVIDER_HOLE_TO_HOLE::Run(), DRC_TEST_PROVIDER_LIBRARY_PARITY::Run(), DRC_TEST_PROVIDER_MISC::Run(), DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::Run(), DRC_TEST_PROVIDER_SCHEMATIC_PARITY::Run(), DRC_TEST_PROVIDER_SILK_CLEARANCE::Run(), DRC_TEST_PROVIDER_SLIVER_CHECKER::Run(), DRC_TEST_PROVIDER_SOLDER_MASK::Run(), DRC_TEST_PROVIDER_TEXT_DIMS::Run(), DRC_TEST_PROVIDER_TRACK_WIDTH::Run(), DRC_TEST_PROVIDER_VIA_DIAMETER::Run(), DRC_TEST_PROVIDER_ZONE_CONNECTIONS::Run(), DRC_TEST_PROVIDER_COURTYARD_CLEARANCE_ON_MOVE::Run(), DRC_TEST_PROVIDER_MATCHED_LENGTH::runInternal(), DRC_TEST_PROVIDER::SetDRCEngine(), testAgainstEdge(), DRC_TEST_PROVIDER_MISC::testAssertions(), DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::testCourtyardClearances(), DRC_TEST_PROVIDER_MISC::testDisabledLayers(), DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::testFootprintCourtyardDefinitions(), DRC_TEST_PROVIDER_HOLE_TO_HOLE::testHoleAgainstHole(), DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testItemAgainstItem(), DRC_TEST_PROVIDER_SOLDER_MASK::testItemAgainstItems(), DRC_TEST_PROVIDER_COPPER_CLEARANCE::testItemAgainstZone(), DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testItemAgainstZones(), DRC_TEST_PROVIDER_SOLDER_MASK::testMaskBridges(), DRC_TEST_PROVIDER_SOLDER_MASK::testMaskItemAgainstZones(), DRC_TEST_PROVIDER_SCHEMATIC_PARITY::testNetlist(), DRC_TEST_PROVIDER_COPPER_CLEARANCE::testPadAgainstItem(), DRC_TEST_PROVIDER_COPPER_CLEARANCE::testPadClearances(), DRC_TEST_PROVIDER_SOLDER_MASK::testSilkToMaskClearance(), DRC_TEST_PROVIDER_MISC::testTextVars(), DRC_TEST_PROVIDER_COPPER_CLEARANCE::testTrackAgainstItem(), DRC_TEST_PROVIDER_COPPER_CLEARANCE::testTrackClearances(), DRC_TEST_PROVIDER_ZONE_CONNECTIONS::testZoneLayer(), DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testZoneLayer(), DRC_TEST_PROVIDER_COPPER_CLEARANCE::testZonesToZones(), and DRC_TEST_PROVIDER::userUnits().

◆ m_isRuleDriven

◆ m_largestEdgeClearance

int DRC_TEST_PROVIDER_EDGE_CLEARANCE::m_largestEdgeClearance
private

Definition at line 80 of file drc_test_provider_edge_clearance.cpp.

Referenced by Run().

◆ m_stats

std::unordered_map<const DRC_RULE*, int> DRC_TEST_PROVIDER::m_stats
protectedinherited

◆ s_allBasicItems

◆ s_allBasicItemsButZones

std::vector< KICAD_T > DRC_TEST_PROVIDER::s_allBasicItemsButZones
staticprotectedinherited

The documentation for this class was generated from the following file: