59 virtual bool Run()
override;
61 virtual const wxString
GetName()
const override 63 return "edge_clearance";
68 return "Tests items vs board edge clearance";
93 if( minClearance >= 0 && itemShape->
Collide( edgeShape.get(), minClearance, &actual, &pos ) )
98 if( minClearance > 0 )
100 m_msg.Printf(
_(
"(%s clearance %s; actual %s)" ),
101 constraint.GetName(),
105 drce->SetErrorMessage( drce->GetErrorText() + wxS(
" " ) +
m_msg );
109 drce->SetViolatingRule( constraint.GetParentRule() );
122 if( !
reportPhase(
_(
"Checking copper to board edge clearances..." ) ) )
127 if( !
reportPhase(
_(
"Checking silk to board edge clearances..." ) ) )
132 reportAux(
"Edge clearance violations ignored. Tests not run." );
145 std::vector<std::unique_ptr<PCB_SHAPE>> edges;
147 std::vector<BOARD_ITEM*> boardItems;
149 auto queryBoardOutlineItems =
152 PCB_SHAPE* shape = static_cast<PCB_SHAPE*>( item );
158 edges.emplace_back( static_cast<PCB_SHAPE*>( shape->
Clone() ) );
160 edges.back()->SetEndX( shape->
GetStartX() );
161 edges.back()->SetWidth( 0 );
162 edges.emplace_back( static_cast<PCB_SHAPE*>( shape->
Clone() ) );
164 edges.back()->SetEndY( shape->
GetStartY() );
165 edges.back()->SetWidth( 0 );
166 edges.emplace_back( static_cast<PCB_SHAPE*>( shape->
Clone() ) );
168 edges.back()->SetStartX( shape->
GetEndX() );
169 edges.back()->SetWidth( 0 );
170 edges.emplace_back( static_cast<PCB_SHAPE*>( shape->
Clone() ) );
172 edges.back()->SetStartY( shape->
GetEndY() );
173 edges.back()->SetWidth( 0 );
184 edges.emplace_back( static_cast<PCB_SHAPE*>( shape->
Clone() ) );
186 edges.back()->SetStart((wxPoint) seg.
A );
187 edges.back()->SetEnd((wxPoint) seg.
B );
188 edges.back()->SetWidth( 0 );
192 edges.emplace_back( static_cast<PCB_SHAPE*>( shape->
Clone() ) );
193 edges.back()->SetWidth( 0 );
197 auto queryBoardGeometryItems =
201 boardItems.push_back( item );
207 queryBoardOutlineItems );
210 for(
const std::unique_ptr<PCB_SHAPE>& edge : edges )
214 wxGetEnv(
"WXTRACE", &val );
216 drc_dbg( 2,
"outline: %d items, board: %d items\n",
217 (
int) edges.size(), (int) boardItems.size() );
220 const int delta = 50;
228 if( !testCopper && !testSilk )
234 const std::shared_ptr<SHAPE>& itemShape = item->GetEffectiveShape();
236 if( testCopper && item->IsOnCopperLayer() )
248 if( testSilk && ( item->GetLayer() ==
F_SilkS || item->GetLayer() ==
B_SilkS ) )
static LSET AllCuMask(int aCuLayerCount=MAX_CU_LAYERS)
Return a mask holding the requested number of Cu PCB_LAYER_IDs.
wxString MessageTextFromValue(EDA_UNITS aUnits, int aValue, bool aAddUnitLabel, EDA_DATA_TYPE aType)
Convert a value to a string using double notation.
virtual size_t GetSegmentCount() const override
static std::shared_ptr< DRC_ITEM > Create(int aErrorCode)
Constructs a DRC_ITEM for the given error code.
SHAPE_POLY_SET & GetPolyShape()
bool isInvisibleText(const BOARD_ITEM *aItem) const
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
virtual const wxString GetName() const override
virtual EDA_ITEM * Clone() const override
Create a duplicate of this item with linked list members set to NULL.
static DRC_REGISTER_TEST_PROVIDER< DRC_TEST_PROVIDER_ANNULUS > dummy
virtual std::set< DRC_CONSTRAINT_T > GetConstraintTypes() const override
bool IsErrorLimitExceeded(int error_code)
polygon (not yet used for tracks, but could be in microwave apps)
usual segment : line with rounded ends
virtual bool reportProgress(int aCount, int aSize, int aDelta)
class FP_SHAPE, a footprint edge
segment with non rounded ends
virtual void reportRuleStatistics()
virtual bool Collide(const VECTOR2I &aP, int aClearance=0, int *aActual=nullptr, VECTOR2I *aLocation=nullptr) const
Check if the boundary of shape (this) lies closer to the point aP than aClearance,...
void Insert(BOARD_ITEM *aItem, int aWorstClearance=0, int aLayer=UNDEFINED_LAYER)
Function Insert() Inserts an item into the tree.
virtual ~DRC_TEST_PROVIDER_EDGE_CLEARANCE()
LSET is a set of PCB_LAYER_IDs.
bool QueryWorstConstraint(DRC_CONSTRAINT_T aRuleId, DRC_CONSTRAINT &aConstraint)
bool testAgainstEdge(BOARD_ITEM *item, SHAPE *itemShape, BOARD_ITEM *other, DRC_CONSTRAINT_T aConstraintType, PCB_DRC_CODE aErrorCode)
virtual bool reportPhase(const wxString &aStageName)
SHAPE_LINE_CHAIN & Outline(int aIndex)
virtual const wxString GetDescription() const override
An abstract shape on 2D plane.
EDA_UNITS userUnits() const
DRC_CONSTRAINT EvalRules(DRC_CONSTRAINT_T aConstraintId, const BOARD_ITEM *a, const BOARD_ITEM *b, PCB_LAYER_ID aLayer, REPORTER *aReporter=nullptr)
virtual void reportViolation(std::shared_ptr< DRC_ITEM > &item, wxPoint aMarkerPos)
int forEachGeometryItem(const std::vector< KICAD_T > &aTypes, LSET aLayers, const std::function< bool(BOARD_ITEM *)> &aFunc)
virtual bool Run() override
Runs this provider against the given PCB with configured options (if any).
const MINOPTMAX< int > & GetValue() const
const SEG CSegment(int aIndex) const
Function CSegment()
static std::vector< KICAD_T > s_allBasicItemsButZones
int GetNumPhases() const override
virtual std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER) const
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
PCB_SHAPE_TYPE_T GetShape() const
#define drc_dbg(level, fmt,...)
DRC_RTREE - Implements an R-tree for fast spatial and layer indexing of connectable items.
class PCB_SHAPE, a segment not on copper layers
virtual PCB_LAYER_ID GetLayer() const
Return the primary layer this item is on.
virtual void reportAux(wxString fmt,...)
DRC_TEST_PROVIDER_EDGE_CLEARANCE()
int QueryColliding(BOARD_ITEM *aRefItem, PCB_LAYER_ID aRefLayer, PCB_LAYER_ID aTargetLayer, std::function< bool(BOARD_ITEM *)> aFilter=nullptr, std::function< bool(BOARD_ITEM *)> aVisitor=nullptr, int aClearance=0) const
This is a fast test which essentially does bounding-box overlap given a worst-case clearance.