KiCad PCB EDA Suite
drc_test_provider_edge_clearance.cpp
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23 
24 #include <common.h>
25 #include <pcb_shape.h>
26 #include <geometry/seg.h>
27 #include <geometry/shape_segment.h>
28 #include <drc/drc_engine.h>
29 #include <drc/drc_item.h>
30 #include <drc/drc_rule.h>
32 #include "drc_rtree.h"
33 
34 /*
35  Board edge clearance test. Checks all items for their mechanical clearances against the board
36  edge.
37  Errors generated:
38  - DRCE_COPPER_EDGE_CLEARANCE
39 
40  TODO:
41  - separate holes to edge check
42  - tester only looks for edge crossings. it doesn't check if items are inside/outside the board
43  area.
44  - pad test missing!
45 */
46 
48 {
49 public:
52  {
53  }
54 
56  {
57  }
58 
59  virtual bool Run() override;
60 
61  virtual const wxString GetName() const override
62  {
63  return "edge_clearance";
64  }
65 
66  virtual const wxString GetDescription() const override
67  {
68  return "Tests items vs board edge clearance";
69  }
70 
71  virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
72 
73  int GetNumPhases() const override;
74 
75 private:
76  bool testAgainstEdge( BOARD_ITEM* item, SHAPE* itemShape, BOARD_ITEM* other,
77  DRC_CONSTRAINT_T aConstraintType, PCB_DRC_CODE aErrorCode );
78 };
79 
80 
82  BOARD_ITEM* edge,
83  DRC_CONSTRAINT_T aConstraintType,
84  PCB_DRC_CODE aErrorCode )
85 {
86  const std::shared_ptr<SHAPE>& edgeShape = edge->GetEffectiveShape( Edge_Cuts );
87 
88  auto constraint = m_drcEngine->EvalRules( aConstraintType, edge, item, item->GetLayer() );
89  int minClearance = constraint.GetValue().Min();
90  int actual;
91  VECTOR2I pos;
92 
93  if( minClearance >= 0 && itemShape->Collide( edgeShape.get(), minClearance, &actual, &pos ) )
94  {
95  std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( aErrorCode );
96 
97  // Only report clearance info if there is any; otherwise it's just a straight collision
98  if( minClearance > 0 )
99  {
100  m_msg.Printf( _( "(%s clearance %s; actual %s)" ),
101  constraint.GetName(),
102  MessageTextFromValue( userUnits(), minClearance ),
103  MessageTextFromValue( userUnits(), actual ) );
104 
105  drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + m_msg );
106  }
107 
108  drce->SetItems( edge->m_Uuid, item->m_Uuid );
109  drce->SetViolatingRule( constraint.GetParentRule() );
110 
111  reportViolation( drce, (wxPoint) pos );
112  }
113 
114  return true;
115 }
116 
117 
119 {
121  {
122  if( !reportPhase( _( "Checking copper to board edge clearances..." ) ) )
123  return false; // DRC cancelled
124  }
126  {
127  if( !reportPhase( _( "Checking silk to board edge clearances..." ) ) )
128  return false; // DRC cancelled
129  }
130  else
131  {
132  reportAux( "Edge clearance violations ignored. Tests not run." );
133  return true; // continue with other tests
134  }
135 
137 
138  DRC_CONSTRAINT worstClearanceConstraint;
139 
140  if( m_drcEngine->QueryWorstConstraint( EDGE_CLEARANCE_CONSTRAINT, worstClearanceConstraint ) )
141  m_largestClearance = worstClearanceConstraint.GetValue().Min();
142 
143  reportAux( "Worst clearance : %d nm", m_largestClearance );
144 
145  std::vector<std::unique_ptr<PCB_SHAPE>> edges; // we own these
146  DRC_RTREE edgesTree;
147  std::vector<BOARD_ITEM*> boardItems; // we don't own these
148 
149  auto queryBoardOutlineItems =
150  [&]( BOARD_ITEM *item ) -> bool
151  {
152  PCB_SHAPE* shape = static_cast<PCB_SHAPE*>( item );
153 
154  if( shape->GetShape() == PCB_SHAPE_TYPE::RECT )
155  {
156  // A single rectangle for the board would make the RTree useless, so
157  // convert to 4 edges
158  edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
159  edges.back()->SetShape( PCB_SHAPE_TYPE::SEGMENT );
160  edges.back()->SetEndX( shape->GetStartX() );
161  edges.back()->SetWidth( 0 );
162  edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
163  edges.back()->SetShape( PCB_SHAPE_TYPE::SEGMENT );
164  edges.back()->SetEndY( shape->GetStartY() );
165  edges.back()->SetWidth( 0 );
166  edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
167  edges.back()->SetShape( PCB_SHAPE_TYPE::SEGMENT );
168  edges.back()->SetStartX( shape->GetEndX() );
169  edges.back()->SetWidth( 0 );
170  edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
171  edges.back()->SetShape( PCB_SHAPE_TYPE::SEGMENT );
172  edges.back()->SetStartY( shape->GetEndY() );
173  edges.back()->SetWidth( 0 );
174  return true;
175  }
176  else if( shape->GetShape() == PCB_SHAPE_TYPE::POLYGON )
177  {
178  // Same for polygons
179  SHAPE_LINE_CHAIN poly = shape->GetPolyShape().Outline( 0 );
180 
181  for( size_t ii = 0; ii < poly.GetSegmentCount(); ++ii )
182  {
183  SEG seg = poly.CSegment( ii );
184  edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
185  edges.back()->SetShape( PCB_SHAPE_TYPE::SEGMENT );
186  edges.back()->SetStart((wxPoint) seg.A );
187  edges.back()->SetEnd((wxPoint) seg.B );
188  edges.back()->SetWidth( 0 );
189  }
190  }
191 
192  edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
193  edges.back()->SetWidth( 0 );
194  return true;
195  };
196 
197  auto queryBoardGeometryItems =
198  [&]( BOARD_ITEM *item ) -> bool
199  {
200  if( !isInvisibleText( item ) )
201  boardItems.push_back( item );
202 
203  return true;
204  };
205 
207  queryBoardOutlineItems );
208  forEachGeometryItem( s_allBasicItemsButZones, LSET::AllCuMask(), queryBoardGeometryItems );
209 
210  for( const std::unique_ptr<PCB_SHAPE>& edge : edges )
211  {
212  for( PCB_LAYER_ID layer : { Edge_Cuts, Margin } )
213  {
214  if( edge->IsOnLayer( layer ) )
215  edgesTree.Insert( edge.get(), layer, m_largestClearance );
216  }
217  }
218 
219  wxString val;
220  wxGetEnv( "WXTRACE", &val );
221 
222  drc_dbg( 2, "outline: %d items, board: %d items\n",
223  (int) edges.size(), (int) boardItems.size() );
224 
225  // This is the number of tests between 2 calls to the progress bar
226  const int delta = 50;
227  int ii = 0;
228 
229  for( BOARD_ITEM* item : boardItems )
230  {
233 
234  if( !testCopper && !testSilk )
235  break;
236 
237  if( !reportProgress( ii++, boardItems.size(), delta ) )
238  return false; // DRC cancelled
239 
240  const std::shared_ptr<SHAPE>& itemShape = item->GetEffectiveShape();
241 
242  for( PCB_LAYER_ID testLayer : { Edge_Cuts, Margin } )
243  {
244  if( testCopper && item->IsOnCopperLayer() )
245  {
246  edgesTree.QueryColliding( item, UNDEFINED_LAYER, testLayer, nullptr,
247  [&]( BOARD_ITEM* edge ) -> bool
248  {
249  return testAgainstEdge( item, itemShape.get(), edge,
252  },
254  }
255 
256  if( testSilk && ( item->GetLayer() == F_SilkS || item->GetLayer() == B_SilkS ) )
257  {
258  edgesTree.QueryColliding( item, UNDEFINED_LAYER, testLayer, nullptr,
259  [&]( BOARD_ITEM* edge ) -> bool
260  {
261  return testAgainstEdge( item, itemShape.get(), edge,
264  },
266  }
267  }
268  }
269 
271 
272  return true;
273 }
274 
275 
277 {
278  return 1;
279 }
280 
281 
283 {
285 }
286 
287 
288 namespace detail
289 {
291 }
static LSET AllCuMask(int aCuLayerCount=MAX_CU_LAYERS)
Return a mask holding the requested number of Cu PCB_LAYER_IDs.
Definition: lset.cpp:750
wxString MessageTextFromValue(EDA_UNITS aUnits, int aValue, bool aAddUnitLabel, EDA_DATA_TYPE aType)
Convert a value to a string using double notation.
Definition: base_units.cpp:103
virtual size_t GetSegmentCount() const override
static std::shared_ptr< DRC_ITEM > Create(int aErrorCode)
Constructs a DRC_ITEM for the given error code.
Definition: drc_item.cpp:253
SHAPE_POLY_SET & GetPolyShape()
Definition: pcb_shape.h:239
bool isInvisibleText(const BOARD_ITEM *aItem) const
int GetEndY()
Definition: pcb_shape.h:135
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition: board_item.h:80
virtual const wxString GetName() const override
PCB_SHAPE_TYPE GetShape() const
Definition: pcb_shape.h:110
virtual EDA_ITEM * Clone() const override
Create a duplicate of this item with linked list members set to NULL.
Definition: pcb_shape.cpp:972
static DRC_REGISTER_TEST_PROVIDER< DRC_TEST_PROVIDER_ANNULUS > dummy
virtual std::set< DRC_CONSTRAINT_T > GetConstraintTypes() const override
bool IsErrorLimitExceeded(int error_code)
virtual bool reportProgress(int aCount, int aSize, int aDelta)
class FP_SHAPE, a footprint edge
Definition: typeinfo.h:93
T Min() const
Definition: minoptmax.h:33
PCB_DRC_CODE
Definition: drc_item.h:34
virtual void reportRuleStatistics()
virtual bool Collide(const VECTOR2I &aP, int aClearance=0, int *aActual=nullptr, VECTOR2I *aLocation=nullptr) const
Check if the boundary of shape (this) lies closer to the point aP than aClearance,...
Definition: shape.h:165
polygon (not yet used for tracks, but could be in microwave apps)
DRC_CONSTRAINT_T
Definition: drc_rule.h:41
PCB_LAYER_ID
A quick note on layer IDs:
LSET is a set of PCB_LAYER_IDs.
bool QueryWorstConstraint(DRC_CONSTRAINT_T aRuleId, DRC_CONSTRAINT &aConstraint)
bool testAgainstEdge(BOARD_ITEM *item, SHAPE *itemShape, BOARD_ITEM *other, DRC_CONSTRAINT_T aConstraintType, PCB_DRC_CODE aErrorCode)
BOARD * GetBoard() const
Definition: drc_engine.h:87
virtual bool reportPhase(const wxString &aStageName)
SHAPE_LINE_CHAIN & Outline(int aIndex)
segment with non rounded ends
virtual const wxString GetDescription() const override
int GetEndX()
Definition: pcb_shape.h:136
#define _(s)
An abstract shape on 2D plane.
Definition: shape.h:116
EDA_UNITS userUnits() const
DRC_CONSTRAINT EvalRules(DRC_CONSTRAINT_T aConstraintId, const BOARD_ITEM *a, const BOARD_ITEM *b, PCB_LAYER_ID aLayer, REPORTER *aReporter=nullptr)
Definition: drc_engine.cpp:765
const KIID m_Uuid
Definition: eda_item.h:475
Definition: seg.h:40
virtual void reportViolation(std::shared_ptr< DRC_ITEM > &item, wxPoint aMarkerPos)
int forEachGeometryItem(const std::vector< KICAD_T > &aTypes, LSET aLayers, const std::function< bool(BOARD_ITEM *)> &aFunc)
virtual bool Run() override
Runs this provider against the given PCB with configured options (if any).
const MINOPTMAX< int > & GetValue() const
Definition: drc_rule.h:122
const SEG CSegment(int aIndex) const
Function CSegment()
SHAPE_LINE_CHAIN.
static std::vector< KICAD_T > s_allBasicItemsButZones
DRC_ENGINE * m_drcEngine
VECTOR2I A
Definition: seg.h:48
usual segment : line with rounded ends
The common library.
void Insert(BOARD_ITEM *aItem, PCB_LAYER_ID aLayer, int aWorstClearance=0)
Function Insert() Inserts an item into the tree on a particular layer with an optional worst clearanc...
Definition: drc_rtree.h:88
virtual std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER) const
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
Definition: board_item.cpp:157
#define drc_dbg(level, fmt,...)
Definition: drc_engine.h:57
DRC_RTREE - Implements an R-tree for fast spatial and layer indexing of connectable items.
Definition: drc_rtree.h:45
class PCB_SHAPE, a segment not on copper layers
Definition: typeinfo.h:90
int GetStartY()
Definition: pcb_shape.h:125
virtual PCB_LAYER_ID GetLayer() const
Return the primary layer this item is on.
Definition: board_item.h:171
virtual void reportAux(wxString fmt,...)
int GetStartX()
Definition: pcb_shape.h:126
int QueryColliding(BOARD_ITEM *aRefItem, PCB_LAYER_ID aRefLayer, PCB_LAYER_ID aTargetLayer, std::function< bool(BOARD_ITEM *)> aFilter=nullptr, std::function< bool(BOARD_ITEM *)> aVisitor=nullptr, int aClearance=0) const
This is a fast test which essentially does bounding-box overlap given a worst-case clearance.
Definition: drc_rtree.h:168
VECTOR2I B
Definition: seg.h:49