KiCad PCB EDA Suite
Loading...
Searching...
No Matches
drc_test_provider_edge_clearance.cpp
Go to the documentation of this file.
1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright The KiCad Developers.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, you may find one here:
18 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
19 * or you may search the http://www.gnu.org website for the version 2 license,
20 * or you may write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
22 */
23
24#include <common.h>
25#include <pcb_shape.h>
26#include <footprint.h>
27#include <geometry/seg.h>
29#include <drc/drc_engine.h>
30#include <drc/drc_item.h>
31#include <drc/drc_rule.h>
33#include "drc_rtree.h"
34
35/*
36 Board edge clearance test. Checks all items for their mechanical clearances against the board
37 edge.
38 Errors generated:
39 - DRCE_EDGE_CLEARANCE
40 - DRCE_SILK_EDGE_CLEARANCE
41*/
42
44{
45public:
49 {}
50
52
53 virtual bool Run() override;
54
55 virtual const wxString GetName() const override { return wxT( "edge_clearance" ); }
56
57private:
58 bool testAgainstEdge( BOARD_ITEM* item, SHAPE* itemShape, BOARD_ITEM* other,
59 DRC_CONSTRAINT_T aConstraintType, PCB_DRC_CODE aErrorCode );
60
61private:
62 std::vector<PAD*> m_castellatedPads;
64};
65
66
68 BOARD_ITEM* edge,
69 DRC_CONSTRAINT_T aConstraintType,
70 PCB_DRC_CODE aErrorCode )
71{
72 std::shared_ptr<SHAPE> shape;
73
74 if( edge->Type() == PCB_PAD_T )
75 shape = edge->GetEffectiveHoleShape();
76 else
77 shape = edge->GetEffectiveShape( Edge_Cuts );
78
79 auto constraint = m_drcEngine->EvalRules( aConstraintType, edge, item, UNDEFINED_LAYER );
80 int minClearance = constraint.GetValue().Min();
81 int actual;
82 VECTOR2I pos;
83
84 if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && minClearance >= 0 )
85 {
86 if( itemShape->Collide( shape.get(), minClearance, &actual, &pos ) )
87 {
88 // Exact clearance is allowed
89 if( minClearance > 0 && actual == minClearance )
90 return true;
91
92 if( item->Type() == PCB_TRACE_T || item->Type() == PCB_ARC_T )
93 {
94 // Edge collisions are allowed inside the holes of castellated pads
95 for( PAD* castellatedPad : m_castellatedPads )
96 {
97 if( castellatedPad->GetEffectiveHoleShape()->Collide( pos ) )
98 return true;
99 }
100 }
101
102 std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( aErrorCode );
103
104 // Only report clearance info if there is any; otherwise it's just a straight collision
105 if( minClearance > 0 )
106 {
107 wxString msg = formatMsg( _( "(%s clearance %s; actual %s)" ),
108 constraint.GetName(),
109 minClearance,
110 actual );
111
112 drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
113 }
114
115 drce->SetItems( edge->m_Uuid, item->m_Uuid );
116 drce->SetViolatingRule( constraint.GetParentRule() );
117
118 reportViolation( drce, pos, Edge_Cuts );
119
120 if( item->Type() == PCB_TRACE_T || item->Type() == PCB_ARC_T )
122 else
123 return false; // don't report violations with multiple edges; one is enough
124 }
125 }
126
127 return true;
128}
129
130
132{
134 {
135 if( !reportPhase( _( "Checking copper to board edge clearances..." ) ) )
136 return false; // DRC cancelled
137 }
139 {
140 if( !reportPhase( _( "Checking silk to board edge clearances..." ) ) )
141 return false; // DRC cancelled
142 }
143 else
144 {
145 REPORT_AUX( wxT( "Edge clearance violations ignored. Tests not run." ) );
146 return true; // continue with other tests
147 }
148
150 m_castellatedPads.clear();
151
152 DRC_CONSTRAINT worstClearanceConstraint;
153
154 if( m_drcEngine->QueryWorstConstraint( EDGE_CLEARANCE_CONSTRAINT, worstClearanceConstraint ) )
155 m_largestEdgeClearance = worstClearanceConstraint.GetValue().Min();
156
157 /*
158 * Build an RTree of the various edges (including NPTH holes) and margins found on the board.
159 */
160 std::vector<std::unique_ptr<PCB_SHAPE>> edges;
161 DRC_RTREE edgesTree;
162
164 [&]( BOARD_ITEM *item ) -> bool
165 {
166 PCB_SHAPE* shape = static_cast<PCB_SHAPE*>( item );
167 STROKE_PARAMS stroke = shape->GetStroke();
168
169 if( item->IsOnLayer( Edge_Cuts ) )
170 stroke.SetWidth( 0 );
171
172 if( shape->GetShape() == SHAPE_T::RECTANGLE && !shape->IsSolidFill() )
173 {
174 // A single rectangle for the board would make the RTree useless, so convert
175 // to 4 edges
176 edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
177 edges.back()->SetShape( SHAPE_T::SEGMENT );
178 edges.back()->SetEndX( shape->GetStartX() );
179 edges.back()->SetStroke( stroke );
180 edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
181 edges.back()->SetShape( SHAPE_T::SEGMENT );
182 edges.back()->SetEndY( shape->GetStartY() );
183 edges.back()->SetStroke( stroke );
184 edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
185 edges.back()->SetShape( SHAPE_T::SEGMENT );
186 edges.back()->SetStartX( shape->GetEndX() );
187 edges.back()->SetStroke( stroke );
188 edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
189 edges.back()->SetShape( SHAPE_T::SEGMENT );
190 edges.back()->SetStartY( shape->GetEndY() );
191 edges.back()->SetStroke( stroke );
192 }
193 else if( shape->GetShape() == SHAPE_T::POLY && !shape->IsSolidFill() )
194 {
195 // A single polygon for the board would make the RTree useless, so convert
196 // to n edges.
197 SHAPE_LINE_CHAIN poly = shape->GetPolyShape().Outline( 0 );
198
199 for( size_t ii = 0; ii < poly.GetSegmentCount(); ++ii )
200 {
201 SEG seg = poly.CSegment( ii );
202 edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
203 edges.back()->SetShape( SHAPE_T::SEGMENT );
204 edges.back()->SetStart( seg.A );
205 edges.back()->SetEnd( seg.B );
206 edges.back()->SetStroke( stroke );
207 }
208 }
209 else
210 {
211 edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
212 edges.back()->SetStroke( stroke );
213 }
214
215 return true;
216 } );
217
218 for( const std::unique_ptr<PCB_SHAPE>& edge : edges )
219 {
220 for( PCB_LAYER_ID layer : { Edge_Cuts, Margin } )
221 {
222 if( edge->IsOnLayer( layer ) )
223 edgesTree.Insert( edge.get(), layer, m_largestEdgeClearance );
224 }
225 }
226
227 for( FOOTPRINT* footprint : m_board->Footprints() )
228 {
229 for( PAD* pad : footprint->Pads() )
230 {
231 if( pad->GetAttribute() == PAD_ATTRIB::NPTH && pad->HasHole() )
232 {
233 // edge-clearances are for milling tolerances (drilling tolerances are handled
234 // by hole-clearances)
235 if( pad->GetDrillSizeX() != pad->GetDrillSizeY() )
237 }
238
239 if( pad->GetProperty() == PAD_PROP::CASTELLATED )
240 m_castellatedPads.push_back( pad );
241 }
242 }
243
244 /*
245 * Test copper and silk items against the set of edges.
246 */
247 const int progressDelta = 200;
248 int count = 0;
249 int ii = 0;
250
252 [&]( BOARD_ITEM *item ) -> bool
253 {
254 count++;
255 return true;
256 } );
257
259 [&]( BOARD_ITEM *item ) -> bool
260 {
263
264 if( !testCopper && !testSilk )
265 return false; // All limits exceeded; we're done
266
267 if( !reportProgress( ii++, count, progressDelta ) )
268 return false; // DRC cancelled; we're done
269
270 if( isInvisibleText( item ) )
271 return true; // Continue with other items
272
273 if( item->Type() == PCB_PAD_T )
274 {
275 PAD* pad = static_cast<PAD*>( item );
276
277 if( pad->GetProperty() == PAD_PROP::CASTELLATED || pad->GetAttribute() == PAD_ATTRIB::CONN )
278 return true; // Continue with other items
279 }
280
281 std::vector<PCB_LAYER_ID> layersToTest;
282
283 switch( item->Type() )
284 {
285 case PCB_PAD_T:
286 layersToTest = static_cast<PAD*>( item )->Padstack().UniqueLayers();
287 break;
288
289 case PCB_VIA_T:
290 layersToTest = static_cast<PCB_VIA*>( item )->Padstack().UniqueLayers();
291 break;
292
293 default:
294 layersToTest = { UNDEFINED_LAYER };
295 }
296
297 for( PCB_LAYER_ID shapeLayer : layersToTest )
298 {
299 const std::shared_ptr<SHAPE>& itemShape = item->GetEffectiveShape( shapeLayer );
300
301 for( PCB_LAYER_ID testLayer : { Edge_Cuts, Margin } )
302 {
303 if( testCopper && item->IsOnCopperLayer() )
304 {
305 edgesTree.QueryColliding( item, shapeLayer, testLayer, nullptr,
306 [&]( BOARD_ITEM* edge ) -> bool
307 {
308 return testAgainstEdge( item, itemShape.get(), edge,
309 EDGE_CLEARANCE_CONSTRAINT,
310 DRCE_EDGE_CLEARANCE );
311 },
313 }
314
315 if( testSilk && ( item->IsOnLayer( F_SilkS ) || item->IsOnLayer( B_SilkS ) ) )
316 {
317 if( edgesTree.QueryColliding( item, shapeLayer, testLayer, nullptr,
318 [&]( BOARD_ITEM* edge ) -> bool
319 {
320 return testAgainstEdge( item, itemShape.get(), edge,
321 SILK_CLEARANCE_CONSTRAINT,
322 DRCE_SILK_EDGE_CLEARANCE );
323 },
325 {
326 // violations reported during QueryColliding
327 }
328 else
329 {
330 // TODO: check postion being outside board boundary
331 }
332 }
333 }
334 }
335
336 return true;
337 } );
338
339 return !m_drcEngine->IsCancelled();
340}
341
342
343namespace detail
344{
346}
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition: board_item.h:79
virtual bool IsOnLayer(PCB_LAYER_ID aLayer) const
Test to see if this object is on the given layer.
Definition: board_item.h:314
virtual std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
Definition: board_item.cpp:326
virtual bool IsOnCopperLayer() const
Definition: board_item.h:151
virtual std::shared_ptr< SHAPE_SEGMENT > GetEffectiveHoleShape() const
Definition: board_item.cpp:336
const FOOTPRINTS & Footprints() const
Definition: board.h:358
const MINOPTMAX< int > & GetValue() const
Definition: drc_rule.h:160
BOARD * GetBoard() const
Definition: drc_engine.h:100
bool GetReportAllTrackErrors() const
Definition: drc_engine.h:174
bool IsErrorLimitExceeded(int error_code)
DRC_CONSTRAINT EvalRules(DRC_CONSTRAINT_T aConstraintType, const BOARD_ITEM *a, const BOARD_ITEM *b, PCB_LAYER_ID aLayer, REPORTER *aReporter=nullptr)
Definition: drc_engine.cpp:706
bool QueryWorstConstraint(DRC_CONSTRAINT_T aRuleId, DRC_CONSTRAINT &aConstraint)
static std::shared_ptr< DRC_ITEM > Create(int aErrorCode)
Constructs a DRC_ITEM for the given error code.
Definition: drc_item.cpp:393
Implement an R-tree for fast spatial and layer indexing of connectable items.
Definition: drc_rtree.h:48
void Insert(BOARD_ITEM *aItem, PCB_LAYER_ID aLayer, int aWorstClearance=0)
Insert an item into the tree on a particular layer with an optional worst clearance.
Definition: drc_rtree.h:104
int QueryColliding(BOARD_ITEM *aRefItem, PCB_LAYER_ID aRefLayer, PCB_LAYER_ID aTargetLayer, std::function< bool(BOARD_ITEM *)> aFilter=nullptr, std::function< bool(BOARD_ITEM *)> aVisitor=nullptr, int aClearance=0) const
This is a fast test which essentially does bounding-box overlap given a worst-case clearance.
Definition: drc_rtree.h:214
virtual bool Run() override
Run this provider against the given PCB with configured options (if any).
virtual ~DRC_TEST_PROVIDER_EDGE_CLEARANCE()=default
virtual const wxString GetName() const override
bool testAgainstEdge(BOARD_ITEM *item, SHAPE *itemShape, BOARD_ITEM *other, DRC_CONSTRAINT_T aConstraintType, PCB_DRC_CODE aErrorCode)
static std::vector< KICAD_T > s_allBasicItemsButZones
virtual bool reportPhase(const wxString &aStageName)
virtual void reportViolation(std::shared_ptr< DRC_ITEM > &item, const VECTOR2I &aMarkerPos, int aMarkerLayer, DRC_CUSTOM_MARKER_HANDLER *aCustomHandler=nullptr)
int forEachGeometryItem(const std::vector< KICAD_T > &aTypes, const LSET &aLayers, const std::function< bool(BOARD_ITEM *)> &aFunc)
DRC_ENGINE * m_drcEngine
bool isInvisibleText(const BOARD_ITEM *aItem) const
wxString formatMsg(const wxString &aFormatString, const wxString &aSource, double aConstraint, double aActual, EDA_DATA_TYPE aDataType=EDA_DATA_TYPE::DISTANCE)
virtual bool reportProgress(size_t aCount, size_t aSize, size_t aDelta=1)
const KIID m_Uuid
Definition: eda_item.h:516
KICAD_T Type() const
Returns the type of object.
Definition: eda_item.h:110
int GetStartY() const
Definition: eda_shape.h:174
int GetEndX() const
Definition: eda_shape.h:217
SHAPE_POLY_SET & GetPolyShape()
Definition: eda_shape.h:337
SHAPE_T GetShape() const
Definition: eda_shape.h:168
int GetEndY() const
Definition: eda_shape.h:216
bool IsSolidFill() const
Definition: eda_shape.h:117
int GetStartX() const
Definition: eda_shape.h:175
LSET is a set of PCB_LAYER_IDs.
Definition: lset.h:37
static const LSET & AllLayersMask()
Definition: lset.cpp:624
T Min() const
Definition: minoptmax.h:33
Definition: pad.h:54
STROKE_PARAMS GetStroke() const override
Definition: pcb_shape.h:91
EDA_ITEM * Clone() const override
Create a duplicate of this item with linked list members set to NULL.
Definition: pcb_shape.cpp:758
Definition: seg.h:42
VECTOR2I A
Definition: seg.h:49
VECTOR2I B
Definition: seg.h:50
Represent a polyline containing arcs as well as line segments: A chain of connected line and/or arc s...
virtual size_t GetSegmentCount() const override
const SEG CSegment(int aIndex) const
Return a constant copy of the aIndex segment in the line chain.
SHAPE_LINE_CHAIN & Outline(int aIndex)
Return the reference to aIndex-th outline in the set.
An abstract shape on 2D plane.
Definition: shape.h:126
virtual bool Collide(const VECTOR2I &aP, int aClearance=0, int *aActual=nullptr, VECTOR2I *aLocation=nullptr) const
Check if the boundary of shape (this) lies closer to the point aP than aClearance,...
Definition: shape.h:181
Simple container to manage line stroke parameters.
Definition: stroke_params.h:94
void SetWidth(int aWidth)
The common library.
PCB_DRC_CODE
Definition: drc_item.h:37
@ DRCE_SILK_EDGE_CLEARANCE
Definition: drc_item.h:98
@ DRCE_EDGE_CLEARANCE
Definition: drc_item.h:46
DRC_CONSTRAINT_T
Definition: drc_rule.h:47
@ EDGE_CLEARANCE_CONSTRAINT
Definition: drc_rule.h:53
#define REPORT_AUX(s)
#define _(s)
PCB_LAYER_ID
A quick note on layer IDs:
Definition: layer_ids.h:60
@ Edge_Cuts
Definition: layer_ids.h:112
@ Margin
Definition: layer_ids.h:113
@ F_SilkS
Definition: layer_ids.h:100
@ UNDEFINED_LAYER
Definition: layer_ids.h:61
@ B_SilkS
Definition: layer_ids.h:101
static DRC_REGISTER_TEST_PROVIDER< DRC_TEST_PROVIDER_ANNULAR_WIDTH > dummy
@ RPT_SEVERITY_IGNORE
int actual
@ PCB_SHAPE_T
class PCB_SHAPE, a segment not on copper layers
Definition: typeinfo.h:88
@ PCB_PAD_T
class PAD, a pad in a footprint
Definition: typeinfo.h:87
@ PCB_ARC_T
class PCB_ARC, an arc track segment on a copper layer
Definition: typeinfo.h:98
@ PCB_TRACE_T
class PCB_TRACK, a track segment (segment on a copper layer)
Definition: typeinfo.h:96