board.h

Go to the documentation of this file.

/*
 * This program source code file is part of KiCad, a free EDA CAD application.
 *
 * Copyright (C) 2007 Jean-Pierre Charras, [email protected]
 * Copyright (C) 1992-2023 KiCad Developers, see AUTHORS.txt for contributors.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, you may find one here:
 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
 * or you may search the http://www.gnu.org website for the version 2 license,
 * or you may write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
 */
 
#ifndef CLASS_BOARD_H_
#define CLASS_BOARD_H_
 
#include <board_item_container.h>
#include <board_stackup_manager/board_stackup.h>
#include <embedded_files.h>
#include <common.h> // Needed for stl hash extensions
#include <convert_shape_list_to_polygon.h> // for OUTLINE_ERROR_HANDLER
#include <hash.h>
#include <layer_ids.h>
#include <lset.h>
#include <netinfo.h>
#include <pcb_item_containers.h>
#include <pcb_plot_params.h>
#include <title_block.h>
#include <tools/pcb_selection.h>
#include <shared_mutex>
#include <list>
 
class BOARD_DESIGN_SETTINGS;
class BOARD_CONNECTED_ITEM;
class BOARD_COMMIT;
class DRC_RTREE;
class PCB_BASE_FRAME;
class PCB_EDIT_FRAME;
class PICKED_ITEMS_LIST;
class BOARD;
class FOOTPRINT;
class ZONE;
class PCB_TRACK;
class PAD;
class PCB_GROUP;
class PCB_GENERATOR;
class PCB_MARKER;
class MSG_PANEL_ITEM;
class NETLIST;
class REPORTER;
class SHAPE_POLY_SET;
class CONNECTIVITY_DATA;
class COMPONENT;
class PROJECT;
class PROGRESS_REPORTER;
struct ISOLATED_ISLANDS;
 
// The default value for m_outlinesChainingEpsilon to convert a board outlines to polygons
// It is the max dist between 2 end points to see them connected
#define DEFAULT_CHAINING_EPSILON_MM 0.01
 
// Forward declare endpoint from class_track.h
enum ENDPOINT_T : int;
 
 
struct PTR_PTR_CACHE_KEY
{
 BOARD_ITEM* A;
 BOARD_ITEM* B;
 
 bool operator==(const PTR_PTR_CACHE_KEY& other) const
 {
 return A == other.A && B == other.B;
 }
};
 
struct PTR_LAYER_CACHE_KEY
{
 BOARD_ITEM* A;
 PCB_LAYER_ID Layer;
 
 bool operator==(const PTR_LAYER_CACHE_KEY& other) const
 {
 return A == other.A && Layer == other.Layer;
 }
};
 
struct PTR_PTR_LAYER_CACHE_KEY
{
 BOARD_ITEM* A;
 BOARD_ITEM* B;
 PCB_LAYER_ID Layer;
 
 bool operator==(const PTR_PTR_LAYER_CACHE_KEY& other) const
 {
 return A == other.A && B == other.B && Layer == other.Layer;
 }
};
 
namespace std
{
 template <>
 struct hash<PTR_PTR_CACHE_KEY>
 {
 std::size_t operator()( const PTR_PTR_CACHE_KEY& k ) const
 {
 std::size_t seed = 0xa82de1c0;
 hash_combine( seed, k.A, k.B );
 return seed;
 }
 };
 
 template <>
 struct hash<PTR_LAYER_CACHE_KEY>
 {
 std::size_t operator()( const PTR_LAYER_CACHE_KEY& k ) const
 {
 std::size_t seed = 0xa82de1c0;
 hash_combine( seed, k.A, k.Layer );
 return seed;
 }
 };
 
 template <>
 struct hash<PTR_PTR_LAYER_CACHE_KEY>
 {
 std::size_t operator()( const PTR_PTR_LAYER_CACHE_KEY& k ) const
 {
 std::size_t seed = 0xa82de1c0;
 hash_combine( seed, k.A, k.B, k.Layer );
 return seed;
 }
 };
}
 
 
enum LAYER_T
{
 LT_UNDEFINED = -1,
 LT_SIGNAL,
 LT_POWER,
 LT_MIXED,
 LT_JUMPER,
 LT_AUX,
 LT_FRONT,
 LT_BACK
};
 
 
struct LAYER
{
 LAYER()
 {
 clear();
 }
 
 void clear()
 {
 m_type = LT_SIGNAL;
 m_visible = true;
 m_number = 0;
 m_name.clear();
 m_userName.clear();
 m_opposite = m_number;
 }
 
 /*
 LAYER( const wxString& aName = wxEmptyString,
 LAYER_T aType = LT_SIGNAL, bool aVisible = true, int aNumber = -1 ) :
 m_name( aName ),
 m_type( aType ),
 m_visible( aVisible ),
 m_number( aNumber )
 {
 }
 */
 
 wxString m_name; 
 wxString m_userName; 
 LAYER_T m_type; 
 bool m_visible;
 int m_number; 
 int m_opposite; 
 
 static const char* ShowType( LAYER_T aType );
 
 static LAYER_T ParseType( const char* aType );
};
 
 
// Helper class to handle high light nets
class HIGH_LIGHT_INFO
{
protected:
 std::set<int> m_netCodes; // net(s) selected for highlight (-1 when no net selected )
 bool m_highLightOn; // highlight active
 
 void Clear()
 {
 m_netCodes.clear();
 m_highLightOn = false;
 }
 
 HIGH_LIGHT_INFO()
 {
 Clear();
 }
 
private:
 friend class BOARD;
};
 
class BOARD;
 
class BOARD_LISTENER
{
public:
 virtual ~BOARD_LISTENER() { }
 virtual void OnBoardItemAdded( BOARD& aBoard, BOARD_ITEM* aBoardItem ) { }
 virtual void OnBoardItemsAdded( BOARD& aBoard, std::vector<BOARD_ITEM*>& aBoardItem ) { }
 virtual void OnBoardItemRemoved( BOARD& aBoard, BOARD_ITEM* aBoardItem ) { }
 virtual void OnBoardItemsRemoved( BOARD& aBoard, std::vector<BOARD_ITEM*>& aBoardItem ) { }
 virtual void OnBoardNetSettingsChanged( BOARD& aBoard ) { }
 virtual void OnBoardItemChanged( BOARD& aBoard, BOARD_ITEM* aBoardItem ) { }
 virtual void OnBoardItemsChanged( BOARD& aBoard, std::vector<BOARD_ITEM*>& aBoardItem ) { }
 virtual void OnBoardHighlightNetChanged( BOARD& aBoard ) { }
 virtual void OnBoardRatsnestChanged( BOARD& aBoard ) { }
 virtual void OnBoardCompositeUpdate( BOARD& aBoard, std::vector<BOARD_ITEM*>& aAddedItems,
 std::vector<BOARD_ITEM*>& aRemovedItems,
 std::vector<BOARD_ITEM*>& aDeletedItems )
 {
 }
};
 
typedef std::set<BOARD_ITEM*, CompareByUuid> BOARD_ITEM_SET;
 
enum class BOARD_USE
{
 NORMAL, // A normal board
 FPHOLDER // A board that holds a single footprint
};
 
 
class BOARD : public BOARD_ITEM_CONTAINER, public EMBEDDED_FILES
{
public:
 static inline bool ClassOf( const EDA_ITEM* aItem )
 {
 return aItem && PCB_T == aItem->Type();
 }
 
 void SetBoardUse( BOARD_USE aUse ) { m_boardUse = aUse; }
 
 BOARD_USE GetBoardUse() const { return m_boardUse; }
 
 void IncrementTimeStamp();
 
 int GetTimeStamp() const { return m_timeStamp; }
 
 bool IsFootprintHolder() const
 {
 return m_boardUse == BOARD_USE::FPHOLDER;
 }
 
 void SetFileName( const wxString& aFileName ) { m_fileName = aFileName; }
 
 const wxString &GetFileName() const { return m_fileName; }
 
 const TRACKS& Tracks() const { return m_tracks; }
 
 const FOOTPRINTS& Footprints() const { return m_footprints; }
 
 const DRAWINGS& Drawings() const { return m_drawings; }
 
 const ZONES& Zones() const { return m_zones; }
 
 const GENERATORS& Generators() const { return m_generators; }
 
 const MARKERS& Markers() const { return m_markers; }
 
 // SWIG requires non-const accessors for some reason to make the custom iterators in board.i
 // work. It would be good to remove this if we can figure out how to fix that.
#ifdef SWIG
 DRAWINGS& Drawings() { return m_drawings; }
 TRACKS& Tracks() { return m_tracks; }
#endif
 
 const BOARD_ITEM_SET GetItemSet();
 
 const GROUPS& Groups() const { return m_groups; }
 
 const std::vector<BOARD_CONNECTED_ITEM*> AllConnectedItems();
 
 const std::map<wxString, wxString>& GetProperties() const { return m_properties; }
 void SetProperties( const std::map<wxString, wxString>& aProps ) { m_properties = aProps; }
 
 void GetContextualTextVars( wxArrayString* aVars ) const;
 bool ResolveTextVar( wxString* token, int aDepth ) const;
 
 LSET m_LegacyVisibleLayers;
 GAL_SET m_LegacyVisibleItems;
 
 bool m_LegacyDesignSettingsLoaded;
 bool m_LegacyCopperEdgeClearanceLoaded;
 
 bool m_LegacyNetclassesLoaded;
 
 BOARD();
 ~BOARD();
 
 VECTOR2I GetPosition() const override;
 void SetPosition( const VECTOR2I& aPos ) override;
 const VECTOR2I GetFocusPosition() const override { return GetBoundingBox().GetCenter(); }
 
 bool IsEmpty() const
 {
 return m_drawings.empty() && m_footprints.empty() && m_tracks.empty() && m_zones.empty();
 }
 
 void Move( const VECTOR2I& aMoveVector ) override;
 
 void SetFileFormatVersionAtLoad( int aVersion ) { m_fileFormatVersionAtLoad = aVersion; }
 int GetFileFormatVersionAtLoad() const { return m_fileFormatVersionAtLoad; }
 
 void SetGenerator( const wxString& aGenerator ) { m_generator = aGenerator; }
 const wxString& GetGenerator() const { return m_generator; }
 
 void Add( BOARD_ITEM* aItem, ADD_MODE aMode = ADD_MODE::INSERT,
 bool aSkipConnectivity = false ) override;
 
 void Remove( BOARD_ITEM* aBoardItem, REMOVE_MODE aMode = REMOVE_MODE::NORMAL ) override;
 
 void RemoveAll( std::initializer_list<KICAD_T> aTypes = { PCB_NETINFO_T, PCB_MARKER_T,
 PCB_GROUP_T, PCB_ZONE_T,
 PCB_GENERATOR_T, PCB_FOOTPRINT_T,
 PCB_TRACE_T, PCB_SHAPE_T } );
 
 void FinalizeBulkAdd( std::vector<BOARD_ITEM*>& aNewItems );
 
 void FinalizeBulkRemove( std::vector<BOARD_ITEM*>& aRemovedItems );
 
 void FixupEmbeddedData();
 
 void CacheTriangulation( PROGRESS_REPORTER* aReporter = nullptr,
 const std::vector<ZONE*>& aZones = {} );
 
 FOOTPRINT* GetFirstFootprint() const
 {
 return m_footprints.empty() ? nullptr : m_footprints.front();
 }
 
 void DeleteAllFootprints();
 
 BOARD_ITEM* GetItem( const KIID& aID ) const;
 
 void FillItemMap( std::map<KIID, EDA_ITEM*>& aMap );
 
 wxString ConvertCrossReferencesToKIIDs( const wxString& aSource ) const;
 wxString ConvertKIIDsToCrossReferences( const wxString& aSource ) const;
 
 std::shared_ptr<CONNECTIVITY_DATA> GetConnectivity() const { return m_connectivity; }
 
 bool BuildConnectivity( PROGRESS_REPORTER* aReporter = nullptr );
 
 void DeleteMARKERs();
 
 void DeleteMARKERs( bool aWarningsAndErrors, bool aExclusions );
 
 PROJECT* GetProject() const { return m_project; }
 
 void SetProject( PROJECT* aProject, bool aReferenceOnly = false );
 
 void ClearProject();
 
 std::vector<PCB_MARKER*> ResolveDRCExclusions( bool aCreateMarkers );
 
 void RecordDRCExclusions();
 
 void UpdateRatsnestExclusions();
 
 void ResetNetHighLight();
 
 const std::set<int>& GetHighLightNetCodes() const
 {
 return m_highLight.m_netCodes;
 }
 
 void SetHighLightNet( int aNetCode, bool aMulti = false );
 
 bool IsHighLightNetON() const { return m_highLight.m_highLightOn; }
 
 void HighLightON( bool aValue = true );
 
 void HighLightOFF()
 {
 HighLightON( false );
 }
 
 int GetCopperLayerCount() const;
 void SetCopperLayerCount( int aCount );
 
 PCB_LAYER_ID FlipLayer( PCB_LAYER_ID aLayer ) const;
 
 int LayerDepth( PCB_LAYER_ID aStartLayer, PCB_LAYER_ID aEndLayer ) const;
 
 LSET GetEnabledLayers() const;
 
 void SetEnabledLayers( LSET aLayerMask );
 
 bool IsLayerEnabled( PCB_LAYER_ID aLayer ) const;
 
 bool IsLayerVisible( PCB_LAYER_ID aLayer ) const;
 
 LSET GetVisibleLayers() const;
 
 void SetVisibleLayers( LSET aLayerMask );
 
 // these 2 functions are not tidy at this time, since there are PCB_LAYER_IDs that
 // are not stored in the bitmap.
 
 GAL_SET GetVisibleElements() const;
 
 void SetVisibleElements( const GAL_SET& aMask );
 
 void SetVisibleAlls();
 
 bool IsElementVisible( GAL_LAYER_ID aLayer ) const;
 
 void SetElementVisibility( GAL_LAYER_ID aLayer, bool aNewState );
 
 bool IsFootprintLayerVisible( PCB_LAYER_ID aLayer ) const;
 
 BOARD_DESIGN_SETTINGS& GetDesignSettings() const;
 
 BOARD_STACKUP GetStackupOrDefault() const;
 
 const PAGE_INFO& GetPageSettings() const { return m_paper; }
 void SetPageSettings( const PAGE_INFO& aPageSettings ) { m_paper = aPageSettings; }
 
 const PCB_PLOT_PARAMS& GetPlotOptions() const { return m_plotOptions; }
 void SetPlotOptions( const PCB_PLOT_PARAMS& aOptions ) { m_plotOptions = aOptions; }
 
 TITLE_BLOCK& GetTitleBlock() { return m_titles; }
 const TITLE_BLOCK& GetTitleBlock() const { return m_titles; }
 void SetTitleBlock( const TITLE_BLOCK& aTitleBlock ) { m_titles = aTitleBlock; }
 
 wxString GetItemDescription( UNITS_PROVIDER* aUnitsProvider, bool aFull ) const override;
 
 EDA_UNITS GetUserUnits() { return m_userUnits; }
 void SetUserUnits( EDA_UNITS aUnits ) { m_userUnits = aUnits; }
 
 void UpdateUserUnits( BOARD_ITEM* aItem, KIGFX::VIEW* aView );
 
 bool GetBoardPolygonOutlines( SHAPE_POLY_SET& aOutlines,
 OUTLINE_ERROR_HANDLER* aErrorHandler = nullptr,
 bool aAllowUseArcsInPolygons = false,
 bool aIncludeNPTHAsOutlines = false );
 
 int GetOutlinesChainingEpsilon() { return( m_outlinesChainingEpsilon ); }
 void SetOutlinesChainingEpsilon( int aValue) { m_outlinesChainingEpsilon = aValue; }
 
 void ConvertBrdLayerToPolygonalContours( PCB_LAYER_ID aLayer, SHAPE_POLY_SET& aOutlines ) const;
 
 PCB_LAYER_ID GetLayerID( const wxString& aLayerName ) const;
 
 const wxString GetLayerName( PCB_LAYER_ID aLayer ) const;
 
 bool SetLayerName( PCB_LAYER_ID aLayer, const wxString& aLayerName );
 
 static wxString GetStandardLayerName( PCB_LAYER_ID aLayerId )
 {
 // a BOARD's standard layer name is the PCB_LAYER_ID fixed name
 return LayerName( aLayerId );
 }
 
 bool SetLayerDescr( PCB_LAYER_ID aIndex, const LAYER& aLayer );
 
 LAYER_T GetLayerType( PCB_LAYER_ID aLayer ) const;
 
 bool SetLayerType( PCB_LAYER_ID aLayer, LAYER_T aLayerType );
 
 unsigned GetNodesCount( int aNet = -1 ) const;
 
 const std::vector<PAD*> GetPads() const;
 
 void BuildListOfNets()
 {
 m_NetInfo.buildListOfNets();
 }
 
 NETINFO_ITEM* FindNet( int aNetcode ) const;
 
 NETINFO_ITEM* FindNet( const wxString& aNetname ) const;
 
 int MatchDpSuffix( const wxString& aNetName, wxString& aComplementNet );
 
 NETINFO_ITEM* DpCoupledNet( const NETINFO_ITEM* aNet );
 
 const NETINFO_LIST& GetNetInfo() const
 {
 return m_NetInfo;
 }
 
 void RemoveUnusedNets( BOARD_COMMIT* aCommit )
 {
 m_NetInfo.RemoveUnusedNets( aCommit );
 }
 
#ifndef SWIG
 NETINFO_LIST::iterator BeginNets() const
 {
 return m_NetInfo.begin();
 }
 
 NETINFO_LIST::iterator EndNets() const
 {
 return m_NetInfo.end();
 }
#endif
 
 unsigned GetNetCount() const
 {
 return m_NetInfo.GetNetCount();
 }
 
 BOX2I ComputeBoundingBox( bool aBoardEdgesOnly = false, bool aIncludeHiddenText = false ) const;
 
 const BOX2I GetBoundingBox() const override
 {
 return ComputeBoundingBox( false, IsElementVisible( LAYER_HIDDEN_TEXT ) );
 }
 
 const BOX2I GetBoardEdgesBoundingBox() const
 {
 return ComputeBoundingBox( true, false );
 }
 
 void GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>& aList ) override;
 
 INSPECT_RESULT Visit( INSPECTOR inspector, void* testData,
 const std::vector<KICAD_T>& scanTypes ) override;
 
 FOOTPRINT* FindFootprintByReference( const wxString& aReference ) const;
 
 FOOTPRINT* FindFootprintByPath( const KIID_PATH& aPath ) const;
 
 std::set<wxString> GetNetClassAssignmentCandidates() const;
 
 void SynchronizeNetsAndNetClasses( bool aResetTrackAndViaSizes );
 
 void SynchronizeProperties();
 
 double Similarity( const BOARD_ITEM& aOther ) const override
 {
 return 1.0;
 }
 
 bool operator==( const BOARD_ITEM& aOther ) const override;
 
 wxString GetClass() const override
 {
 return wxT( "BOARD" );
 }
 
#if defined(DEBUG)
 void Show( int nestLevel, std::ostream& os ) const override { ShowDummy( os ); }
#endif
 
 
 /*************************/
 /* Copper Areas handling */
 /*************************/
 
 int SetAreasNetCodesFromNetNames();
 
 ZONE* GetArea( int index ) const
 {
 if( (unsigned) index < m_zones.size() )
 return m_zones[index];
 
 return nullptr;
 }
 
 std::list<ZONE*> GetZoneList( bool aIncludeZonesInFootprints = false ) const;
 
 int GetAreaCount() const
 {
 return static_cast<int>( m_zones.size() );
 }
 
 /* Functions used in test, merge and cut outlines */
 
 ZONE* AddArea( PICKED_ITEMS_LIST* aNewZonesList, int aNetcode, PCB_LAYER_ID aLayer,
 VECTOR2I aStartPointPosition, ZONE_BORDER_DISPLAY_STYLE aHatch );
 
 bool TestZoneIntersection( ZONE* aZone1, ZONE* aZone2 );
 
 PAD* GetPad( const VECTOR2I& aPosition, LSET aLayerMask ) const;
 PAD* GetPad( const VECTOR2I& aPosition ) const
 {
 return GetPad( aPosition, LSET().set() );
 }
 
 PAD* GetPad( const PCB_TRACK* aTrace, ENDPOINT_T aEndPoint ) const;
 
 PAD* GetPadFast( const VECTOR2I& aPosition, LSET aLayerMask ) const;
 
 PAD* GetPad( std::vector<PAD*>& aPadList, const VECTOR2I& aPosition, LSET aLayerMask ) const;
 
 void GetSortedPadListByXthenYCoord( std::vector<PAD*>& aVector, int aNetCode = -1 ) const;
 
 std::tuple<int, double, double> GetTrackLength( const PCB_TRACK& aTrack ) const;
 
 TRACKS TracksInNet( int aNetCode );
 
 FOOTPRINT* GetFootprint( const VECTOR2I& aPosition, PCB_LAYER_ID aActiveLayer,
 bool aVisibleOnly, bool aIgnoreLocked = false ) const;
 
 int GetMaxClearanceValue() const;
 
 void MapNets( BOARD* aDestBoard );
 
 void SanitizeNetcodes();
 
 void AddListener( BOARD_LISTENER* aListener );
 
 void RemoveListener( BOARD_LISTENER* aListener );
 
 void RemoveAllListeners();
 
 void OnItemChanged( BOARD_ITEM* aItem );
 
 void OnItemsChanged( std::vector<BOARD_ITEM*>& aItems );
 
 void OnItemsCompositeUpdate( std::vector<BOARD_ITEM*>& aAddedItems,
 std::vector<BOARD_ITEM*>& aRemovedItems,
 std::vector<BOARD_ITEM*>& aChangedItems );
 
 void OnRatsnestChanged();
 
 wxString GroupsSanityCheck( bool repair = false );
 
 wxString GroupsSanityCheckInternal( bool repair );
 
 struct GroupLegalOpsField
 {
 bool create : 1;
 bool ungroup : 1;
 bool removeItems : 1;
 };
 
 GroupLegalOpsField GroupLegalOps( const PCB_SELECTION& selection ) const;
 
 bool LegacyTeardrops() const { return m_legacyTeardrops; }
 void SetLegacyTeardrops( bool aFlag ) { m_legacyTeardrops = aFlag; }
 
 EMBEDDED_FILES* GetEmbeddedFiles() override;
 const EMBEDDED_FILES* GetEmbeddedFiles() const;
 
 void EmbedFonts() override;
 
 // --------- Item order comparators ---------
 
 struct cmp_items
 {
 bool operator() ( const BOARD_ITEM* aFirst, const BOARD_ITEM* aSecond ) const;
 };
 
 struct cmp_drawings
 {
 bool operator()( const BOARD_ITEM* aFirst, const BOARD_ITEM* aSecond ) const;
 };
 
public:
 // ------------ Run-time caches -------------
 mutable std::shared_mutex m_CachesMutex;
 std::unordered_map<PTR_PTR_CACHE_KEY, bool> m_IntersectsCourtyardCache;
 std::unordered_map<PTR_PTR_CACHE_KEY, bool> m_IntersectsFCourtyardCache;
 std::unordered_map<PTR_PTR_CACHE_KEY, bool> m_IntersectsBCourtyardCache;
 std::unordered_map<PTR_PTR_LAYER_CACHE_KEY, bool> m_IntersectsAreaCache;
 std::unordered_map<PTR_PTR_LAYER_CACHE_KEY, bool> m_EnclosedByAreaCache;
 std::unordered_map< wxString, LSET > m_LayerExpressionCache;
 std::unordered_map<ZONE*, std::unique_ptr<DRC_RTREE>> m_CopperZoneRTreeCache;
 std::shared_ptr<DRC_RTREE> m_CopperItemRTreeCache;
 mutable std::unordered_map<const ZONE*, BOX2I> m_ZoneBBoxCache;
 mutable std::optional<int> m_maxClearanceValue;
 
 // ------------ DRC caches -------------
 std::vector<ZONE*> m_DRCZones;
 std::vector<ZONE*> m_DRCCopperZones;
 int m_DRCMaxClearance;
 int m_DRCMaxPhysicalClearance;
 ZONE* m_SolderMaskBridges; // A container to build bridges on solder mask layers
 std::map<ZONE*, std::map<PCB_LAYER_ID, ISOLATED_ISLANDS>> m_ZoneIsolatedIslandsMap;
 
private:
 // The default copy constructor & operator= are inadequate,
 // either write one or do not use it at all
 BOARD( const BOARD& aOther ) = delete;
 
 BOARD& operator=( const BOARD& aOther ) = delete;
 
 template <typename Func, typename... Args>
 void InvokeListeners( Func&& aFunc, Args&&... args )
 {
 for( auto&& l : m_listeners )
 ( l->*aFunc )( std::forward<Args>( args )... );
 }
 
 // Refresh user layer opposites.
 void recalcOpposites();
 
 friend class PCB_EDIT_FRAME;
 
private:
 int m_outlinesChainingEpsilon;
 
 BOARD_USE m_boardUse;
 int m_timeStamp; // actually a modification counter
 
 wxString m_fileName;
 
 // These containers only have const accessors and must only be modified by Add()/Remove()
 MARKERS m_markers;
 DRAWINGS m_drawings;
 FOOTPRINTS m_footprints;
 TRACKS m_tracks;
 GROUPS m_groups;
 ZONES m_zones;
 GENERATORS m_generators;
 
 // Cache for fast access to items in the containers above by KIID, including children
 std::unordered_map<KIID, BOARD_ITEM*> m_itemByIdCache;
 
 LAYER m_layers[PCB_LAYER_ID_COUNT];
 
 HIGH_LIGHT_INFO m_highLight; // current high light data
 HIGH_LIGHT_INFO m_highLightPrevious; // a previously stored high light data
 
 int m_fileFormatVersionAtLoad; // the version loaded from the file
 wxString m_generator; // the generator tag from the file
 
 std::map<wxString, wxString> m_properties;
 std::shared_ptr<CONNECTIVITY_DATA> m_connectivity;
 
 PAGE_INFO m_paper;
 TITLE_BLOCK m_titles; // text in lower right of screen and plots
 PCB_PLOT_PARAMS m_plotOptions;
 PROJECT* m_project; // project this board is a part of
 EDA_UNITS m_userUnits;
 
 std::unique_ptr<BOARD_DESIGN_SETTINGS> m_designSettings;
 
 bool m_legacyTeardrops = false;
 
 NETINFO_LIST m_NetInfo; // net info list (name, design constraints...
 
 std::vector<BOARD_LISTENER*> m_listeners;
 
 bool m_embedFonts;
};
 
 
#endif // CLASS_BOARD_H_