KiCad PCB EDA Suite
board_design_settings.h
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24 
25 #ifndef BOARD_DESIGN_SETTINGS_H_
26 #define BOARD_DESIGN_SETTINGS_H_
27 
28 #include <pad.h>
29 #include <netclass.h>
30 #include <config_params.h>
32 #include <drc/drc_engine.h>
34 #include <widgets/ui_common.h>
35 #include <zone_settings.h>
36 
37 
38 #define DEFAULT_SILK_LINE_WIDTH 0.12
39 #define DEFAULT_COPPER_LINE_WIDTH 0.20
40 #define DEFAULT_EDGE_WIDTH 0.05
41 #define DEFAULT_COURTYARD_WIDTH 0.05
42 #define DEFAULT_LINE_WIDTH 0.10
43 
44 #define DEFAULT_SILK_TEXT_SIZE 1.0
45 #define DEFAULT_COPPER_TEXT_SIZE 1.5
46 #define DEFAULT_TEXT_SIZE 1.0
47 
48 #define DEFAULT_SILK_TEXT_WIDTH 0.15
49 #define DEFAULT_COPPER_TEXT_WIDTH 0.30
50 #define DEFAULT_TEXT_WIDTH 0.15
51 
52 #define DEFAULT_DIMENSION_ARROW_LENGTH 50 // mils, for legacy purposes
53 #define DEFAULT_DIMENSION_EXTENSION_OFFSET 0.5
54 
55 // Board thickness, mainly for 3D view:
56 #define DEFAULT_BOARD_THICKNESS_MM 1.6
57 
58 #define DEFAULT_PCB_EDGE_THICKNESS 0.15
59 
60 // soldermask to pad clearance. The default is 0 because usually board houses
61 // create a clearance depending on their fab process:
62 // mask material, color, price ...
63 #define DEFAULT_SOLDERMASK_CLEARANCE 0.0
64 
65 // DEFAULT_SOLDERMASK_MIN_WIDTH is only used in Gerber files: soldermask minimum size.
66 // Set to 0, because using non 0 value creates an annoying issue in Gerber files:
67 // pads are no longer identified as pads (Flashed items or regions)
68 // Therefore solder mask min width must be used only in specific cases
69 // for instance for home made boards
70 #define DEFAULT_SOLDERMASK_MIN_WIDTH 0.0
71 
72 #define DEFAULT_SOLDERPASTE_CLEARANCE 0.0
73 #define DEFAULT_SOLDERPASTE_RATIO 0.0
74 
75 #define DEFAULT_CUSTOMTRACKWIDTH 0.2
76 #define DEFAULT_CUSTOMDPAIRWIDTH 0.125
77 #define DEFAULT_CUSTOMDPAIRGAP 0.18
78 #define DEFAULT_CUSTOMDPAIRVIAGAP 0.18
79 
80 #define DEFAULT_MINCLEARANCE 0.0 // overall min clearance
81 #define DEFAULT_TRACKMINWIDTH 0.2 // track width min value
82 #define DEFAULT_VIASMINSIZE 0.4 // vias (not micro vias) min diameter
83 #define DEFAULT_MINTHROUGHDRILL 0.3 // through holes (not micro vias) min drill diameter
84 #define DEFAULT_MICROVIASMINSIZE 0.2 // micro vias (not vias) min diameter
85 #define DEFAULT_MICROVIASMINDRILL 0.1 // micro vias (not vias) min drill diameter
86 #define DEFAULT_HOLETOHOLEMIN 0.25 // minimum web thickness between two drilled holes
87 #define DEFAULT_HOLECLEARANCE 0.0 // copper-to-hole clearance
88 
89 #define DEFAULT_COPPEREDGECLEARANCE 0.01 // clearance between copper items and edge cuts
90 #define LEGACY_COPPEREDGECLEARANCE -0.01 // A flag to indicate the legacy method (based
91  // on edge cut line thicknesses) should be used.
92 #define DEFAULT_SILKCLEARANCE 0.0
93 
94 #define MINIMUM_ERROR_SIZE_MM 0.001
95 #define MAXIMUM_ERROR_SIZE_MM 0.1
96 
97 
103 {
104  int m_Diameter; // <= 0 means use Netclass via diameter
105  int m_Drill; // <= 0 means use Netclass via drill
106 
108  {
109  m_Diameter = 0;
110  m_Drill = 0;
111  }
112 
113  VIA_DIMENSION( int aDiameter, int aDrill )
114  {
115  m_Diameter = aDiameter;
116  m_Drill = aDrill;
117  }
118 
119  bool operator==( const VIA_DIMENSION& aOther ) const
120  {
121  return ( m_Diameter == aOther.m_Diameter ) && ( m_Drill == aOther.m_Drill );
122  }
123 
124  bool operator<( const VIA_DIMENSION& aOther ) const
125  {
126  if( m_Diameter != aOther.m_Diameter )
127  return m_Diameter < aOther.m_Diameter;
128 
129  return m_Drill < aOther.m_Drill;
130  }
131 };
132 
133 
139 {
140  int m_Width; // <= 0 means use Netclass differential pair width
141  int m_Gap; // <= 0 means use Netclass differential pair gap
142  int m_ViaGap; // <= 0 means use Netclass differential pair via gap
143 
145  {
146  m_Width = 0;
147  m_Gap = 0;
148  m_ViaGap = 0;
149  }
150 
151  DIFF_PAIR_DIMENSION( int aWidth, int aGap, int aViaGap )
152  {
153  m_Width = aWidth;
154  m_Gap = aGap;
155  m_ViaGap = aViaGap;
156  }
157 
158  bool operator==( const DIFF_PAIR_DIMENSION& aOther ) const
159  {
160  return ( m_Width == aOther.m_Width )
161  && ( m_Gap == aOther.m_Gap )
162  && ( m_ViaGap == aOther.m_ViaGap );
163  }
164 
165  bool operator<( const DIFF_PAIR_DIMENSION& aOther ) const
166  {
167  if( m_Width != aOther.m_Width )
168  return m_Width < aOther.m_Width;
169 
170  if( m_Gap != aOther.m_Gap )
171  return m_Gap < aOther.m_Gap;
172 
173  return m_ViaGap < aOther.m_ViaGap;
174  }
175 };
176 
177 
178 enum
179 {
186 
188 };
189 
190 
192 {
193  wxString m_Text;
194  bool m_Visible;
195  int m_Layer;
196 
197  TEXT_ITEM_INFO( const wxString& aText, bool aVisible, int aLayer )
198  {
199  m_Text = aText;
200  m_Visible = aVisible;
201  m_Layer = aLayer;
202  }
203 };
204 
205 
206 // forward declaration from class_track.h
207 enum class VIATYPE : int;
208 
209 // forward declarations from dimension.h
210 enum class DIM_UNITS_FORMAT : int;
211 enum class DIM_TEXT_POSITION : int;
212 enum class DIM_UNITS_MODE : int;
213 
214 
219 {
220 public:
221  BOARD_DESIGN_SETTINGS( JSON_SETTINGS* aParent, const std::string& aPath );
222 
223  virtual ~BOARD_DESIGN_SETTINGS();
224 
226 
228 
229  bool LoadFromFile( const wxString& aDirectory = "" ) override;
230 
232  const BOARD_STACKUP& GetStackupDescriptor() const { return m_stackup; }
233 
234  SEVERITY GetSeverity( int aDRCErrorCode );
235 
239  bool Ignore( int aDRCErrorCode );
240 
242  {
243  return *m_netClasses;
244  }
245 
246  void SetNetClasses( NETCLASSES* aNetClasses )
247  {
248  if( aNetClasses )
249  m_netClasses = aNetClasses;
250  else
251  m_netClasses = &m_internalNetClasses;
252  }
253 
255  {
256  return m_defaultZoneSettings;
257  }
258 
259  void SetDefaultZoneSettings( const ZONE_SETTINGS& aSettings )
260  {
261  m_defaultZoneSettings = aSettings;
262  }
263 
267  inline NETCLASS* GetDefault() const
268  {
269  return GetNetClasses().GetDefaultPtr();
270  }
271 
275  inline const wxString& GetCurrentNetClassName() const
276  {
277  return m_currentNetClassName;
278  }
279 
283  inline bool UseNetClassTrack() const
284  {
285  return ( m_trackWidthIndex == 0 && !m_useCustomTrackVia );
286  }
287 
291  inline bool UseNetClassVia() const
292  {
293  return ( m_viaSizeIndex == 0 && !m_useCustomTrackVia );
294  }
295 
299  inline bool UseNetClassDiffPair() const
300  {
301  return ( m_diffPairIndex == 0 && !m_useCustomDiffPair );
302  }
303 
308 
313 
318 
323 
327  inline unsigned GetTrackWidthIndex() const { return m_trackWidthIndex; }
328 
334  void SetTrackWidthIndex( unsigned aIndex );
335 
341  int GetCurrentTrackWidth() const;
342 
351  inline void SetCustomTrackWidth( int aWidth )
352  {
353  m_customTrackWidth = aWidth;
354  }
355 
359  inline int GetCustomTrackWidth() const
360  {
361  return m_customTrackWidth;
362  }
363 
367  inline unsigned GetViaSizeIndex() const
368  {
369  return m_viaSizeIndex;
370  }
371 
377  void SetViaSizeIndex( unsigned aIndex );
378 
384  int GetCurrentViaSize() const;
385 
394  inline void SetCustomViaSize( int aSize )
395  {
396  m_customViaSize.m_Diameter = aSize;
397  }
398 
402  inline int GetCustomViaSize() const
403  {
404  return m_customViaSize.m_Diameter;
405  }
406 
412  int GetCurrentViaDrill() const;
413 
422  inline void SetCustomViaDrill( int aDrill )
423  {
424  m_customViaSize.m_Drill = aDrill;
425  }
426 
430  inline int GetCustomViaDrill() const
431  {
432  return m_customViaSize.m_Drill;
433  }
434 
443  inline void UseCustomTrackViaSize( bool aEnabled )
444  {
445  m_useCustomTrackVia = aEnabled;
446  }
447 
451  inline bool UseCustomTrackViaSize() const
452  {
453  return m_useCustomTrackVia;
454  }
455 
459  inline unsigned GetDiffPairIndex() const { return m_diffPairIndex; }
460 
464  void SetDiffPairIndex( unsigned aIndex );
465 
472  inline void SetCustomDiffPairWidth( int aWidth )
473  {
474  m_customDiffPair.m_Width = aWidth;
475  }
476 
481  {
482  return m_customDiffPair.m_Width;
483  }
484 
490  inline void SetCustomDiffPairGap( int aGap )
491  {
492  m_customDiffPair.m_Gap = aGap;
493  }
494 
499  inline int GetCustomDiffPairGap()
500  {
501  return m_customDiffPair.m_Gap;
502  }
503 
510  inline void SetCustomDiffPairViaGap( int aGap )
511  {
512  m_customDiffPair.m_ViaGap = aGap;
513  }
514 
519  {
520  return m_customDiffPair.m_ViaGap > 0 ? m_customDiffPair.m_ViaGap : m_customDiffPair.m_Gap;
521  }
522 
528  inline void UseCustomDiffPairDimensions( bool aEnabled )
529  {
530  m_useCustomDiffPair = aEnabled;
531  }
532 
536  inline bool UseCustomDiffPairDimensions() const
537  {
538  return m_useCustomDiffPair;
539  }
540 
546  inline int GetCurrentDiffPairWidth() const
547  {
548  if( m_useCustomDiffPair )
549  return m_customDiffPair.m_Width;
550  else
551  return m_DiffPairDimensionsList[m_diffPairIndex].m_Width;
552  }
553 
559  inline int GetCurrentDiffPairGap() const
560  {
561  if( m_useCustomDiffPair )
562  return m_customDiffPair.m_Gap;
563  else
564  return m_DiffPairDimensionsList[m_diffPairIndex].m_Gap;
565  }
566 
572  inline int GetCurrentDiffPairViaGap() const
573  {
574  if( m_useCustomDiffPair )
575  return m_customDiffPair.m_ViaGap;
576  else
577  return m_DiffPairDimensionsList[m_diffPairIndex].m_ViaGap;
578  }
579 
584  void SetMinHoleSeparation( int aDistance );
585 
589  void SetCopperEdgeClearance( int aDistance );
590 
599  void SetSilkClearance( int aDistance );
600 
606  inline LSET GetEnabledLayers() const
607  {
608  return m_enabledLayers;
609  }
610 
616  void SetEnabledLayers( LSET aMask );
617 
624  inline bool IsLayerEnabled( PCB_LAYER_ID aLayerId ) const
625  {
626  if( aLayerId >= 0 && aLayerId < PCB_LAYER_ID_COUNT )
627  return m_enabledLayers[aLayerId];
628 
629  return false;
630  }
631 
635  inline int GetCopperLayerCount() const
636  {
637  return m_copperLayerCount;
638  }
639 
645  void SetCopperLayerCount( int aNewLayerCount );
646 
647  inline int GetBoardThickness() const { return m_boardThickness; }
648  inline void SetBoardThickness( int aThickness ) { m_boardThickness = aThickness; }
649 
650  /*
651  * Return an epsilon which accounts for rounding errors, etc.
652  *
653  * While currently an advanced cfg, going through this API allows us to easily change
654  * it to board-specific if so desired.
655  */
656  int GetDRCEpsilon() const;
657 
663  int GetHolePlatingThickness() const;
664 
668  int GetLineThickness( PCB_LAYER_ID aLayer ) const;
669 
673  wxSize GetTextSize( PCB_LAYER_ID aLayer ) const;
674 
678  int GetTextThickness( PCB_LAYER_ID aLayer ) const;
679 
680  bool GetTextItalic( PCB_LAYER_ID aLayer ) const;
681  bool GetTextUpright( PCB_LAYER_ID aLayer ) const;
682 
683  int GetLayerClass( PCB_LAYER_ID aLayer ) const;
684 
685 private:
686  void initFromOther( const BOARD_DESIGN_SETTINGS& aOther );
687 
688  bool migrateSchema0to1();
689 
690 public:
691  // Note: the first value in each dimensions list is the current netclass value
692  std::vector<int> m_TrackWidthList;
693  std::vector<VIA_DIMENSION> m_ViasDimensionsList;
694  std::vector<DIFF_PAIR_DIMENSION> m_DiffPairDimensionsList;
695 
699 
700  bool m_UseConnectedTrackWidth; // use width of existing track when creating a new,
701  // connected track
702  int m_MinClearance; // overall min clearance
703  int m_TrackMinWidth; // overall min track width
704  int m_ViasMinAnnulus; // overall minimum width of the via copper ring
705  int m_ViasMinSize; // overall vias (not micro vias) min diameter
706  int m_MinThroughDrill; // through hole (not micro vias) min drill diameter
707  int m_MicroViasMinSize; // micro vias min diameter
708  int m_MicroViasMinDrill; // micro vias min drill diameter
710  int m_HoleClearance; // Hole to copper clearance
711  int m_HoleToHoleMin; // Min width of web between two drilled holes
713 
714  std::shared_ptr<DRC_ENGINE> m_DRCEngine;
715  std::map<int, SEVERITY> m_DRCSeverities; // Map from DRCErrorCode to SEVERITY
716  std::set<wxString> m_DrcExclusions;
717 
732 
733  // When smoothing the zone's outline there's the question of external fillets (that is, those
734  // applied to concave corners). While it seems safer to never have copper extend outside the
735  // zone outline, 5.1.x and prior did indeed fill them so we leave the mode available.
737 
738  // Maximum error allowed when approximating circles and arcs to segments
740 
741  // Global mask margins:
742  int m_SolderMaskMargin; // Solder mask margin
743  int m_SolderMaskMinWidth; // Solder mask min width (2 areas closer than this
744  // width are merged)
745  int m_SolderPasteMargin; // Solder paste margin absolute value
746  double m_SolderPasteMarginRatio; // Solder mask margin ratio value of pad size
747  // The final margin is the sum of these 2 values
748 
749  // Variables used in footprint editing (default value in item/footprint creation)
750  std::vector<TEXT_ITEM_INFO> m_DefaultFPTextItems;
751 
752  // Arrays of default values for the various layer classes.
753  int m_LineThickness[ LAYER_CLASS_COUNT ];
754  wxSize m_TextSize[ LAYER_CLASS_COUNT ];
755  int m_TextThickness[ LAYER_CLASS_COUNT ];
756  bool m_TextItalic[ LAYER_CLASS_COUNT ];
757  bool m_TextUpright[ LAYER_CLASS_COUNT ];
758 
759  // Default values for dimension objects
768 
769  // Miscellaneous
770  wxPoint m_AuxOrigin;
771  wxPoint m_GridOrigin;
772 
773  PAD m_Pad_Master; // A dummy pad to store all default parameters
774  // when importing values or creating a new pad
775 
776  // Set to true if the board has a stackup management.
777  // If not set a default basic stackup will be used to generate the gbrjob file.
778  // Could be removed later, or at least always set to true
780 
781 private:
782  // Indices into the trackWidth, viaSizes and diffPairDimensions lists.
783  // The 0 index is always the current netclass value(s)
785  unsigned m_viaSizeIndex;
786  unsigned m_diffPairIndex;
787 
788  // Custom values for track/via sizes (specified via dialog instead of netclass or lists)
792 
793  // Custom values for differential pairs (specified via dialog instead of netclass/lists)
796 
798 
800 
802 
806 
812 
815 
818 
821 };
822 
823 #endif // BOARD_DESIGN_SETTINGS_H_
bool UseNetClassTrack() const
Return true if netclass values should be used to obtain appropriate track width.
void SetNetClasses(NETCLASSES *aNetClasses)
void SetCopperLayerCount(int aNewLayerCount)
Set the copper layer count to aNewLayerCount.
Container to handle a stock of specific vias each with unique diameter and drill sizes in the BOARD c...
int m_ZoneFillVersion
Option to select different fill algorithms.
void SetEnabledLayers(LSET aMask)
Change the bit-mask of enabled layers to aMask.
void SetCopperEdgeClearance(int aDistance)
bool UseCustomDiffPairDimensions() const
void SetTrackWidthIndex(unsigned aIndex)
Set the current track width list index to aIndex.
wxString m_currentNetClassName
Current net class name used to display netclass info.
std::vector< TEXT_ITEM_INFO > m_DefaultFPTextItems
wxPoint m_GridOrigin
origin for grid offsets
this class manage the layers needed to make a physical board they are solder mask,...
void SetCustomDiffPairViaGap(int aGap)
Sets custom via gap for differential pairs (i.e.
BOARD_DESIGN_SETTINGS(JSON_SETTINGS *aParent, const std::string &aPath)
std::vector< int > m_TrackWidthList
void SetDefaultZoneSettings(const ZONE_SETTINGS &aSettings)
bool IsLayerEnabled(PCB_LAYER_ID aLayerId) const
Test whether a given layer aLayerId is enabled.
BOARD_STACKUP m_stackup
the description of layers stackup, for board fabrication only physical layers are in layers stackup.
SEVERITY
Definition: ui_common.h:83
bool UseNetClassDiffPair() const
Return true if netclass values should be used to obtain appropriate diff pair dimensions.
std::vector< DIFF_PAIR_DIMENSION > m_DiffPairDimensionsList
void SetCustomViaDrill(int aDrill)
Sets custom size for via drill (i.e.
int GetHolePlatingThickness() const
Pad & via drills are finish size.
NETCLASSES m_internalNetClasses
Net classes that are loaded from the board file before these were stored in the project.
bool Ignore(int aDRCErrorCode)
Return true if the DRC error code's severity is SEVERITY_IGNORE.
void UseCustomDiffPairDimensions(bool aEnabled)
Enables/disables custom differential pair dimensions.
bool operator<(const VIA_DIMENSION &aOther) const
int m_DimensionPrecision
Number of digits after the decimal.
ZONE_SETTINGS m_defaultZoneSettings
The default settings that will be used for new zones.
bool operator<(const DIFF_PAIR_DIMENSION &aOther) const
const BOARD_STACKUP & GetStackupDescriptor() const
DIFF_PAIR_DIMENSION m_customDiffPair
int GetTextThickness(PCB_LAYER_ID aLayer) const
Return the default text thickness from the layer class for the given layer.
TEXT_ITEM_INFO(const wxString &aText, bool aVisible, int aLayer)
void SetBoardThickness(int aThickness)
VIATYPE m_CurrentViaType
(VIA_BLIND_BURIED, VIA_THROUGH, VIA_MICROVIA)
Container to handle a stock of specific differential pairs each with unique track width,...
void SetCustomViaSize(int aSize)
Set custom size for via diameter (i.e.
DIM_TEXT_POSITION m_DimensionTextPosition
DIM_UNITS_MODE m_DimensionUnitsMode
int GetLayerClass(PCB_LAYER_ID aLayer) const
bool GetTextUpright(PCB_LAYER_ID aLayer) const
bool GetTextItalic(PCB_LAYER_ID aLayer) const
int GetLineThickness(PCB_LAYER_ID aLayer) const
Return the default graphic segment thickness from the layer class for the given layer.
void SetViaSizeIndex(unsigned aIndex)
Set the current via size list index to aIndex.
NESTED_SETTINGS is a JSON_SETTINGS that lives inside a JSON_SETTINGS.
BOARD_STACKUP & GetStackupDescriptor()
PCB_LAYER_ID
A quick note on layer IDs:
LSET is a set of PCB_LAYER_IDs.
A container for NETCLASS instances.
Definition: netclass.h:218
const wxString & GetCurrentNetClassName() const
unsigned GetViaSizeIndex() const
void SetMinHoleSeparation(int aDistance)
bool UseNetClassVia() const
Return true if netclass values should be used to obtain appropriate via size.
void SetCustomDiffPairWidth(int aWidth)
Sets custom track width for differential pairs (i.e.
bool LoadFromFile(const wxString &aDirectory="") override
Loads the backing file from disk and then calls Load()
A collection of nets and the parameters used to route or test these nets.
Definition: netclass.h:46
unsigned GetTrackWidthIndex() const
Functions to provide common constants and other functions to assist in making a consistent UI.
BOARD_DESIGN_SETTINGS & operator=(const BOARD_DESIGN_SETTINGS &aOther)
NETCLASSES & GetNetClasses() const
bool m_BlindBuriedViaAllowed
true to allow blind/buried vias
SEVERITY GetSeverity(int aDRCErrorCode)
void SetDiffPairIndex(unsigned aIndex)
void SetCustomDiffPairGap(int aGap)
Sets custom gap for differential pairs (i.e.
NETCLASS * GetDefaultPtr() const
Definition: netclass.h:258
void SetCustomTrackWidth(int aWidth)
Sets custom width for track (i.e.
ZONE_SETTINGS handles zones parameters.
Definition: zone_settings.h:67
bool operator==(const VIA_DIMENSION &aOther) const
LSET GetEnabledLayers() const
Return a bit-mask of all the layers that are enabled.
std::map< int, SEVERITY > m_DRCSeverities
DIM_UNITS_MODE
Used for storing the units selection in the file because EDA_UNITS alone doesn't cut it.
Definition: dimension.h:57
NETCLASS * GetDefault() const
void SetSilkClearance(int aDistance)
Set the minimum distance between silk items to aValue.
void initFromOther(const BOARD_DESIGN_SETTINGS &aOther)
std::vector< VIA_DIMENSION > m_ViasDimensionsList
DIFF_PAIR_DIMENSION(int aWidth, int aGap, int aViaGap)
DIM_TEXT_POSITION
Where to place the text on a dimension.
Definition: dimension.h:47
DIM_UNITS_FORMAT m_DimensionUnitsFormat
bool operator==(const DIFF_PAIR_DIMENSION &aOther) const
VIA_DIMENSION(int aDiameter, int aDrill)
unsigned GetDiffPairIndex() const
DIM_UNITS_FORMAT
How to display the units in a dimension's text.
Definition: dimension.h:39
NETCLASSES * m_netClasses
This will point to m_internalNetClasses until it is repointed to the project after load.
ZONE_SETTINGS & GetDefaultZoneSettings()
int m_copperLayerCount
Number of copper layers for this design.
bool m_MicroViasAllowed
true to allow micro vias
VIATYPE
Definition: track.h:68
Definition: pad.h:60
std::set< wxString > m_DrcExclusions
LSET m_enabledLayers
Bit-mask for layer enabling.
wxPoint m_AuxOrigin
origin for plot exports
wxSize GetTextSize(PCB_LAYER_ID aLayer) const
Return the default text size from the layer class for the given layer.
int m_boardThickness
Board thickness for 3D viewer.
std::shared_ptr< DRC_ENGINE > m_DRCEngine
int GetCustomDiffPairGap()
Function GetCustomDiffPairGap.
void UseCustomTrackViaSize(bool aEnabled)
Enables/disables custom track/via size settings.
Container for design settings for a BOARD object.