KiCad PCB EDA Suite
board_design_settings.h
Go to the documentation of this file.
1 /*
2  * This program source code file is part of KiCad, a free EDA CAD application.
3  *
4  * Copyright (C) 2009-2019 Jean-Pierre Charras, jp.charras at wanadoo.fr
5  * Copyright (C) 1992-2021 KiCad Developers, see AUTHORS.txt for contributors.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License
9  * as published by the Free Software Foundation; either version 2
10  * of the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, you may find one here:
19  * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
20  * or you may search the http://www.gnu.org website for the version 2 license,
21  * or you may write to the Free Software Foundation, Inc.,
22  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
23  */
24 
25 #ifndef BOARD_DESIGN_SETTINGS_H_
26 #define BOARD_DESIGN_SETTINGS_H_
27 
28 #include <memory>
29 
30 #include <netclass.h>
31 #include <config_params.h>
33 #include <drc/drc_engine.h>
35 #include <widgets/ui_common.h>
36 #include <zone_settings.h>
37 
38 
39 #define DEFAULT_SILK_LINE_WIDTH 0.12
40 #define DEFAULT_COPPER_LINE_WIDTH 0.20
41 #define DEFAULT_EDGE_WIDTH 0.05
42 #define DEFAULT_COURTYARD_WIDTH 0.05
43 #define DEFAULT_LINE_WIDTH 0.10
44 
45 #define DEFAULT_SILK_TEXT_SIZE 1.0
46 #define DEFAULT_COPPER_TEXT_SIZE 1.5
47 #define DEFAULT_TEXT_SIZE 1.0
48 
49 #define DEFAULT_SILK_TEXT_WIDTH 0.15
50 #define DEFAULT_COPPER_TEXT_WIDTH 0.30
51 #define DEFAULT_TEXT_WIDTH 0.15
52 
53 #define DEFAULT_DIMENSION_ARROW_LENGTH 50 // mils, for legacy purposes
54 #define DEFAULT_DIMENSION_EXTENSION_OFFSET 0.5
55 
56 // Board thickness, mainly for 3D view:
57 #define DEFAULT_BOARD_THICKNESS_MM 1.6
58 
59 #define DEFAULT_PCB_EDGE_THICKNESS 0.15
60 
61 // soldermask to pad clearance. The default is 0 because usually board houses
62 // create a clearance depending on their fab process:
63 // mask material, color, price ...
64 #define DEFAULT_SOLDERMASK_CLEARANCE 0.0
65 
66 // DEFAULT_SOLDERMASK_MIN_WIDTH is only used in Gerber files: soldermask minimum size.
67 // Set to 0, because using non 0 value creates an annoying issue in Gerber files:
68 // pads are no longer identified as pads (Flashed items or regions)
69 // Therefore solder mask min width must be used only in specific cases
70 // for instance for home made boards
71 #define DEFAULT_SOLDERMASK_MIN_WIDTH 0.0
72 
73 #define DEFAULT_SOLDERPASTE_CLEARANCE 0.0
74 #define DEFAULT_SOLDERPASTE_RATIO 0.0
75 
76 #define DEFAULT_CUSTOMTRACKWIDTH 0.2
77 #define DEFAULT_CUSTOMDPAIRWIDTH 0.125
78 #define DEFAULT_CUSTOMDPAIRGAP 0.18
79 #define DEFAULT_CUSTOMDPAIRVIAGAP 0.18
80 
81 #define DEFAULT_MINCLEARANCE 0.0 // overall min clearance
82 #define DEFAULT_TRACKMINWIDTH 0.2 // track width min value
83 #define DEFAULT_VIASMINSIZE 0.4 // vias (not micro vias) min diameter
84 #define DEFAULT_MINTHROUGHDRILL 0.3 // through holes (not micro vias) min drill diameter
85 #define DEFAULT_MICROVIASMINSIZE 0.2 // micro vias (not vias) min diameter
86 #define DEFAULT_MICROVIASMINDRILL 0.1 // micro vias (not vias) min drill diameter
87 #define DEFAULT_HOLETOHOLEMIN 0.25 // minimum web thickness between two drilled holes
88 #define DEFAULT_HOLECLEARANCE 0.0 // copper-to-hole clearance
89 
90 #define DEFAULT_COPPEREDGECLEARANCE 0.01 // clearance between copper items and edge cuts
91 #define LEGACY_COPPEREDGECLEARANCE -0.01 // A flag to indicate the legacy method (based
92  // on edge cut line thicknesses) should be used.
93 #define DEFAULT_SILKCLEARANCE 0.0
94 
95 #define MINIMUM_ERROR_SIZE_MM 0.001
96 #define MAXIMUM_ERROR_SIZE_MM 0.1
97 
98 
104 {
105  int m_Diameter; // <= 0 means use Netclass via diameter
106  int m_Drill; // <= 0 means use Netclass via drill
107 
109  {
110  m_Diameter = 0;
111  m_Drill = 0;
112  }
113 
114  VIA_DIMENSION( int aDiameter, int aDrill )
115  {
116  m_Diameter = aDiameter;
117  m_Drill = aDrill;
118  }
119 
120  bool operator==( const VIA_DIMENSION& aOther ) const
121  {
122  return ( m_Diameter == aOther.m_Diameter ) && ( m_Drill == aOther.m_Drill );
123  }
124 
125  bool operator<( const VIA_DIMENSION& aOther ) const
126  {
127  if( m_Diameter != aOther.m_Diameter )
128  return m_Diameter < aOther.m_Diameter;
129 
130  return m_Drill < aOther.m_Drill;
131  }
132 };
133 
134 
140 {
141  int m_Width; // <= 0 means use Netclass differential pair width
142  int m_Gap; // <= 0 means use Netclass differential pair gap
143  int m_ViaGap; // <= 0 means use Netclass differential pair via gap
144 
146  {
147  m_Width = 0;
148  m_Gap = 0;
149  m_ViaGap = 0;
150  }
151 
152  DIFF_PAIR_DIMENSION( int aWidth, int aGap, int aViaGap )
153  {
154  m_Width = aWidth;
155  m_Gap = aGap;
156  m_ViaGap = aViaGap;
157  }
158 
159  bool operator==( const DIFF_PAIR_DIMENSION& aOther ) const
160  {
161  return ( m_Width == aOther.m_Width )
162  && ( m_Gap == aOther.m_Gap )
163  && ( m_ViaGap == aOther.m_ViaGap );
164  }
165 
166  bool operator<( const DIFF_PAIR_DIMENSION& aOther ) const
167  {
168  if( m_Width != aOther.m_Width )
169  return m_Width < aOther.m_Width;
170 
171  if( m_Gap != aOther.m_Gap )
172  return m_Gap < aOther.m_Gap;
173 
174  return m_ViaGap < aOther.m_ViaGap;
175  }
176 };
177 
178 
179 enum
180 {
187 
189 };
190 
191 
193 {
194  wxString m_Text;
195  bool m_Visible;
196  int m_Layer;
197 
198  TEXT_ITEM_INFO( const wxString& aText, bool aVisible, int aLayer )
199  {
200  m_Text = aText;
201  m_Visible = aVisible;
202  m_Layer = aLayer;
203  }
204 };
205 
206 
207 // forward declaration from class_track.h
208 enum class VIATYPE : int;
209 
210 // forward declarations from dimension.h
211 enum class DIM_UNITS_FORMAT : int;
212 enum class DIM_TEXT_POSITION : int;
213 enum class DIM_UNITS_MODE : int;
214 
215 class PAD;
216 
221 {
222 public:
223  BOARD_DESIGN_SETTINGS( JSON_SETTINGS* aParent, const std::string& aPath );
224 
225  virtual ~BOARD_DESIGN_SETTINGS();
226 
228 
230 
231  bool LoadFromFile( const wxString& aDirectory = "" ) override;
232 
234  const BOARD_STACKUP& GetStackupDescriptor() const { return m_stackup; }
235 
236  SEVERITY GetSeverity( int aDRCErrorCode );
237 
241  bool Ignore( int aDRCErrorCode );
242 
244  {
245  return *m_netClasses;
246  }
247 
248  void SetNetClasses( NETCLASSES* aNetClasses )
249  {
250  if( aNetClasses )
251  m_netClasses = aNetClasses;
252  else
253  m_netClasses = &m_internalNetClasses;
254  }
255 
257  {
258  return m_defaultZoneSettings;
259  }
260 
261  void SetDefaultZoneSettings( const ZONE_SETTINGS& aSettings )
262  {
263  m_defaultZoneSettings = aSettings;
264  }
265 
269  inline NETCLASS* GetDefault() const
270  {
271  return GetNetClasses().GetDefaultPtr();
272  }
273 
277  inline const wxString& GetCurrentNetClassName() const
278  {
279  return m_currentNetClassName;
280  }
281 
285  inline bool UseNetClassTrack() const
286  {
287  return ( m_trackWidthIndex == 0 && !m_useCustomTrackVia );
288  }
289 
293  inline bool UseNetClassVia() const
294  {
295  return ( m_viaSizeIndex == 0 && !m_useCustomTrackVia );
296  }
297 
301  inline bool UseNetClassDiffPair() const
302  {
303  return ( m_diffPairIndex == 0 && !m_useCustomDiffPair );
304  }
305 
309  int GetBiggestClearanceValue() const;
310 
314  int GetSmallestClearanceValue() const;
315 
320 
325 
329  inline unsigned GetTrackWidthIndex() const { return m_trackWidthIndex; }
330 
336  void SetTrackWidthIndex( unsigned aIndex );
337 
343  int GetCurrentTrackWidth() const;
344 
353  inline void SetCustomTrackWidth( int aWidth )
354  {
355  m_customTrackWidth = aWidth;
356  }
357 
361  inline int GetCustomTrackWidth() const
362  {
363  return m_customTrackWidth;
364  }
365 
369  inline unsigned GetViaSizeIndex() const
370  {
371  return m_viaSizeIndex;
372  }
373 
379  void SetViaSizeIndex( unsigned aIndex );
380 
386  int GetCurrentViaSize() const;
387 
396  inline void SetCustomViaSize( int aSize )
397  {
398  m_customViaSize.m_Diameter = aSize;
399  }
400 
404  inline int GetCustomViaSize() const
405  {
406  return m_customViaSize.m_Diameter;
407  }
408 
414  int GetCurrentViaDrill() const;
415 
424  inline void SetCustomViaDrill( int aDrill )
425  {
426  m_customViaSize.m_Drill = aDrill;
427  }
428 
432  inline int GetCustomViaDrill() const
433  {
434  return m_customViaSize.m_Drill;
435  }
436 
445  inline void UseCustomTrackViaSize( bool aEnabled )
446  {
447  m_useCustomTrackVia = aEnabled;
448  }
449 
453  inline bool UseCustomTrackViaSize() const
454  {
455  return m_useCustomTrackVia;
456  }
457 
461  inline unsigned GetDiffPairIndex() const { return m_diffPairIndex; }
462 
466  void SetDiffPairIndex( unsigned aIndex );
467 
474  inline void SetCustomDiffPairWidth( int aWidth )
475  {
476  m_customDiffPair.m_Width = aWidth;
477  }
478 
483  {
484  return m_customDiffPair.m_Width;
485  }
486 
492  inline void SetCustomDiffPairGap( int aGap )
493  {
494  m_customDiffPair.m_Gap = aGap;
495  }
496 
501  inline int GetCustomDiffPairGap()
502  {
503  return m_customDiffPair.m_Gap;
504  }
505 
512  inline void SetCustomDiffPairViaGap( int aGap )
513  {
514  m_customDiffPair.m_ViaGap = aGap;
515  }
516 
521  {
522  return m_customDiffPair.m_ViaGap > 0 ? m_customDiffPair.m_ViaGap : m_customDiffPair.m_Gap;
523  }
524 
530  inline void UseCustomDiffPairDimensions( bool aEnabled )
531  {
532  m_useCustomDiffPair = aEnabled;
533  }
534 
538  inline bool UseCustomDiffPairDimensions() const
539  {
540  return m_useCustomDiffPair;
541  }
542 
547  int GetCurrentDiffPairWidth() const;
548 
553  int GetCurrentDiffPairGap() const;
554 
560  int GetCurrentDiffPairViaGap() const;
561 
566  void SetMinHoleSeparation( int aDistance );
567 
571  void SetCopperEdgeClearance( int aDistance );
572 
581  void SetSilkClearance( int aDistance );
582 
588  inline LSET GetEnabledLayers() const
589  {
590  return m_enabledLayers;
591  }
592 
598  void SetEnabledLayers( LSET aMask );
599 
606  inline bool IsLayerEnabled( PCB_LAYER_ID aLayerId ) const
607  {
608  if( aLayerId >= 0 && aLayerId < PCB_LAYER_ID_COUNT )
609  return m_enabledLayers[aLayerId];
610 
611  return false;
612  }
613 
617  inline int GetCopperLayerCount() const
618  {
619  return m_copperLayerCount;
620  }
621 
627  void SetCopperLayerCount( int aNewLayerCount );
628 
629  inline int GetBoardThickness() const { return m_boardThickness; }
630  inline void SetBoardThickness( int aThickness ) { m_boardThickness = aThickness; }
631 
632  /*
633  * Return an epsilon which accounts for rounding errors, etc.
634  *
635  * While currently an advanced cfg, going through this API allows us to easily change
636  * it to board-specific if so desired.
637  */
638  int GetDRCEpsilon() const;
639 
645  int GetHolePlatingThickness() const;
646 
650  int GetLineThickness( PCB_LAYER_ID aLayer ) const;
651 
655  wxSize GetTextSize( PCB_LAYER_ID aLayer ) const;
656 
660  int GetTextThickness( PCB_LAYER_ID aLayer ) const;
661 
662  bool GetTextItalic( PCB_LAYER_ID aLayer ) const;
663  bool GetTextUpright( PCB_LAYER_ID aLayer ) const;
664 
665  int GetLayerClass( PCB_LAYER_ID aLayer ) const;
666 
667 private:
668  void initFromOther( const BOARD_DESIGN_SETTINGS& aOther );
669 
670  bool migrateSchema0to1();
671 
672 public:
673  // Note: the first value in each dimensions list is the current netclass value
674  std::vector<int> m_TrackWidthList;
675  std::vector<VIA_DIMENSION> m_ViasDimensionsList;
676  std::vector<DIFF_PAIR_DIMENSION> m_DiffPairDimensionsList;
677 
681 
682  bool m_UseConnectedTrackWidth; // use width of existing track when creating a new,
683  // connected track
684  int m_MinClearance; // overall min clearance
685  int m_TrackMinWidth; // overall min track width
686  int m_ViasMinAnnularWidth; // overall minimum width of the via copper ring
687  int m_ViasMinSize; // overall vias (not micro vias) min diameter
688  int m_MinThroughDrill; // through hole (not micro vias) min drill diameter
689  int m_MicroViasMinSize; // micro vias min diameter
690  int m_MicroViasMinDrill; // micro vias min drill diameter
692  int m_HoleClearance; // Hole to copper clearance
693  int m_HoleToHoleMin; // Min width of web between two drilled holes
695 
696  std::shared_ptr<DRC_ENGINE> m_DRCEngine;
697  std::map<int, SEVERITY> m_DRCSeverities; // Map from DRCErrorCode to SEVERITY
698  std::set<wxString> m_DrcExclusions;
699 
714 
715  // When smoothing the zone's outline there's the question of external fillets (that is, those
716  // applied to concave corners). While it seems safer to never have copper extend outside the
717  // zone outline, 5.1.x and prior did indeed fill them so we leave the mode available.
719 
720  // Maximum error allowed when approximating circles and arcs to segments
722 
723  // Global mask margins:
724  int m_SolderMaskMargin; // Solder mask margin
725  int m_SolderMaskMinWidth; // Solder mask min width (2 areas closer than this
726  // width are merged)
727  int m_SolderPasteMargin; // Solder paste margin absolute value
728  double m_SolderPasteMarginRatio; // Solder mask margin ratio value of pad size
729  // The final margin is the sum of these 2 values
730 
731  // Variables used in footprint editing (default value in item/footprint creation)
732  std::vector<TEXT_ITEM_INFO> m_DefaultFPTextItems;
733 
734  // Arrays of default values for the various layer classes.
735  int m_LineThickness[ LAYER_CLASS_COUNT ];
736  wxSize m_TextSize[ LAYER_CLASS_COUNT ];
737  int m_TextThickness[ LAYER_CLASS_COUNT ];
738  bool m_TextItalic[ LAYER_CLASS_COUNT ];
739  bool m_TextUpright[ LAYER_CLASS_COUNT ];
740 
741  // Default values for dimension objects
750 
751  // Miscellaneous
752  wxPoint m_AuxOrigin;
753  wxPoint m_GridOrigin;
754 
755  std::unique_ptr<PAD> m_Pad_Master; // A dummy pad to store all default parameters
756  // when importing values or creating a new pad
757 
758  // Set to true if the board has a stackup management.
759  // If not set a default basic stackup will be used to generate the gbrjob file.
760  // Could be removed later, or at least always set to true
762 
765 
766 private:
767  // Indices into the trackWidth, viaSizes and diffPairDimensions lists.
768  // The 0 index is always the current netclass value(s)
770  unsigned m_viaSizeIndex;
771  unsigned m_diffPairIndex;
772 
773  // Custom values for track/via sizes (specified via dialog instead of netclass or lists)
777 
778  // Custom values for differential pairs (specified via dialog instead of netclass/lists)
781 
783 
785 
787 
791 
797 
800 
803 
806 };
807 
808 #endif // BOARD_DESIGN_SETTINGS_H_
bool UseNetClassTrack() const
Return true if netclass values should be used to obtain appropriate track width.
void SetNetClasses(NETCLASSES *aNetClasses)
void SetCopperLayerCount(int aNewLayerCount)
Set the copper layer count to aNewLayerCount.
Container to handle a stock of specific vias each with unique diameter and drill sizes in the BOARD c...
int m_ZoneFillVersion
Option to select different fill algorithms.
void SetEnabledLayers(LSET aMask)
Change the bit-mask of enabled layers to aMask.
void SetCopperEdgeClearance(int aDistance)
DIM_TEXT_POSITION
Where to place the text on a dimension.
Definition: pcb_dimension.h:47
bool UseCustomDiffPairDimensions() const
void SetTrackWidthIndex(unsigned aIndex)
Set the current track width list index to aIndex.
wxString m_currentNetClassName
Current net class name used to display netclass info.
std::vector< TEXT_ITEM_INFO > m_DefaultFPTextItems
wxPoint m_GridOrigin
origin for grid offsets
Manage layers needed to make a physical board.
void SetCustomDiffPairViaGap(int aGap)
Sets custom via gap for differential pairs (i.e.
BOARD_DESIGN_SETTINGS(JSON_SETTINGS *aParent, const std::string &aPath)
std::vector< int > m_TrackWidthList
void SetDefaultZoneSettings(const ZONE_SETTINGS &aSettings)
bool IsLayerEnabled(PCB_LAYER_ID aLayerId) const
Test whether a given layer aLayerId is enabled.
BOARD_STACKUP m_stackup
the description of layers stackup, for board fabrication only physical layers are in layers stackup.
bool UseNetClassDiffPair() const
Return true if netclass values should be used to obtain appropriate diff pair dimensions.
std::vector< DIFF_PAIR_DIMENSION > m_DiffPairDimensionsList
void SetCustomViaDrill(int aDrill)
Sets custom size for via drill (i.e.
int GetHolePlatingThickness() const
Pad & via drills are finish size.
NETCLASSES m_internalNetClasses
Net classes that are loaded from the board file before these were stored in the project.
bool Ignore(int aDRCErrorCode)
Return true if the DRC error code's severity is SEVERITY_IGNORE.
void UseCustomDiffPairDimensions(bool aEnabled)
Enables/disables custom differential pair dimensions.
bool operator<(const VIA_DIMENSION &aOther) const
int m_DimensionPrecision
Number of digits after the decimal.
ZONE_SETTINGS m_defaultZoneSettings
The default settings that will be used for new zones.
bool operator<(const DIFF_PAIR_DIMENSION &aOther) const
const BOARD_STACKUP & GetStackupDescriptor() const
DIFF_PAIR_DIMENSION m_customDiffPair
int GetTextThickness(PCB_LAYER_ID aLayer) const
Return the default text thickness from the layer class for the given layer.
TEXT_ITEM_INFO(const wxString &aText, bool aVisible, int aLayer)
void SetBoardThickness(int aThickness)
VIATYPE m_CurrentViaType
(VIA_BLIND_BURIED, VIA_THROUGH, VIA_MICROVIA)
Container to handle a stock of specific differential pairs each with unique track width,...
std::unique_ptr< PAD > m_Pad_Master
void SetCustomViaSize(int aSize)
Set custom size for via diameter (i.e.
DIM_TEXT_POSITION m_DimensionTextPosition
DIM_UNITS_MODE m_DimensionUnitsMode
int GetLayerClass(PCB_LAYER_ID aLayer) const
bool GetTextUpright(PCB_LAYER_ID aLayer) const
bool GetTextItalic(PCB_LAYER_ID aLayer) const
int GetLineThickness(PCB_LAYER_ID aLayer) const
Return the default graphic segment thickness from the layer class for the given layer.
void SetViaSizeIndex(unsigned aIndex)
Set the current via size list index to aIndex.
NESTED_SETTINGS is a JSON_SETTINGS that lives inside a JSON_SETTINGS.
BOARD_STACKUP & GetStackupDescriptor()
LSET is a set of PCB_LAYER_IDs.
Definition: layer_ids.h:502
A container for NETCLASS instances.
Definition: netclass.h:218
DIM_UNITS_MODE
Used for storing the units selection in the file because EDA_UNITS alone doesn't cut it.
Definition: pcb_dimension.h:57
const wxString & GetCurrentNetClassName() const
unsigned GetViaSizeIndex() const
void SetMinHoleSeparation(int aDistance)
DIM_UNITS_FORMAT
How to display the units in a dimension's text.
Definition: pcb_dimension.h:39
bool UseNetClassVia() const
Return true if netclass values should be used to obtain appropriate via size.
void SetCustomDiffPairWidth(int aWidth)
Sets custom track width for differential pairs (i.e.
bool LoadFromFile(const wxString &aDirectory="") override
Loads the backing file from disk and then calls Load()
A collection of nets and the parameters used to route or test these nets.
Definition: netclass.h:46
unsigned GetTrackWidthIndex() const
Functions to provide common constants and other functions to assist in making a consistent UI.
BOARD_DESIGN_SETTINGS & operator=(const BOARD_DESIGN_SETTINGS &aOther)
NETCLASSES & GetNetClasses() const
bool m_BlindBuriedViaAllowed
true to allow blind/buried vias
SEVERITY GetSeverity(int aDRCErrorCode)
void SetDiffPairIndex(unsigned aIndex)
void SetCustomDiffPairGap(int aGap)
Sets custom gap for differential pairs (i.e.
SEVERITY
NETCLASS * GetDefaultPtr() const
Definition: netclass.h:258
void SetCustomTrackWidth(int aWidth)
Sets custom width for track (i.e.
ZONE_SETTINGS handles zones parameters.
Definition: zone_settings.h:67
bool operator==(const VIA_DIMENSION &aOther) const
bool m_UseHeightForLengthCalcs
Enable inclusion of stackup height in track length measurements and length tuning.
VIATYPE
Definition: pcb_track.h:60
LSET GetEnabledLayers() const
Return a bit-mask of all the layers that are enabled.
PCB_LAYER_ID
A quick note on layer IDs:
Definition: layer_ids.h:64
std::map< int, SEVERITY > m_DRCSeverities
NETCLASS * GetDefault() const
void SetSilkClearance(int aDistance)
Set the minimum distance between silk items to aValue.
void initFromOther(const BOARD_DESIGN_SETTINGS &aOther)
std::vector< VIA_DIMENSION > m_ViasDimensionsList
DIFF_PAIR_DIMENSION(int aWidth, int aGap, int aViaGap)
DIM_UNITS_FORMAT m_DimensionUnitsFormat
bool operator==(const DIFF_PAIR_DIMENSION &aOther) const
VIA_DIMENSION(int aDiameter, int aDrill)
unsigned GetDiffPairIndex() const
NETCLASSES * m_netClasses
This will point to m_internalNetClasses until it is repointed to the project after load.
ZONE_SETTINGS & GetDefaultZoneSettings()
int m_copperLayerCount
Number of copper layers for this design.
bool m_MicroViasAllowed
true to allow micro vias
Definition: pad.h:57
std::set< wxString > m_DrcExclusions
LSET m_enabledLayers
Bit-mask for layer enabling.
wxPoint m_AuxOrigin
origin for plot exports
wxSize GetTextSize(PCB_LAYER_ID aLayer) const
Return the default text size from the layer class for the given layer.
int m_boardThickness
Board thickness for 3D viewer.
std::shared_ptr< DRC_ENGINE > m_DRCEngine
int GetCustomDiffPairGap()
Function GetCustomDiffPairGap.
void UseCustomTrackViaSize(bool aEnabled)
Enables/disables custom track/via size settings.
Container for design settings for a BOARD object.