KiCad PCB EDA Suite
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board_design_settings.h
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1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright (C) 2009-2019 Jean-Pierre Charras, jp.charras at wanadoo.fr
5 * Copyright (C) 1992-2023 KiCad Developers, see AUTHORS.txt for contributors.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, you may find one here:
19 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
20 * or you may search the http://www.gnu.org website for the version 2 license,
21 * or you may write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
23 */
24
25#ifndef BOARD_DESIGN_SETTINGS_H_
26#define BOARD_DESIGN_SETTINGS_H_
27
28#include <memory>
29
30#include <netclass.h>
33#include <drc/drc_engine.h>
35#include <widgets/ui_common.h>
36#include <zone_settings.h>
38#include <router/pns_meander.h>
39
40
41#define DEFAULT_SILK_LINE_WIDTH 0.1
42#define DEFAULT_COPPER_LINE_WIDTH 0.2
43#define DEFAULT_EDGE_WIDTH 0.05
44#define DEFAULT_COURTYARD_WIDTH 0.05
45#define DEFAULT_LINE_WIDTH 0.10
46
47#define DEFAULT_SILK_TEXT_SIZE 1.0
48#define DEFAULT_COPPER_TEXT_SIZE 1.5
49#define DEFAULT_TEXT_SIZE 1.0
50
51#define DEFAULT_SILK_TEXT_WIDTH 0.1
52#define DEFAULT_COPPER_TEXT_WIDTH 0.30
53#define DEFAULT_TEXT_WIDTH 0.15
54
55#define DEFAULT_DIMENSION_ARROW_LENGTH 50 // mils, for legacy purposes
56#define DEFAULT_DIMENSION_EXTENSION_OFFSET 0.5
57
58// Board thickness, mainly for 3D view:
59#define DEFAULT_BOARD_THICKNESS_MM 1.6
60
61#define DEFAULT_PCB_EDGE_THICKNESS 0.15
62
63// soldermask to pad clearance. The default is 0 because usually board houses
64// create a clearance depending on their fab process: mask material, color, price, etc.
65#define DEFAULT_SOLDERMASK_EXPANSION 0.0
66
67#define DEFAULT_SOLDERMASK_TO_COPPER_CLEARANCE 0.0
68
69#define DEFAULT_SOLDERMASK_MIN_WIDTH 0.0
70
71#define DEFAULT_SOLDERPASTE_CLEARANCE 0.0
72#define DEFAULT_SOLDERPASTE_RATIO 0.0
73
74#define DEFAULT_CUSTOMTRACKWIDTH 0.2
75#define DEFAULT_CUSTOMDPAIRWIDTH 0.125
76#define DEFAULT_CUSTOMDPAIRGAP 0.18
77#define DEFAULT_CUSTOMDPAIRVIAGAP 0.18
78
79#define DEFAULT_MEANDER_SPACING 0.6
80#define DEFAULT_DP_MEANDER_SPACING 1.0
81
82#define DEFAULT_MINCLEARANCE 0.0 // overall min clearance
83#define DEFAULT_MINCONNECTION 0.0 // overall min connection width
84#define DEFAULT_TRACKMINWIDTH 0.0 // track width min value
85#define DEFAULT_VIASMINSIZE 0.5 // vias (not micro vias) min diameter
86#define DEFAULT_MINTHROUGHDRILL 0.3 // through holes (not micro vias) min drill diameter
87#define DEFAULT_MICROVIASMINSIZE 0.2 // micro vias (not vias) min diameter
88#define DEFAULT_MICROVIASMINDRILL 0.1 // micro vias (not vias) min drill diameter
89#define DEFAULT_HOLETOHOLEMIN 0.25 // minimum web thickness between two drilled holes
90#define DEFAULT_HOLECLEARANCE 0.25 // copper-to-hole clearance (from IPC level A)
91
92#define DEFAULT_COPPEREDGECLEARANCE 0.5 // clearance between copper items and edge cuts
93#define LEGACY_COPPEREDGECLEARANCE -0.01 // A flag to indicate the legacy method (based
94 // on edge cut line thicknesses) should be used.
95#define DEFAULT_SILKCLEARANCE 0.0
96
97#define DEFAULT_MINRESOLVEDSPOKES 2 // Fewer resolved spokes indicates a starved thermal
98
99#define MINIMUM_ERROR_SIZE_MM 0.001 // For arc approximation
100#define MAXIMUM_ERROR_SIZE_MM 0.1 // For arc approximation
101
102// Min/max values used in dialogs to validate settings
103#define MINIMUM_LINE_WIDTH_MM 0.005 // minimal line width entered in a dialog
104#define MAXIMUM_LINE_WIDTH_MM 100.0 // max line width entered in a dialog
105
106
112{
113 int m_Diameter; // <= 0 means use Netclass via diameter
114 int m_Drill; // <= 0 means use Netclass via drill
115
117 {
118 m_Diameter = 0;
119 m_Drill = 0;
120 }
121
122 VIA_DIMENSION( int aDiameter, int aDrill )
123 {
124 m_Diameter = aDiameter;
125 m_Drill = aDrill;
126 }
127
128 bool operator==( const VIA_DIMENSION& aOther ) const
129 {
130 return ( m_Diameter == aOther.m_Diameter ) && ( m_Drill == aOther.m_Drill );
131 }
132
133 bool operator!=( const VIA_DIMENSION& aOther ) const { return !operator==( aOther ); }
134
135 bool operator<( const VIA_DIMENSION& aOther ) const
136 {
137 if( m_Diameter != aOther.m_Diameter )
138 return m_Diameter < aOther.m_Diameter;
139
140 return m_Drill < aOther.m_Drill;
141 }
142};
143
144
150{
151 int m_Width; // <= 0 means use Netclass differential pair width
152 int m_Gap; // <= 0 means use Netclass differential pair gap
153 int m_ViaGap; // <= 0 means use Netclass differential pair via gap
154
156 {
157 m_Width = 0;
158 m_Gap = 0;
159 m_ViaGap = 0;
160 }
161
162 DIFF_PAIR_DIMENSION( int aWidth, int aGap, int aViaGap )
163 {
164 m_Width = aWidth;
165 m_Gap = aGap;
166 m_ViaGap = aViaGap;
167 }
168
169 bool operator==( const DIFF_PAIR_DIMENSION& aOther ) const
170 {
171 return ( m_Width == aOther.m_Width )
172 && ( m_Gap == aOther.m_Gap )
173 && ( m_ViaGap == aOther.m_ViaGap );
174 }
175
176 bool operator!=( const DIFF_PAIR_DIMENSION& aOther ) const { return !operator==( aOther ); }
177
178 bool operator<( const DIFF_PAIR_DIMENSION& aOther ) const
179 {
180 if( m_Width != aOther.m_Width )
181 return m_Width < aOther.m_Width;
182
183 if( m_Gap != aOther.m_Gap )
184 return m_Gap < aOther.m_Gap;
185
186 return m_ViaGap < aOther.m_ViaGap;
187 }
188};
189
190
191enum
192{
199
202
203
205{
206 wxString m_Text;
209
210 TEXT_ITEM_INFO( const wxString& aText, bool aVisible, int aLayer )
211 {
212 m_Text = aText;
213 m_Visible = aVisible;
214 m_Layer = aLayer;
215 }
216
217 bool operator==( const TEXT_ITEM_INFO& aOther ) const
218 {
219 return m_Text.IsSameAs( aOther.m_Text )
220 && ( m_Visible == aOther.m_Visible )
221 && ( m_Layer == aOther.m_Layer );
222 }
223};
224
225
226// forward declaration from class_track.h
227enum class VIATYPE : int;
228
229// forward declarations from dimension.h
230enum class DIM_UNITS_FORMAT : int;
231enum class DIM_TEXT_POSITION : int;
232enum class DIM_UNITS_MODE : int;
233enum class DIM_PRECISION : int;
234
235class PAD;
236
241{
242public:
243 BOARD_DESIGN_SETTINGS( JSON_SETTINGS* aParent, const std::string& aPath );
244
245 virtual ~BOARD_DESIGN_SETTINGS();
246
247 bool operator==( const BOARD_DESIGN_SETTINGS& aOther ) const;
248 bool operator!=( const BOARD_DESIGN_SETTINGS& aOther ) const
249 {
250 return !operator==( aOther );
251 }
252
254
256
257 bool LoadFromFile( const wxString& aDirectory = "" ) override;
258
261
263 {
264 return &m_TeardropParamsList;
265 }
266
267 SEVERITY GetSeverity( int aDRCErrorCode );
268
272 bool Ignore( int aDRCErrorCode );
273
275 {
277 }
278
279 void SetDefaultZoneSettings( const ZONE_SETTINGS& aSettings )
280 {
281 m_defaultZoneSettings = aSettings;
282 }
283
287 inline const wxString& GetCurrentNetClassName() const
288 {
290 }
291
295 inline bool UseNetClassTrack() const
296 {
297 return ( m_trackWidthIndex == 0 && !m_useCustomTrackVia );
298 }
299
303 inline bool UseNetClassVia() const
304 {
305 return ( m_viaSizeIndex == 0 && !m_useCustomTrackVia );
306 }
307
311 inline bool UseNetClassDiffPair() const
312 {
313 return ( m_diffPairIndex == 0 && !m_useCustomDiffPair );
314 }
315
319 int GetBiggestClearanceValue() const;
320
324 int GetSmallestClearanceValue() const;
325
329 inline unsigned GetTrackWidthIndex() const { return m_trackWidthIndex; }
330
336 void SetTrackWidthIndex( unsigned aIndex );
337
343 int GetCurrentTrackWidth() const;
344
353 inline void SetCustomTrackWidth( int aWidth )
354 {
355 m_customTrackWidth = aWidth;
356 }
357
361 inline int GetCustomTrackWidth() const
362 {
363 return m_customTrackWidth;
364 }
365
369 inline unsigned GetViaSizeIndex() const
370 {
371 return m_viaSizeIndex;
372 }
373
379 void SetViaSizeIndex( unsigned aIndex );
380
386 int GetCurrentViaSize() const;
387
396 inline void SetCustomViaSize( int aSize )
397 {
399 }
400
404 inline int GetCustomViaSize() const
405 {
407 }
408
414 int GetCurrentViaDrill() const;
415
424 inline void SetCustomViaDrill( int aDrill )
425 {
426 m_customViaSize.m_Drill = aDrill;
427 }
428
432 inline int GetCustomViaDrill() const
433 {
435 }
436
445 inline void UseCustomTrackViaSize( bool aEnabled )
446 {
447 m_useCustomTrackVia = aEnabled;
448 }
449
453 inline bool UseCustomTrackViaSize() const
454 {
455 return m_useCustomTrackVia;
456 }
457
461 inline unsigned GetDiffPairIndex() const { return m_diffPairIndex; }
462
466 void SetDiffPairIndex( unsigned aIndex );
467
474 inline void SetCustomDiffPairWidth( int aWidth )
475 {
476 m_customDiffPair.m_Width = aWidth;
477 }
478
483 {
485 }
486
492 inline void SetCustomDiffPairGap( int aGap )
493 {
494 m_customDiffPair.m_Gap = aGap;
495 }
496
502 {
503 return m_customDiffPair.m_Gap;
504 }
505
512 inline void SetCustomDiffPairViaGap( int aGap )
513 {
515 }
516
521 {
523 }
524
530 inline void UseCustomDiffPairDimensions( bool aEnabled )
531 {
532 m_useCustomDiffPair = aEnabled;
533 }
534
538 inline bool UseCustomDiffPairDimensions() const
539 {
540 return m_useCustomDiffPair;
541 }
542
547 int GetCurrentDiffPairWidth() const;
548
553 int GetCurrentDiffPairGap() const;
554
560 int GetCurrentDiffPairViaGap() const;
561
567 inline LSET GetEnabledLayers() const
568 {
569 return m_enabledLayers;
570 }
571
577 void SetEnabledLayers( LSET aMask );
578
585 inline bool IsLayerEnabled( PCB_LAYER_ID aLayerId ) const
586 {
587 if( aLayerId >= 0 && aLayerId < PCB_LAYER_ID_COUNT )
588 return m_enabledLayers[aLayerId];
589
590 return false;
591 }
592
596 inline int GetCopperLayerCount() const
597 {
598 return m_copperLayerCount;
599 }
600
606 void SetCopperLayerCount( int aNewLayerCount );
607
612 inline int GetBoardThickness() const { return m_boardThickness; }
613 inline void SetBoardThickness( int aThickness ) { m_boardThickness = aThickness; }
614
615 /*
616 * Return an epsilon which accounts for rounding errors, etc.
617 *
618 * While currently an advanced cfg, going through this API allows us to easily change
619 * it to board-specific if so desired.
620 */
621 int GetDRCEpsilon() const;
622
628 int GetHolePlatingThickness() const;
629
633 int GetLineThickness( PCB_LAYER_ID aLayer ) const;
634
638 VECTOR2I GetTextSize( PCB_LAYER_ID aLayer ) const;
639
643 int GetTextThickness( PCB_LAYER_ID aLayer ) const;
644
645 bool GetTextItalic( PCB_LAYER_ID aLayer ) const;
646 bool GetTextUpright( PCB_LAYER_ID aLayer ) const;
647
648 int GetLayerClass( PCB_LAYER_ID aLayer ) const;
649
650 void SetAuxOrigin( const VECTOR2I& aOrigin ) { m_auxOrigin = aOrigin; }
651 const VECTOR2I& GetAuxOrigin() { return m_auxOrigin; }
652
653 void SetGridOrigin( const VECTOR2I& aOrigin ) { m_gridOrigin = aOrigin; }
655
656private:
657 void initFromOther( const BOARD_DESIGN_SETTINGS& aOther );
658
659 bool migrateSchema0to1();
660
661public:
662 // Note: the first value in each dimensions list is the current netclass value
663 std::vector<int> m_TrackWidthList;
664 std::vector<VIA_DIMENSION> m_ViasDimensionsList;
665 std::vector<DIFF_PAIR_DIMENSION> m_DiffPairDimensionsList;
666
671
675
677
678 bool m_UseConnectedTrackWidth; // use width of existing track when creating a new,
679 // connected track
680 bool m_TempOverrideTrackWidth; // use selected track width temporarily even when
681 // using connected track width
682 int m_MinClearance; // overall min clearance
683 int m_MinConn; // overall min connection width
684 int m_TrackMinWidth; // overall min track width
685 int m_ViasMinAnnularWidth; // overall minimum width of the via copper ring
686 int m_ViasMinSize; // overall vias (not micro vias) min diameter
687 int m_MinThroughDrill; // through hole (not micro vias) min drill diameter
688 int m_MicroViasMinSize; // micro vias min diameter
689 int m_MicroViasMinDrill; // micro vias min drill diameter
691 int m_HoleClearance; // Hole to copper clearance
692 int m_HoleToHoleMin; // Min width of web between two drilled holes
693 int m_SilkClearance; // Min dist between two silk items
694 int m_MinResolvedSpokes; // Min spoke count to not be a starved thermal
695 int m_MinSilkTextHeight; // Min text height for silkscreen layers
696 int m_MinSilkTextThickness; // Min text thickness for silkscreen layers
697
698 std::shared_ptr<DRC_ENGINE> m_DRCEngine;
699 std::map<int, SEVERITY> m_DRCSeverities; // Map from DRCErrorCode to SEVERITY
700 std::set<wxString> m_DrcExclusions;
701
702 // When smoothing the zone's outline there's the question of external fillets (that is, those
703 // applied to concave corners). While it seems safer to never have copper extend outside the
704 // zone outline, 5.1.x and prior did indeed fill them so we leave the mode available.
706
707 // Maximum error allowed when approximating circles and arcs to segments
709
710 // Global mask margins:
711 int m_SolderMaskExpansion; // Solder mask inflation around the pad or via
712 int m_SolderMaskMinWidth; // Solder mask min width (2 areas closer than this
713 // width are merged)
714 int m_SolderMaskToCopperClearance; // Min distance allowed from copper to a mask
715 // aperture of another net
716
717 int m_SolderPasteMargin; // Solder paste margin absolute value
718 double m_SolderPasteMarginRatio; // Solder mask margin ratio value of pad size
719 // The final margin is the sum of these 2 values
721
722 std::shared_ptr<NET_SETTINGS> m_NetSettings;
723
724 // Variables used in footprint editing (default value in item/footprint creation)
725 std::vector<TEXT_ITEM_INFO> m_DefaultFPTextItems;
726
727 // Arrays of default values for the various layer classes.
733
734 // Default values for dimension objects
743
747
748 // Miscellaneous
749 std::unique_ptr<PAD> m_Pad_Master; // A dummy pad to store all default parameters
750 // when importing values or creating a new pad
751
752 // Set to true if the board has a stackup management.
753 // If not set a default basic stackup will be used to generate the gbrjob file.
754 // Could be removed later, or at least always set to true
756
759
760private:
763
764 // Indices into the trackWidth, viaSizes and diffPairDimensions lists.
765 // The 0 index is always the current netclass value(s)
769
770 // Custom values for track/via sizes (specified via dialog instead of netclass or lists)
774
775 // Custom values for differential pairs (specified via dialog instead of netclass/lists)
778
780
782
784
788
794
797};
798
799#endif // BOARD_DESIGN_SETTINGS_H_
@ LAYER_CLASS_OTHERS
@ LAYER_CLASS_COUNT
@ LAYER_CLASS_FAB
@ LAYER_CLASS_COURTYARD
@ LAYER_CLASS_SILK
@ LAYER_CLASS_COPPER
@ LAYER_CLASS_EDGES
Container for design settings for a BOARD object.
DIM_PRECISION m_DimensionPrecision
Number of digits after the decimal.
TEARDROP_PARAMETERS_LIST * GetTeadropParamsList()
void UseCustomTrackViaSize(bool aEnabled)
Enables/disables custom track/via size settings.
std::vector< TEXT_ITEM_INFO > m_DefaultFPTextItems
int GetHolePlatingThickness() const
Pad & via drills are finish size.
void SetCustomDiffPairWidth(int aWidth)
Sets custom track width for differential pairs (i.e.
VIATYPE m_CurrentViaType
(VIA_BLIND_BURIED, VIA_THROUGH, VIA_MICROVIA)
void SetDiffPairIndex(unsigned aIndex)
int GetCustomDiffPairGap()
Function GetCustomDiffPairGap.
std::shared_ptr< NET_SETTINGS > m_NetSettings
bool operator==(const BOARD_DESIGN_SETTINGS &aOther) const
void SetCustomTrackWidth(int aWidth)
Sets custom width for track (i.e.
DIM_UNITS_FORMAT m_DimensionUnitsFormat
void initFromOther(const BOARD_DESIGN_SETTINGS &aOther)
bool GetTextUpright(PCB_LAYER_ID aLayer) const
std::map< int, SEVERITY > m_DRCSeverities
VECTOR2I m_gridOrigin
origin for grid offsets
int GetTextThickness(PCB_LAYER_ID aLayer) const
Return the default text thickness from the layer class for the given layer.
void SetGridOrigin(const VECTOR2I &aOrigin)
VECTOR2I m_auxOrigin
origin for plot exports
bool m_TextUpright[LAYER_CLASS_COUNT]
bool GetTextItalic(PCB_LAYER_ID aLayer) const
const wxString & GetCurrentNetClassName() const
wxString m_currentNetClassName
Current net class name used to display netclass info.
std::shared_ptr< DRC_ENGINE > m_DRCEngine
void SetEnabledLayers(LSET aMask)
Change the bit-mask of enabled layers to aMask.
std::vector< DIFF_PAIR_DIMENSION > m_DiffPairDimensionsList
LSET GetEnabledLayers() const
Return a bit-mask of all the layers that are enabled.
std::set< wxString > m_DrcExclusions
bool Ignore(int aDRCErrorCode)
Return true if the DRC error code's severity is SEVERITY_IGNORE.
void SetCustomViaSize(int aSize)
Set custom size for via diameter (i.e.
int GetBoardThickness() const
The full thickness of the board including copper and masks.
const VECTOR2I & GetGridOrigin()
const VECTOR2I & GetAuxOrigin()
std::unique_ptr< PAD > m_Pad_Master
void SetCustomDiffPairGap(int aGap)
Sets custom gap for differential pairs (i.e.
bool IsLayerEnabled(PCB_LAYER_ID aLayerId) const
Test whether a given layer aLayerId is enabled.
void SetTrackWidthIndex(unsigned aIndex)
Set the current track width list index to aIndex.
TEARDROP_PARAMETERS_LIST m_TeardropParamsList
The parameters of teardrops for the different teardrop targets (via/pad, track end) 3 set of paramete...
void SetAuxOrigin(const VECTOR2I &aOrigin)
void SetViaSizeIndex(unsigned aIndex)
Set the current via size list index to aIndex.
bool operator!=(const BOARD_DESIGN_SETTINGS &aOther) const
unsigned GetTrackWidthIndex() const
int GetLayerClass(PCB_LAYER_ID aLayer) const
PNS::MEANDER_SETTINGS m_DiffPairMeanderSettings
bool UseNetClassVia() const
Return true if netclass values should be used to obtain appropriate via size.
BOARD_STACKUP & GetStackupDescriptor()
int m_boardThickness
Board thickness for 3D viewer.
int m_copperLayerCount
Number of copper layers for this design.
unsigned GetViaSizeIndex() const
bool UseNetClassTrack() const
Return true if netclass values should be used to obtain appropriate track width.
bool UseNetClassDiffPair() const
Return true if netclass values should be used to obtain appropriate diff pair dimensions.
void SetCustomViaDrill(int aDrill)
Sets custom size for via drill (i.e.
bool LoadFromFile(const wxString &aDirectory="") override
Loads the backing file from disk and then calls Load()
void SetDefaultZoneSettings(const ZONE_SETTINGS &aSettings)
PNS::MEANDER_SETTINGS m_SingleTrackMeanderSettings
int m_TextThickness[LAYER_CLASS_COUNT]
ZONE_SETTINGS m_defaultZoneSettings
The default settings that will be used for new zones.
const BOARD_STACKUP & GetStackupDescriptor() const
void UseCustomDiffPairDimensions(bool aEnabled)
Enables/disables custom differential pair dimensions.
bool UseCustomDiffPairDimensions() const
SEVERITY GetSeverity(int aDRCErrorCode)
std::vector< int > m_TrackWidthList
unsigned GetDiffPairIndex() const
DIFF_PAIR_DIMENSION m_customDiffPair
int m_LineThickness[LAYER_CLASS_COUNT]
VECTOR2I GetTextSize(PCB_LAYER_ID aLayer) const
Return the default text size from the layer class for the given layer.
void SetBoardThickness(int aThickness)
int GetLineThickness(PCB_LAYER_ID aLayer) const
Return the default graphic segment thickness from the layer class for the given layer.
ZONE_SETTINGS & GetDefaultZoneSettings()
bool m_UseHeightForLengthCalcs
Enable inclusion of stackup height in track length measurements and length tuning.
VECTOR2I m_TextSize[LAYER_CLASS_COUNT]
PNS::MEANDER_SETTINGS m_SkewMeanderSettings
LSET m_enabledLayers
Bit-mask for layer enabling.
bool m_TextItalic[LAYER_CLASS_COUNT]
void SetCopperLayerCount(int aNewLayerCount)
Set the copper layer count to aNewLayerCount.
DIM_TEXT_POSITION m_DimensionTextPosition
BOARD_STACKUP m_stackup
the description of layers stackup, for board fabrication only physical layers are in layers stackup.
DIM_UNITS_MODE m_DimensionUnitsMode
std::vector< VIA_DIMENSION > m_ViasDimensionsList
BOARD_DESIGN_SETTINGS & operator=(const BOARD_DESIGN_SETTINGS &aOther)
void SetCustomDiffPairViaGap(int aGap)
Sets custom via gap for differential pairs (i.e.
Manage layers needed to make a physical board.
LSET is a set of PCB_LAYER_IDs.
Definition: layer_ids.h:573
NESTED_SETTINGS is a JSON_SETTINGS that lives inside a JSON_SETTINGS.
Definition: pad.h:59
Dimensions for the meandering algorithm.
Definition: pns_meander.h:68
TEARDROP_PARAMETERS_LIST is a helper class to handle the list of TEARDROP_PARAMETERS needed to build ...
ZONE_SETTINGS handles zones parameters.
Definition: zone_settings.h:71
PCB_LAYER_ID
A quick note on layer IDs:
Definition: layer_ids.h:60
@ PCB_LAYER_ID_COUNT
Definition: layer_ids.h:138
DIM_TEXT_POSITION
Where to place the text on a dimension.
Definition: pcb_dimension.h:62
DIM_UNITS_FORMAT
How to display the units in a dimension's text.
Definition: pcb_dimension.h:40
DIM_UNITS_MODE
Used for storing the units selection in the file because EDA_UNITS alone doesn't cut it.
Definition: pcb_dimension.h:72
DIM_PRECISION
Definition: pcb_dimension.h:47
VIATYPE
Definition: pcb_track.h:64
SEVERITY
Container to handle a stock of specific differential pairs each with unique track width,...
DIFF_PAIR_DIMENSION(int aWidth, int aGap, int aViaGap)
bool operator<(const DIFF_PAIR_DIMENSION &aOther) const
bool operator==(const DIFF_PAIR_DIMENSION &aOther) const
bool operator!=(const DIFF_PAIR_DIMENSION &aOther) const
TEXT_ITEM_INFO(const wxString &aText, bool aVisible, int aLayer)
bool operator==(const TEXT_ITEM_INFO &aOther) const
Container to handle a stock of specific vias each with unique diameter and drill sizes in the BOARD c...
bool operator==(const VIA_DIMENSION &aOther) const
VIA_DIMENSION(int aDiameter, int aDrill)
bool operator!=(const VIA_DIMENSION &aOther) const
bool operator<(const VIA_DIMENSION &aOther) const
Functions to provide common constants and other functions to assist in making a consistent UI.
Class ZONE_SETTINGS used to handle zones parameters in dialogs.