KiCad PCB EDA Suite
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board_design_settings.h
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1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright (C) 2009-2019 Jean-Pierre Charras, jp.charras at wanadoo.fr
5 * Copyright The KiCad Developers, see AUTHORS.txt for contributors.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, you may find one here:
19 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
20 * or you may search the http://www.gnu.org website for the version 2 license,
21 * or you may write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
23 */
24
25#ifndef BOARD_DESIGN_SETTINGS_H_
26#define BOARD_DESIGN_SETTINGS_H_
27
28#include <memory>
29
30#include <netclass.h>
33#include <drc/drc_engine.h>
34#include <lset.h>
36#include <widgets/ui_common.h>
37#include <zone_settings.h>
39#include <router/pns_meander.h>
40
41
42#define DEFAULT_SILK_LINE_WIDTH 0.1
43#define DEFAULT_COPPER_LINE_WIDTH 0.2
44#define DEFAULT_EDGE_WIDTH 0.05
45#define DEFAULT_COURTYARD_WIDTH 0.05
46#define DEFAULT_LINE_WIDTH 0.10
47
48#define DEFAULT_SILK_TEXT_SIZE 1.0
49#define DEFAULT_COPPER_TEXT_SIZE 1.5
50#define DEFAULT_TEXT_SIZE 1.0
51
52#define DEFAULT_SILK_TEXT_WIDTH 0.1
53#define DEFAULT_COPPER_TEXT_WIDTH 0.30
54#define DEFAULT_TEXT_WIDTH 0.15
55
56#define DEFAULT_DIMENSION_ARROW_LENGTH 50 // mils, for legacy purposes
57#define DEFAULT_DIMENSION_EXTENSION_OFFSET 0.5
58
59// Board thickness, mainly for 3D view:
60#define DEFAULT_BOARD_THICKNESS_MM 1.6
61
62#define DEFAULT_PCB_EDGE_THICKNESS 0.15
63
64// soldermask to pad clearance. The default is 0 because usually board houses
65// create a clearance depending on their fab process: mask material, color, price, etc.
66#define DEFAULT_SOLDERMASK_EXPANSION 0.0
67
68#define DEFAULT_SOLDERMASK_TO_COPPER_CLEARANCE 0.0
69
70#define DEFAULT_SOLDERMASK_MIN_WIDTH 0.0
71
72#define DEFAULT_SOLDERPASTE_CLEARANCE 0.0
73#define DEFAULT_SOLDERPASTE_RATIO 0.0
74
75#define DEFAULT_CUSTOMTRACKWIDTH 0.2
76#define DEFAULT_CUSTOMDPAIRWIDTH 0.125
77#define DEFAULT_CUSTOMDPAIRGAP 0.18
78#define DEFAULT_CUSTOMDPAIRVIAGAP 0.18
79
80#define DEFAULT_MEANDER_SPACING 0.6
81#define DEFAULT_DP_MEANDER_SPACING 1.0
82
83#define DEFAULT_MINCLEARANCE 0.0 // overall min clearance
84#define DEFAULT_MINCONNECTION 0.0 // overall min connection width
85#define DEFAULT_TRACKMINWIDTH 0.0 // track width min value
86#define DEFAULT_VIASMINSIZE 0.5 // vias (not micro vias) min diameter
87#define DEFAULT_MINTHROUGHDRILL 0.3 // through holes (not micro vias) min drill diameter
88#define DEFAULT_MICROVIASMINSIZE 0.2 // micro vias (not vias) min diameter
89#define DEFAULT_MICROVIASMINDRILL 0.1 // micro vias (not vias) min drill diameter
90#define DEFAULT_HOLETOHOLEMIN 0.25 // minimum web thickness between two drilled holes
91#define DEFAULT_HOLECLEARANCE 0.25 // copper-to-hole clearance (from IPC level A)
92
93#define DEFAULT_COPPEREDGECLEARANCE 0.5 // clearance between copper items and edge cuts
94#define LEGACY_COPPEREDGECLEARANCE -0.01 // A flag to indicate the legacy method (based
95 // on edge cut line thicknesses) should be used.
96#define DEFAULT_SILKCLEARANCE 0.0
97#define DEFAULT_MINGROOVEWIDTH 0.0
98
99#define DEFAULT_MINRESOLVEDSPOKES 2 // Fewer resolved spokes indicates a starved thermal
100
101#define MINIMUM_ERROR_SIZE_MM 0.001 // For arc approximation
102#define MAXIMUM_ERROR_SIZE_MM 0.1 // For arc approximation
103
104#define MAXIMUM_CLEARANCE pcbIUScale.mmToIU( 500 ) // to prevent int-overflows
105
106// Min/max values used in dialogs to validate settings
107#define MINIMUM_LINE_WIDTH_MM 0.005 // minimal line width entered in a dialog
108#define MAXIMUM_LINE_WIDTH_MM 100.0 // max line width entered in a dialog
109
110// Default pad properties
111#define DEFAULT_PAD_WIDTH_MM 2.54 // master pad width
112#define DEFAULT_PAD_HEIGTH_MM 1.27 // master pad height
113#define DEFAULT_PAD_DRILL_DIAMETER_MM 0.8 // master pad drill diameter for PTH
114#define DEFAULT_PAD_RR_RADIUS_RATIO 0.15 // master pad corner radius ratio
115
121{
122 int m_Diameter; // <= 0 means use Netclass via diameter
123 int m_Drill; // <= 0 means use Netclass via drill
124
126 {
127 m_Diameter = 0;
128 m_Drill = 0;
129 }
130
131 VIA_DIMENSION( int aDiameter, int aDrill )
132 {
133 m_Diameter = aDiameter;
134 m_Drill = aDrill;
135 }
136
137 bool operator==( const VIA_DIMENSION& aOther ) const
138 {
139 return ( m_Diameter == aOther.m_Diameter ) && ( m_Drill == aOther.m_Drill );
140 }
141
142 bool operator!=( const VIA_DIMENSION& aOther ) const { return !operator==( aOther ); }
143
144 bool operator<( const VIA_DIMENSION& aOther ) const
145 {
146 if( m_Diameter != aOther.m_Diameter )
147 return m_Diameter < aOther.m_Diameter;
148
149 return m_Drill < aOther.m_Drill;
150 }
151};
152
153
159{
160 int m_Width; // <= 0 means use Netclass differential pair width
161 int m_Gap; // <= 0 means use Netclass differential pair gap
162 int m_ViaGap; // <= 0 means use Netclass differential pair via gap
163
165 {
166 m_Width = 0;
167 m_Gap = 0;
168 m_ViaGap = 0;
169 }
170
171 DIFF_PAIR_DIMENSION( int aWidth, int aGap, int aViaGap )
172 {
173 m_Width = aWidth;
174 m_Gap = aGap;
175 m_ViaGap = aViaGap;
176 }
177
178 bool operator==( const DIFF_PAIR_DIMENSION& aOther ) const
179 {
180 return ( m_Width == aOther.m_Width )
181 && ( m_Gap == aOther.m_Gap )
182 && ( m_ViaGap == aOther.m_ViaGap );
183 }
184
185 bool operator!=( const DIFF_PAIR_DIMENSION& aOther ) const { return !operator==( aOther ); }
186
187 bool operator<( const DIFF_PAIR_DIMENSION& aOther ) const
188 {
189 if( m_Width != aOther.m_Width )
190 return m_Width < aOther.m_Width;
191
192 if( m_Gap != aOther.m_Gap )
193 return m_Gap < aOther.m_Gap;
194
195 return m_ViaGap < aOther.m_ViaGap;
196 }
197};
198
199
200enum
201{
208
210};
211
212
214{
215 wxString m_Text;
218
219 TEXT_ITEM_INFO( const wxString& aText, bool aVisible, PCB_LAYER_ID aLayer )
220 {
221 m_Text = aText;
222 m_Visible = aVisible;
223 m_Layer = aLayer;
224 }
225
226 bool operator==( const TEXT_ITEM_INFO& aOther ) const
227 {
228 return m_Text.IsSameAs( aOther.m_Text )
229 && ( m_Visible == aOther.m_Visible )
230 && ( m_Layer == aOther.m_Layer );
231 }
232};
233
234
235// forward declaration from class_track.h
236enum class VIATYPE : int;
237
238// forward declarations from dimension.h
239enum class DIM_UNITS_FORMAT : int;
240enum class DIM_TEXT_POSITION : int;
241enum class DIM_UNITS_MODE : int;
242enum class DIM_PRECISION : int;
243
244class PAD;
245
250{
251public:
252 BOARD_DESIGN_SETTINGS( JSON_SETTINGS* aParent, const std::string& aPath );
253
254 virtual ~BOARD_DESIGN_SETTINGS();
255
256 bool operator==( const BOARD_DESIGN_SETTINGS& aOther ) const;
257 bool operator!=( const BOARD_DESIGN_SETTINGS& aOther ) const
258 {
259 return !operator==( aOther );
260 }
261
263
265
266 bool LoadFromFile( const wxString& aDirectory = "" ) override;
267
270
275
276 SEVERITY GetSeverity( int aDRCErrorCode );
277
281 bool Ignore( int aDRCErrorCode );
282
287
288 void SetDefaultZoneSettings( const ZONE_SETTINGS& aSettings )
289 {
290 m_defaultZoneSettings = aSettings;
291 }
292
296 inline const wxString& GetCurrentNetClassName() const
297 {
299 }
300
304 inline bool UseNetClassTrack() const
305 {
306 return ( m_trackWidthIndex == 0 && !m_useCustomTrackVia );
307 }
308
312 inline bool UseNetClassVia() const
313 {
314 return ( m_viaSizeIndex == 0 && !m_useCustomTrackVia );
315 }
316
320 inline bool UseNetClassDiffPair() const
321 {
322 return ( m_diffPairIndex == 0 && !m_useCustomDiffPair );
323 }
324
328 int GetBiggestClearanceValue() const;
329
333 int GetSmallestClearanceValue() const;
334
338 inline int GetTrackWidthIndex() const { return m_trackWidthIndex; }
339
345 void SetTrackWidthIndex( int aIndex );
346
352 int GetCurrentTrackWidth() const;
353
362 inline void SetCustomTrackWidth( int aWidth ) { m_customTrackWidth = aWidth; }
363 inline int GetCustomTrackWidth() const { return m_customTrackWidth; }
364
368 inline int GetViaSizeIndex() const { return m_viaSizeIndex; }
369
375 void SetViaSizeIndex( int aIndex );
376
382 int GetCurrentViaSize() const;
383
392 inline void SetCustomViaSize( int aSize )
393 {
394 m_customViaSize.m_Diameter = aSize;
395 }
396
400 inline int GetCustomViaSize() const
401 {
402 return m_customViaSize.m_Diameter;
403 }
404
410 int GetCurrentViaDrill() const;
411
420 inline void SetCustomViaDrill( int aDrill )
421 {
422 m_customViaSize.m_Drill = aDrill;
423 }
424
428 inline int GetCustomViaDrill() const
429 {
430 return m_customViaSize.m_Drill;
431 }
432
441 inline void UseCustomTrackViaSize( bool aEnabled )
442 {
443 m_useCustomTrackVia = aEnabled;
444 }
445
449 inline bool UseCustomTrackViaSize() const
450 {
451 return m_useCustomTrackVia;
452 }
453
457 inline int GetDiffPairIndex() const { return m_diffPairIndex; }
458
462 void SetDiffPairIndex( int aIndex );
463
470 inline void SetCustomDiffPairWidth( int aWidth )
471 {
472 m_customDiffPair.m_Width = aWidth;
473 }
474
479 {
480 return m_customDiffPair.m_Width;
481 }
482
488 inline void SetCustomDiffPairGap( int aGap )
489 {
490 m_customDiffPair.m_Gap = aGap;
491 }
492
498 {
499 return m_customDiffPair.m_Gap;
500 }
501
508 inline void SetCustomDiffPairViaGap( int aGap )
509 {
510 m_customDiffPair.m_ViaGap = aGap;
511 }
512
517 {
518 return m_customDiffPair.m_ViaGap > 0 ? m_customDiffPair.m_ViaGap : m_customDiffPair.m_Gap;
519 }
520
526 inline void UseCustomDiffPairDimensions( bool aEnabled )
527 {
528 m_useCustomDiffPair = aEnabled;
529 }
530
534 inline bool UseCustomDiffPairDimensions() const
535 {
536 return m_useCustomDiffPair;
537 }
538
543 int GetCurrentDiffPairWidth() const;
544
549 int GetCurrentDiffPairGap() const;
550
556 int GetCurrentDiffPairViaGap() const;
557
563 inline const LSET& GetEnabledLayers() const
564 {
565 return m_enabledLayers;
566 }
567
573 void SetEnabledLayers( const LSET& aMask );
574
581 inline bool IsLayerEnabled( PCB_LAYER_ID aLayerId ) const
582 {
583 if( aLayerId >= 0 && aLayerId < PCB_LAYER_ID_COUNT )
584 return m_enabledLayers[aLayerId];
585
586 return false;
587 }
588
592 inline int GetCopperLayerCount() const
593 {
594 return m_copperLayerCount;
595 }
596
602 void SetCopperLayerCount( int aNewLayerCount );
603
607 inline int GetUserDefinedLayerCount() const
608 {
610 }
611
617 void SetUserDefinedLayerCount( int aNewLayerCount );
618
623 inline int GetBoardThickness() const { return m_boardThickness; }
624 inline void SetBoardThickness( int aThickness ) { m_boardThickness = aThickness; }
625
632 int GetDRCEpsilon() const;
633
639 int GetHolePlatingThickness() const;
640
644 int GetLineThickness( PCB_LAYER_ID aLayer ) const;
645
649 VECTOR2I GetTextSize( PCB_LAYER_ID aLayer ) const;
650
654 int GetTextThickness( PCB_LAYER_ID aLayer ) const;
655
656 bool GetTextItalic( PCB_LAYER_ID aLayer ) const;
657 bool GetTextUpright( PCB_LAYER_ID aLayer ) const;
658
659 int GetLayerClass( PCB_LAYER_ID aLayer ) const;
660
661 void SetAuxOrigin( const VECTOR2I& aOrigin ) { m_auxOrigin = aOrigin; }
662 const VECTOR2I& GetAuxOrigin() const { return m_auxOrigin; }
663
664 void SetGridOrigin( const VECTOR2I& aOrigin ) { m_gridOrigin = aOrigin; }
665 const VECTOR2I& GetGridOrigin() const { return m_gridOrigin; }
666
667 void SetDefaultMasterPad();
668
669private:
670 void initFromOther( const BOARD_DESIGN_SETTINGS& aOther );
671
672 bool migrateSchema0to1();
673
674public:
675 // Note: the first value in each dimensions list is the current netclass value
676 std::vector<int> m_TrackWidthList;
677 std::vector<VIA_DIMENSION> m_ViasDimensionsList;
678 std::vector<DIFF_PAIR_DIMENSION> m_DiffPairDimensionsList;
679
686
690
692
693 bool m_UseConnectedTrackWidth; // use width of existing track when creating a new,
694 // connected track
695 bool m_TempOverrideTrackWidth; // use selected track width temporarily even when
696 // using connected track width
697 int m_MinClearance; // overall min
698 int m_MinGrooveWidth; // Minimum groove width for creepage checks
699 int m_MinConn; // overall min connection width
700 int m_TrackMinWidth; // overall min track width
701 int m_ViasMinAnnularWidth; // overall minimum width of the via copper ring
702 int m_ViasMinSize; // overall vias (not micro vias) min diameter
703 int m_MinThroughDrill; // through hole (not micro vias) min drill diameter
704 int m_MicroViasMinSize; // micro vias min diameter
705 int m_MicroViasMinDrill; // micro vias min drill diameter
707 int m_HoleClearance; // Hole to copper clearance
708 int m_HoleToHoleMin; // Min width of web between two drilled holes
709 int m_SilkClearance; // Min dist between two silk items
710 int m_MinResolvedSpokes; // Min spoke count to not be a starved thermal
711 int m_MinSilkTextHeight; // Min text height for silkscreen layers
712 int m_MinSilkTextThickness; // Min text thickness for silkscreen layers
713
714 std::shared_ptr<DRC_ENGINE> m_DRCEngine;
715 std::map<int, SEVERITY> m_DRCSeverities; // Map from DRCErrorCode to SEVERITY
716 std::set<wxString> m_DrcExclusions; // Serialized excluded DRC markers
717 std::map<wxString, wxString> m_DrcExclusionComments; // Map from serialization to comment
718
719 // When smoothing the zone's outline there's the question of external fillets (that is, those
720 // applied to concave corners). While it seems safer to never have copper extend outside the
721 // zone outline, 5.1.x and prior did indeed fill them so we leave the mode available.
723
724 // Maximum error allowed when approximating circles and arcs to segments
726
727 // Global mask margins:
728 int m_SolderMaskExpansion; // Solder mask inflation around the pad or via
729 int m_SolderMaskMinWidth; // Solder mask min width (2 areas closer than this
730 // width are merged)
731 int m_SolderMaskToCopperClearance; // Min distance allowed from copper to a mask
732 // aperture of another net
733
734 int m_SolderPasteMargin; // Solder paste margin absolute value
735 double m_SolderPasteMarginRatio; // Solder mask margin ratio value of pad size
736 // The final margin is the sum of these 2 values
738
739 bool m_TentViasFront; // The default tenting option if not overridden on an
740 bool m_TentViasBack; // individual via
741
742 bool m_CoverViasFront; // The default covering option if not overridden on an
743 bool m_CoverViasBack; // individual via
744
745 bool m_PlugViasFront; // The default plugging option if not overridden on an
746 bool m_PlugViasBack; // individual via
747
748 bool m_CapVias; // The default capping option if not overridden on an
749 // individual via
750
751 bool m_FillVias; // The default filling option if not overridden on ana
752 // individual via
753
754 std::shared_ptr<NET_SETTINGS> m_NetSettings;
755
756 // Variables used in footprint editing (default value in item/footprint creation)
757 std::vector<TEXT_ITEM_INFO> m_DefaultFPTextItems;
758
759 // Map between user layer default names and custom names
760 std::map<std::string, wxString> m_UserLayerNames;
761
762 // Arrays of default values for the various layer classes.
768
769 // Default values for dimension objects
778
782
783 // Miscellaneous
784 std::unique_ptr<PAD> m_Pad_Master; // A dummy pad to store all default parameters
785 // when importing values or creating a new pad
786
787 // Set to true if the board has a stackup management.
788 // If not set a default basic stackup will be used to generate the gbrjob file.
789 // Could be removed later, or at least always set to true
791
794
795private:
798
799 // Indices into the trackWidth, viaSizes and diffPairDimensions lists.
800 // The 0 index is always the current netclass value(s)
804
805 // Custom values for track/via sizes (specified via dialog instead of netclass or lists)
809
810 // Custom values for differential pairs (specified via dialog instead of netclass/lists)
813
815
817
819
821
825
833
836};
837
838#endif // BOARD_DESIGN_SETTINGS_H_
@ LAYER_CLASS_OTHERS
@ LAYER_CLASS_COUNT
@ LAYER_CLASS_FAB
@ LAYER_CLASS_COURTYARD
@ LAYER_CLASS_SILK
@ LAYER_CLASS_COPPER
@ LAYER_CLASS_EDGES
Container for design settings for a BOARD object.
DIM_PRECISION m_DimensionPrecision
Number of digits after the decimal.
TEARDROP_PARAMETERS_LIST * GetTeadropParamsList()
void UseCustomTrackViaSize(bool aEnabled)
Enables/disables custom track/via size settings.
std::vector< TEXT_ITEM_INFO > m_DefaultFPTextItems
int GetHolePlatingThickness() const
Pad & via drills are finish size.
void SetCustomDiffPairWidth(int aWidth)
Sets custom track width for differential pairs (i.e.
VIATYPE m_CurrentViaType
(VIA_BLIND_BURIED, VIA_THROUGH, VIA_MICROVIA)
int GetCustomDiffPairGap()
Function GetCustomDiffPairGap.
void SetEnabledLayers(const LSET &aMask)
Change the bit-mask of enabled layers to aMask.
std::shared_ptr< NET_SETTINGS > m_NetSettings
bool operator==(const BOARD_DESIGN_SETTINGS &aOther) const
void SetCustomTrackWidth(int aWidth)
Sets custom width for track (i.e.
std::map< wxString, wxString > m_DrcExclusionComments
DIM_UNITS_FORMAT m_DimensionUnitsFormat
void initFromOther(const BOARD_DESIGN_SETTINGS &aOther)
bool GetTextUpright(PCB_LAYER_ID aLayer) const
std::map< int, SEVERITY > m_DRCSeverities
VECTOR2I m_gridOrigin
origin for grid offsets
int GetTextThickness(PCB_LAYER_ID aLayer) const
Return the default text thickness from the layer class for the given layer.
void SetGridOrigin(const VECTOR2I &aOrigin)
VECTOR2I m_auxOrigin
origin for plot exports
bool m_TextUpright[LAYER_CLASS_COUNT]
BOARD_DESIGN_SETTINGS(JSON_SETTINGS *aParent, const std::string &aPath)
bool GetTextItalic(PCB_LAYER_ID aLayer) const
const wxString & GetCurrentNetClassName() const
wxString m_currentNetClassName
Current net class name used to display netclass info.
void SetViaSizeIndex(int aIndex)
Set the current via size list index to aIndex.
std::shared_ptr< DRC_ENGINE > m_DRCEngine
std::vector< DIFF_PAIR_DIMENSION > m_DiffPairDimensionsList
std::set< wxString > m_DrcExclusions
bool Ignore(int aDRCErrorCode)
Return true if the DRC error code's severity is SEVERITY_IGNORE.
void SetCustomViaSize(int aSize)
Set custom size for via diameter (i.e.
const LSET & GetEnabledLayers() const
Return a bit-mask of all the layers that are enabled.
std::map< std::string, wxString > m_UserLayerNames
const VECTOR2I & GetGridOrigin() const
int GetBoardThickness() const
The full thickness of the board including copper and masks.
std::unique_ptr< PAD > m_Pad_Master
void SetCustomDiffPairGap(int aGap)
Sets custom gap for differential pairs (i.e.
bool IsLayerEnabled(PCB_LAYER_ID aLayerId) const
Test whether a given layer aLayerId is enabled.
TEARDROP_PARAMETERS_LIST m_TeardropParamsList
The parameters of teardrops for the different teardrop targets (via/pad, track end).
void SetUserDefinedLayerCount(int aNewLayerCount)
Set the number of user defined layers to aNewLayerCount.
void SetAuxOrigin(const VECTOR2I &aOrigin)
const VECTOR2I & GetAuxOrigin() const
bool operator!=(const BOARD_DESIGN_SETTINGS &aOther) const
int GetDRCEpsilon() const
Return an epsilon which accounts for rounding errors, etc.
int GetLayerClass(PCB_LAYER_ID aLayer) const
PNS::MEANDER_SETTINGS m_DiffPairMeanderSettings
bool UseNetClassVia() const
Return true if netclass values should be used to obtain appropriate via size.
BOARD_STACKUP & GetStackupDescriptor()
int m_boardThickness
Board thickness for 3D viewer.
int m_copperLayerCount
Number of copper layers for this design.
bool UseNetClassTrack() const
Return true if netclass values should be used to obtain appropriate track width.
int m_userDefinedLayerCount
Number of user defined layers for this design.
bool UseNetClassDiffPair() const
Return true if netclass values should be used to obtain appropriate diff pair dimensions.
void SetCustomViaDrill(int aDrill)
Sets custom size for via drill (i.e.
bool LoadFromFile(const wxString &aDirectory="") override
Loads the backing file from disk and then calls Load()
void SetDefaultZoneSettings(const ZONE_SETTINGS &aSettings)
PNS::MEANDER_SETTINGS m_SingleTrackMeanderSettings
void SetTrackWidthIndex(int aIndex)
Set the current track width list index to aIndex.
int m_TextThickness[LAYER_CLASS_COUNT]
ZONE_SETTINGS m_defaultZoneSettings
The default settings that will be used for new zones.
const BOARD_STACKUP & GetStackupDescriptor() const
void UseCustomDiffPairDimensions(bool aEnabled)
Enables/disables custom differential pair dimensions.
SEVERITY GetSeverity(int aDRCErrorCode)
std::vector< int > m_TrackWidthList
DIFF_PAIR_DIMENSION m_customDiffPair
int m_LineThickness[LAYER_CLASS_COUNT]
VECTOR2I GetTextSize(PCB_LAYER_ID aLayer) const
Return the default text size from the layer class for the given layer.
void SetBoardThickness(int aThickness)
int GetLineThickness(PCB_LAYER_ID aLayer) const
Return the default graphic segment thickness from the layer class for the given layer.
ZONE_SETTINGS & GetDefaultZoneSettings()
bool m_UseHeightForLengthCalcs
Enable inclusion of stackup height in track length measurements and length tuning.
VECTOR2I m_TextSize[LAYER_CLASS_COUNT]
PNS::MEANDER_SETTINGS m_SkewMeanderSettings
LSET m_enabledLayers
Bit-mask for layer enabling.
bool m_TextItalic[LAYER_CLASS_COUNT]
void SetCopperLayerCount(int aNewLayerCount)
Set the copper layer count to aNewLayerCount.
DIM_TEXT_POSITION m_DimensionTextPosition
BOARD_STACKUP m_stackup
The description of layers stackup, for board fabrication only physical layers are in layers stackup.
std::vector< VIA_DIMENSION > m_ViasDimensionsList
BOARD_DESIGN_SETTINGS & operator=(const BOARD_DESIGN_SETTINGS &aOther)
void SetCustomDiffPairViaGap(int aGap)
Sets custom via gap for differential pairs (i.e.
Manage layers needed to make a physical board.
JSON_SETTINGS(const wxString &aFilename, SETTINGS_LOC aLocation, int aSchemaVersion)
LSET is a set of PCB_LAYER_IDs.
Definition lset.h:37
NESTED_SETTINGS(const std::string &aName, int aSchemaVersion, JSON_SETTINGS *aParent, const std::string &aPath, bool aLoadFromFile=true)
Definition pad.h:54
Dimensions for the meandering algorithm.
Definition pns_meander.h:68
TEARDROP_PARAMETERS_LIST is a helper class to handle the list of TEARDROP_PARAMETERS needed to build ...
ZONE_SETTINGS handles zones parameters.
PCB_LAYER_ID
A quick note on layer IDs:
Definition layer_ids.h:60
@ PCB_LAYER_ID_COUNT
Definition layer_ids.h:171
DIM_TEXT_POSITION
Where to place the text on a dimension.
DIM_UNITS_FORMAT
How to display the units in a dimension's text.
DIM_UNITS_MODE
Used for storing the units selection in the file because EDA_UNITS alone doesn't cut it.
DIM_PRECISION
VIATYPE
Definition pcb_track.h:66
SEVERITY
Container to handle a stock of specific differential pairs each with unique track width,...
DIFF_PAIR_DIMENSION(int aWidth, int aGap, int aViaGap)
bool operator<(const DIFF_PAIR_DIMENSION &aOther) const
bool operator==(const DIFF_PAIR_DIMENSION &aOther) const
bool operator!=(const DIFF_PAIR_DIMENSION &aOther) const
TEXT_ITEM_INFO(const wxString &aText, bool aVisible, PCB_LAYER_ID aLayer)
bool operator==(const TEXT_ITEM_INFO &aOther) const
Container to handle a stock of specific vias each with unique diameter and drill sizes in the BOARD c...
bool operator==(const VIA_DIMENSION &aOther) const
VIA_DIMENSION(int aDiameter, int aDrill)
bool operator!=(const VIA_DIMENSION &aOther) const
bool operator<(const VIA_DIMENSION &aOther) const
Functions to provide common constants and other functions to assist in making a consistent UI.
VECTOR2< int32_t > VECTOR2I
Definition vector2d.h:695
Class ZONE_SETTINGS used to handle zones parameters in dialogs.