KiCad PCB EDA Suite
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board_design_settings.h
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1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright (C) 2009-2019 Jean-Pierre Charras, jp.charras at wanadoo.fr
5 * Copyright The KiCad Developers, see AUTHORS.txt for contributors.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, you may find one here:
19 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
20 * or you may search the http://www.gnu.org website for the version 2 license,
21 * or you may write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
23 */
24
25#pragma once
26
27#include <memory>
28
29#include <netclass.h>
32#include <drc/drc_engine.h>
33#include <lset.h>
35#include <widgets/ui_common.h>
36#include <zone_settings.h>
38#include <router/pns_meander.h>
39
40
41#define DEFAULT_SILK_LINE_WIDTH 0.1
42#define DEFAULT_COPPER_LINE_WIDTH 0.2
43#define DEFAULT_EDGE_WIDTH 0.05
44#define DEFAULT_COURTYARD_WIDTH 0.05
45#define DEFAULT_LINE_WIDTH 0.10
46
47#define DEFAULT_SILK_TEXT_SIZE 1.0
48#define DEFAULT_COPPER_TEXT_SIZE 1.5
49#define DEFAULT_TEXT_SIZE 1.0
50
51#define DEFAULT_SILK_TEXT_WIDTH 0.1
52#define DEFAULT_COPPER_TEXT_WIDTH 0.30
53#define DEFAULT_TEXT_WIDTH 0.15
54
55#define DEFAULT_DIMENSION_ARROW_LENGTH 50 // mils, for legacy purposes
56#define DEFAULT_DIMENSION_EXTENSION_OFFSET 0.5
57
58// Board thickness, mainly for 3D view:
59#define DEFAULT_BOARD_THICKNESS_MM 1.6
60
61#define DEFAULT_PCB_EDGE_THICKNESS 0.15
62
63// soldermask to pad clearance. The default is 0 because usually board houses
64// create a clearance depending on their fab process: mask material, color, price, etc.
65#define DEFAULT_SOLDERMASK_EXPANSION 0.0
66
67#define DEFAULT_SOLDERMASK_TO_COPPER_CLEARANCE 0.0
68
69#define DEFAULT_SOLDERMASK_MIN_WIDTH 0.0
70
71#define DEFAULT_SOLDERPASTE_CLEARANCE 0.0
72#define DEFAULT_SOLDERPASTE_RATIO 0.0
73
74#define DEFAULT_CUSTOMTRACKWIDTH 0.2
75#define DEFAULT_CUSTOMDPAIRWIDTH 0.125
76#define DEFAULT_CUSTOMDPAIRGAP 0.18
77#define DEFAULT_CUSTOMDPAIRVIAGAP 0.18
78
79#define DEFAULT_MEANDER_SPACING 0.6
80#define DEFAULT_DP_MEANDER_SPACING 1.0
81
82#define DEFAULT_MINCLEARANCE 0.0 // overall min clearance
83#define DEFAULT_MINCONNECTION 0.0 // overall min connection width
84#define DEFAULT_TRACKMINWIDTH 0.0 // track width min value
85#define DEFAULT_VIASMINSIZE 0.5 // vias (not micro vias) min diameter
86#define DEFAULT_MINTHROUGHDRILL 0.3 // through holes (not micro vias) min drill diameter
87#define DEFAULT_MICROVIASMINSIZE 0.2 // micro vias (not vias) min diameter
88#define DEFAULT_MICROVIASMINDRILL 0.1 // micro vias (not vias) min drill diameter
89#define DEFAULT_HOLETOHOLEMIN 0.25 // minimum web thickness between two drilled holes
90#define DEFAULT_HOLECLEARANCE 0.25 // copper-to-hole clearance (from IPC level A)
91
92#define DEFAULT_COPPEREDGECLEARANCE 0.5 // clearance between copper items and edge cuts
93#define LEGACY_COPPEREDGECLEARANCE -0.01 // A flag to indicate the legacy method (based
94 // on edge cut line thicknesses) should be used.
95#define DEFAULT_SILKCLEARANCE 0.0
96#define DEFAULT_MINGROOVEWIDTH 0.0
97
98#define DEFAULT_MINRESOLVEDSPOKES 2 // Fewer resolved spokes indicates a starved thermal
99
100#define MINIMUM_ERROR_SIZE_MM 0.001 // For arc approximation
101#define MAXIMUM_ERROR_SIZE_MM 0.1 // For arc approximation
102
103#define MAXIMUM_CLEARANCE pcbIUScale.mmToIU( 500 ) // to prevent int-overflows
104
105// Min/max values used in dialogs to validate settings
106#define MINIMUM_LINE_WIDTH_MM 0.005 // minimal line width entered in a dialog
107#define MAXIMUM_LINE_WIDTH_MM 100.0 // max line width entered in a dialog
108
109// Default pad properties
110#define DEFAULT_PAD_WIDTH_MM 2.54 // master pad width
111#define DEFAULT_PAD_HEIGTH_MM 1.27 // master pad height
112#define DEFAULT_PAD_DRILL_DIAMETER_MM 0.8 // master pad drill diameter for PTH
113#define DEFAULT_PAD_RR_RADIUS_RATIO 0.15 // master pad corner radius ratio
114
120{
121 int m_Diameter; // <= 0 means use Netclass via diameter
122 int m_Drill; // <= 0 means use Netclass via drill
123
125 {
126 m_Diameter = 0;
127 m_Drill = 0;
128 }
129
130 VIA_DIMENSION( int aDiameter, int aDrill )
131 {
132 m_Diameter = aDiameter;
133 m_Drill = aDrill;
134 }
135
136 bool operator==( const VIA_DIMENSION& aOther ) const
137 {
138 return ( m_Diameter == aOther.m_Diameter ) && ( m_Drill == aOther.m_Drill );
139 }
140
141 bool operator!=( const VIA_DIMENSION& aOther ) const { return !operator==( aOther ); }
142
143 bool operator<( const VIA_DIMENSION& aOther ) const
144 {
145 if( m_Diameter != aOther.m_Diameter )
146 return m_Diameter < aOther.m_Diameter;
147
148 return m_Drill < aOther.m_Drill;
149 }
150};
151
152
158{
159 int m_Width; // <= 0 means use Netclass differential pair width
160 int m_Gap; // <= 0 means use Netclass differential pair gap
161 int m_ViaGap; // <= 0 means use Netclass differential pair via gap
162
164 {
165 m_Width = 0;
166 m_Gap = 0;
167 m_ViaGap = 0;
168 }
169
170 DIFF_PAIR_DIMENSION( int aWidth, int aGap, int aViaGap )
171 {
172 m_Width = aWidth;
173 m_Gap = aGap;
174 m_ViaGap = aViaGap;
175 }
176
177 bool operator==( const DIFF_PAIR_DIMENSION& aOther ) const
178 {
179 return ( m_Width == aOther.m_Width )
180 && ( m_Gap == aOther.m_Gap )
181 && ( m_ViaGap == aOther.m_ViaGap );
182 }
183
184 bool operator!=( const DIFF_PAIR_DIMENSION& aOther ) const { return !operator==( aOther ); }
185
186 bool operator<( const DIFF_PAIR_DIMENSION& aOther ) const
187 {
188 if( m_Width != aOther.m_Width )
189 return m_Width < aOther.m_Width;
190
191 if( m_Gap != aOther.m_Gap )
192 return m_Gap < aOther.m_Gap;
193
194 return m_ViaGap < aOther.m_ViaGap;
195 }
196};
197
198
199enum
200{
207
209};
210
211
213{
214 wxString m_Text;
217
218 TEXT_ITEM_INFO( const wxString& aText, bool aVisible, PCB_LAYER_ID aLayer )
219 {
220 m_Text = aText;
221 m_Visible = aVisible;
222 m_Layer = aLayer;
223 }
224
225 bool operator==( const TEXT_ITEM_INFO& aOther ) const
226 {
227 return m_Text.IsSameAs( aOther.m_Text )
228 && ( m_Visible == aOther.m_Visible )
229 && ( m_Layer == aOther.m_Layer );
230 }
231};
232
233
234// forward declaration from class_track.h
235enum class VIATYPE : int;
236
237// forward declarations from dimension.h
238enum class DIM_UNITS_FORMAT : int;
239enum class DIM_TEXT_POSITION : int;
240enum class DIM_UNITS_MODE : int;
241enum class DIM_PRECISION : int;
242
243class PAD;
244
249{
250public:
251 BOARD_DESIGN_SETTINGS( JSON_SETTINGS* aParent, const std::string& aPath );
252
253 virtual ~BOARD_DESIGN_SETTINGS();
254
255 bool operator==( const BOARD_DESIGN_SETTINGS& aOther ) const;
256 bool operator!=( const BOARD_DESIGN_SETTINGS& aOther ) const
257 {
258 return !operator==( aOther );
259 }
260
262
264
265 bool LoadFromFile( const wxString& aDirectory = "" ) override;
266
269
274
275 SEVERITY GetSeverity( int aDRCErrorCode );
276
280 bool Ignore( int aDRCErrorCode );
281
286
287 void SetDefaultZoneSettings( const ZONE_SETTINGS& aSettings )
288 {
289 m_defaultZoneSettings = aSettings;
290 }
291
295 inline const wxString& GetCurrentNetClassName() const
296 {
298 }
299
303 inline bool UseNetClassTrack() const
304 {
305 return ( m_trackWidthIndex == 0 && !m_useCustomTrackVia );
306 }
307
311 inline bool UseNetClassVia() const
312 {
313 return ( m_viaSizeIndex == 0 && !m_useCustomTrackVia );
314 }
315
319 inline bool UseNetClassDiffPair() const
320 {
321 return ( m_diffPairIndex == 0 && !m_useCustomDiffPair );
322 }
323
327 int GetBiggestClearanceValue() const;
328
332 int GetSmallestClearanceValue() const;
333
337 inline int GetTrackWidthIndex() const { return m_trackWidthIndex; }
338
344 void SetTrackWidthIndex( int aIndex );
345
351 int GetCurrentTrackWidth() const;
352
361 inline void SetCustomTrackWidth( int aWidth ) { m_customTrackWidth = aWidth; }
362 inline int GetCustomTrackWidth() const { return m_customTrackWidth; }
363
367 inline int GetViaSizeIndex() const { return m_viaSizeIndex; }
368
374 void SetViaSizeIndex( int aIndex );
375
381 int GetCurrentViaSize() const;
382
391 inline void SetCustomViaSize( int aSize )
392 {
393 m_customViaSize.m_Diameter = aSize;
394 }
395
399 inline int GetCustomViaSize() const
400 {
401 return m_customViaSize.m_Diameter;
402 }
403
409 int GetCurrentViaDrill() const;
410
419 inline void SetCustomViaDrill( int aDrill )
420 {
421 m_customViaSize.m_Drill = aDrill;
422 }
423
427 inline int GetCustomViaDrill() const
428 {
429 return m_customViaSize.m_Drill;
430 }
431
440 inline void UseCustomTrackViaSize( bool aEnabled )
441 {
442 m_useCustomTrackVia = aEnabled;
443 }
444
448 inline bool UseCustomTrackViaSize() const
449 {
450 return m_useCustomTrackVia;
451 }
452
456 inline int GetDiffPairIndex() const { return m_diffPairIndex; }
457
461 void SetDiffPairIndex( int aIndex );
462
469 inline void SetCustomDiffPairWidth( int aWidth )
470 {
471 m_customDiffPair.m_Width = aWidth;
472 }
473
478 {
479 return m_customDiffPair.m_Width;
480 }
481
487 inline void SetCustomDiffPairGap( int aGap )
488 {
489 m_customDiffPair.m_Gap = aGap;
490 }
491
497 {
498 return m_customDiffPair.m_Gap;
499 }
500
507 inline void SetCustomDiffPairViaGap( int aGap )
508 {
509 m_customDiffPair.m_ViaGap = aGap;
510 }
511
516 {
517 return m_customDiffPair.m_ViaGap > 0 ? m_customDiffPair.m_ViaGap : m_customDiffPair.m_Gap;
518 }
519
525 inline void UseCustomDiffPairDimensions( bool aEnabled )
526 {
527 m_useCustomDiffPair = aEnabled;
528 }
529
533 inline bool UseCustomDiffPairDimensions() const
534 {
535 return m_useCustomDiffPair;
536 }
537
542 int GetCurrentDiffPairWidth() const;
543
548 int GetCurrentDiffPairGap() const;
549
555 int GetCurrentDiffPairViaGap() const;
556
562 inline const LSET& GetEnabledLayers() const
563 {
564 return m_enabledLayers;
565 }
566
572 void SetEnabledLayers( const LSET& aMask );
573
580 inline bool IsLayerEnabled( PCB_LAYER_ID aLayerId ) const
581 {
582 if( aLayerId >= 0 && aLayerId < PCB_LAYER_ID_COUNT )
583 return m_enabledLayers[aLayerId];
584
585 return false;
586 }
587
591 inline int GetCopperLayerCount() const
592 {
593 return m_copperLayerCount;
594 }
595
601 void SetCopperLayerCount( int aNewLayerCount );
602
606 inline int GetUserDefinedLayerCount() const
607 {
609 }
610
616 void SetUserDefinedLayerCount( int aNewLayerCount );
617
622 inline int GetBoardThickness() const { return m_boardThickness; }
623 inline void SetBoardThickness( int aThickness ) { m_boardThickness = aThickness; }
624
631 int GetDRCEpsilon() const;
632
638 int GetHolePlatingThickness() const;
639
643 int GetLineThickness( PCB_LAYER_ID aLayer ) const;
644
648 VECTOR2I GetTextSize( PCB_LAYER_ID aLayer ) const;
649
653 int GetTextThickness( PCB_LAYER_ID aLayer ) const;
654
655 bool GetTextItalic( PCB_LAYER_ID aLayer ) const;
656 bool GetTextUpright( PCB_LAYER_ID aLayer ) const;
657
658 int GetLayerClass( PCB_LAYER_ID aLayer ) const;
659
660 void SetAuxOrigin( const VECTOR2I& aOrigin ) { m_auxOrigin = aOrigin; }
661 const VECTOR2I& GetAuxOrigin() const { return m_auxOrigin; }
662
663 void SetGridOrigin( const VECTOR2I& aOrigin ) { m_gridOrigin = aOrigin; }
664 const VECTOR2I& GetGridOrigin() const { return m_gridOrigin; }
665
666 void SetDefaultMasterPad();
667
668private:
669 void initFromOther( const BOARD_DESIGN_SETTINGS& aOther );
670
671 bool migrateSchema0to1();
672
673public:
674 // Note: the first value in each dimensions list is the current netclass value
675 std::vector<int> m_TrackWidthList;
676 std::vector<VIA_DIMENSION> m_ViasDimensionsList;
677 std::vector<DIFF_PAIR_DIMENSION> m_DiffPairDimensionsList;
678
685
689
691
692 bool m_UseConnectedTrackWidth; // use width of existing track when creating a new,
693 // connected track
694 bool m_TempOverrideTrackWidth; // use selected track width temporarily even when
695 // using connected track width
696 int m_MinClearance; // overall min
697 int m_MinGrooveWidth; // Minimum groove width for creepage checks
698 int m_MinConn; // overall min connection width
699 int m_TrackMinWidth; // overall min track width
700 int m_ViasMinAnnularWidth; // overall minimum width of the via copper ring
701 int m_ViasMinSize; // overall vias (not micro vias) min diameter
702 int m_MinThroughDrill; // through hole (not micro vias) min drill diameter
703 int m_MicroViasMinSize; // micro vias min diameter
704 int m_MicroViasMinDrill; // micro vias min drill diameter
706 int m_HoleClearance; // Hole to copper clearance
707 int m_HoleToHoleMin; // Min width of web between two drilled holes
708 int m_SilkClearance; // Min dist between two silk items
709 int m_MinResolvedSpokes; // Min spoke count to not be a starved thermal
710 int m_MinSilkTextHeight; // Min text height for silkscreen layers
711 int m_MinSilkTextThickness; // Min text thickness for silkscreen layers
712
713 std::shared_ptr<DRC_ENGINE> m_DRCEngine;
714 std::map<int, SEVERITY> m_DRCSeverities; // Map from DRCErrorCode to SEVERITY
715 std::set<wxString> m_DrcExclusions; // Serialized excluded DRC markers
716 std::map<wxString, wxString> m_DrcExclusionComments; // Map from serialization to comment
717
718 // When smoothing the zone's outline there's the question of external fillets (that is, those
719 // applied to concave corners). While it seems safer to never have copper extend outside the
720 // zone outline, 5.1.x and prior did indeed fill them so we leave the mode available.
722
723 // Maximum error allowed when approximating circles and arcs to segments
725
726 // Global mask margins:
727 int m_SolderMaskExpansion; // Solder mask inflation around the pad or via
728 int m_SolderMaskMinWidth; // Solder mask min width (2 areas closer than this
729 // width are merged)
730 int m_SolderMaskToCopperClearance; // Min distance allowed from copper to a mask
731 // aperture of another net
732
733 int m_SolderPasteMargin; // Solder paste margin absolute value
734 double m_SolderPasteMarginRatio; // Solder mask margin ratio value of pad size
735 // The final margin is the sum of these 2 values
737
738 bool m_TentViasFront; // The default tenting option if not overridden on an
739 bool m_TentViasBack; // individual via
740
741 bool m_CoverViasFront; // The default covering option if not overridden on an
742 bool m_CoverViasBack; // individual via
743
744 bool m_PlugViasFront; // The default plugging option if not overridden on an
745 bool m_PlugViasBack; // individual via
746
747 bool m_CapVias; // The default capping option if not overridden on an
748 // individual via
749
750 bool m_FillVias; // The default filling option if not overridden on ana
751 // individual via
752
753 std::shared_ptr<NET_SETTINGS> m_NetSettings;
754
755 // Variables used in footprint editing (default value in item/footprint creation)
756 std::vector<TEXT_ITEM_INFO> m_DefaultFPTextItems;
757
758 // Map between user layer default names and custom names
759 std::map<std::string, wxString> m_UserLayerNames;
760
761 // Default zone hatching offsets
762 std::map<PCB_LAYER_ID, ZONE_LAYER_PROPERTIES> m_ZoneLayerProperties;
763
764 // Arrays of default values for the various layer classes.
770
771 // Default values for dimension objects
780
786
787 // Miscellaneous
788 std::unique_ptr<PAD> m_Pad_Master; // A dummy pad to store all default parameters
789 // when importing values or creating a new pad
790
791 // Set to true if the board has a stackup management.
792 // If not set a default basic stackup will be used to generate the gbrjob file.
793 // Could be removed later, or at least always set to true
795
798
799private:
802
803 // Indices into the trackWidth, viaSizes and diffPairDimensions lists.
804 // The 0 index is always the current netclass value(s)
808
809 // Custom values for track/via sizes (specified via dialog instead of netclass or lists)
813
814 // Custom values for differential pairs (specified via dialog instead of netclass/lists)
817
821
823
827
835
838};
@ LAYER_CLASS_OTHERS
@ LAYER_CLASS_COUNT
@ LAYER_CLASS_FAB
@ LAYER_CLASS_COURTYARD
@ LAYER_CLASS_SILK
@ LAYER_CLASS_COPPER
@ LAYER_CLASS_EDGES
Container for design settings for a BOARD object.
DIM_PRECISION m_DimensionPrecision
Number of digits after the decimal.
TEARDROP_PARAMETERS_LIST * GetTeadropParamsList()
void UseCustomTrackViaSize(bool aEnabled)
Enables/disables custom track/via size settings.
std::vector< TEXT_ITEM_INFO > m_DefaultFPTextItems
int GetHolePlatingThickness() const
Pad & via drills are finish size.
void SetCustomDiffPairWidth(int aWidth)
Sets custom track width for differential pairs (i.e.
VIATYPE m_CurrentViaType
(VIA_BLIND_BURIED, VIA_THROUGH, VIA_MICROVIA)
int GetCustomDiffPairGap()
Function GetCustomDiffPairGap.
void SetEnabledLayers(const LSET &aMask)
Change the bit-mask of enabled layers to aMask.
std::shared_ptr< NET_SETTINGS > m_NetSettings
bool operator==(const BOARD_DESIGN_SETTINGS &aOther) const
void SetCustomTrackWidth(int aWidth)
Sets custom width for track (i.e.
std::map< wxString, wxString > m_DrcExclusionComments
DIM_UNITS_FORMAT m_DimensionUnitsFormat
void initFromOther(const BOARD_DESIGN_SETTINGS &aOther)
bool GetTextUpright(PCB_LAYER_ID aLayer) const
std::map< int, SEVERITY > m_DRCSeverities
VECTOR2I m_gridOrigin
origin for grid offsets
int GetTextThickness(PCB_LAYER_ID aLayer) const
Return the default text thickness from the layer class for the given layer.
std::map< PCB_LAYER_ID, ZONE_LAYER_PROPERTIES > m_ZoneLayerProperties
void SetGridOrigin(const VECTOR2I &aOrigin)
VECTOR2I m_auxOrigin
origin for plot exports
bool m_TextUpright[LAYER_CLASS_COUNT]
BOARD_DESIGN_SETTINGS(JSON_SETTINGS *aParent, const std::string &aPath)
bool GetTextItalic(PCB_LAYER_ID aLayer) const
const wxString & GetCurrentNetClassName() const
wxString m_currentNetClassName
Current net class name used to display netclass info.
void SetViaSizeIndex(int aIndex)
Set the current via size list index to aIndex.
std::shared_ptr< DRC_ENGINE > m_DRCEngine
std::vector< DIFF_PAIR_DIMENSION > m_DiffPairDimensionsList
std::set< wxString > m_DrcExclusions
bool Ignore(int aDRCErrorCode)
Return true if the DRC error code's severity is SEVERITY_IGNORE.
void SetCustomViaSize(int aSize)
Set custom size for via diameter (i.e.
const LSET & GetEnabledLayers() const
Return a bit-mask of all the layers that are enabled.
std::map< std::string, wxString > m_UserLayerNames
const VECTOR2I & GetGridOrigin() const
int GetBoardThickness() const
The full thickness of the board including copper and masks.
std::unique_ptr< PAD > m_Pad_Master
void SetCustomDiffPairGap(int aGap)
Sets custom gap for differential pairs (i.e.
bool IsLayerEnabled(PCB_LAYER_ID aLayerId) const
Test whether a given layer aLayerId is enabled.
TEARDROP_PARAMETERS_LIST m_TeardropParamsList
The parameters of teardrops for the different teardrop targets (via/pad, track end).
void SetUserDefinedLayerCount(int aNewLayerCount)
Set the number of user defined layers to aNewLayerCount.
void SetAuxOrigin(const VECTOR2I &aOrigin)
const VECTOR2I & GetAuxOrigin() const
bool operator!=(const BOARD_DESIGN_SETTINGS &aOther) const
int GetDRCEpsilon() const
Return an epsilon which accounts for rounding errors, etc.
int GetLayerClass(PCB_LAYER_ID aLayer) const
PNS::MEANDER_SETTINGS m_DiffPairMeanderSettings
bool UseNetClassVia() const
Return true if netclass values should be used to obtain appropriate via size.
BOARD_STACKUP & GetStackupDescriptor()
int m_boardThickness
Board thickness for 3D viewer.
int m_copperLayerCount
Number of copper layers for this design.
bool UseNetClassTrack() const
Return true if netclass values should be used to obtain appropriate track width.
int m_userDefinedLayerCount
Number of user defined layers for this design.
bool UseNetClassDiffPair() const
Return true if netclass values should be used to obtain appropriate diff pair dimensions.
void SetCustomViaDrill(int aDrill)
Sets custom size for via drill (i.e.
bool LoadFromFile(const wxString &aDirectory="") override
Loads the backing file from disk and then calls Load()
void SetDefaultZoneSettings(const ZONE_SETTINGS &aSettings)
PNS::MEANDER_SETTINGS m_SingleTrackMeanderSettings
void SetTrackWidthIndex(int aIndex)
Set the current track width list index to aIndex.
int m_TextThickness[LAYER_CLASS_COUNT]
ZONE_SETTINGS m_defaultZoneSettings
The default settings that will be used for new zones.
const BOARD_STACKUP & GetStackupDescriptor() const
void UseCustomDiffPairDimensions(bool aEnabled)
Enables/disables custom differential pair dimensions.
SEVERITY GetSeverity(int aDRCErrorCode)
std::vector< int > m_TrackWidthList
DIFF_PAIR_DIMENSION m_customDiffPair
int m_LineThickness[LAYER_CLASS_COUNT]
VECTOR2I GetTextSize(PCB_LAYER_ID aLayer) const
Return the default text size from the layer class for the given layer.
void SetBoardThickness(int aThickness)
int GetLineThickness(PCB_LAYER_ID aLayer) const
Return the default graphic segment thickness from the layer class for the given layer.
ZONE_SETTINGS & GetDefaultZoneSettings()
bool m_UseHeightForLengthCalcs
Enable inclusion of stackup height in track length measurements and length tuning.
VECTOR2I m_TextSize[LAYER_CLASS_COUNT]
PNS::MEANDER_SETTINGS m_SkewMeanderSettings
LSET m_enabledLayers
Bit-mask for layer enabling.
bool m_TextItalic[LAYER_CLASS_COUNT]
void SetCopperLayerCount(int aNewLayerCount)
Set the copper layer count to aNewLayerCount.
DIM_TEXT_POSITION m_DimensionTextPosition
BOARD_STACKUP m_stackup
The description of layers stackup, for board fabrication only physical layers are in layers stackup.
std::vector< VIA_DIMENSION > m_ViasDimensionsList
BOARD_DESIGN_SETTINGS & operator=(const BOARD_DESIGN_SETTINGS &aOther)
void SetCustomDiffPairViaGap(int aGap)
Sets custom via gap for differential pairs (i.e.
Manage layers needed to make a physical board.
JSON_SETTINGS(const wxString &aFilename, SETTINGS_LOC aLocation, int aSchemaVersion)
LSET is a set of PCB_LAYER_IDs.
Definition lset.h:37
NESTED_SETTINGS(const std::string &aName, int aSchemaVersion, JSON_SETTINGS *aParent, const std::string &aPath, bool aLoadFromFile=true)
Definition pad.h:54
Dimensions for the meandering algorithm.
Definition pns_meander.h:68
TEARDROP_PARAMETERS_LIST is a helper class to handle the list of TEARDROP_PARAMETERS needed to build ...
ZONE_SETTINGS handles zones parameters.
PCB_LAYER_ID
A quick note on layer IDs:
Definition layer_ids.h:60
@ PCB_LAYER_ID_COUNT
Definition layer_ids.h:171
DIM_TEXT_POSITION
Where to place the text on a dimension.
DIM_UNITS_FORMAT
How to display the units in a dimension's text.
DIM_UNITS_MODE
Used for storing the units selection in the file because EDA_UNITS alone doesn't cut it.
DIM_PRECISION
VIATYPE
Definition pcb_track.h:67
SEVERITY
Container to handle a stock of specific differential pairs each with unique track width,...
DIFF_PAIR_DIMENSION(int aWidth, int aGap, int aViaGap)
bool operator<(const DIFF_PAIR_DIMENSION &aOther) const
bool operator==(const DIFF_PAIR_DIMENSION &aOther) const
bool operator!=(const DIFF_PAIR_DIMENSION &aOther) const
TEXT_ITEM_INFO(const wxString &aText, bool aVisible, PCB_LAYER_ID aLayer)
bool operator==(const TEXT_ITEM_INFO &aOther) const
Container to handle a stock of specific vias each with unique diameter and drill sizes in the BOARD c...
bool operator==(const VIA_DIMENSION &aOther) const
VIA_DIMENSION(int aDiameter, int aDrill)
bool operator!=(const VIA_DIMENSION &aOther) const
bool operator<(const VIA_DIMENSION &aOther) const
Functions to provide common constants and other functions to assist in making a consistent UI.
VECTOR2< int32_t > VECTOR2I
Definition vector2d.h:695
Class ZONE_SETTINGS used to handle zones parameters in dialogs.