KiCad PCB EDA Suite
BOARD_STACKUP Class Reference

Manage layers needed to make a physical board. More...

#include <board_stackup.h>

Public Member Functions

 BOARD_STACKUP ()
 
 BOARD_STACKUP (const BOARD_STACKUP &aOther)
 
BOARD_STACKUPoperator= (const BOARD_STACKUP &aOther)
 
 ~BOARD_STACKUP ()
 
const std::vector< BOARD_STACKUP_ITEM * > & GetList () const
 
BOARD_STACKUP_ITEMGetStackupLayer (int aIndex)
 
void RemoveAll ()
 Delete all items in list and clear the list. More...
 
int GetCount () const
 
int BuildBoardThicknessFromStackup () const
 
void Add (BOARD_STACKUP_ITEM *aItem)
 Add a new item in stackup layer. More...
 
bool SynchronizeWithBoard (BOARD_DESIGN_SETTINGS *aSettings)
 Synchronize the BOARD_STACKUP_ITEM* list with the board. More...
 
void BuildDefaultStackupList (const BOARD_DESIGN_SETTINGS *aSettings, int aActiveCopperLayersCount=0)
 Create a default stackup, according to the current BOARD_DESIGN_SETTINGS settings. More...
 
void FormatBoardStackup (OUTPUTFORMATTER *aFormatter, const BOARD *aBoard, int aNestLevel) const
 Write the stackup info on board file. More...
 
int GetLayerDistance (PCB_LAYER_ID aFirstLayer, PCB_LAYER_ID aSecondLayer) const
 Calculate the distance (height) between the two given copper layers. More...
 

Static Public Member Functions

static LSET StackupAllowedBrdLayers ()
 

Public Attributes

wxString m_FinishType
 The name of external copper finish. More...
 
bool m_HasDielectricConstrains
 True if some layers have impedance controlled tracks or have specific constrains for micro-wave applications If the board has dielectric constrains, the .gbrjob will contain info about dielectric constrains: loss tangent and Epsilon rel. More...
 
bool m_HasThicknessConstrains
 True if some layers (copper and/or dielectric) have specific thickness. More...
 
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
 If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTOR_NONE = no edge connector BS_EDGE_CONNECTOR_IN_USE = board has edge connectors BS_EDGE_CONNECTOR_BEVELLED = edge connectors are beveled. More...
 
bool m_CastellatedPads
 True if castellated pads exist. More...
 
bool m_EdgePlating
 True if the edge board is plated. More...
 

Private Attributes

std::vector< BOARD_STACKUP_ITEM * > m_list
 

Detailed Description

Manage layers needed to make a physical board.

They are solder mask, silk screen, copper and dielectric. Some other layers, used in fabrication, are not managed here because they are not used to make a physical board itself.

Note
There are a few other parameters related to the physical stackup like finish type, impedance control and a few others.

Definition at line 210 of file board_stackup.h.

Constructor & Destructor Documentation

◆ BOARD_STACKUP() [1/2]

BOARD_STACKUP::BOARD_STACKUP ( )

Definition at line 313 of file board_stackup.cpp.

314 {
315  m_HasDielectricConstrains = false; // True if some dielectric layers have constrains
316  // (Loss tg and Epison R)
317  m_HasThicknessConstrains = false; // True if some dielectric or copper layers have constrains
319  m_CastellatedPads = false; // True if some castellated pads exist
320  m_EdgePlating = false; // True if edge board is plated
321  m_FinishType = "None"; // undefined finish type
322 }
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTO...
bool m_CastellatedPads
True if castellated pads exist.
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
bool m_HasThicknessConstrains
True if some layers (copper and/or dielectric) have specific thickness.

References BS_EDGE_CONNECTOR_NONE, m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, and m_HasThicknessConstrains.

◆ BOARD_STACKUP() [2/2]

BOARD_STACKUP::BOARD_STACKUP ( const BOARD_STACKUP aOther)

Definition at line 325 of file board_stackup.cpp.

326 {
331  m_EdgePlating = aOther.m_EdgePlating;
332  m_FinishType = aOther.m_FinishType;
333 
334  // All items in aOther.m_list have to be duplicated, because aOther.m_list
335  // manage pointers to these items
336  for( auto item : aOther.m_list )
337  {
338  BOARD_STACKUP_ITEM* dup_item = new BOARD_STACKUP_ITEM( *item );
339  Add( dup_item );
340  }
341 }
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTO...
bool m_CastellatedPads
True if castellated pads exist.
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
std::vector< BOARD_STACKUP_ITEM * > m_list
bool m_HasThicknessConstrains
True if some layers (copper and/or dielectric) have specific thickness.
Manage one layer needed to make a physical board.
Definition: board_stackup.h:89
void Add(BOARD_STACKUP_ITEM *aItem)
Add a new item in stackup layer.

References Add(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_HasThicknessConstrains, and m_list.

◆ ~BOARD_STACKUP()

BOARD_STACKUP::~BOARD_STACKUP ( )
inline

Definition at line 217 of file board_stackup.h.

217 { RemoveAll(); }
void RemoveAll()
Delete all items in list and clear the list.

References RemoveAll().

Member Function Documentation

◆ Add()

void BOARD_STACKUP::Add ( BOARD_STACKUP_ITEM aItem)
inline

Add a new item in stackup layer.

Definition at line 245 of file board_stackup.h.

245 { m_list.push_back( aItem ); }
std::vector< BOARD_STACKUP_ITEM * > m_list

References m_list.

Referenced by BOARD_STACKUP(), BuildDefaultStackupList(), operator=(), PCB_PARSER::parseBoardStackup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ BuildBoardThicknessFromStackup()

int BOARD_STACKUP::BuildBoardThicknessFromStackup ( ) const
Returns
the board thickness ( in UI) from the thickness of BOARD_STACKUP_ITEM list

Definition at line 385 of file board_stackup.cpp.

386 {
387  // return the board thickness from the thickness of BOARD_STACKUP_ITEM list
388  int thickness = 0;
389 
390  for( auto item : m_list )
391  {
392  if( item->IsThicknessEditable() && item->IsEnabled() )
393  thickness += item->GetThickness();
394  }
395 
396  return thickness;
397 }
std::vector< BOARD_STACKUP_ITEM * > m_list

References m_list.

Referenced by CADSTAR_PCB_ARCHIVE_LOADER::loadBoardStackup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ BuildDefaultStackupList()

void BOARD_STACKUP::BuildDefaultStackupList ( const BOARD_DESIGN_SETTINGS aSettings,
int  aActiveCopperLayersCount = 0 
)

Create a default stackup, according to the current BOARD_DESIGN_SETTINGS settings.

Parameters
aSettingsis the current board setting. if nullptr, build a full stackup (with 32 copper layers)
aActiveCopperLayersCountis used only if aSettings == nullptr is the number of copper layers to use to calculate a default dielectric thickness. ((<= 0 to use all copper layers)

Definition at line 494 of file board_stackup.cpp.

496 {
497  // Creates a default stackup, according to the current BOARD_DESIGN_SETTINGS settings.
498  // Note: the m_TypeName string is made translatable using _HKI marker, but is not
499  // translated when building the stackup.
500  // It will be used as this in files, and can be translated only in dialog
501  // if aSettings == NULL, build a full stackup (with 32 copper layers)
502  LSET enabledLayer = aSettings ? aSettings->GetEnabledLayers() : StackupAllowedBrdLayers();
503  int copperLayerCount = aSettings ? aSettings->GetCopperLayerCount() : B_Cu+1;
504 
505  // We need to calculate a suitable dielectric layer thickness.
506  // If no settings, and if aActiveCopperLayersCount is given, use it
507  // (If no settings, and no aActiveCopperLayersCount, the full 32 layers are used)
508  int activeCuLayerCount = copperLayerCount;
509 
510  if( aSettings == nullptr && aActiveCopperLayersCount > 0 )
511  activeCuLayerCount = aActiveCopperLayersCount;
512 
513  int brd__thickness = aSettings ? aSettings->GetBoardThickness() : Millimeter2iu( 1.6 );
514  int diel_thickness = brd__thickness -
515  ( BOARD_STACKUP_ITEM::GetCopperDefaultThickness() * activeCuLayerCount );
516 
517  // Take in account the solder mask thickness:
518  int sm_count = ( enabledLayer & LSET( 2, F_Mask, B_Mask) ).count();
519  diel_thickness -= BOARD_STACKUP_ITEM::GetMaskDefaultThickness() * sm_count;
520  diel_thickness /= std::max( 1, activeCuLayerCount - 1 );
521 
522  int dielectric_idx = 0;
523 
524  // Add silk screen, solder mask and solder paste layers on top
525  if( enabledLayer[F_SilkS] )
526  {
528  item->SetBrdLayerId( F_SilkS );
529  item->SetTypeName( _HKI( "Top Silk Screen" ) );
530  Add( item );
531  }
532 
533  if( enabledLayer[F_Paste] )
534  {
536  item->SetBrdLayerId( F_Paste );
537  item->SetTypeName( _HKI( "Top Solder Paste" ) );
538  Add( item );
539  }
540 
541  if( enabledLayer[F_Mask] )
542  {
544  item->SetBrdLayerId( F_Mask );
545  item->SetTypeName( _HKI( "Top Solder Mask" ) );
546  Add( item );
547  }
548 
549  // Add copper and dielectric layers
550  for( int ii = 0; ii < copperLayerCount; ii++ )
551  {
553  item->SetBrdLayerId( ( PCB_LAYER_ID )ii );
554  item->SetTypeName( KEY_COPPER );
555  Add( item );
556 
557  if( ii == copperLayerCount-1 )
558  {
559  item->SetBrdLayerId( B_Cu );
560  break;
561  }
562 
563  // Add the dielectric layer:
565  item->SetThickness( diel_thickness );
566  item->SetDielectricLayerId( dielectric_idx + 1 );
567 
568  // Display a dielectric default layer name:
569  if( (dielectric_idx & 1) == 0 )
570  {
571  item->SetTypeName( KEY_CORE );
572  item->SetMaterial( "FR4" );
573  }
574  else
575  {
576  item->SetTypeName( KEY_PREPREG );
577  item->SetMaterial( "FR4" );
578  }
579 
580  Add( item );
581  dielectric_idx++;
582  }
583 
584  // Add silk screen, solder mask and solder paste layers on bottom
585  if( enabledLayer[B_Mask] )
586  {
588  item->SetBrdLayerId( B_Mask );
589  item->SetTypeName( _HKI( "Bottom Solder Mask" ) );
590  Add( item );
591  }
592 
593  if( enabledLayer[B_Paste] )
594  {
596  item->SetBrdLayerId( B_Paste );
597  item->SetTypeName( _HKI( "Bottom Solder Paste" ) );
598  Add( item );
599  }
600 
601  if( enabledLayer[B_SilkS] )
602  {
604  item->SetBrdLayerId( B_SilkS );
605  item->SetTypeName( _HKI( "Bottom Silk Screen" ) );
606  Add( item );
607  }
608 
609  // Transfer other stackup settings from aSettings
610  if( aSettings )
611  {
612  const BOARD_STACKUP& source_stackup = aSettings->GetStackupDescriptor();
614  m_CastellatedPads = source_stackup.m_CastellatedPads;
615  m_EdgePlating = source_stackup.m_EdgePlating;
616  m_FinishType = source_stackup.m_FinishType;
617  }
618 }
void SetBrdLayerId(PCB_LAYER_ID aBrdLayerId)
void SetTypeName(const wxString &aName)
Manage layers needed to make a physical board.
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTO...
bool m_CastellatedPads
True if castellated pads exist.
#define KEY_COPPER
static int GetCopperDefaultThickness()
BOARD_STACKUP & GetStackupDescriptor()
LSET is a set of PCB_LAYER_IDs.
Definition: layer_ids.h:504
static LSET StackupAllowedBrdLayers()
void SetDielectricLayerId(int aLayerId)
void SetMaterial(const wxString &aName, int aDielectricSubLayer=0)
#define KEY_PREPREG
Manage one layer needed to make a physical board.
Definition: board_stackup.h:89
void SetThickness(int aThickness, int aDielectricSubLayer=0)
static int GetMaskDefaultThickness()
LSET GetEnabledLayers() const
Return a bit-mask of all the layers that are enabled.
PCB_LAYER_ID
A quick note on layer IDs:
Definition: layer_ids.h:65
#define KEY_CORE
void Add(BOARD_STACKUP_ITEM *aItem)
Add a new item in stackup layer.
static constexpr int Millimeter2iu(double mm)
#define _HKI(x)

References _HKI, Add(), B_Cu, B_Mask, B_Paste, B_SilkS, BS_ITEM_TYPE_COPPER, BS_ITEM_TYPE_DIELECTRIC, BS_ITEM_TYPE_SILKSCREEN, BS_ITEM_TYPE_SOLDERMASK, BS_ITEM_TYPE_SOLDERPASTE, F_Mask, F_Paste, F_SilkS, BOARD_DESIGN_SETTINGS::GetBoardThickness(), BOARD_STACKUP_ITEM::GetCopperDefaultThickness(), BOARD_DESIGN_SETTINGS::GetCopperLayerCount(), BOARD_DESIGN_SETTINGS::GetEnabledLayers(), BOARD_STACKUP_ITEM::GetMaskDefaultThickness(), BOARD_DESIGN_SETTINGS::GetStackupDescriptor(), KEY_COPPER, KEY_CORE, KEY_PREPREG, m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, Millimeter2iu(), BOARD_STACKUP_ITEM::SetBrdLayerId(), BOARD_STACKUP_ITEM::SetDielectricLayerId(), BOARD_STACKUP_ITEM::SetMaterial(), BOARD_STACKUP_ITEM::SetThickness(), BOARD_STACKUP_ITEM::SetTypeName(), and StackupAllowedBrdLayers().

Referenced by PANEL_SETUP_BOARD_STACKUP::buildLayerStackPanel(), CADSTAR_PCB_ARCHIVE_LOADER::loadBoardStackup(), ALTIUM_PCB::ParseBoard6Data(), and SynchronizeWithBoard().

◆ FormatBoardStackup()

void BOARD_STACKUP::FormatBoardStackup ( OUTPUTFORMATTER aFormatter,
const BOARD aBoard,
int  aNestLevel 
) const

Write the stackup info on board file.

Parameters
aFormatteris the OUTPUTFORMATTER used to create the file
aBoardis the board
aNestLevelis the index to nest level to indent the lines in file

Definition at line 621 of file board_stackup.cpp.

623 {
624  // Board stackup is the ordered list from top to bottom of
625  // physical layers and substrate used to build the board.
626  if( m_list.empty() )
627  return;
628 
629  aFormatter->Print( aNestLevel, "(stackup\n" );
630  int nest_level = aNestLevel+1;
631 
632  // Note:
633  // Unspecified parameters are not stored in file.
634  for( BOARD_STACKUP_ITEM* item: m_list )
635  {
636  wxString layer_name;
637 
638  if( item->GetBrdLayerId() == UNDEFINED_LAYER )
639  layer_name.Printf( "dielectric %d", item->GetDielectricLayerId() );
640  else
641  layer_name = LSET::Name( item->GetBrdLayerId() );
642 
643  aFormatter->Print( nest_level, "(layer %s (type %s)",
644  aFormatter->Quotew( layer_name ).c_str(),
645  aFormatter->Quotew( item->GetTypeName() ).c_str() );
646 
647  if( item->IsColorEditable() && IsPrmSpecified( item->GetColor() ) )
648  aFormatter->Print( 0, " (color %s)",
649  aFormatter->Quotew( item->GetColor() ).c_str() );
650 
651  for( int idx = 0; idx < item->GetSublayersCount(); idx++ )
652  {
653  if( idx ) // not for the main (first) layer.
654  {
655  aFormatter->Print( 0, "\n" );
656  aFormatter->Print( nest_level+1, "addsublayer" );
657  }
658 
659  if( item->IsThicknessEditable() )
660  {
661  if( item->GetType() == BS_ITEM_TYPE_DIELECTRIC && item->IsThicknessLocked( idx ) )
662  aFormatter->Print( 0, " (thickness %s locked)",
663  FormatInternalUnits( item->GetThickness( idx ) ).c_str() );
664  else
665  aFormatter->Print( 0, " (thickness %s)",
666  FormatInternalUnits( item->GetThickness( idx ) ).c_str() );
667  }
668 
669  if( item->HasMaterialValue( idx ) )
670  aFormatter->Print( 0, " (material %s)",
671  aFormatter->Quotew( item->GetMaterial( idx ) ).c_str() );
672 
673  if( item->HasEpsilonRValue() && item->HasMaterialValue( idx ) )
674  aFormatter->Print( 0, " (epsilon_r %g)", item->GetEpsilonR( idx ) );
675 
676  if( item->HasLossTangentValue() && item->HasMaterialValue( idx ) )
677  aFormatter->Print( 0, " (loss_tangent %s)",
678  Double2Str(item->GetLossTangent( idx ) ).c_str() );
679  }
680 
681  aFormatter->Print( 0, ")\n" );
682  }
683 
684  // Other infos about board, related to layers and other fabrication specifications
686  aFormatter->Print( nest_level, "(copper_finish %s)\n",
687  aFormatter->Quotew( m_FinishType ).c_str() );
688 
689  aFormatter->Print( nest_level, "(dielectric_constraints %s)\n",
690  m_HasDielectricConstrains ? "yes" : "no" );
691 
693  aFormatter->Print( nest_level, "(edge_connector %s)\n",
694  m_EdgeConnectorConstraints > 1 ? "bevelled": "yes" );
695 
696  if( m_CastellatedPads )
697  aFormatter->Print( nest_level, "(castellated_pads yes)\n" );
698 
699  if( m_EdgePlating )
700  aFormatter->Print( nest_level, "(edge_plating yes)\n" );
701 
702  aFormatter->Print( aNestLevel, ")\n" );
703 }
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTO...
bool m_CastellatedPads
True if castellated pads exist.
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
static const wxChar * Name(PCB_LAYER_ID aLayerId)
Return the fixed name association with aLayerId.
Definition: lset.cpp:82
std::vector< BOARD_STACKUP_ITEM * > m_list
Manage one layer needed to make a physical board.
Definition: board_stackup.h:89
bool IsPrmSpecified(const wxString &aPrmValue)
std::string Double2Str(double aValue)
Print a float number without using scientific notation and no trailing 0 We want to avoid scientific ...
int PRINTF_FUNC Print(int nestLevel, const char *fmt,...)
Format and write text to the output stream.
Definition: richio.cpp:426
std::string FormatInternalUnits(int aValue)
Function FormatInternalUnits converts aValue from internal units to a string appropriate for writing ...
Definition: base_units.cpp:485
std::string Quotew(const wxString &aWrapee) const
Definition: richio.cpp:494

References BS_ITEM_TYPE_DIELECTRIC, Double2Str(), FormatInternalUnits(), IsPrmSpecified(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_list, LSET::Name(), OUTPUTFORMATTER::Print(), OUTPUTFORMATTER::Quotew(), and UNDEFINED_LAYER.

Referenced by PCB_IO::formatSetup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ GetCount()

int BOARD_STACKUP::GetCount ( ) const
inline
Returns
the number of layers in the stackup

Definition at line 239 of file board_stackup.h.

239 { return (int) m_list.size(); }
std::vector< BOARD_STACKUP_ITEM * > m_list

References m_list.

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup(), DRAWING_TOOL::DrawSpecificationStackup(), and GetStackupLayer().

◆ GetLayerDistance()

int BOARD_STACKUP::GetLayerDistance ( PCB_LAYER_ID  aFirstLayer,
PCB_LAYER_ID  aSecondLayer 
) const

Calculate the distance (height) between the two given copper layers.

This factors in the thickness of any dielectric and copper layers between the two given layers, and half the height of the given start and end layers. This half-height calculation allows this to be used for consistent length measurements when calculating net length through a series of vias. A more advanced algorithm would be possible once we have a good concept of the start and end for a length measurement, but for now this will do. See https://gitlab.com/kicad/code/kicad/-/issues/8384 for more background.

Parameters
aFirstLayeris a copper layer
aSecondLayeris a different copper layer
Returns
the height (in IU) between the two layers

Definition at line 706 of file board_stackup.cpp.

707 {
708  wxASSERT( IsCopperLayer( aFirstLayer ) && IsCopperLayer( aSecondLayer ) );
709 
710  if( aFirstLayer == aSecondLayer )
711  return 0;
712 
713  if( aSecondLayer < aFirstLayer )
714  std::swap( aFirstLayer, aSecondLayer );
715 
716  int total = 0;
717  bool start = false;
718  bool half = false;
719 
720  for( BOARD_STACKUP_ITEM* item : m_list )
721  {
722  // Will be UNDEFINED_LAYER for dielectrics
723  PCB_LAYER_ID layer = item->GetBrdLayerId();
724 
725  if( layer != UNDEFINED_LAYER && !IsCopperLayer( layer ) )
726  continue; // Silk/mask layer
727 
728  // Reached the start copper layer? Start counting the next dielectric after it
729  if( !start && ( layer != UNDEFINED_LAYER && layer >= aFirstLayer ) )
730  {
731  start = true;
732  half = true;
733  }
734  else if( !start )
735  continue;
736 
737  // Reached the stop copper layer? we're done
738  if( start && ( layer != UNDEFINED_LAYER && layer >= aSecondLayer ) )
739  half = true;
740 
741  for( int sublayer = 0; sublayer < item->GetSublayersCount(); sublayer++ )
742  {
743  int subThickness = item->GetThickness( sublayer );
744  total += half ? ( subThickness / 2 ) : subThickness;
745  }
746 
747  half = false;
748 
749  if( layer != UNDEFINED_LAYER && layer >= aSecondLayer )
750  break;
751  }
752 
753  return total;
754 }
std::vector< BOARD_STACKUP_ITEM * > m_list
Manage one layer needed to make a physical board.
Definition: board_stackup.h:89
bool IsCopperLayer(LAYER_NUM aLayerId)
Tests whether a layer is a copper layer.
Definition: layer_ids.h:796
PCB_LAYER_ID
A quick note on layer IDs:
Definition: layer_ids.h:65

References IsCopperLayer(), m_list, and UNDEFINED_LAYER.

Referenced by DIALOG_NET_INSPECTOR::calculateViaLength(), BOARD::GetTrackLength(), and PNS_KICAD_IFACE_BASE::StackupHeight().

◆ GetList()

◆ GetStackupLayer()

BOARD_STACKUP_ITEM * BOARD_STACKUP::GetStackupLayer ( int  aIndex)
Returns
a reference to the layer aIndex, or nullptr if not exists

Definition at line 376 of file board_stackup.cpp.

377 {
378  if( aIndex < 0 || aIndex >= GetCount() )
379  return nullptr;
380 
381  return GetList()[aIndex];
382 }
int GetCount() const
const std::vector< BOARD_STACKUP_ITEM * > & GetList() const

References GetCount(), and GetList().

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup().

◆ operator=()

BOARD_STACKUP & BOARD_STACKUP::operator= ( const BOARD_STACKUP aOther)

Definition at line 344 of file board_stackup.cpp.

345 {
350  m_EdgePlating = aOther.m_EdgePlating;
351  m_FinishType = aOther.m_FinishType;
352 
353  RemoveAll();
354 
355  // All items in aOther.m_list have to be duplicated, because aOther.m_list
356  // manage pointers to these items
357  for( auto item : aOther.m_list )
358  {
359  BOARD_STACKUP_ITEM* dup_item = new BOARD_STACKUP_ITEM( *item );
360  Add( dup_item );
361  }
362 
363  return *this;
364 }
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTO...
bool m_CastellatedPads
True if castellated pads exist.
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
std::vector< BOARD_STACKUP_ITEM * > m_list
bool m_HasThicknessConstrains
True if some layers (copper and/or dielectric) have specific thickness.
Manage one layer needed to make a physical board.
Definition: board_stackup.h:89
void RemoveAll()
Delete all items in list and clear the list.
void Add(BOARD_STACKUP_ITEM *aItem)
Add a new item in stackup layer.

References Add(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_HasThicknessConstrains, m_list, and RemoveAll().

◆ RemoveAll()

void BOARD_STACKUP::RemoveAll ( )

Delete all items in list and clear the list.

Definition at line 367 of file board_stackup.cpp.

368 {
369  for( auto item : m_list )
370  delete item;
371 
372  m_list.clear();
373 }
std::vector< BOARD_STACKUP_ITEM * > m_list

References m_list.

Referenced by CADSTAR_PCB_ARCHIVE_LOADER::loadBoardStackup(), operator=(), ALTIUM_PCB::ParseBoard6Data(), PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow(), and ~BOARD_STACKUP().

◆ StackupAllowedBrdLayers()

static LSET BOARD_STACKUP::StackupAllowedBrdLayers ( )
inlinestatic
Returns
the board layers full mask allowed in the stackup list i.e. the SilkS, Mask, Paste and all copper layers

Definition at line 228 of file board_stackup.h.

229  {
230  return LSET( 6, F_SilkS, F_Mask, F_Paste, B_SilkS, B_Mask, B_Paste )
232  }
LSET is a set of PCB_LAYER_IDs.
Definition: layer_ids.h:504
static LSET InternalCuMask()
Return a complete set of internal copper layers which is all Cu layers except F_Cu and B_Cu.
Definition: lset.cpp:710
static LSET ExternalCuMask()
Return a mask holding the Front and Bottom layers.
Definition: lset.cpp:780

References B_Mask, B_Paste, B_SilkS, LSET::ExternalCuMask(), F_Mask, F_Paste, F_SilkS, and LSET::InternalCuMask().

Referenced by BuildDefaultStackupList(), PANEL_SETUP_BOARD_STACKUP::ImportSettingsFrom(), PANEL_SETUP_BOARD_STACKUP::OnLayersOptionsChanged(), and PANEL_SETUP_BOARD_STACKUP::PANEL_SETUP_BOARD_STACKUP().

◆ SynchronizeWithBoard()

bool BOARD_STACKUP::SynchronizeWithBoard ( BOARD_DESIGN_SETTINGS aSettings)

Synchronize the BOARD_STACKUP_ITEM* list with the board.

Not enabled layers are removed Missing layers are added

Parameters
aSettings,isthe current board setting.
Returns
true if changes are made

Definition at line 400 of file board_stackup.cpp.

401 {
402  bool change = false;
403  // Build the suitable stackup:
404  BOARD_STACKUP stackup;
405  stackup.BuildDefaultStackupList( aSettings );
406 
407  // First, find removed layers:
408  for( BOARD_STACKUP_ITEM* curr_item: m_list )
409  {
410  bool found = false;
411 
412  for( BOARD_STACKUP_ITEM* item: stackup.GetList() )
413  {
414  if( curr_item->GetBrdLayerId() != UNDEFINED_LAYER )
415  {
416  if( item->GetBrdLayerId() == curr_item->GetBrdLayerId() )
417  {
418  found = true;
419  break;
420  }
421  }
422  else // curr_item = dielectric layer
423  {
424  if( item->GetBrdLayerId() != UNDEFINED_LAYER )
425  continue;
426 
427  if( item->GetDielectricLayerId() == curr_item->GetDielectricLayerId() )
428  {
429  found = true;
430  break;
431  }
432  }
433  }
434 
435  if( !found ) // a layer was removed: a change is found
436  {
437  change = true;
438  break;
439  }
440  }
441 
442  // Now initialize all stackup items to the initial values, when exist
443  for( BOARD_STACKUP_ITEM* item : stackup.GetList() )
444  {
445  bool found = false;
446  // Search for initial settings:
447  for( const BOARD_STACKUP_ITEM* initial_item : m_list )
448  {
449  if( item->GetBrdLayerId() != UNDEFINED_LAYER )
450  {
451  if( item->GetBrdLayerId() == initial_item->GetBrdLayerId() )
452  {
453  *item = *initial_item;
454  found = true;
455  break;
456  }
457  }
458  else // dielectric layer: see m_DielectricLayerId for identification
459  {
460  // Compare dielectric layer with dielectric layer
461  if( initial_item->GetBrdLayerId() != UNDEFINED_LAYER )
462  continue;
463 
464  if( item->GetDielectricLayerId() == initial_item->GetDielectricLayerId() )
465  {
466  *item = *initial_item;
467  found = true;
468  break;
469  }
470  }
471  }
472 
473  if( !found )
474  {
475  change = true;
476  }
477  }
478 
479  // Transfert layer settings:
480  *this = stackup;
481 
482  // Transfer other stackup settings from aSettings
483  const BOARD_STACKUP& source_stackup = aSettings->GetStackupDescriptor();
486  m_CastellatedPads = source_stackup.m_CastellatedPads;
487  m_EdgePlating = source_stackup.m_EdgePlating;
488  m_FinishType = source_stackup.m_FinishType;
489 
490  return change;
491 }
Manage layers needed to make a physical board.
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTO...
bool m_CastellatedPads
True if castellated pads exist.
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
BOARD_STACKUP & GetStackupDescriptor()
std::vector< BOARD_STACKUP_ITEM * > m_list
Manage one layer needed to make a physical board.
Definition: board_stackup.h:89
const std::vector< BOARD_STACKUP_ITEM * > & GetList() const
void BuildDefaultStackupList(const BOARD_DESIGN_SETTINGS *aSettings, int aActiveCopperLayersCount=0)
Create a default stackup, according to the current BOARD_DESIGN_SETTINGS settings.

References BuildDefaultStackupList(), GetList(), BOARD_DESIGN_SETTINGS::GetStackupDescriptor(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_list, and UNDEFINED_LAYER.

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup(), and DRAWING_TOOL::DrawSpecificationStackup().

Member Data Documentation

◆ m_CastellatedPads

◆ m_EdgeConnectorConstraints

BS_EDGE_CONNECTOR_CONSTRAINTS BOARD_STACKUP::m_EdgeConnectorConstraints

If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTOR_NONE = no edge connector BS_EDGE_CONNECTOR_IN_USE = board has edge connectors BS_EDGE_CONNECTOR_BEVELLED = edge connectors are beveled.

Definition at line 318 of file board_stackup.h.

Referenced by BOARD_STACKUP(), BuildDefaultStackupList(), BuildStackupReport(), DRAWING_TOOL::DrawBoardCharacteristics(), FormatBoardStackup(), operator=(), PCB_PARSER::parseBoardStackup(), PANEL_SETUP_BOARD_FINISH::synchronizeWithBoard(), SynchronizeWithBoard(), PANEL_SETUP_BOARD_FINISH::TransferDataFromWindow(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ m_EdgePlating

◆ m_FinishType

◆ m_HasDielectricConstrains

bool BOARD_STACKUP::m_HasDielectricConstrains

True if some layers have impedance controlled tracks or have specific constrains for micro-wave applications If the board has dielectric constrains, the .gbrjob will contain info about dielectric constrains: loss tangent and Epsilon rel.

If not, these values will be not specified in job file.

Definition at line 304 of file board_stackup.h.

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup(), BOARD_STACKUP(), BuildStackupReport(), DRAWING_TOOL::DrawBoardCharacteristics(), FormatBoardStackup(), operator=(), PCB_PARSER::parseBoardStackup(), PANEL_SETUP_BOARD_STACKUP::synchronizeWithBoard(), SynchronizeWithBoard(), PANEL_SETUP_BOARD_STACKUP::transferDataFromUIToStackup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ m_HasThicknessConstrains

bool BOARD_STACKUP::m_HasThicknessConstrains

True if some layers (copper and/or dielectric) have specific thickness.

Definition at line 309 of file board_stackup.h.

Referenced by BOARD_STACKUP(), and operator=().

◆ m_list


The documentation for this class was generated from the following files: