KiCad PCB EDA Suite
BOARD_STACKUP Class Reference

Manage layers needed to make a physical board. More...

#include <board_stackup.h>

Public Member Functions

 BOARD_STACKUP ()
 
 BOARD_STACKUP (const BOARD_STACKUP &aOther)
 
BOARD_STACKUPoperator= (const BOARD_STACKUP &aOther)
 
 ~BOARD_STACKUP ()
 
const std::vector< BOARD_STACKUP_ITEM * > & GetList () const
 
BOARD_STACKUP_ITEMGetStackupLayer (int aIndex)
 
void RemoveAll ()
 Delete all items in list and clear the list. More...
 
int GetCount () const
 
int BuildBoardThicknessFromStackup () const
 
void Add (BOARD_STACKUP_ITEM *aItem)
 Add a new item in stackup layer. More...
 
bool SynchronizeWithBoard (BOARD_DESIGN_SETTINGS *aSettings)
 Synchronize the BOARD_STACKUP_ITEM* list with the board. More...
 
void BuildDefaultStackupList (const BOARD_DESIGN_SETTINGS *aSettings, int aActiveCopperLayersCount=0)
 Create a default stackup, according to the current BOARD_DESIGN_SETTINGS settings. More...
 
void FormatBoardStackup (OUTPUTFORMATTER *aFormatter, const BOARD *aBoard, int aNestLevel) const
 Write the stackup info on board file. More...
 
int GetLayerDistance (PCB_LAYER_ID aFirstLayer, PCB_LAYER_ID aSecondLayer) const
 Calculate the distance (height) between the two given copper layers. More...
 

Static Public Member Functions

static LSET StackupAllowedBrdLayers ()
 

Public Attributes

wxString m_FinishType
 The name of external copper finish. More...
 
bool m_HasDielectricConstrains
 True if some layers have impedance controlled tracks or have specific constrains for micro-wave applications If the board has dielectric constrains, the .gbrjob will contain info about dielectric constrains: loss tangent and Epsilon rel. More...
 
bool m_HasThicknessConstrains
 True if some layers (copper and/or dielectric) have specific thickness. More...
 
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
 If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTOR_NONE = no edge connector BS_EDGE_CONNECTOR_IN_USE = board has edge connectors BS_EDGE_CONNECTOR_BEVELLED = edge connectors are beveled. More...
 
bool m_CastellatedPads
 True if castellated pads exist. More...
 
bool m_EdgePlating
 True if the edge board is plated. More...
 

Private Attributes

std::vector< BOARD_STACKUP_ITEM * > m_list
 

Detailed Description

Manage layers needed to make a physical board.

They are solder mask, silk screen, copper and dielectric. Some other layers, used in fabrication, are not managed here because they are not used to make a physical board itself.

Note
There are a few other parameters related to the physical stackup like finish type, impedance control and a few others.

Definition at line 210 of file board_stackup.h.

Constructor & Destructor Documentation

◆ BOARD_STACKUP() [1/2]

BOARD_STACKUP::BOARD_STACKUP ( )

Definition at line 313 of file board_stackup.cpp.

314 {
315  m_HasDielectricConstrains = false; // True if some dielectric layers have constrains
316  // (Loss tg and Epison R)
317  m_HasThicknessConstrains = false; // True if some dielectric or copper layers have constrains
319  m_CastellatedPads = false; // True if some castellated pads exist
320  m_EdgePlating = false; // True if edge board is plated
321  m_FinishType = wxT( "None" ); // undefined finish type
322 }
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTO...
bool m_CastellatedPads
True if castellated pads exist.
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
bool m_HasThicknessConstrains
True if some layers (copper and/or dielectric) have specific thickness.

References BS_EDGE_CONNECTOR_NONE, m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, and m_HasThicknessConstrains.

◆ BOARD_STACKUP() [2/2]

BOARD_STACKUP::BOARD_STACKUP ( const BOARD_STACKUP aOther)

Definition at line 325 of file board_stackup.cpp.

326 {
331  m_EdgePlating = aOther.m_EdgePlating;
332  m_FinishType = aOther.m_FinishType;
333 
334  // All items in aOther.m_list have to be duplicated, because aOther.m_list
335  // manage pointers to these items
336  for( auto item : aOther.m_list )
337  {
338  BOARD_STACKUP_ITEM* dup_item = new BOARD_STACKUP_ITEM( *item );
339  Add( dup_item );
340  }
341 }
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTO...
bool m_CastellatedPads
True if castellated pads exist.
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
std::vector< BOARD_STACKUP_ITEM * > m_list
bool m_HasThicknessConstrains
True if some layers (copper and/or dielectric) have specific thickness.
Manage one layer needed to make a physical board.
Definition: board_stackup.h:89
void Add(BOARD_STACKUP_ITEM *aItem)
Add a new item in stackup layer.

References Add(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_HasThicknessConstrains, and m_list.

◆ ~BOARD_STACKUP()

BOARD_STACKUP::~BOARD_STACKUP ( )
inline

Definition at line 217 of file board_stackup.h.

217 { RemoveAll(); }
void RemoveAll()
Delete all items in list and clear the list.

References RemoveAll().

Member Function Documentation

◆ Add()

void BOARD_STACKUP::Add ( BOARD_STACKUP_ITEM aItem)
inline

Add a new item in stackup layer.

Definition at line 245 of file board_stackup.h.

245 { m_list.push_back( aItem ); }
std::vector< BOARD_STACKUP_ITEM * > m_list

References m_list.

Referenced by BOARD_STACKUP(), BuildDefaultStackupList(), operator=(), PCB_PARSER::parseBoardStackup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ BuildBoardThicknessFromStackup()

int BOARD_STACKUP::BuildBoardThicknessFromStackup ( ) const
Returns
the board thickness ( in UI) from the thickness of BOARD_STACKUP_ITEM list

Definition at line 385 of file board_stackup.cpp.

386 {
387  // return the board thickness from the thickness of BOARD_STACKUP_ITEM list
388  int thickness = 0;
389 
390  for( auto item : m_list )
391  {
392  if( item->IsThicknessEditable() && item->IsEnabled() )
393  {
394  thickness += item->GetThickness();
395 
396  // dielectric layers can have more than one main layer
397  // add thickness of all sublayers
398  for( int idx = 1; idx < item->GetSublayersCount(); idx++ )
399  {
400  thickness += item->GetThickness( idx );
401  }
402  }
403  }
404 
405  return thickness;
406 }
std::vector< BOARD_STACKUP_ITEM * > m_list

References m_list.

Referenced by CADSTAR_PCB_ARCHIVE_LOADER::loadBoardStackup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ BuildDefaultStackupList()

void BOARD_STACKUP::BuildDefaultStackupList ( const BOARD_DESIGN_SETTINGS aSettings,
int  aActiveCopperLayersCount = 0 
)

Create a default stackup, according to the current BOARD_DESIGN_SETTINGS settings.

Parameters
aSettingsis the current board setting. if nullptr, build a full stackup (with 32 copper layers)
aActiveCopperLayersCountis used only if aSettings == nullptr is the number of copper layers to use to calculate a default dielectric thickness. ((<= 0 to use all copper layers)

Definition at line 503 of file board_stackup.cpp.

505 {
506  // Creates a default stackup, according to the current BOARD_DESIGN_SETTINGS settings.
507  // Note: the m_TypeName string is made translatable using _HKI marker, but is not
508  // translated when building the stackup.
509  // It will be used as this in files, and can be translated only in dialog
510  // if aSettings == NULL, build a full stackup (with 32 copper layers)
511  LSET enabledLayer = aSettings ? aSettings->GetEnabledLayers() : StackupAllowedBrdLayers();
512  int copperLayerCount = aSettings ? aSettings->GetCopperLayerCount() : B_Cu+1;
513 
514  // We need to calculate a suitable dielectric layer thickness.
515  // If no settings, and if aActiveCopperLayersCount is given, use it
516  // (If no settings, and no aActiveCopperLayersCount, the full 32 layers are used)
517  int activeCuLayerCount = copperLayerCount;
518 
519  if( aSettings == nullptr && aActiveCopperLayersCount > 0 )
520  activeCuLayerCount = aActiveCopperLayersCount;
521 
522  int brd__thickness = aSettings ? aSettings->GetBoardThickness() : Millimeter2iu( 1.6 );
523  int diel_thickness = brd__thickness -
524  ( BOARD_STACKUP_ITEM::GetCopperDefaultThickness() * activeCuLayerCount );
525 
526  // Take in account the solder mask thickness:
527  int sm_count = ( enabledLayer & LSET( 2, F_Mask, B_Mask) ).count();
528  diel_thickness -= BOARD_STACKUP_ITEM::GetMaskDefaultThickness() * sm_count;
529  diel_thickness /= std::max( 1, activeCuLayerCount - 1 );
530 
531  int dielectric_idx = 0;
532 
533  // Add silk screen, solder mask and solder paste layers on top
534  if( enabledLayer[F_SilkS] )
535  {
537  item->SetBrdLayerId( F_SilkS );
538  item->SetTypeName( _HKI( "Top Silk Screen" ) );
539  Add( item );
540  }
541 
542  if( enabledLayer[F_Paste] )
543  {
545  item->SetBrdLayerId( F_Paste );
546  item->SetTypeName( _HKI( "Top Solder Paste" ) );
547  Add( item );
548  }
549 
550  if( enabledLayer[F_Mask] )
551  {
553  item->SetBrdLayerId( F_Mask );
554  item->SetTypeName( _HKI( "Top Solder Mask" ) );
555  Add( item );
556  }
557 
558  // Add copper and dielectric layers
559  for( int ii = 0; ii < copperLayerCount; ii++ )
560  {
562  item->SetBrdLayerId( ( PCB_LAYER_ID )ii );
563  item->SetTypeName( KEY_COPPER );
564  Add( item );
565 
566  if( ii == copperLayerCount-1 )
567  {
568  item->SetBrdLayerId( B_Cu );
569  break;
570  }
571 
572  // Add the dielectric layer:
574  item->SetThickness( diel_thickness );
575  item->SetDielectricLayerId( dielectric_idx + 1 );
576 
577  // Display a dielectric default layer name:
578  if( (dielectric_idx & 1) == 0 )
579  {
580  item->SetTypeName( KEY_CORE );
581  item->SetMaterial( wxT( "FR4" ) );
582  }
583  else
584  {
585  item->SetTypeName( KEY_PREPREG );
586  item->SetMaterial( wxT( "FR4" ) );
587  }
588 
589  Add( item );
590  dielectric_idx++;
591  }
592 
593  // Add silk screen, solder mask and solder paste layers on bottom
594  if( enabledLayer[B_Mask] )
595  {
597  item->SetBrdLayerId( B_Mask );
598  item->SetTypeName( _HKI( "Bottom Solder Mask" ) );
599  Add( item );
600  }
601 
602  if( enabledLayer[B_Paste] )
603  {
605  item->SetBrdLayerId( B_Paste );
606  item->SetTypeName( _HKI( "Bottom Solder Paste" ) );
607  Add( item );
608  }
609 
610  if( enabledLayer[B_SilkS] )
611  {
613  item->SetBrdLayerId( B_SilkS );
614  item->SetTypeName( _HKI( "Bottom Silk Screen" ) );
615  Add( item );
616  }
617 
618  // Transfer other stackup settings from aSettings
619  if( aSettings )
620  {
621  const BOARD_STACKUP& source_stackup = aSettings->GetStackupDescriptor();
623  m_CastellatedPads = source_stackup.m_CastellatedPads;
624  m_EdgePlating = source_stackup.m_EdgePlating;
625  m_FinishType = source_stackup.m_FinishType;
626  }
627 }
void SetBrdLayerId(PCB_LAYER_ID aBrdLayerId)
void SetTypeName(const wxString &aName)
Manage layers needed to make a physical board.
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTO...
bool m_CastellatedPads
True if castellated pads exist.
#define KEY_COPPER
static int GetCopperDefaultThickness()
BOARD_STACKUP & GetStackupDescriptor()
LSET is a set of PCB_LAYER_IDs.
Definition: layer_ids.h:516
static LSET StackupAllowedBrdLayers()
void SetDielectricLayerId(int aLayerId)
void SetMaterial(const wxString &aName, int aDielectricSubLayer=0)
#define KEY_PREPREG
Manage one layer needed to make a physical board.
Definition: board_stackup.h:89
void SetThickness(int aThickness, int aDielectricSubLayer=0)
static int GetMaskDefaultThickness()
LSET GetEnabledLayers() const
Return a bit-mask of all the layers that are enabled.
PCB_LAYER_ID
A quick note on layer IDs:
Definition: layer_ids.h:65
#define KEY_CORE
void Add(BOARD_STACKUP_ITEM *aItem)
Add a new item in stackup layer.
static constexpr int Millimeter2iu(double mm)
#define _HKI(x)

References _HKI, Add(), B_Cu, B_Mask, B_Paste, B_SilkS, BS_ITEM_TYPE_COPPER, BS_ITEM_TYPE_DIELECTRIC, BS_ITEM_TYPE_SILKSCREEN, BS_ITEM_TYPE_SOLDERMASK, BS_ITEM_TYPE_SOLDERPASTE, F_Mask, F_Paste, F_SilkS, BOARD_DESIGN_SETTINGS::GetBoardThickness(), BOARD_STACKUP_ITEM::GetCopperDefaultThickness(), BOARD_DESIGN_SETTINGS::GetCopperLayerCount(), BOARD_DESIGN_SETTINGS::GetEnabledLayers(), BOARD_STACKUP_ITEM::GetMaskDefaultThickness(), BOARD_DESIGN_SETTINGS::GetStackupDescriptor(), KEY_COPPER, KEY_CORE, KEY_PREPREG, m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, Millimeter2iu(), BOARD_STACKUP_ITEM::SetBrdLayerId(), BOARD_STACKUP_ITEM::SetDielectricLayerId(), BOARD_STACKUP_ITEM::SetMaterial(), BOARD_STACKUP_ITEM::SetThickness(), BOARD_STACKUP_ITEM::SetTypeName(), and StackupAllowedBrdLayers().

Referenced by PANEL_SETUP_BOARD_STACKUP::buildLayerStackPanel(), CADSTAR_PCB_ARCHIVE_LOADER::loadBoardStackup(), ALTIUM_PCB::ParseBoard6Data(), and SynchronizeWithBoard().

◆ FormatBoardStackup()

void BOARD_STACKUP::FormatBoardStackup ( OUTPUTFORMATTER aFormatter,
const BOARD aBoard,
int  aNestLevel 
) const

Write the stackup info on board file.

Parameters
aFormatteris the OUTPUTFORMATTER used to create the file
aBoardis the board
aNestLevelis the index to nest level to indent the lines in file

Definition at line 630 of file board_stackup.cpp.

632 {
633  // Board stackup is the ordered list from top to bottom of
634  // physical layers and substrate used to build the board.
635  if( m_list.empty() )
636  return;
637 
638  aFormatter->Print( aNestLevel, "(stackup\n" );
639  int nest_level = aNestLevel+1;
640 
641  // Note:
642  // Unspecified parameters are not stored in file.
643  for( BOARD_STACKUP_ITEM* item: m_list )
644  {
645  wxString layer_name;
646 
647  if( item->GetBrdLayerId() == UNDEFINED_LAYER )
648  layer_name.Printf( wxT( "dielectric %d" ), item->GetDielectricLayerId() );
649  else
650  layer_name = LSET::Name( item->GetBrdLayerId() );
651 
652  aFormatter->Print( nest_level, "(layer %s (type %s)",
653  aFormatter->Quotew( layer_name ).c_str(),
654  aFormatter->Quotew( item->GetTypeName() ).c_str() );
655 
656  if( item->IsColorEditable() && IsPrmSpecified( item->GetColor() ) )
657  aFormatter->Print( 0, " (color %s)",
658  aFormatter->Quotew( item->GetColor() ).c_str() );
659 
660  for( int idx = 0; idx < item->GetSublayersCount(); idx++ )
661  {
662  if( idx ) // not for the main (first) layer.
663  {
664  aFormatter->Print( 0, "\n" );
665  aFormatter->Print( nest_level+1, "addsublayer" );
666  }
667 
668  if( item->IsThicknessEditable() )
669  {
670  if( item->GetType() == BS_ITEM_TYPE_DIELECTRIC && item->IsThicknessLocked( idx ) )
671  aFormatter->Print( 0, " (thickness %s locked)",
672  FormatInternalUnits( item->GetThickness( idx ) ).c_str() );
673  else
674  aFormatter->Print( 0, " (thickness %s)",
675  FormatInternalUnits( item->GetThickness( idx ) ).c_str() );
676  }
677 
678  if( item->HasMaterialValue( idx ) )
679  aFormatter->Print( 0, " (material %s)",
680  aFormatter->Quotew( item->GetMaterial( idx ) ).c_str() );
681 
682  if( item->HasEpsilonRValue() && item->HasMaterialValue( idx ) )
683  aFormatter->Print( 0, " (epsilon_r %g)", item->GetEpsilonR( idx ) );
684 
685  if( item->HasLossTangentValue() && item->HasMaterialValue( idx ) )
686  aFormatter->Print( 0, " (loss_tangent %s)",
687  Double2Str(item->GetLossTangent( idx ) ).c_str() );
688  }
689 
690  aFormatter->Print( 0, ")\n" );
691  }
692 
693  // Other infos about board, related to layers and other fabrication specifications
695  aFormatter->Print( nest_level, "(copper_finish %s)\n",
696  aFormatter->Quotew( m_FinishType ).c_str() );
697 
698  aFormatter->Print( nest_level, "(dielectric_constraints %s)\n",
699  m_HasDielectricConstrains ? "yes" : "no" );
700 
702  aFormatter->Print( nest_level, "(edge_connector %s)\n",
703  m_EdgeConnectorConstraints > 1 ? "bevelled": "yes" );
704 
705  if( m_CastellatedPads )
706  aFormatter->Print( nest_level, "(castellated_pads yes)\n" );
707 
708  if( m_EdgePlating )
709  aFormatter->Print( nest_level, "(edge_plating yes)\n" );
710 
711  aFormatter->Print( aNestLevel, ")\n" );
712 }
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTO...
bool m_CastellatedPads
True if castellated pads exist.
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
static const wxChar * Name(PCB_LAYER_ID aLayerId)
Return the fixed name association with aLayerId.
Definition: lset.cpp:82
std::vector< BOARD_STACKUP_ITEM * > m_list
Manage one layer needed to make a physical board.
Definition: board_stackup.h:89
bool IsPrmSpecified(const wxString &aPrmValue)
std::string Double2Str(double aValue)
Print a float number without using scientific notation and no trailing 0 We want to avoid scientific ...
int PRINTF_FUNC Print(int nestLevel, const char *fmt,...)
Format and write text to the output stream.
Definition: richio.cpp:426
std::string FormatInternalUnits(int aValue)
Function FormatInternalUnits converts aValue from internal units to a string appropriate for writing ...
Definition: base_units.cpp:485
std::string Quotew(const wxString &aWrapee) const
Definition: richio.cpp:494

References BS_ITEM_TYPE_DIELECTRIC, Double2Str(), FormatInternalUnits(), IsPrmSpecified(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_list, LSET::Name(), OUTPUTFORMATTER::Print(), OUTPUTFORMATTER::Quotew(), and UNDEFINED_LAYER.

Referenced by PCB_PLUGIN::formatSetup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ GetCount()

int BOARD_STACKUP::GetCount ( ) const
inline
Returns
the number of layers in the stackup

Definition at line 239 of file board_stackup.h.

239 { return (int) m_list.size(); }
std::vector< BOARD_STACKUP_ITEM * > m_list

References m_list.

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup(), DRAWING_TOOL::DrawSpecificationStackup(), and GetStackupLayer().

◆ GetLayerDistance()

int BOARD_STACKUP::GetLayerDistance ( PCB_LAYER_ID  aFirstLayer,
PCB_LAYER_ID  aSecondLayer 
) const

Calculate the distance (height) between the two given copper layers.

This factors in the thickness of any dielectric and copper layers between the two given layers, and half the height of the given start and end layers. This half-height calculation allows this to be used for consistent length measurements when calculating net length through a series of vias. A more advanced algorithm would be possible once we have a good concept of the start and end for a length measurement, but for now this will do. See https://gitlab.com/kicad/code/kicad/-/issues/8384 for more background.

Parameters
aFirstLayeris a copper layer
aSecondLayeris a different copper layer
Returns
the height (in IU) between the two layers

Definition at line 715 of file board_stackup.cpp.

716 {
717  wxASSERT( IsCopperLayer( aFirstLayer ) && IsCopperLayer( aSecondLayer ) );
718 
719  if( aFirstLayer == aSecondLayer )
720  return 0;
721 
722  if( aSecondLayer < aFirstLayer )
723  std::swap( aFirstLayer, aSecondLayer );
724 
725  int total = 0;
726  bool start = false;
727  bool half = false;
728 
729  for( BOARD_STACKUP_ITEM* item : m_list )
730  {
731  // Will be UNDEFINED_LAYER for dielectrics
732  PCB_LAYER_ID layer = item->GetBrdLayerId();
733 
734  if( layer != UNDEFINED_LAYER && !IsCopperLayer( layer ) )
735  continue; // Silk/mask layer
736 
737  // Reached the start copper layer? Start counting the next dielectric after it
738  if( !start && ( layer != UNDEFINED_LAYER && layer >= aFirstLayer ) )
739  {
740  start = true;
741  half = true;
742  }
743  else if( !start )
744  continue;
745 
746  // Reached the stop copper layer? we're done
747  if( start && ( layer != UNDEFINED_LAYER && layer >= aSecondLayer ) )
748  half = true;
749 
750  for( int sublayer = 0; sublayer < item->GetSublayersCount(); sublayer++ )
751  {
752  int subThickness = item->GetThickness( sublayer );
753  total += half ? ( subThickness / 2 ) : subThickness;
754  }
755 
756  half = false;
757 
758  if( layer != UNDEFINED_LAYER && layer >= aSecondLayer )
759  break;
760  }
761 
762  return total;
763 }
std::vector< BOARD_STACKUP_ITEM * > m_list
Manage one layer needed to make a physical board.
Definition: board_stackup.h:89
bool IsCopperLayer(LAYER_NUM aLayerId)
Tests whether a layer is a copper layer.
Definition: layer_ids.h:808
PCB_LAYER_ID
A quick note on layer IDs:
Definition: layer_ids.h:65

References IsCopperLayer(), m_list, and UNDEFINED_LAYER.

Referenced by DIALOG_NET_INSPECTOR::calculateViaLength(), BOARD::GetTrackLength(), DRC_TEST_PROVIDER_MATCHED_LENGTH::runInternal(), and PNS_KICAD_IFACE_BASE::StackupHeight().

◆ GetList()

◆ GetStackupLayer()

BOARD_STACKUP_ITEM * BOARD_STACKUP::GetStackupLayer ( int  aIndex)
Returns
a reference to the layer aIndex, or nullptr if not exists

Definition at line 376 of file board_stackup.cpp.

377 {
378  if( aIndex < 0 || aIndex >= GetCount() )
379  return nullptr;
380 
381  return GetList()[aIndex];
382 }
int GetCount() const
const std::vector< BOARD_STACKUP_ITEM * > & GetList() const

References GetCount(), and GetList().

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup().

◆ operator=()

BOARD_STACKUP & BOARD_STACKUP::operator= ( const BOARD_STACKUP aOther)

Definition at line 344 of file board_stackup.cpp.

345 {
350  m_EdgePlating = aOther.m_EdgePlating;
351  m_FinishType = aOther.m_FinishType;
352 
353  RemoveAll();
354 
355  // All items in aOther.m_list have to be duplicated, because aOther.m_list
356  // manage pointers to these items
357  for( auto item : aOther.m_list )
358  {
359  BOARD_STACKUP_ITEM* dup_item = new BOARD_STACKUP_ITEM( *item );
360  Add( dup_item );
361  }
362 
363  return *this;
364 }
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTO...
bool m_CastellatedPads
True if castellated pads exist.
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
std::vector< BOARD_STACKUP_ITEM * > m_list
bool m_HasThicknessConstrains
True if some layers (copper and/or dielectric) have specific thickness.
Manage one layer needed to make a physical board.
Definition: board_stackup.h:89
void RemoveAll()
Delete all items in list and clear the list.
void Add(BOARD_STACKUP_ITEM *aItem)
Add a new item in stackup layer.

References Add(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_HasThicknessConstrains, m_list, and RemoveAll().

◆ RemoveAll()

void BOARD_STACKUP::RemoveAll ( )

Delete all items in list and clear the list.

Definition at line 367 of file board_stackup.cpp.

368 {
369  for( auto item : m_list )
370  delete item;
371 
372  m_list.clear();
373 }
std::vector< BOARD_STACKUP_ITEM * > m_list

References m_list.

Referenced by CADSTAR_PCB_ARCHIVE_LOADER::loadBoardStackup(), operator=(), ALTIUM_PCB::ParseBoard6Data(), PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow(), and ~BOARD_STACKUP().

◆ StackupAllowedBrdLayers()

static LSET BOARD_STACKUP::StackupAllowedBrdLayers ( )
inlinestatic
Returns
the board layers full mask allowed in the stackup list i.e. the SilkS, Mask, Paste and all copper layers

Definition at line 228 of file board_stackup.h.

229  {
230  return LSET( 6, F_SilkS, F_Mask, F_Paste, B_SilkS, B_Mask, B_Paste )
232  }
LSET is a set of PCB_LAYER_IDs.
Definition: layer_ids.h:516
static LSET InternalCuMask()
Return a complete set of internal copper layers which is all Cu layers except F_Cu and B_Cu.
Definition: lset.cpp:719
static LSET ExternalCuMask()
Return a mask holding the Front and Bottom layers.
Definition: lset.cpp:789

References B_Mask, B_Paste, B_SilkS, LSET::ExternalCuMask(), F_Mask, F_Paste, F_SilkS, and LSET::InternalCuMask().

Referenced by BuildDefaultStackupList(), PANEL_SETUP_BOARD_STACKUP::ImportSettingsFrom(), PANEL_SETUP_BOARD_STACKUP::OnLayersOptionsChanged(), and PANEL_SETUP_BOARD_STACKUP::PANEL_SETUP_BOARD_STACKUP().

◆ SynchronizeWithBoard()

bool BOARD_STACKUP::SynchronizeWithBoard ( BOARD_DESIGN_SETTINGS aSettings)

Synchronize the BOARD_STACKUP_ITEM* list with the board.

Not enabled layers are removed Missing layers are added

Parameters
aSettings,isthe current board setting.
Returns
true if changes are made

Definition at line 409 of file board_stackup.cpp.

410 {
411  bool change = false;
412  // Build the suitable stackup:
413  BOARD_STACKUP stackup;
414  stackup.BuildDefaultStackupList( aSettings );
415 
416  // First, find removed layers:
417  for( BOARD_STACKUP_ITEM* curr_item: m_list )
418  {
419  bool found = false;
420 
421  for( BOARD_STACKUP_ITEM* item: stackup.GetList() )
422  {
423  if( curr_item->GetBrdLayerId() != UNDEFINED_LAYER )
424  {
425  if( item->GetBrdLayerId() == curr_item->GetBrdLayerId() )
426  {
427  found = true;
428  break;
429  }
430  }
431  else // curr_item = dielectric layer
432  {
433  if( item->GetBrdLayerId() != UNDEFINED_LAYER )
434  continue;
435 
436  if( item->GetDielectricLayerId() == curr_item->GetDielectricLayerId() )
437  {
438  found = true;
439  break;
440  }
441  }
442  }
443 
444  if( !found ) // a layer was removed: a change is found
445  {
446  change = true;
447  break;
448  }
449  }
450 
451  // Now initialize all stackup items to the initial values, when exist
452  for( BOARD_STACKUP_ITEM* item : stackup.GetList() )
453  {
454  bool found = false;
455  // Search for initial settings:
456  for( const BOARD_STACKUP_ITEM* initial_item : m_list )
457  {
458  if( item->GetBrdLayerId() != UNDEFINED_LAYER )
459  {
460  if( item->GetBrdLayerId() == initial_item->GetBrdLayerId() )
461  {
462  *item = *initial_item;
463  found = true;
464  break;
465  }
466  }
467  else // dielectric layer: see m_DielectricLayerId for identification
468  {
469  // Compare dielectric layer with dielectric layer
470  if( initial_item->GetBrdLayerId() != UNDEFINED_LAYER )
471  continue;
472 
473  if( item->GetDielectricLayerId() == initial_item->GetDielectricLayerId() )
474  {
475  *item = *initial_item;
476  found = true;
477  break;
478  }
479  }
480  }
481 
482  if( !found )
483  {
484  change = true;
485  }
486  }
487 
488  // Transfert layer settings:
489  *this = stackup;
490 
491  // Transfer other stackup settings from aSettings
492  const BOARD_STACKUP& source_stackup = aSettings->GetStackupDescriptor();
495  m_CastellatedPads = source_stackup.m_CastellatedPads;
496  m_EdgePlating = source_stackup.m_EdgePlating;
497  m_FinishType = source_stackup.m_FinishType;
498 
499  return change;
500 }
Manage layers needed to make a physical board.
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTO...
bool m_CastellatedPads
True if castellated pads exist.
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
BOARD_STACKUP & GetStackupDescriptor()
std::vector< BOARD_STACKUP_ITEM * > m_list
Manage one layer needed to make a physical board.
Definition: board_stackup.h:89
const std::vector< BOARD_STACKUP_ITEM * > & GetList() const
void BuildDefaultStackupList(const BOARD_DESIGN_SETTINGS *aSettings, int aActiveCopperLayersCount=0)
Create a default stackup, according to the current BOARD_DESIGN_SETTINGS settings.

References BuildDefaultStackupList(), GetList(), BOARD_DESIGN_SETTINGS::GetStackupDescriptor(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_list, and UNDEFINED_LAYER.

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup(), and DRAWING_TOOL::DrawSpecificationStackup().

Member Data Documentation

◆ m_CastellatedPads

◆ m_EdgeConnectorConstraints

BS_EDGE_CONNECTOR_CONSTRAINTS BOARD_STACKUP::m_EdgeConnectorConstraints

If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTOR_NONE = no edge connector BS_EDGE_CONNECTOR_IN_USE = board has edge connectors BS_EDGE_CONNECTOR_BEVELLED = edge connectors are beveled.

Definition at line 318 of file board_stackup.h.

Referenced by BOARD_STACKUP(), BuildDefaultStackupList(), BuildStackupReport(), DRAWING_TOOL::DrawBoardCharacteristics(), FormatBoardStackup(), operator=(), PCB_PARSER::parseBoardStackup(), PANEL_SETUP_BOARD_FINISH::synchronizeWithBoard(), SynchronizeWithBoard(), PANEL_SETUP_BOARD_FINISH::TransferDataFromWindow(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ m_EdgePlating

◆ m_FinishType

◆ m_HasDielectricConstrains

bool BOARD_STACKUP::m_HasDielectricConstrains

True if some layers have impedance controlled tracks or have specific constrains for micro-wave applications If the board has dielectric constrains, the .gbrjob will contain info about dielectric constrains: loss tangent and Epsilon rel.

If not, these values will be not specified in job file.

Definition at line 304 of file board_stackup.h.

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup(), BOARD_STACKUP(), BuildStackupReport(), DRAWING_TOOL::DrawBoardCharacteristics(), FormatBoardStackup(), operator=(), PCB_PARSER::parseBoardStackup(), PANEL_SETUP_BOARD_STACKUP::synchronizeWithBoard(), SynchronizeWithBoard(), PANEL_SETUP_BOARD_STACKUP::transferDataFromUIToStackup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ m_HasThicknessConstrains

bool BOARD_STACKUP::m_HasThicknessConstrains

True if some layers (copper and/or dielectric) have specific thickness.

Definition at line 309 of file board_stackup.h.

Referenced by BOARD_STACKUP(), and operator=().

◆ m_list


The documentation for this class was generated from the following files: