KiCad PCB EDA Suite
BOARD_STACKUP Class Reference

Manage layers needed to make a physical board. More...

#include <board_stackup.h>

Public Member Functions

 BOARD_STACKUP ()
 
 BOARD_STACKUP (const BOARD_STACKUP &aOther)
 
BOARD_STACKUPoperator= (const BOARD_STACKUP &aOther)
 
 ~BOARD_STACKUP ()
 
const std::vector< BOARD_STACKUP_ITEM * > & GetList () const
 
BOARD_STACKUP_ITEMGetStackupLayer (int aIndex)
 
void RemoveAll ()
 Delete all items in list and clear the list. More...
 
int GetCount () const
 
int BuildBoardThicknessFromStackup () const
 
void Add (BOARD_STACKUP_ITEM *aItem)
 Add a new item in stackup layer. More...
 
bool SynchronizeWithBoard (BOARD_DESIGN_SETTINGS *aSettings)
 Synchronize the BOARD_STACKUP_ITEM* list with the board. More...
 
void BuildDefaultStackupList (const BOARD_DESIGN_SETTINGS *aSettings, int aActiveCopperLayersCount=0)
 Create a default stackup, according to the current BOARD_DESIGN_SETTINGS settings. More...
 
void FormatBoardStackup (OUTPUTFORMATTER *aFormatter, const BOARD *aBoard, int aNestLevel) const
 Write the stackup info on board file. More...
 
int GetLayerDistance (PCB_LAYER_ID aFirstLayer, PCB_LAYER_ID aSecondLayer) const
 Calculate the distance (height) between the two given copper layers. More...
 

Static Public Member Functions

static LSET StackupAllowedBrdLayers ()
 

Public Attributes

wxString m_FinishType
 The name of external copper finish. More...
 
bool m_HasDielectricConstrains
 True if some layers have impedance controlled tracks or have specific constrains for micro-wave applications If the board has dielectric constrains, the .gbrjob will contain info about dielectric constrains: loss tangent and Epsilon rel. More...
 
bool m_HasThicknessConstrains
 True if some layers (copper and/or dielectric) have specific thickness. More...
 
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
 If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTOR_NONE = no edge connector BS_EDGE_CONNECTOR_IN_USE = board has edge connectors BS_EDGE_CONNECTOR_BEVELLED = edge connectors are beveled. More...
 
bool m_CastellatedPads
 True if castellated pads exist. More...
 
bool m_EdgePlating
 True if the edge board is plated. More...
 

Private Attributes

std::vector< BOARD_STACKUP_ITEM * > m_list
 

Detailed Description

Manage layers needed to make a physical board.

They are solder mask, silk screen, copper and dielectric. Some other layers, used in fabrication, are not managed here because they are not used to make a physical board itself.

Note
There are a few other parameters related to the physical stackup like finish type, impedance control and a few others.

Definition at line 210 of file board_stackup.h.

Constructor & Destructor Documentation

◆ BOARD_STACKUP() [1/2]

BOARD_STACKUP::BOARD_STACKUP ( )

Definition at line 312 of file board_stackup.cpp.

313 {
314  m_HasDielectricConstrains = false; // True if some dielectric layers have constrains
315  // (Loss tg and Epison R)
316  m_HasThicknessConstrains = false; // True if some dielectric or copper layers have constrains
318  m_CastellatedPads = false; // True if some castellated pads exist
319  m_EdgePlating = false; // True if edge board is plated
320  m_FinishType = "None"; // undefined finish type
321 }
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTO...
bool m_CastellatedPads
True if castellated pads exist.
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
bool m_HasThicknessConstrains
True if some layers (copper and/or dielectric) have specific thickness.

References BS_EDGE_CONNECTOR_NONE, m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, and m_HasThicknessConstrains.

◆ BOARD_STACKUP() [2/2]

BOARD_STACKUP::BOARD_STACKUP ( const BOARD_STACKUP aOther)

Definition at line 324 of file board_stackup.cpp.

325 {
330  m_EdgePlating = aOther.m_EdgePlating;
331  m_FinishType = aOther.m_FinishType;
332 
333  // All items in aOther.m_list have to be duplicated, because aOther.m_list
334  // manage pointers to these items
335  for( auto item : aOther.m_list )
336  {
337  BOARD_STACKUP_ITEM* dup_item = new BOARD_STACKUP_ITEM( *item );
338  Add( dup_item );
339  }
340 }
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTO...
bool m_CastellatedPads
True if castellated pads exist.
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
std::vector< BOARD_STACKUP_ITEM * > m_list
bool m_HasThicknessConstrains
True if some layers (copper and/or dielectric) have specific thickness.
Manage one layer needed to make a physical board.
Definition: board_stackup.h:89
void Add(BOARD_STACKUP_ITEM *aItem)
Add a new item in stackup layer.

References Add(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_HasThicknessConstrains, and m_list.

◆ ~BOARD_STACKUP()

BOARD_STACKUP::~BOARD_STACKUP ( )
inline

Definition at line 217 of file board_stackup.h.

217 { RemoveAll(); }
void RemoveAll()
Delete all items in list and clear the list.

References RemoveAll().

Member Function Documentation

◆ Add()

void BOARD_STACKUP::Add ( BOARD_STACKUP_ITEM aItem)
inline

Add a new item in stackup layer.

Definition at line 245 of file board_stackup.h.

245 { m_list.push_back( aItem ); }
std::vector< BOARD_STACKUP_ITEM * > m_list

References m_list.

Referenced by BOARD_STACKUP(), BuildDefaultStackupList(), operator=(), PCB_PARSER::parseBoardStackup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ BuildBoardThicknessFromStackup()

int BOARD_STACKUP::BuildBoardThicknessFromStackup ( ) const
Returns
the board thickness ( in UI) from the thickness of BOARD_STACKUP_ITEM list

Definition at line 384 of file board_stackup.cpp.

385 {
386  // return the board thickness from the thickness of BOARD_STACKUP_ITEM list
387  int thickness = 0;
388 
389  for( auto item : m_list )
390  {
391  if( item->IsThicknessEditable() && item->IsEnabled() )
392  thickness += item->GetThickness();
393  }
394 
395  return thickness;
396 }
std::vector< BOARD_STACKUP_ITEM * > m_list

References m_list.

Referenced by PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ BuildDefaultStackupList()

void BOARD_STACKUP::BuildDefaultStackupList ( const BOARD_DESIGN_SETTINGS aSettings,
int  aActiveCopperLayersCount = 0 
)

Create a default stackup, according to the current BOARD_DESIGN_SETTINGS settings.

Parameters
aSettingsis the current board setting. if nullptr, build a full stackup (with 32 copper layers)
aActiveCopperLayersCountis used only if aSettings == nullptr is the number of copper layers to use to calculate a default dielectric thickness. ((<= 0 to use all copper layers)

Definition at line 492 of file board_stackup.cpp.

494 {
495  // Creates a default stackup, according to the current BOARD_DESIGN_SETTINGS settings.
496  // Note: the m_TypeName string is made translatable using _HKI marker, but is not
497  // translated when building the stackup.
498  // It will be used as this in files, and can be translated only in dialog
499  // if aSettings == NULL, build a full stackup (with 32 copper layers)
500  LSET enabledLayer = aSettings ? aSettings->GetEnabledLayers() : StackupAllowedBrdLayers();
501  int copperLayerCount = aSettings ? aSettings->GetCopperLayerCount() : B_Cu+1;
502 
503  // We need to calculate a suitable dielectric layer thickness.
504  // If no settings, and if aActiveCopperLayersCount is given, use it
505  // (If no settings, and no aActiveCopperLayersCount, the full 32 layers are used)
506  int activeCuLayerCount = copperLayerCount;
507 
508  if( aSettings == nullptr && aActiveCopperLayersCount > 0 )
509  activeCuLayerCount = aActiveCopperLayersCount;
510 
511  int brd__thickness = aSettings ? aSettings->GetBoardThickness() : Millimeter2iu( 1.6 );
512  int diel_thickness = brd__thickness -
513  ( BOARD_STACKUP_ITEM::GetCopperDefaultThickness() * activeCuLayerCount );
514 
515  // Take in account the solder mask thickness:
516  int sm_count = ( enabledLayer & LSET( 2, F_Mask, B_Mask) ).count();
517  diel_thickness -= BOARD_STACKUP_ITEM::GetMaskDefaultThickness() * sm_count;
518 
519  int dielectric_idx = 0;
520 
521  // Add silk screen, solder mask and solder paste layers on top
522  if( enabledLayer[F_SilkS] )
523  {
525  item->SetBrdLayerId( F_SilkS );
526  item->SetTypeName( _HKI( "Top Silk Screen" ) );
527  Add( item );
528  }
529 
530  if( enabledLayer[F_Paste] )
531  {
533  item->SetBrdLayerId( F_Paste );
534  item->SetTypeName( _HKI( "Top Solder Paste" ) );
535  Add( item );
536  }
537 
538  if( enabledLayer[F_Mask] )
539  {
541  item->SetBrdLayerId( F_Mask );
542  item->SetTypeName( _HKI( "Top Solder Mask" ) );
543  Add( item );
544  }
545 
546  // Add copper and dielectric layers
547  for( int ii = 0; ii < copperLayerCount; ii++ )
548  {
550  item->SetBrdLayerId( ( PCB_LAYER_ID )ii );
551  item->SetTypeName( KEY_COPPER );
552  Add( item );
553 
554  if( ii == copperLayerCount-1 )
555  {
556  item->SetBrdLayerId( B_Cu );
557  break;
558  }
559 
560  // Add the dielectric layer:
562  item->SetThickness( diel_thickness );
563  item->SetDielectricLayerId( dielectric_idx + 1 );
564 
565  // Display a dielectric default layer name:
566  if( (dielectric_idx & 1) == 0 )
567  {
568  item->SetTypeName( KEY_CORE );
569  item->SetMaterial( "FR4" );
570  }
571  else
572  {
573  item->SetTypeName( KEY_PREPREG );
574  item->SetMaterial( "FR4" );
575  }
576 
577  Add( item );
578  dielectric_idx++;
579  }
580 
581  // Add silk screen, solder mask and solder paste layers on bottom
582  if( enabledLayer[B_Mask] )
583  {
585  item->SetBrdLayerId( B_Mask );
586  item->SetTypeName( _HKI( "Bottom Solder Mask" ) );
587  Add( item );
588  }
589 
590  if( enabledLayer[B_Paste] )
591  {
593  item->SetBrdLayerId( B_Paste );
594  item->SetTypeName( _HKI( "Bottom Solder Paste" ) );
595  Add( item );
596  }
597 
598  if( enabledLayer[B_SilkS] )
599  {
601  item->SetBrdLayerId( B_SilkS );
602  item->SetTypeName( _HKI( "Bottom Silk Screen" ) );
603  Add( item );
604  }
605 
606  // Transfer other stackup settings from aSettings
607  if( aSettings )
608  {
609  const BOARD_STACKUP& source_stackup = aSettings->GetStackupDescriptor();
611  m_CastellatedPads = source_stackup.m_CastellatedPads;
612  m_EdgePlating = source_stackup.m_EdgePlating;
613  m_FinishType = source_stackup.m_FinishType;
614  }
615 }
void SetBrdLayerId(PCB_LAYER_ID aBrdLayerId)
void SetTypeName(const wxString &aName)
Manage layers needed to make a physical board.
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTO...
bool m_CastellatedPads
True if castellated pads exist.
#define KEY_COPPER
static int GetCopperDefaultThickness()
BOARD_STACKUP & GetStackupDescriptor()
PCB_LAYER_ID
A quick note on layer IDs:
LSET is a set of PCB_LAYER_IDs.
static LSET StackupAllowedBrdLayers()
void SetDielectricLayerId(int aLayerId)
void SetMaterial(const wxString &aName, int aDielectricSubLayer=0)
#define KEY_PREPREG
Manage one layer needed to make a physical board.
Definition: board_stackup.h:89
void SetThickness(int aThickness, int aDielectricSubLayer=0)
static int GetMaskDefaultThickness()
LSET GetEnabledLayers() const
Return a bit-mask of all the layers that are enabled.
#define KEY_CORE
void Add(BOARD_STACKUP_ITEM *aItem)
Add a new item in stackup layer.
static constexpr int Millimeter2iu(double mm)
#define _HKI(x)

References _HKI, Add(), B_Cu, B_Mask, B_Paste, B_SilkS, BS_ITEM_TYPE_COPPER, BS_ITEM_TYPE_DIELECTRIC, BS_ITEM_TYPE_SILKSCREEN, BS_ITEM_TYPE_SOLDERMASK, BS_ITEM_TYPE_SOLDERPASTE, F_Mask, F_Paste, F_SilkS, BOARD_DESIGN_SETTINGS::GetBoardThickness(), BOARD_STACKUP_ITEM::GetCopperDefaultThickness(), BOARD_DESIGN_SETTINGS::GetCopperLayerCount(), BOARD_DESIGN_SETTINGS::GetEnabledLayers(), BOARD_STACKUP_ITEM::GetMaskDefaultThickness(), BOARD_DESIGN_SETTINGS::GetStackupDescriptor(), KEY_COPPER, KEY_CORE, KEY_PREPREG, m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, Millimeter2iu(), BOARD_STACKUP_ITEM::SetBrdLayerId(), BOARD_STACKUP_ITEM::SetDielectricLayerId(), BOARD_STACKUP_ITEM::SetMaterial(), BOARD_STACKUP_ITEM::SetThickness(), BOARD_STACKUP_ITEM::SetTypeName(), and StackupAllowedBrdLayers().

Referenced by PANEL_SETUP_BOARD_STACKUP::buildLayerStackPanel(), ALTIUM_PCB::ParseBoard6Data(), and SynchronizeWithBoard().

◆ FormatBoardStackup()

void BOARD_STACKUP::FormatBoardStackup ( OUTPUTFORMATTER aFormatter,
const BOARD aBoard,
int  aNestLevel 
) const

Write the stackup info on board file.

Parameters
aFormatteris the OUTPUTFORMATTER used to create the file
aBoardis the board
aNestLevelis the index to nest level to indent the lines in file

Definition at line 618 of file board_stackup.cpp.

620 {
621  // Board stackup is the ordered list from top to bottom of
622  // physical layers and substrate used to build the board.
623  if( m_list.empty() )
624  return;
625 
626  aFormatter->Print( aNestLevel, "(stackup\n" );
627  int nest_level = aNestLevel+1;
628 
629  // Note:
630  // Unspecified parameters are not stored in file.
631  for( BOARD_STACKUP_ITEM* item: m_list )
632  {
633  wxString layer_name;
634 
635  if( item->GetBrdLayerId() == UNDEFINED_LAYER )
636  layer_name.Printf( "dielectric %d", item->GetDielectricLayerId() );
637  else
638  layer_name = LSET::Name( item->GetBrdLayerId() );
639 
640  aFormatter->Print( nest_level, "(layer %s (type %s)",
641  aFormatter->Quotew( layer_name ).c_str(),
642  aFormatter->Quotew( item->GetTypeName() ).c_str() );
643 
644  if( item->IsColorEditable() && IsPrmSpecified( item->GetColor() ) )
645  aFormatter->Print( 0, " (color %s)",
646  aFormatter->Quotew( item->GetColor() ).c_str() );
647 
648  for( int idx = 0; idx < item->GetSublayersCount(); idx++ )
649  {
650  if( idx ) // not for the main (first) layer.
651  {
652  aFormatter->Print( 0, "\n" );
653  aFormatter->Print( nest_level+1, "addsublayer" );
654  }
655 
656  if( item->IsThicknessEditable() )
657  {
658  if( item->GetType() == BS_ITEM_TYPE_DIELECTRIC && item->IsThicknessLocked( idx ) )
659  aFormatter->Print( 0, " (thickness %s locked)",
660  FormatInternalUnits( item->GetThickness( idx ) ).c_str() );
661  else
662  aFormatter->Print( 0, " (thickness %s)",
663  FormatInternalUnits( item->GetThickness( idx ) ).c_str() );
664  }
665 
666  if( item->HasMaterialValue( idx ) )
667  aFormatter->Print( 0, " (material %s)",
668  aFormatter->Quotew( item->GetMaterial( idx ) ).c_str() );
669 
670  if( item->HasEpsilonRValue() && item->HasMaterialValue( idx ) )
671  aFormatter->Print( 0, " (epsilon_r %g)", item->GetEpsilonR( idx ) );
672 
673  if( item->HasLossTangentValue() && item->HasMaterialValue( idx ) )
674  aFormatter->Print( 0, " (loss_tangent %s)",
675  Double2Str(item->GetLossTangent( idx ) ).c_str() );
676  }
677 
678  aFormatter->Print( 0, ")\n" );
679  }
680 
681  // Other infos about board, related to layers and other fabrication specifications
683  aFormatter->Print( nest_level, "(copper_finish %s)\n",
684  aFormatter->Quotew( m_FinishType ).c_str() );
685 
686  aFormatter->Print( nest_level, "(dielectric_constraints %s)\n",
687  m_HasDielectricConstrains ? "yes" : "no" );
688 
690  aFormatter->Print( nest_level, "(edge_connector %s)\n",
691  m_EdgeConnectorConstraints > 1 ? "bevelled": "yes" );
692 
693  if( m_CastellatedPads )
694  aFormatter->Print( nest_level, "(castellated_pads yes)\n" );
695 
696  if( m_EdgePlating )
697  aFormatter->Print( nest_level, "(edge_plating yes)\n" );
698 
699  aFormatter->Print( aNestLevel, ")\n" );
700 }
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTO...
bool m_CastellatedPads
True if castellated pads exist.
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
static const wxChar * Name(PCB_LAYER_ID aLayerId)
Return the fixed name association with aLayerId.
Definition: lset.cpp:82
std::vector< BOARD_STACKUP_ITEM * > m_list
Manage one layer needed to make a physical board.
Definition: board_stackup.h:89
bool IsPrmSpecified(const wxString &aPrmValue)
int PRINTF_FUNC Print(int nestLevel, const char *fmt,...)
Format and write text to the output stream.
Definition: richio.cpp:408
std::string FormatInternalUnits(int aValue)
Function FormatInternalUnits converts aValue from internal units to a string appropriate for writing ...
Definition: base_units.cpp:471
std::string Quotew(const wxString &aWrapee) const
Definition: richio.cpp:476
std::string Double2Str(double aValue)
Prints a float number without using scientific notation and no trailing 0 We want to avoid scientific...
Definition: string.cpp:872

References BS_ITEM_TYPE_DIELECTRIC, Double2Str(), FormatInternalUnits(), IsPrmSpecified(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_list, LSET::Name(), OUTPUTFORMATTER::Print(), OUTPUTFORMATTER::Quotew(), and UNDEFINED_LAYER.

Referenced by PCB_IO::formatSetup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ GetCount()

int BOARD_STACKUP::GetCount ( ) const
inline
Returns
the number of layers in the stackup

Definition at line 239 of file board_stackup.h.

239 { return (int) m_list.size(); }
std::vector< BOARD_STACKUP_ITEM * > m_list

References m_list.

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup(), DRAWING_TOOL::DrawSpecificationStackup(), and GetStackupLayer().

◆ GetLayerDistance()

int BOARD_STACKUP::GetLayerDistance ( PCB_LAYER_ID  aFirstLayer,
PCB_LAYER_ID  aSecondLayer 
) const

Calculate the distance (height) between the two given copper layers.

This factors in the thickness of any dielectric and copper layers between the two given layers, but not the height of the given copper layers.

Parameters
aFirstLayeris a copper layer
aSecondLayeris a different copper layer
Returns
the height (in IU) between the two layers

Definition at line 703 of file board_stackup.cpp.

704 {
705  wxASSERT( IsCopperLayer( aFirstLayer ) && IsCopperLayer( aSecondLayer ) );
706 
707  if( aFirstLayer == aSecondLayer )
708  return 0;
709 
710  if( aSecondLayer < aFirstLayer )
711  std::swap( aFirstLayer, aSecondLayer );
712 
713  int total = 0;
714 
715  for( BOARD_STACKUP_ITEM* item : m_list )
716  {
717  // Will be UNDEFINED_LAYER for dielectrics
718  PCB_LAYER_ID layer = item->GetBrdLayerId();
719 
720  if( layer != UNDEFINED_LAYER && !IsCopperLayer( layer ) )
721  continue; // Silk/mask layer
722  else if( layer != UNDEFINED_LAYER && layer <= aFirstLayer )
723  continue; // Copper layer before first
724  else if( layer != UNDEFINED_LAYER && layer >= aSecondLayer )
725  break; // Copper layer after last: we're done
726 
727  for( int sublayer = 0; sublayer < item->GetSublayersCount(); sublayer++ )
728  total += item->GetThickness( sublayer );
729  }
730 
731  return total;
732 }
PCB_LAYER_ID
A quick note on layer IDs:
std::vector< BOARD_STACKUP_ITEM * > m_list
Manage one layer needed to make a physical board.
Definition: board_stackup.h:89
bool IsCopperLayer(LAYER_NUM aLayerId)
Tests whether a layer is a copper layer.

References IsCopperLayer(), m_list, and UNDEFINED_LAYER.

Referenced by DIALOG_NET_INSPECTOR::calculateViaLength(), BOARD::GetTrackLength(), and PNS_KICAD_IFACE_BASE::StackupHeight().

◆ GetList()

◆ GetStackupLayer()

BOARD_STACKUP_ITEM * BOARD_STACKUP::GetStackupLayer ( int  aIndex)
Returns
a reference to the layer aIndex, or nullptr if not exists

Definition at line 375 of file board_stackup.cpp.

376 {
377  if( aIndex < 0 || aIndex >= GetCount() )
378  return nullptr;
379 
380  return GetList()[aIndex];
381 }
int GetCount() const
const std::vector< BOARD_STACKUP_ITEM * > & GetList() const

References GetCount(), and GetList().

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup().

◆ operator=()

BOARD_STACKUP & BOARD_STACKUP::operator= ( const BOARD_STACKUP aOther)

Definition at line 343 of file board_stackup.cpp.

344 {
349  m_EdgePlating = aOther.m_EdgePlating;
350  m_FinishType = aOther.m_FinishType;
351 
352  RemoveAll();
353 
354  // All items in aOther.m_list have to be duplicated, because aOther.m_list
355  // manage pointers to these items
356  for( auto item : aOther.m_list )
357  {
358  BOARD_STACKUP_ITEM* dup_item = new BOARD_STACKUP_ITEM( *item );
359  Add( dup_item );
360  }
361 
362  return *this;
363 }
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTO...
bool m_CastellatedPads
True if castellated pads exist.
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
std::vector< BOARD_STACKUP_ITEM * > m_list
bool m_HasThicknessConstrains
True if some layers (copper and/or dielectric) have specific thickness.
Manage one layer needed to make a physical board.
Definition: board_stackup.h:89
void RemoveAll()
Delete all items in list and clear the list.
void Add(BOARD_STACKUP_ITEM *aItem)
Add a new item in stackup layer.

References Add(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_HasThicknessConstrains, m_list, and RemoveAll().

◆ RemoveAll()

void BOARD_STACKUP::RemoveAll ( )

Delete all items in list and clear the list.

Definition at line 366 of file board_stackup.cpp.

367 {
368  for( auto item : m_list )
369  delete item;
370 
371  m_list.clear();
372 }
std::vector< BOARD_STACKUP_ITEM * > m_list

References m_list.

Referenced by CADSTAR_PCB_ARCHIVE_LOADER::loadBoardStackup(), operator=(), ALTIUM_PCB::ParseBoard6Data(), PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow(), and ~BOARD_STACKUP().

◆ StackupAllowedBrdLayers()

static LSET BOARD_STACKUP::StackupAllowedBrdLayers ( )
inlinestatic
Returns
the board layers full mask allowed in the stackup list i.e. the SilkS, Mask, Paste and all copper layers

Definition at line 228 of file board_stackup.h.

229  {
230  return LSET( 6, F_SilkS, F_Mask, F_Paste, B_SilkS, B_Mask, B_Paste )
232  }
LSET is a set of PCB_LAYER_IDs.
static LSET InternalCuMask()
Return a complete set of internal copper layers which is all Cu layers except F_Cu and B_Cu.
Definition: lset.cpp:710
static LSET ExternalCuMask()
Return a mask holding the Front and Bottom layers.
Definition: lset.cpp:780

References B_Mask, B_Paste, B_SilkS, LSET::ExternalCuMask(), F_Mask, F_Paste, F_SilkS, and LSET::InternalCuMask().

Referenced by BuildDefaultStackupList(), PANEL_SETUP_BOARD_STACKUP::ImportSettingsFrom(), PANEL_SETUP_BOARD_STACKUP::OnLayersOptionsChanged(), PANEL_SETUP_BOARD_STACKUP::PANEL_SETUP_BOARD_STACKUP(), and PANEL_SETUP_BOARD_STACKUP::transferDataFromUIToStackup().

◆ SynchronizeWithBoard()

bool BOARD_STACKUP::SynchronizeWithBoard ( BOARD_DESIGN_SETTINGS aSettings)

Synchronize the BOARD_STACKUP_ITEM* list with the board.

Not enabled layers are removed Missing layers are added

Parameters
aSettings,isthe current board setting.
Returns
true if changes are made

Definition at line 399 of file board_stackup.cpp.

400 {
401  bool change = false;
402  // Build the suitable stackup:
403  BOARD_STACKUP stackup;
404  stackup.BuildDefaultStackupList( aSettings );
405 
406  // First, find removed layers:
407  for( BOARD_STACKUP_ITEM* curr_item: m_list )
408  {
409  bool found = false;
410 
411  for( BOARD_STACKUP_ITEM* item: stackup.GetList() )
412  {
413  if( curr_item->GetBrdLayerId() != UNDEFINED_LAYER )
414  {
415  if( item->GetBrdLayerId() == curr_item->GetBrdLayerId() )
416  {
417  found = true;
418  break;
419  }
420  }
421  else // curr_item = dielectric layer
422  {
423  if( item->GetBrdLayerId() != UNDEFINED_LAYER )
424  continue;
425 
426  if( item->GetDielectricLayerId() == curr_item->GetDielectricLayerId() )
427  {
428  found = true;
429  break;
430  }
431  }
432  }
433 
434  if( !found ) // a layer was removed: a change is found
435  {
436  change = true;
437  break;
438  }
439  }
440 
441  // Now initialize all stackup items to the initial values, when exist
442  for( BOARD_STACKUP_ITEM* item : stackup.GetList() )
443  {
444  bool found = false;
445  // Search for initial settings:
446  for( const BOARD_STACKUP_ITEM* initial_item : m_list )
447  {
448  if( item->GetBrdLayerId() != UNDEFINED_LAYER )
449  {
450  if( item->GetBrdLayerId() == initial_item->GetBrdLayerId() )
451  {
452  *item = *initial_item;
453  found = true;
454  break;
455  }
456  }
457  else // dielectric layer: see m_DielectricLayerId for identification
458  {
459  // Compare dielectric layer with dielectric layer
460  if( initial_item->GetBrdLayerId() != UNDEFINED_LAYER )
461  continue;
462 
463  if( item->GetDielectricLayerId() == initial_item->GetDielectricLayerId() )
464  {
465  *item = *initial_item;
466  found = true;
467  break;
468  }
469  }
470  }
471 
472  if( !found )
473  {
474  change = true;
475  }
476  }
477 
478  // Transfer other stackup settings from aSettings
479  const BOARD_STACKUP& source_stackup = aSettings->GetStackupDescriptor();
482  m_CastellatedPads = source_stackup.m_CastellatedPads;
483  m_EdgePlating = source_stackup.m_EdgePlating;
484  m_FinishType = source_stackup.m_FinishType;
485 
486  *this = stackup;
487 
488  return change;
489 }
Manage layers needed to make a physical board.
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTO...
bool m_CastellatedPads
True if castellated pads exist.
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
BOARD_STACKUP & GetStackupDescriptor()
std::vector< BOARD_STACKUP_ITEM * > m_list
Manage one layer needed to make a physical board.
Definition: board_stackup.h:89
const std::vector< BOARD_STACKUP_ITEM * > & GetList() const
void BuildDefaultStackupList(const BOARD_DESIGN_SETTINGS *aSettings, int aActiveCopperLayersCount=0)
Create a default stackup, according to the current BOARD_DESIGN_SETTINGS settings.

References BuildDefaultStackupList(), GetList(), BOARD_DESIGN_SETTINGS::GetStackupDescriptor(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_list, and UNDEFINED_LAYER.

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup().

Member Data Documentation

◆ m_CastellatedPads

◆ m_EdgeConnectorConstraints

BS_EDGE_CONNECTOR_CONSTRAINTS BOARD_STACKUP::m_EdgeConnectorConstraints

If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTOR_NONE = no edge connector BS_EDGE_CONNECTOR_IN_USE = board has edge connectors BS_EDGE_CONNECTOR_BEVELLED = edge connectors are beveled.

Definition at line 313 of file board_stackup.h.

Referenced by BOARD_STACKUP(), BuildDefaultStackupList(), BuildStackupReport(), FormatBoardStackup(), operator=(), PCB_PARSER::parseBoardStackup(), PANEL_SETUP_BOARD_FINISH::synchronizeWithBoard(), SynchronizeWithBoard(), PANEL_SETUP_BOARD_FINISH::TransferDataFromWindow(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ m_EdgePlating

◆ m_FinishType

◆ m_HasDielectricConstrains

bool BOARD_STACKUP::m_HasDielectricConstrains

True if some layers have impedance controlled tracks or have specific constrains for micro-wave applications If the board has dielectric constrains, the .gbrjob will contain info about dielectric constrains: loss tangent and Epsilon rel.

If not, these values will be not specified in job file.

Definition at line 299 of file board_stackup.h.

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup(), BOARD_STACKUP(), BuildStackupReport(), DRAWING_TOOL::DrawBoardCharacteristics(), FormatBoardStackup(), operator=(), PCB_PARSER::parseBoardStackup(), PANEL_SETUP_BOARD_STACKUP::synchronizeWithBoard(), SynchronizeWithBoard(), PANEL_SETUP_BOARD_STACKUP::transferDataFromUIToStackup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ m_HasThicknessConstrains

bool BOARD_STACKUP::m_HasThicknessConstrains

True if some layers (copper and/or dielectric) have specific thickness.

Definition at line 304 of file board_stackup.h.

Referenced by BOARD_STACKUP(), and operator=().

◆ m_list


The documentation for this class was generated from the following files: