BOARD_STACKUP Class Reference

Manage layers needed to make a physical board. More...

#include <board_stackup.h>

Public Member Functions
	BOARD_STACKUP ()
	BOARD_STACKUP (const BOARD_STACKUP &aOther)
BOARD_STACKUP &	operator= (const BOARD_STACKUP &aOther)
	~BOARD_STACKUP ()
const std::vector< BOARD_STACKUP_ITEM * > &	GetList () const
BOARD_STACKUP_ITEM *	GetStackupLayer (int aIndex)
void	RemoveAll ()
	Delete all items in list and clear the list. More...
int	GetCount () const
int	BuildBoardThicknessFromStackup () const
void	Add (BOARD_STACKUP_ITEM *aItem)
	Add a new item in stackup layer. More...
bool	SynchronizeWithBoard (BOARD_DESIGN_SETTINGS *aSettings)
	Synchronize the BOARD_STACKUP_ITEM* list with the board. More...
void	BuildDefaultStackupList (const BOARD_DESIGN_SETTINGS *aSettings, int aActiveCopperLayersCount=0)
	Create a default stackup, according to the current BOARD_DESIGN_SETTINGS settings. More...
void	FormatBoardStackup (OUTPUTFORMATTER *aFormatter, const BOARD *aBoard, int aNestLevel) const
	Write the stackup info on board file. More...
int	GetLayerDistance (PCB_LAYER_ID aFirstLayer, PCB_LAYER_ID aSecondLayer) const
	Calculate the distance (height) between the two given copper layers. More...

Static Public Member Functions
static LSET	StackupAllowedBrdLayers ()

Public Attributes
wxString	m_FinishType
	The name of external copper finish. More...
bool	m_HasDielectricConstrains
	True if some layers have impedance controlled tracks or have specific constrains for micro-wave applications If the board has dielectric constrains, the .gbrjob will contain info about dielectric constrains: loss tangent and Epsilon rel. More...
bool	m_HasThicknessConstrains
	True if some layers (copper and/or dielectric) have specific thickness. More...
BS_EDGE_CONNECTOR_CONSTRAINTS	m_EdgeConnectorConstraints
	If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTOR_NONE = no edge connector BS_EDGE_CONNECTOR_IN_USE = board has edge connectors BS_EDGE_CONNECTOR_BEVELLED = edge connectors are beveled. More...
bool	m_CastellatedPads
	True if castellated pads exist. More...
bool	m_EdgePlating
	True if the edge board is plated. More...

Private Attributes
std::vector< BOARD_STACKUP_ITEM * >	m_list

Detailed Description

Manage layers needed to make a physical board.

They are solder mask, silk screen, copper and dielectric. Some other layers, used in fabrication, are not managed here because they are not used to make a physical board itself.

Note

There are a few other parameters related to the physical stackup like finish type, impedance control and a few others.

Definition at line 210 of file board_stackup.h.

Constructor & Destructor Documentation

BOARD_STACKUP() [1/2]

BOARD_STACKUP::BOARD_STACKUP

(

)

Definition at line 309 of file board_stackup.cpp.

{
 m_HasDielectricConstrains = false; // True if some dielectric layers have constrains
 // (Loss tg and Epison R)
 m_HasThicknessConstrains = false; // True if some dielectric or copper layers have constrains
 m_EdgeConnectorConstraints = BS_EDGE_CONNECTOR_NONE;
 m_CastellatedPads = false; // True if some castellated pads exist
 m_EdgePlating = false; // True if edge board is plated
 m_FinishType = wxT( "None" ); // undefined finish type
}

References BS_EDGE_CONNECTOR_NONE, m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, and m_HasThicknessConstrains.

BOARD_STACKUP() [2/2]

BOARD_STACKUP::BOARD_STACKUP

(

const BOARD_STACKUP &

aOther

)

Definition at line 321 of file board_stackup.cpp.

{
 m_HasDielectricConstrains = aOther.m_HasDielectricConstrains;
 m_HasThicknessConstrains = aOther.m_HasThicknessConstrains;
 m_EdgeConnectorConstraints = aOther.m_EdgeConnectorConstraints;
 m_CastellatedPads = aOther.m_CastellatedPads;
 m_EdgePlating = aOther.m_EdgePlating;
 m_FinishType = aOther.m_FinishType;
 
 // All items in aOther.m_list have to be duplicated, because aOther.m_list
 // manage pointers to these items
 for( BOARD_STACKUP_ITEM* item : aOther.m_list )
 {
 BOARD_STACKUP_ITEM* dup_item = new BOARD_STACKUP_ITEM( *item );
 Add( dup_item );
 }
}

References Add(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_HasThicknessConstrains, and m_list.

~BOARD_STACKUP()

BOARD_STACKUP::~BOARD_STACKUP ( )

inline

Definition at line 217 of file board_stackup.h.

{ RemoveAll(); }

References RemoveAll().

Member Function Documentation

Add()

void BOARD_STACKUP::Add ( BOARD_STACKUP_ITEM *  aItem )

inline

Add a new item in stackup layer.

Definition at line 245 of file board_stackup.h.

{ m_list.push_back( aItem ); }

References m_list.

Referenced by BOARD_STACKUP(), BuildDefaultStackupList(), operator=(), PCB_PARSER::parseBoardStackup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

BuildBoardThicknessFromStackup()

int BOARD_STACKUP::BuildBoardThicknessFromStackup

(

)

const

Returns

the board thickness ( in UI) from the thickness of BOARD_STACKUP_ITEM list

Definition at line 381 of file board_stackup.cpp.

{
 // return the board thickness from the thickness of BOARD_STACKUP_ITEM list
 int thickness = 0;
 
 for( BOARD_STACKUP_ITEM* item : m_list )
 {
 if( item->IsThicknessEditable() && item->IsEnabled() )
 {
 thickness += item->GetThickness();
 
 // dielectric layers can have more than one main layer
 // add thickness of all sublayers
 for( int idx = 1; idx < item->GetSublayersCount(); idx++ )
 {
 thickness += item->GetThickness( idx );
 }
 }
 }
 
 return thickness;
}

References m_list.

Referenced by CADSTAR_PCB_ARCHIVE_LOADER::loadBoardStackup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

BuildDefaultStackupList()

void BOARD_STACKUP::BuildDefaultStackupList	(	const BOARD_DESIGN_SETTINGS *	aSettings,
		int	aActiveCopperLayersCount = 0
	)

Create a default stackup, according to the current BOARD_DESIGN_SETTINGS settings.

Parameters

aSettings	is the current board setting. if nullptr, build a full stackup (with 32 copper layers)
aActiveCopperLayersCount	is used only if aSettings == nullptr is the number of copper layers to use to calculate a default dielectric thickness. ((<= 0 to use all copper layers)

Definition at line 499 of file board_stackup.cpp.

{
 // Creates a default stackup, according to the current BOARD_DESIGN_SETTINGS settings.
 // Note: the m_TypeName string is made translatable using _HKI marker, but is not
 // translated when building the stackup.
 // It will be used as this in files, and can be translated only in dialog
 // if aSettings == NULL, build a full stackup (with 32 copper layers)
 LSET enabledLayer = aSettings ? aSettings->GetEnabledLayers() : StackupAllowedBrdLayers();
 int copperLayerCount = aSettings ? aSettings->GetCopperLayerCount() : B_Cu+1;
 
 // We need to calculate a suitable dielectric layer thickness.
 // If no settings, and if aActiveCopperLayersCount is given, use it
 // (If no settings, and no aActiveCopperLayersCount, the full 32 layers are used)
 int activeCuLayerCount = copperLayerCount;
 
 if( aSettings == nullptr && aActiveCopperLayersCount > 0 )
 activeCuLayerCount = aActiveCopperLayersCount;
 
 int brd__thickness = aSettings ? aSettings->GetBoardThickness() : pcbIUScale.mmToIU( 1.6 );
 int diel_thickness = brd__thickness -
 ( BOARD_STACKUP_ITEM::GetCopperDefaultThickness() * activeCuLayerCount );
 
 // Take in account the solder mask thickness:
 int sm_count = ( enabledLayer & LSET( 2, F_Mask, B_Mask) ).count();
 diel_thickness -= BOARD_STACKUP_ITEM::GetMaskDefaultThickness() * sm_count;
 diel_thickness /= std::max( 1, activeCuLayerCount - 1 );
 
 int dielectric_idx = 0;
 
 // Add silk screen, solder mask and solder paste layers on top
 if( enabledLayer[F_SilkS] )
 {
 BOARD_STACKUP_ITEM* item = new BOARD_STACKUP_ITEM( BS_ITEM_TYPE_SILKSCREEN );
 item->SetBrdLayerId( F_SilkS );
 item->SetTypeName( _HKI( "Top Silk Screen" ) );
 Add( item );
 }
 
 if( enabledLayer[F_Paste] )
 {
 BOARD_STACKUP_ITEM* item = new BOARD_STACKUP_ITEM( BS_ITEM_TYPE_SOLDERPASTE );
 item->SetBrdLayerId( F_Paste );
 item->SetTypeName( _HKI( "Top Solder Paste" ) );
 Add( item );
 }
 
 if( enabledLayer[F_Mask] )
 {
 BOARD_STACKUP_ITEM* item = new BOARD_STACKUP_ITEM( BS_ITEM_TYPE_SOLDERMASK );
 item->SetBrdLayerId( F_Mask );
 item->SetTypeName( _HKI( "Top Solder Mask" ) );
 Add( item );
 }
 
 // Add copper and dielectric layers
 for( int ii = 0; ii < copperLayerCount; ii++ )
 {
 BOARD_STACKUP_ITEM* item = new BOARD_STACKUP_ITEM( BS_ITEM_TYPE_COPPER );
 item->SetBrdLayerId( ( PCB_LAYER_ID )ii );
 item->SetTypeName( KEY_COPPER );
 Add( item );
 
 if( ii == copperLayerCount-1 )
 {
 item->SetBrdLayerId( B_Cu );
 break;
 }
 
 // Add the dielectric layer:
 item = new BOARD_STACKUP_ITEM( BS_ITEM_TYPE_DIELECTRIC );
 item->SetThickness( diel_thickness );
 item->SetDielectricLayerId( dielectric_idx + 1 );
 
 // Display a dielectric default layer name:
 if( (dielectric_idx & 1) == 0 )
 {
 item->SetTypeName( KEY_CORE );
 item->SetMaterial( wxT( "FR4" ) );
 }
 else
 {
 item->SetTypeName( KEY_PREPREG );
 item->SetMaterial( wxT( "FR4" ) );
 }
 
 Add( item );
 dielectric_idx++;
 }
 
 // Add silk screen, solder mask and solder paste layers on bottom
 if( enabledLayer[B_Mask] )
 {
 BOARD_STACKUP_ITEM* item = new BOARD_STACKUP_ITEM( BS_ITEM_TYPE_SOLDERMASK );
 item->SetBrdLayerId( B_Mask );
 item->SetTypeName( _HKI( "Bottom Solder Mask" ) );
 Add( item );
 }
 
 if( enabledLayer[B_Paste] )
 {
 BOARD_STACKUP_ITEM* item = new BOARD_STACKUP_ITEM( BS_ITEM_TYPE_SOLDERPASTE );
 item->SetBrdLayerId( B_Paste );
 item->SetTypeName( _HKI( "Bottom Solder Paste" ) );
 Add( item );
 }
 
 if( enabledLayer[B_SilkS] )
 {
 BOARD_STACKUP_ITEM* item = new BOARD_STACKUP_ITEM( BS_ITEM_TYPE_SILKSCREEN );
 item->SetBrdLayerId( B_SilkS );
 item->SetTypeName( _HKI( "Bottom Silk Screen" ) );
 Add( item );
 }
 
 // Transfer other stackup settings from aSettings
 if( aSettings )
 {
 const BOARD_STACKUP& source_stackup = aSettings->GetStackupDescriptor();
 m_EdgeConnectorConstraints = source_stackup.m_EdgeConnectorConstraints;
 m_CastellatedPads = source_stackup.m_CastellatedPads;
 m_EdgePlating = source_stackup.m_EdgePlating;
 m_FinishType = source_stackup.m_FinishType;
 }
}

References _HKI, Add(), B_Cu, B_Mask, B_Paste, B_SilkS, BS_ITEM_TYPE_COPPER, BS_ITEM_TYPE_DIELECTRIC, BS_ITEM_TYPE_SILKSCREEN, BS_ITEM_TYPE_SOLDERMASK, BS_ITEM_TYPE_SOLDERPASTE, F_Mask, F_Paste, F_SilkS, BOARD_DESIGN_SETTINGS::GetBoardThickness(), BOARD_STACKUP_ITEM::GetCopperDefaultThickness(), BOARD_DESIGN_SETTINGS::GetCopperLayerCount(), BOARD_DESIGN_SETTINGS::GetEnabledLayers(), BOARD_STACKUP_ITEM::GetMaskDefaultThickness(), BOARD_DESIGN_SETTINGS::GetStackupDescriptor(), KEY_COPPER, KEY_CORE, KEY_PREPREG, m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, EDA_IU_SCALE::mmToIU(), pcbIUScale, BOARD_STACKUP_ITEM::SetBrdLayerId(), BOARD_STACKUP_ITEM::SetDielectricLayerId(), BOARD_STACKUP_ITEM::SetMaterial(), BOARD_STACKUP_ITEM::SetThickness(), BOARD_STACKUP_ITEM::SetTypeName(), and StackupAllowedBrdLayers().

Referenced by PANEL_SETUP_BOARD_STACKUP::buildLayerStackPanel(), CADSTAR_PCB_ARCHIVE_LOADER::loadBoardStackup(), PANEL_PREVIEW_3D_MODEL::PANEL_PREVIEW_3D_MODEL(), ALTIUM_PCB::ParseBoard6Data(), SynchronizeWithBoard(), and PANEL_PREVIEW_3D_MODEL::updateBoardThickness().

FormatBoardStackup()

void BOARD_STACKUP::FormatBoardStackup	(	OUTPUTFORMATTER *	aFormatter,
		const BOARD *	aBoard,
		int	aNestLevel
	)		const

Write the stackup info on board file.

Parameters

aFormatter	is the OUTPUTFORMATTER used to create the file
aBoard	is the board
aNestLevel	is the index to nest level to indent the lines in file

Definition at line 626 of file board_stackup.cpp.

{
 // Board stackup is the ordered list from top to bottom of
 // physical layers and substrate used to build the board.
 if( m_list.empty() )
 return;
 
 aFormatter->Print( aNestLevel, "(stackup\n" );
 int nest_level = aNestLevel+1;
 
 // Note:
 // Unspecified parameters are not stored in file.
 for( BOARD_STACKUP_ITEM* item: m_list )
 {
 wxString layer_name;
 
 if( item->GetBrdLayerId() == UNDEFINED_LAYER )
 layer_name.Printf( wxT( "dielectric %d" ), item->GetDielectricLayerId() );
 else
 layer_name = LSET::Name( item->GetBrdLayerId() );
 
 aFormatter->Print( nest_level, "(layer %s (type %s)",
 aFormatter->Quotew( layer_name ).c_str(),
 aFormatter->Quotew( item->GetTypeName() ).c_str() );
 
 // Output other parameters ( in sub layer list there is at least one item)
 for( int idx = 0; idx < item->GetSublayersCount(); idx++ )
 {
 if( idx ) // not for the main (first) layer.
 {
 aFormatter->Print( 0, "\n" );
 aFormatter->Print( nest_level+1, "addsublayer" );
 }
 
 if( item->IsColorEditable() && IsPrmSpecified( item->GetColor( idx ) ) )
 {
 aFormatter->Print( 0, " (color %s)",
 aFormatter->Quotew( item->GetColor( idx ) ).c_str() );
 }
 
 if( item->IsThicknessEditable() )
 {
 if( item->GetType() == BS_ITEM_TYPE_DIELECTRIC && item->IsThicknessLocked( idx ) )
 aFormatter->Print( 0, " (thickness %s locked)",
 EDA_UNIT_UTILS::FormatInternalUnits( pcbIUScale, item->GetThickness( idx ) ).c_str() );
 else
 aFormatter->Print( 0, " (thickness %s)",
 EDA_UNIT_UTILS::FormatInternalUnits( pcbIUScale, item->GetThickness( idx ) ).c_str() );
 }
 
 if( item->HasMaterialValue( idx ) )
 aFormatter->Print( 0, " (material %s)",
 aFormatter->Quotew( item->GetMaterial( idx ) ).c_str() );
 
 if( item->HasEpsilonRValue() && item->HasMaterialValue( idx ) )
 aFormatter->Print( 0, " (epsilon_r %g)", item->GetEpsilonR( idx ) );
 
 if( item->HasLossTangentValue() && item->HasMaterialValue( idx ) )
 aFormatter->Print( 0, " (loss_tangent %s)",
 FormatDouble2Str( item->GetLossTangent( idx ) ).c_str() );
 }
 
 aFormatter->Print( 0, ")\n" );
 }
 
 // Other infos about board, related to layers and other fabrication specifications
 if( IsPrmSpecified( m_FinishType ) )
 {
 aFormatter->Print( nest_level, "(copper_finish %s)\n",
 aFormatter->Quotew( m_FinishType ).c_str() );
 }
 
 aFormatter->Print( nest_level, "(dielectric_constraints %s)\n",
 m_HasDielectricConstrains ? "yes" : "no" );
 
 if( m_EdgeConnectorConstraints > 0 )
 {
 aFormatter->Print( nest_level, "(edge_connector %s)\n",
 m_EdgeConnectorConstraints > 1 ? "bevelled": "yes" );
 }
 
 if( m_CastellatedPads )
 aFormatter->Print( nest_level, "(castellated_pads yes)\n" );
 
 if( m_EdgePlating )
 aFormatter->Print( nest_level, "(edge_plating yes)\n" );
 
 aFormatter->Print( aNestLevel, ")\n" );
}

References BS_ITEM_TYPE_DIELECTRIC, FormatDouble2Str(), EDA_UNIT_UTILS::FormatInternalUnits(), IsPrmSpecified(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_list, LSET::Name(), pcbIUScale, OUTPUTFORMATTER::Print(), OUTPUTFORMATTER::Quotew(), and UNDEFINED_LAYER.

Referenced by PCB_PLUGIN::formatSetup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

GetCount()

int BOARD_STACKUP::GetCount ( ) const

inline

Returns

the number of layers in the stackup

Definition at line 239 of file board_stackup.h.

{ return (int) m_list.size(); }

References m_list.

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup(), EXPORTER_STEP::determinePcbThickness(), DRAWING_TOOL::DrawSpecificationStackup(), GetStackupLayer(), and BOARD_ADAPTER::InitSettings().

GetLayerDistance()

int BOARD_STACKUP::GetLayerDistance	(	PCB_LAYER_ID	aFirstLayer,
		PCB_LAYER_ID	aSecondLayer
	)		const

Calculate the distance (height) between the two given copper layers.

This factors in the thickness of any dielectric and copper layers between the two given layers, and half the height of the given start and end layers. This half-height calculation allows this to be used for consistent length measurements when calculating net length through a series of vias. A more advanced algorithm would be possible once we have a good concept of the start and end for a length measurement, but for now this will do. See https://gitlab.com/kicad/code/kicad/-/issues/8384 for more background.

Parameters

aFirstLayer	is a copper layer
aSecondLayer	is a different copper layer

Returns

the height (in IU) between the two layers

Definition at line 718 of file board_stackup.cpp.

{
 wxASSERT( IsCopperLayer( aFirstLayer ) && IsCopperLayer( aSecondLayer ) );
 
 if( aFirstLayer == aSecondLayer )
 return 0;
 
 if( aSecondLayer < aFirstLayer )
 std::swap( aFirstLayer, aSecondLayer );
 
 int total = 0;
 bool start = false;
 bool half = false;
 
 for( BOARD_STACKUP_ITEM* item : m_list )
 {
 // Will be UNDEFINED_LAYER for dielectrics
 PCB_LAYER_ID layer = item->GetBrdLayerId();
 
 if( layer != UNDEFINED_LAYER && !IsCopperLayer( layer ) )
 continue; // Silk/mask layer
 
 // Reached the start copper layer? Start counting the next dielectric after it
 if( !start && ( layer != UNDEFINED_LAYER && layer >= aFirstLayer ) )
 {
 start = true;
 half = true;
 }
 else if( !start )
 continue;
 
 // Reached the stop copper layer? we're done
 if( start && ( layer != UNDEFINED_LAYER && layer >= aSecondLayer ) )
 half = true;
 
 for( int sublayer = 0; sublayer < item->GetSublayersCount(); sublayer++ )
 {
 int subThickness = item->GetThickness( sublayer );
 total += half ? ( subThickness / 2 ) : subThickness;
 }
 
 half = false;
 
 if( layer != UNDEFINED_LAYER && layer >= aSecondLayer )
 break;
 }
 
 return total;
}

References IsCopperLayer(), m_list, and UNDEFINED_LAYER.

Referenced by DIALOG_NET_INSPECTOR::calculateViaLength(), BOARD::GetTrackLength(), DRC_TEST_PROVIDER_MATCHED_LENGTH::runInternal(), and PNS_KICAD_IFACE_BASE::StackupHeight().

GetList()

const std::vector< BOARD_STACKUP_ITEM * > & BOARD_STACKUP::GetList ( ) const

inline

Definition at line 219 of file board_stackup.h.

{ return m_list; }

References m_list.

Referenced by PANEL_SETUP_BOARD_STACKUP::buildLayerStackPanel(), BuildStackupReport(), EXPORTER_STEP::determinePcbThickness(), DRAWING_TOOL::DrawSpecificationStackup(), EXPORTER_PCB_VRML::EXPORTER_PCB_VRML(), GetStackupLayer(), BOARD_ADAPTER::InitSettings(), CADSTAR_PCB_ARCHIVE_LOADER::loadBoardStackup(), PANEL_SETUP_BOARD_STACKUP::onMaterialChange(), PANEL_SETUP_BOARD_STACKUP::onRemoveDielectricLayer(), PANEL_SETUP_BOARD_STACKUP::onRemoveDielUI(), ALTIUM_PCB::ParseBoard6Data(), SynchronizeWithBoard(), PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow(), and HYPERLYNX_EXPORTER::writeStackupInfo().

GetStackupLayer()

BOARD_STACKUP_ITEM * BOARD_STACKUP::GetStackupLayer

(

int

aIndex

)

Returns

a reference to the layer aIndex, or nullptr if not exists

Definition at line 372 of file board_stackup.cpp.

{
 if( aIndex < 0 || aIndex >= GetCount() )
 return nullptr;
 
 return GetList()[aIndex];
}

References GetCount(), and GetList().

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup().

operator=()

BOARD_STACKUP & BOARD_STACKUP::operator=

(

const BOARD_STACKUP &

aOther

)

Definition at line 340 of file board_stackup.cpp.

{
 m_HasDielectricConstrains = aOther.m_HasDielectricConstrains;
 m_HasThicknessConstrains = aOther.m_HasThicknessConstrains;
 m_EdgeConnectorConstraints = aOther.m_EdgeConnectorConstraints;
 m_CastellatedPads = aOther.m_CastellatedPads;
 m_EdgePlating = aOther.m_EdgePlating;
 m_FinishType = aOther.m_FinishType;
 
 RemoveAll();
 
 // All items in aOther.m_list have to be duplicated, because aOther.m_list
 // manage pointers to these items
 for( BOARD_STACKUP_ITEM* item : aOther.m_list )
 {
 BOARD_STACKUP_ITEM* dup_item = new BOARD_STACKUP_ITEM( *item );
 Add( dup_item );
 }
 
 return *this;
}

References Add(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_HasThicknessConstrains, m_list, and RemoveAll().

RemoveAll()

void BOARD_STACKUP::RemoveAll

(

)

Delete all items in list and clear the list.

Definition at line 363 of file board_stackup.cpp.

{
 for( BOARD_STACKUP_ITEM* item : m_list )
 delete item;
 
 m_list.clear();
}

References m_list.

Referenced by CADSTAR_PCB_ARCHIVE_LOADER::loadBoardStackup(), operator=(), PANEL_PREVIEW_3D_MODEL::PANEL_PREVIEW_3D_MODEL(), ALTIUM_PCB::ParseBoard6Data(), PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow(), PANEL_PREVIEW_3D_MODEL::updateBoardThickness(), and ~BOARD_STACKUP().

StackupAllowedBrdLayers()

static LSET BOARD_STACKUP::StackupAllowedBrdLayers ( )

inlinestatic

Returns

the board layers full mask allowed in the stackup list i.e. the SilkS, Mask, Paste and all copper layers

Definition at line 228 of file board_stackup.h.

 {
 return LSET( 6, F_SilkS, F_Mask, F_Paste, B_SilkS, B_Mask, B_Paste )
 | LSET::ExternalCuMask() | LSET::InternalCuMask();
 }

References B_Mask, B_Paste, B_SilkS, LSET::ExternalCuMask(), F_Mask, F_Paste, F_SilkS, and LSET::InternalCuMask().

Referenced by BuildDefaultStackupList(), PANEL_SETUP_BOARD_STACKUP::ImportSettingsFrom(), PANEL_SETUP_BOARD_STACKUP::OnLayersOptionsChanged(), and PANEL_SETUP_BOARD_STACKUP::PANEL_SETUP_BOARD_STACKUP().

SynchronizeWithBoard()

bool BOARD_STACKUP::SynchronizeWithBoard

(

BOARD_DESIGN_SETTINGS *

aSettings

)

Synchronize the BOARD_STACKUP_ITEM* list with the board.

Not enabled layers are removed Missing layers are added

Parameters

aSettings,is

the current board setting.

Returns

true if changes are made

Definition at line 405 of file board_stackup.cpp.

{
 bool change = false;
 // Build the suitable stackup:
 BOARD_STACKUP stackup;
 stackup.BuildDefaultStackupList( aSettings );
 
 // First, find removed layers:
 for( BOARD_STACKUP_ITEM* curr_item: m_list )
 {
 bool found = false;
 
 for( BOARD_STACKUP_ITEM* item: stackup.GetList() )
 {
 if( curr_item->GetBrdLayerId() != UNDEFINED_LAYER )
 {
 if( item->GetBrdLayerId() == curr_item->GetBrdLayerId() )
 {
 found = true;
 break;
 }
 }
 else // curr_item = dielectric layer
 {
 if( item->GetBrdLayerId() != UNDEFINED_LAYER )
 continue;
 
 if( item->GetDielectricLayerId() == curr_item->GetDielectricLayerId() )
 {
 found = true;
 break;
 }
 }
 }
 
 if( !found ) // a layer was removed: a change is found
 {
 change = true;
 break;
 }
 }
 
 // Now initialize all stackup items to the initial values, when exist
 for( BOARD_STACKUP_ITEM* item : stackup.GetList() )
 {
 bool found = false;
 // Search for initial settings:
 for( const BOARD_STACKUP_ITEM* initial_item : m_list )
 {
 if( item->GetBrdLayerId() != UNDEFINED_LAYER )
 {
 if( item->GetBrdLayerId() == initial_item->GetBrdLayerId() )
 {
 *item = *initial_item;
 found = true;
 break;
 }
 }
 else // dielectric layer: see m_DielectricLayerId for identification
 {
 // Compare dielectric layer with dielectric layer
 if( initial_item->GetBrdLayerId() != UNDEFINED_LAYER )
 continue;
 
 if( item->GetDielectricLayerId() == initial_item->GetDielectricLayerId() )
 {
 *item = *initial_item;
 found = true;
 break;
 }
 }
 }
 
 if( !found )
 {
 change = true;
 }
 }
 
 // Transfer layer settings:
 *this = stackup;
 
 // Transfer other stackup settings from aSettings
 const BOARD_STACKUP& source_stackup = aSettings->GetStackupDescriptor();
 m_HasDielectricConstrains = source_stackup.m_HasDielectricConstrains;
 m_EdgeConnectorConstraints = source_stackup.m_EdgeConnectorConstraints;
 m_CastellatedPads = source_stackup.m_CastellatedPads;
 m_EdgePlating = source_stackup.m_EdgePlating;
 m_FinishType = source_stackup.m_FinishType;
 
 return change;
}

References BuildDefaultStackupList(), GetList(), BOARD_DESIGN_SETTINGS::GetStackupDescriptor(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_list, and UNDEFINED_LAYER.

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup(), and DRAWING_TOOL::DrawSpecificationStackup().

Member Data Documentation

m_CastellatedPads

bool BOARD_STACKUP::m_CastellatedPads

True if castellated pads exist.

Definition at line 320 of file board_stackup.h.

Referenced by GERBER_JOBFILE_WRITER::addJSONGeneralSpecs(), BOARD_STACKUP(), BuildDefaultStackupList(), BuildStackupReport(), DRAWING_TOOL::DrawBoardCharacteristics(), FormatBoardStackup(), operator=(), PCB_PARSER::parseBoardStackup(), PANEL_SETUP_BOARD_FINISH::synchronizeWithBoard(), SynchronizeWithBoard(), PANEL_SETUP_BOARD_FINISH::TransferDataFromWindow(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

m_EdgeConnectorConstraints

BS_EDGE_CONNECTOR_CONSTRAINTS BOARD_STACKUP::m_EdgeConnectorConstraints

If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTOR_NONE = no edge connector BS_EDGE_CONNECTOR_IN_USE = board has edge connectors BS_EDGE_CONNECTOR_BEVELLED = edge connectors are beveled.

Definition at line 318 of file board_stackup.h.

Referenced by GERBER_JOBFILE_WRITER::addJSONGeneralSpecs(), BOARD_STACKUP(), BuildDefaultStackupList(), BuildStackupReport(), DRAWING_TOOL::DrawBoardCharacteristics(), FormatBoardStackup(), operator=(), PCB_PARSER::parseBoardStackup(), PANEL_SETUP_BOARD_FINISH::synchronizeWithBoard(), SynchronizeWithBoard(), PANEL_SETUP_BOARD_FINISH::TransferDataFromWindow(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

m_EdgePlating

bool BOARD_STACKUP::m_EdgePlating

True if the edge board is plated.

Definition at line 321 of file board_stackup.h.

Referenced by GERBER_JOBFILE_WRITER::addJSONGeneralSpecs(), BOARD_STACKUP(), BuildDefaultStackupList(), BuildStackupReport(), DRAWING_TOOL::DrawBoardCharacteristics(), FormatBoardStackup(), operator=(), PCB_PARSER::parseBoardStackup(), PANEL_SETUP_BOARD_FINISH::synchronizeWithBoard(), SynchronizeWithBoard(), PANEL_SETUP_BOARD_FINISH::TransferDataFromWindow(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

m_FinishType

wxString BOARD_STACKUP::m_FinishType

The name of external copper finish.

Definition at line 295 of file board_stackup.h.

Referenced by GERBER_JOBFILE_WRITER::addJSONGeneralSpecs(), BOARD_STACKUP(), BuildDefaultStackupList(), BuildStackupReport(), DRAWING_TOOL::DrawBoardCharacteristics(), EXPORTER_PCB_VRML::EXPORTER_PCB_VRML(), FormatBoardStackup(), BOARD_ADAPTER::InitSettings(), operator=(), PCB_PARSER::parseBoardStackup(), PANEL_SETUP_BOARD_FINISH::synchronizeWithBoard(), SynchronizeWithBoard(), PANEL_SETUP_BOARD_FINISH::TransferDataFromWindow(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

m_HasDielectricConstrains

bool BOARD_STACKUP::m_HasDielectricConstrains

True if some layers have impedance controlled tracks or have specific constrains for micro-wave applications If the board has dielectric constrains, the .gbrjob will contain info about dielectric constrains: loss tangent and Epsilon rel.

If not, these values will be not specified in job file.

Definition at line 304 of file board_stackup.h.

Referenced by GERBER_JOBFILE_WRITER::addJSONGeneralSpecs(), GERBER_JOBFILE_WRITER::addJSONMaterialStackup(), BOARD_STACKUP(), BuildStackupReport(), DRAWING_TOOL::DrawBoardCharacteristics(), FormatBoardStackup(), operator=(), PCB_PARSER::parseBoardStackup(), SynchronizeWithBoard(), PANEL_SETUP_BOARD_STACKUP::synchronizeWithBoard(), PANEL_SETUP_BOARD_STACKUP::transferDataFromUIToStackup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

m_HasThicknessConstrains

bool BOARD_STACKUP::m_HasThicknessConstrains

True if some layers (copper and/or dielectric) have specific thickness.

Definition at line 309 of file board_stackup.h.

Referenced by BOARD_STACKUP(), and operator=().

m_list

std::vector<BOARD_STACKUP_ITEM*> BOARD_STACKUP::m_list

private

Definition at line 326 of file board_stackup.h.

Referenced by Add(), BOARD_STACKUP(), BuildBoardThicknessFromStackup(), FormatBoardStackup(), GetCount(), GetLayerDistance(), GetList(), operator=(), RemoveAll(), and SynchronizeWithBoard().

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The documentation for this class was generated from the following files:

• board_stackup.h
• board_stackup.cpp