KiCad PCB EDA Suite
BOARD_STACKUP Class Reference

Manage layers needed to make a physical board. More...

#include <board_stackup.h>

Public Member Functions

 BOARD_STACKUP ()
 
 BOARD_STACKUP (const BOARD_STACKUP &aOther)
 
BOARD_STACKUPoperator= (const BOARD_STACKUP &aOther)
 
 ~BOARD_STACKUP ()
 
const std::vector< BOARD_STACKUP_ITEM * > & GetList () const
 
BOARD_STACKUP_ITEMGetStackupLayer (int aIndex)
 
void RemoveAll ()
 Delete all items in list and clear the list. More...
 
int GetCount () const
 
int BuildBoardThicknessFromStackup () const
 
void Add (BOARD_STACKUP_ITEM *aItem)
 Add a new item in stackup layer. More...
 
bool SynchronizeWithBoard (BOARD_DESIGN_SETTINGS *aSettings)
 Synchronize the BOARD_STACKUP_ITEM* list with the board. More...
 
void BuildDefaultStackupList (const BOARD_DESIGN_SETTINGS *aSettings, int aActiveCopperLayersCount=0)
 Create a default stackup, according to the current BOARD_DESIGN_SETTINGS settings. More...
 
void FormatBoardStackup (OUTPUTFORMATTER *aFormatter, const BOARD *aBoard, int aNestLevel) const
 Write the stackup info on board file. More...
 
int GetLayerDistance (PCB_LAYER_ID aFirstLayer, PCB_LAYER_ID aSecondLayer) const
 Calculate the distance (height) between the two given copper layers. More...
 

Static Public Member Functions

static LSET StackupAllowedBrdLayers ()
 

Public Attributes

wxString m_FinishType
 The name of external copper finish. More...
 
bool m_HasDielectricConstrains
 True if some layers have impedance controlled tracks or have specific constrains for micro-wave applications If the board has dielectric constrains, the .gbrjob will contain info about dielectric constrains: loss tangent and Epsilon rel. More...
 
bool m_HasThicknessConstrains
 True if some layers (copper and/or dielectric) have specific thickness. More...
 
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
 If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTOR_NONE = no edge connector BS_EDGE_CONNECTOR_IN_USE = board has edge connectors BS_EDGE_CONNECTOR_BEVELLED = edge connectors are beveled. More...
 
bool m_CastellatedPads
 True if castellated pads exist. More...
 
bool m_EdgePlating
 True if the edge board is plated. More...
 

Private Attributes

std::vector< BOARD_STACKUP_ITEM * > m_list
 

Detailed Description

Manage layers needed to make a physical board.

They are solder mask, silk screen, copper and dielectric. Some other layers, used in fabrication, are not managed here because they are not used to make a physical board itself.

Note
There are a few other parameters related to the physical stackup like finish type, impedance control and a few others.

Definition at line 210 of file board_stackup.h.

Constructor & Destructor Documentation

◆ BOARD_STACKUP() [1/2]

BOARD_STACKUP::BOARD_STACKUP ( )

Definition at line 309 of file board_stackup.cpp.

310{
311 m_HasDielectricConstrains = false; // True if some dielectric layers have constrains
312 // (Loss tg and Epison R)
313 m_HasThicknessConstrains = false; // True if some dielectric or copper layers have constrains
315 m_CastellatedPads = false; // True if some castellated pads exist
316 m_EdgePlating = false; // True if edge board is plated
317 m_FinishType = wxT( "None" ); // undefined finish type
318}
@ BS_EDGE_CONNECTOR_NONE
Definition: board_stackup.h:55
bool m_CastellatedPads
True if castellated pads exist.
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTO...
bool m_HasThicknessConstrains
True if some layers (copper and/or dielectric) have specific thickness.
wxString m_FinishType
The name of external copper finish.

References BS_EDGE_CONNECTOR_NONE, m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, and m_HasThicknessConstrains.

◆ BOARD_STACKUP() [2/2]

BOARD_STACKUP::BOARD_STACKUP ( const BOARD_STACKUP aOther)

Definition at line 321 of file board_stackup.cpp.

322{
328 m_FinishType = aOther.m_FinishType;
329
330 // All items in aOther.m_list have to be duplicated, because aOther.m_list
331 // manage pointers to these items
332 for( BOARD_STACKUP_ITEM* item : aOther.m_list )
333 {
334 BOARD_STACKUP_ITEM* dup_item = new BOARD_STACKUP_ITEM( *item );
335 Add( dup_item );
336 }
337}
Manage one layer needed to make a physical board.
Definition: board_stackup.h:91
void Add(BOARD_STACKUP_ITEM *aItem)
Add a new item in stackup layer.
std::vector< BOARD_STACKUP_ITEM * > m_list

References Add(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_HasThicknessConstrains, and m_list.

◆ ~BOARD_STACKUP()

BOARD_STACKUP::~BOARD_STACKUP ( )
inline

Definition at line 217 of file board_stackup.h.

217{ RemoveAll(); }
void RemoveAll()
Delete all items in list and clear the list.

References RemoveAll().

Member Function Documentation

◆ Add()

void BOARD_STACKUP::Add ( BOARD_STACKUP_ITEM aItem)
inline

Add a new item in stackup layer.

Definition at line 245 of file board_stackup.h.

245{ m_list.push_back( aItem ); }

References m_list.

Referenced by BOARD_STACKUP(), BuildDefaultStackupList(), operator=(), PCB_PARSER::parseBoardStackup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ BuildBoardThicknessFromStackup()

int BOARD_STACKUP::BuildBoardThicknessFromStackup ( ) const
Returns
the board thickness ( in UI) from the thickness of BOARD_STACKUP_ITEM list

Definition at line 381 of file board_stackup.cpp.

382{
383 // return the board thickness from the thickness of BOARD_STACKUP_ITEM list
384 int thickness = 0;
385
386 for( BOARD_STACKUP_ITEM* item : m_list )
387 {
388 if( item->IsThicknessEditable() && item->IsEnabled() )
389 {
390 thickness += item->GetThickness();
391
392 // dielectric layers can have more than one main layer
393 // add thickness of all sublayers
394 for( int idx = 1; idx < item->GetSublayersCount(); idx++ )
395 {
396 thickness += item->GetThickness( idx );
397 }
398 }
399 }
400
401 return thickness;
402}

References m_list.

Referenced by CADSTAR_PCB_ARCHIVE_LOADER::loadBoardStackup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ BuildDefaultStackupList()

void BOARD_STACKUP::BuildDefaultStackupList ( const BOARD_DESIGN_SETTINGS aSettings,
int  aActiveCopperLayersCount = 0 
)

Create a default stackup, according to the current BOARD_DESIGN_SETTINGS settings.

Parameters
aSettingsis the current board setting. if nullptr, build a full stackup (with 32 copper layers)
aActiveCopperLayersCountis used only if aSettings == nullptr is the number of copper layers to use to calculate a default dielectric thickness. ((<= 0 to use all copper layers)

Definition at line 499 of file board_stackup.cpp.

501{
502 // Creates a default stackup, according to the current BOARD_DESIGN_SETTINGS settings.
503 // Note: the m_TypeName string is made translatable using _HKI marker, but is not
504 // translated when building the stackup.
505 // It will be used as this in files, and can be translated only in dialog
506 // if aSettings == NULL, build a full stackup (with 32 copper layers)
507 LSET enabledLayer = aSettings ? aSettings->GetEnabledLayers() : StackupAllowedBrdLayers();
508 int copperLayerCount = aSettings ? aSettings->GetCopperLayerCount() : B_Cu+1;
509
510 // We need to calculate a suitable dielectric layer thickness.
511 // If no settings, and if aActiveCopperLayersCount is given, use it
512 // (If no settings, and no aActiveCopperLayersCount, the full 32 layers are used)
513 int activeCuLayerCount = copperLayerCount;
514
515 if( aSettings == nullptr && aActiveCopperLayersCount > 0 )
516 activeCuLayerCount = aActiveCopperLayersCount;
517
518 int brd__thickness = aSettings ? aSettings->GetBoardThickness() : pcbIUScale.mmToIU( 1.6 );
519 int diel_thickness = brd__thickness -
520 ( BOARD_STACKUP_ITEM::GetCopperDefaultThickness() * activeCuLayerCount );
521
522 // Take in account the solder mask thickness:
523 int sm_count = ( enabledLayer & LSET( 2, F_Mask, B_Mask) ).count();
524 diel_thickness -= BOARD_STACKUP_ITEM::GetMaskDefaultThickness() * sm_count;
525 diel_thickness /= std::max( 1, activeCuLayerCount - 1 );
526
527 int dielectric_idx = 0;
528
529 // Add silk screen, solder mask and solder paste layers on top
530 if( enabledLayer[F_SilkS] )
531 {
533 item->SetBrdLayerId( F_SilkS );
534 item->SetTypeName( _HKI( "Top Silk Screen" ) );
535 Add( item );
536 }
537
538 if( enabledLayer[F_Paste] )
539 {
541 item->SetBrdLayerId( F_Paste );
542 item->SetTypeName( _HKI( "Top Solder Paste" ) );
543 Add( item );
544 }
545
546 if( enabledLayer[F_Mask] )
547 {
549 item->SetBrdLayerId( F_Mask );
550 item->SetTypeName( _HKI( "Top Solder Mask" ) );
551 Add( item );
552 }
553
554 // Add copper and dielectric layers
555 for( int ii = 0; ii < copperLayerCount; ii++ )
556 {
558 item->SetBrdLayerId( ( PCB_LAYER_ID )ii );
559 item->SetTypeName( KEY_COPPER );
560 Add( item );
561
562 if( ii == copperLayerCount-1 )
563 {
564 item->SetBrdLayerId( B_Cu );
565 break;
566 }
567
568 // Add the dielectric layer:
570 item->SetThickness( diel_thickness );
571 item->SetDielectricLayerId( dielectric_idx + 1 );
572
573 // Display a dielectric default layer name:
574 if( (dielectric_idx & 1) == 0 )
575 {
576 item->SetTypeName( KEY_CORE );
577 item->SetMaterial( wxT( "FR4" ) );
578 }
579 else
580 {
581 item->SetTypeName( KEY_PREPREG );
582 item->SetMaterial( wxT( "FR4" ) );
583 }
584
585 Add( item );
586 dielectric_idx++;
587 }
588
589 // Add silk screen, solder mask and solder paste layers on bottom
590 if( enabledLayer[B_Mask] )
591 {
593 item->SetBrdLayerId( B_Mask );
594 item->SetTypeName( _HKI( "Bottom Solder Mask" ) );
595 Add( item );
596 }
597
598 if( enabledLayer[B_Paste] )
599 {
601 item->SetBrdLayerId( B_Paste );
602 item->SetTypeName( _HKI( "Bottom Solder Paste" ) );
603 Add( item );
604 }
605
606 if( enabledLayer[B_SilkS] )
607 {
609 item->SetBrdLayerId( B_SilkS );
610 item->SetTypeName( _HKI( "Bottom Silk Screen" ) );
611 Add( item );
612 }
613
614 // Transfer other stackup settings from aSettings
615 if( aSettings )
616 {
617 const BOARD_STACKUP& source_stackup = aSettings->GetStackupDescriptor();
619 m_CastellatedPads = source_stackup.m_CastellatedPads;
620 m_EdgePlating = source_stackup.m_EdgePlating;
621 m_FinishType = source_stackup.m_FinishType;
622 }
623}
constexpr EDA_IU_SCALE pcbIUScale
Definition: base_units.h:109
@ BS_ITEM_TYPE_COPPER
Definition: board_stackup.h:43
@ BS_ITEM_TYPE_SILKSCREEN
Definition: board_stackup.h:49
@ BS_ITEM_TYPE_DIELECTRIC
Definition: board_stackup.h:44
@ BS_ITEM_TYPE_SOLDERPASTE
Definition: board_stackup.h:46
@ BS_ITEM_TYPE_SOLDERMASK
Definition: board_stackup.h:47
LSET GetEnabledLayers() const
Return a bit-mask of all the layers that are enabled.
int GetBoardThickness() const
The full thickness of the board including copper and masks.
BOARD_STACKUP & GetStackupDescriptor()
void SetDielectricLayerId(int aLayerId)
void SetThickness(int aThickness, int aDielectricSubLayer=0)
void SetMaterial(const wxString &aName, int aDielectricSubLayer=0)
static int GetMaskDefaultThickness()
void SetBrdLayerId(PCB_LAYER_ID aBrdLayerId)
void SetTypeName(const wxString &aName)
static int GetCopperDefaultThickness()
Manage layers needed to make a physical board.
static LSET StackupAllowedBrdLayers()
LSET is a set of PCB_LAYER_IDs.
Definition: layer_ids.h:530
#define _HKI(x)
PCB_LAYER_ID
A quick note on layer IDs:
Definition: layer_ids.h:59
@ F_Paste
Definition: layer_ids.h:101
@ B_Mask
Definition: layer_ids.h:106
@ B_Cu
Definition: layer_ids.h:95
@ F_Mask
Definition: layer_ids.h:107
@ B_Paste
Definition: layer_ids.h:100
@ F_SilkS
Definition: layer_ids.h:104
@ B_SilkS
Definition: layer_ids.h:103
#define KEY_PREPREG
#define KEY_COPPER
#define KEY_CORE
constexpr int mmToIU(double mm) const
Definition: base_units.h:89

References _HKI, Add(), B_Cu, B_Mask, B_Paste, B_SilkS, BS_ITEM_TYPE_COPPER, BS_ITEM_TYPE_DIELECTRIC, BS_ITEM_TYPE_SILKSCREEN, BS_ITEM_TYPE_SOLDERMASK, BS_ITEM_TYPE_SOLDERPASTE, F_Mask, F_Paste, F_SilkS, BOARD_DESIGN_SETTINGS::GetBoardThickness(), BOARD_STACKUP_ITEM::GetCopperDefaultThickness(), BOARD_DESIGN_SETTINGS::GetCopperLayerCount(), BOARD_DESIGN_SETTINGS::GetEnabledLayers(), BOARD_STACKUP_ITEM::GetMaskDefaultThickness(), BOARD_DESIGN_SETTINGS::GetStackupDescriptor(), KEY_COPPER, KEY_CORE, KEY_PREPREG, m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, EDA_IU_SCALE::mmToIU(), pcbIUScale, BOARD_STACKUP_ITEM::SetBrdLayerId(), BOARD_STACKUP_ITEM::SetDielectricLayerId(), BOARD_STACKUP_ITEM::SetMaterial(), BOARD_STACKUP_ITEM::SetThickness(), BOARD_STACKUP_ITEM::SetTypeName(), and StackupAllowedBrdLayers().

Referenced by PANEL_SETUP_BOARD_STACKUP::buildLayerStackPanel(), CADSTAR_PCB_ARCHIVE_LOADER::loadBoardStackup(), PANEL_PREVIEW_3D_MODEL::PANEL_PREVIEW_3D_MODEL(), ALTIUM_PCB::ParseBoard6Data(), SynchronizeWithBoard(), and PANEL_PREVIEW_3D_MODEL::updateBoardThickness().

◆ FormatBoardStackup()

void BOARD_STACKUP::FormatBoardStackup ( OUTPUTFORMATTER aFormatter,
const BOARD aBoard,
int  aNestLevel 
) const

Write the stackup info on board file.

Parameters
aFormatteris the OUTPUTFORMATTER used to create the file
aBoardis the board
aNestLevelis the index to nest level to indent the lines in file

Definition at line 626 of file board_stackup.cpp.

628{
629 // Board stackup is the ordered list from top to bottom of
630 // physical layers and substrate used to build the board.
631 if( m_list.empty() )
632 return;
633
634 aFormatter->Print( aNestLevel, "(stackup\n" );
635 int nest_level = aNestLevel+1;
636
637 // Note:
638 // Unspecified parameters are not stored in file.
639 for( BOARD_STACKUP_ITEM* item: m_list )
640 {
641 wxString layer_name;
642
643 if( item->GetBrdLayerId() == UNDEFINED_LAYER )
644 layer_name.Printf( wxT( "dielectric %d" ), item->GetDielectricLayerId() );
645 else
646 layer_name = LSET::Name( item->GetBrdLayerId() );
647
648 aFormatter->Print( nest_level, "(layer %s (type %s)",
649 aFormatter->Quotew( layer_name ).c_str(),
650 aFormatter->Quotew( item->GetTypeName() ).c_str() );
651
652 // Output other parameters ( in sub layer list there is at least one item)
653 for( int idx = 0; idx < item->GetSublayersCount(); idx++ )
654 {
655 if( idx ) // not for the main (first) layer.
656 {
657 aFormatter->Print( 0, "\n" );
658 aFormatter->Print( nest_level+1, "addsublayer" );
659 }
660
661 if( item->IsColorEditable() && IsPrmSpecified( item->GetColor( idx ) ) )
662 {
663 aFormatter->Print( 0, " (color %s)",
664 aFormatter->Quotew( item->GetColor( idx ) ).c_str() );
665 }
666
667 if( item->IsThicknessEditable() )
668 {
669 if( item->GetType() == BS_ITEM_TYPE_DIELECTRIC && item->IsThicknessLocked( idx ) )
670 aFormatter->Print( 0, " (thickness %s locked)",
671 EDA_UNIT_UTILS::FormatInternalUnits( pcbIUScale, item->GetThickness( idx ) ).c_str() );
672 else
673 aFormatter->Print( 0, " (thickness %s)",
674 EDA_UNIT_UTILS::FormatInternalUnits( pcbIUScale, item->GetThickness( idx ) ).c_str() );
675 }
676
677 if( item->HasMaterialValue( idx ) )
678 aFormatter->Print( 0, " (material %s)",
679 aFormatter->Quotew( item->GetMaterial( idx ) ).c_str() );
680
681 if( item->HasEpsilonRValue() && item->HasMaterialValue( idx ) )
682 aFormatter->Print( 0, " (epsilon_r %g)", item->GetEpsilonR( idx ) );
683
684 if( item->HasLossTangentValue() && item->HasMaterialValue( idx ) )
685 aFormatter->Print( 0, " (loss_tangent %s)",
686 FormatDouble2Str( item->GetLossTangent( idx ) ).c_str() );
687 }
688
689 aFormatter->Print( 0, ")\n" );
690 }
691
692 // Other infos about board, related to layers and other fabrication specifications
694 {
695 aFormatter->Print( nest_level, "(copper_finish %s)\n",
696 aFormatter->Quotew( m_FinishType ).c_str() );
697 }
698
699 aFormatter->Print( nest_level, "(dielectric_constraints %s)\n",
700 m_HasDielectricConstrains ? "yes" : "no" );
701
703 {
704 aFormatter->Print( nest_level, "(edge_connector %s)\n",
705 m_EdgeConnectorConstraints > 1 ? "bevelled": "yes" );
706 }
707
709 aFormatter->Print( nest_level, "(castellated_pads yes)\n" );
710
711 if( m_EdgePlating )
712 aFormatter->Print( nest_level, "(edge_plating yes)\n" );
713
714 aFormatter->Print( aNestLevel, ")\n" );
715}
bool IsPrmSpecified(const wxString &aPrmValue)
static const wxChar * Name(PCB_LAYER_ID aLayerId)
Return the fixed name association with aLayerId.
Definition: lset.cpp:82
std::string Quotew(const wxString &aWrapee) const
Definition: richio.cpp:501
int PRINTF_FUNC Print(int nestLevel, const char *fmt,...)
Format and write text to the output stream.
Definition: richio.cpp:433
@ UNDEFINED_LAYER
Definition: layer_ids.h:60
std::string FormatInternalUnits(const EDA_IU_SCALE &aIuScale, int aValue)
Converts aValue from internal units to a string appropriate for writing to file.
Definition: eda_units.cpp:139
std::string FormatDouble2Str(double aValue)
Print a float number without using scientific notation and no trailing 0 This function is intended in...

References BS_ITEM_TYPE_DIELECTRIC, FormatDouble2Str(), EDA_UNIT_UTILS::FormatInternalUnits(), IsPrmSpecified(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_list, LSET::Name(), pcbIUScale, OUTPUTFORMATTER::Print(), OUTPUTFORMATTER::Quotew(), and UNDEFINED_LAYER.

Referenced by PCB_PLUGIN::formatSetup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ GetCount()

int BOARD_STACKUP::GetCount ( ) const
inline
Returns
the number of layers in the stackup

Definition at line 239 of file board_stackup.h.

239{ return (int) m_list.size(); }

References m_list.

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup(), EXPORTER_STEP::determinePcbThickness(), DRAWING_TOOL::DrawSpecificationStackup(), GetStackupLayer(), and BOARD_ADAPTER::InitSettings().

◆ GetLayerDistance()

int BOARD_STACKUP::GetLayerDistance ( PCB_LAYER_ID  aFirstLayer,
PCB_LAYER_ID  aSecondLayer 
) const

Calculate the distance (height) between the two given copper layers.

This factors in the thickness of any dielectric and copper layers between the two given layers, and half the height of the given start and end layers. This half-height calculation allows this to be used for consistent length measurements when calculating net length through a series of vias. A more advanced algorithm would be possible once we have a good concept of the start and end for a length measurement, but for now this will do. See https://gitlab.com/kicad/code/kicad/-/issues/8384 for more background.

Parameters
aFirstLayeris a copper layer
aSecondLayeris a different copper layer
Returns
the height (in IU) between the two layers

Definition at line 718 of file board_stackup.cpp.

719{
720 wxASSERT( IsCopperLayer( aFirstLayer ) && IsCopperLayer( aSecondLayer ) );
721
722 if( aFirstLayer == aSecondLayer )
723 return 0;
724
725 if( aSecondLayer < aFirstLayer )
726 std::swap( aFirstLayer, aSecondLayer );
727
728 int total = 0;
729 bool start = false;
730 bool half = false;
731
732 for( BOARD_STACKUP_ITEM* item : m_list )
733 {
734 // Will be UNDEFINED_LAYER for dielectrics
735 PCB_LAYER_ID layer = item->GetBrdLayerId();
736
737 if( layer != UNDEFINED_LAYER && !IsCopperLayer( layer ) )
738 continue; // Silk/mask layer
739
740 // Reached the start copper layer? Start counting the next dielectric after it
741 if( !start && ( layer != UNDEFINED_LAYER && layer >= aFirstLayer ) )
742 {
743 start = true;
744 half = true;
745 }
746 else if( !start )
747 continue;
748
749 // Reached the stop copper layer? we're done
750 if( start && ( layer != UNDEFINED_LAYER && layer >= aSecondLayer ) )
751 half = true;
752
753 for( int sublayer = 0; sublayer < item->GetSublayersCount(); sublayer++ )
754 {
755 int subThickness = item->GetThickness( sublayer );
756 total += half ? ( subThickness / 2 ) : subThickness;
757 }
758
759 half = false;
760
761 if( layer != UNDEFINED_LAYER && layer >= aSecondLayer )
762 break;
763 }
764
765 return total;
766}
bool IsCopperLayer(int aLayerId)
Tests whether a layer is a copper layer.
Definition: layer_ids.h:825

References IsCopperLayer(), m_list, and UNDEFINED_LAYER.

Referenced by DIALOG_NET_INSPECTOR::calculateViaLength(), BOARD::GetTrackLength(), DRC_TEST_PROVIDER_MATCHED_LENGTH::runInternal(), and PNS_KICAD_IFACE_BASE::StackupHeight().

◆ GetList()

◆ GetStackupLayer()

BOARD_STACKUP_ITEM * BOARD_STACKUP::GetStackupLayer ( int  aIndex)
Returns
a reference to the layer aIndex, or nullptr if not exists

Definition at line 372 of file board_stackup.cpp.

373{
374 if( aIndex < 0 || aIndex >= GetCount() )
375 return nullptr;
376
377 return GetList()[aIndex];
378}
const std::vector< BOARD_STACKUP_ITEM * > & GetList() const
int GetCount() const

References GetCount(), and GetList().

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup().

◆ operator=()

BOARD_STACKUP & BOARD_STACKUP::operator= ( const BOARD_STACKUP aOther)

Definition at line 340 of file board_stackup.cpp.

341{
347 m_FinishType = aOther.m_FinishType;
348
349 RemoveAll();
350
351 // All items in aOther.m_list have to be duplicated, because aOther.m_list
352 // manage pointers to these items
353 for( BOARD_STACKUP_ITEM* item : aOther.m_list )
354 {
355 BOARD_STACKUP_ITEM* dup_item = new BOARD_STACKUP_ITEM( *item );
356 Add( dup_item );
357 }
358
359 return *this;
360}

References Add(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_HasThicknessConstrains, m_list, and RemoveAll().

◆ RemoveAll()

void BOARD_STACKUP::RemoveAll ( )

◆ StackupAllowedBrdLayers()

static LSET BOARD_STACKUP::StackupAllowedBrdLayers ( )
inlinestatic
Returns
the board layers full mask allowed in the stackup list i.e. the SilkS, Mask, Paste and all copper layers

Definition at line 228 of file board_stackup.h.

229 {
232 }
static LSET ExternalCuMask()
Return a mask holding the Front and Bottom layers.
Definition: lset.cpp:801
static LSET InternalCuMask()
Return a complete set of internal copper layers which is all Cu layers except F_Cu and B_Cu.
Definition: lset.cpp:733

References B_Mask, B_Paste, B_SilkS, LSET::ExternalCuMask(), F_Mask, F_Paste, F_SilkS, and LSET::InternalCuMask().

Referenced by BuildDefaultStackupList(), PANEL_SETUP_BOARD_STACKUP::ImportSettingsFrom(), PANEL_SETUP_BOARD_STACKUP::OnLayersOptionsChanged(), and PANEL_SETUP_BOARD_STACKUP::PANEL_SETUP_BOARD_STACKUP().

◆ SynchronizeWithBoard()

bool BOARD_STACKUP::SynchronizeWithBoard ( BOARD_DESIGN_SETTINGS aSettings)

Synchronize the BOARD_STACKUP_ITEM* list with the board.

Not enabled layers are removed Missing layers are added

Parameters
aSettings,isthe current board setting.
Returns
true if changes are made

Definition at line 405 of file board_stackup.cpp.

406{
407 bool change = false;
408 // Build the suitable stackup:
409 BOARD_STACKUP stackup;
410 stackup.BuildDefaultStackupList( aSettings );
411
412 // First, find removed layers:
413 for( BOARD_STACKUP_ITEM* curr_item: m_list )
414 {
415 bool found = false;
416
417 for( BOARD_STACKUP_ITEM* item: stackup.GetList() )
418 {
419 if( curr_item->GetBrdLayerId() != UNDEFINED_LAYER )
420 {
421 if( item->GetBrdLayerId() == curr_item->GetBrdLayerId() )
422 {
423 found = true;
424 break;
425 }
426 }
427 else // curr_item = dielectric layer
428 {
429 if( item->GetBrdLayerId() != UNDEFINED_LAYER )
430 continue;
431
432 if( item->GetDielectricLayerId() == curr_item->GetDielectricLayerId() )
433 {
434 found = true;
435 break;
436 }
437 }
438 }
439
440 if( !found ) // a layer was removed: a change is found
441 {
442 change = true;
443 break;
444 }
445 }
446
447 // Now initialize all stackup items to the initial values, when exist
448 for( BOARD_STACKUP_ITEM* item : stackup.GetList() )
449 {
450 bool found = false;
451 // Search for initial settings:
452 for( const BOARD_STACKUP_ITEM* initial_item : m_list )
453 {
454 if( item->GetBrdLayerId() != UNDEFINED_LAYER )
455 {
456 if( item->GetBrdLayerId() == initial_item->GetBrdLayerId() )
457 {
458 *item = *initial_item;
459 found = true;
460 break;
461 }
462 }
463 else // dielectric layer: see m_DielectricLayerId for identification
464 {
465 // Compare dielectric layer with dielectric layer
466 if( initial_item->GetBrdLayerId() != UNDEFINED_LAYER )
467 continue;
468
469 if( item->GetDielectricLayerId() == initial_item->GetDielectricLayerId() )
470 {
471 *item = *initial_item;
472 found = true;
473 break;
474 }
475 }
476 }
477
478 if( !found )
479 {
480 change = true;
481 }
482 }
483
484 // Transfer layer settings:
485 *this = stackup;
486
487 // Transfer other stackup settings from aSettings
488 const BOARD_STACKUP& source_stackup = aSettings->GetStackupDescriptor();
491 m_CastellatedPads = source_stackup.m_CastellatedPads;
492 m_EdgePlating = source_stackup.m_EdgePlating;
493 m_FinishType = source_stackup.m_FinishType;
494
495 return change;
496}
void BuildDefaultStackupList(const BOARD_DESIGN_SETTINGS *aSettings, int aActiveCopperLayersCount=0)
Create a default stackup, according to the current BOARD_DESIGN_SETTINGS settings.

References BuildDefaultStackupList(), GetList(), BOARD_DESIGN_SETTINGS::GetStackupDescriptor(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_list, and UNDEFINED_LAYER.

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup(), and DRAWING_TOOL::DrawSpecificationStackup().

Member Data Documentation

◆ m_CastellatedPads

◆ m_EdgeConnectorConstraints

BS_EDGE_CONNECTOR_CONSTRAINTS BOARD_STACKUP::m_EdgeConnectorConstraints

If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTOR_NONE = no edge connector BS_EDGE_CONNECTOR_IN_USE = board has edge connectors BS_EDGE_CONNECTOR_BEVELLED = edge connectors are beveled.

Definition at line 318 of file board_stackup.h.

Referenced by GERBER_JOBFILE_WRITER::addJSONGeneralSpecs(), BOARD_STACKUP(), BuildDefaultStackupList(), BuildStackupReport(), DRAWING_TOOL::DrawBoardCharacteristics(), FormatBoardStackup(), operator=(), PCB_PARSER::parseBoardStackup(), PANEL_SETUP_BOARD_FINISH::synchronizeWithBoard(), SynchronizeWithBoard(), PANEL_SETUP_BOARD_FINISH::TransferDataFromWindow(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ m_EdgePlating

◆ m_FinishType

◆ m_HasDielectricConstrains

bool BOARD_STACKUP::m_HasDielectricConstrains

True if some layers have impedance controlled tracks or have specific constrains for micro-wave applications If the board has dielectric constrains, the .gbrjob will contain info about dielectric constrains: loss tangent and Epsilon rel.

If not, these values will be not specified in job file.

Definition at line 304 of file board_stackup.h.

Referenced by GERBER_JOBFILE_WRITER::addJSONGeneralSpecs(), GERBER_JOBFILE_WRITER::addJSONMaterialStackup(), BOARD_STACKUP(), BuildStackupReport(), DRAWING_TOOL::DrawBoardCharacteristics(), FormatBoardStackup(), operator=(), PCB_PARSER::parseBoardStackup(), SynchronizeWithBoard(), PANEL_SETUP_BOARD_STACKUP::synchronizeWithBoard(), PANEL_SETUP_BOARD_STACKUP::transferDataFromUIToStackup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ m_HasThicknessConstrains

bool BOARD_STACKUP::m_HasThicknessConstrains

True if some layers (copper and/or dielectric) have specific thickness.

Definition at line 309 of file board_stackup.h.

Referenced by BOARD_STACKUP(), and operator=().

◆ m_list


The documentation for this class was generated from the following files: