KiCad PCB EDA Suite
BOARD_STACKUP Class Reference

Manage layers needed to make a physical board. More...

#include <board_stackup.h>

Public Member Functions

 BOARD_STACKUP ()
 
 BOARD_STACKUP (const BOARD_STACKUP &aOther)
 
BOARD_STACKUPoperator= (const BOARD_STACKUP &aOther)
 
 ~BOARD_STACKUP ()
 
const std::vector< BOARD_STACKUP_ITEM * > & GetList () const
 
BOARD_STACKUP_ITEMGetStackupLayer (int aIndex)
 
void RemoveAll ()
 Delete all items in list and clear the list. More...
 
int GetCount () const
 
int BuildBoardThicknessFromStackup () const
 
void Add (BOARD_STACKUP_ITEM *aItem)
 Add a new item in stackup layer. More...
 
bool SynchronizeWithBoard (BOARD_DESIGN_SETTINGS *aSettings)
 Synchronize the BOARD_STACKUP_ITEM* list with the board. More...
 
void BuildDefaultStackupList (const BOARD_DESIGN_SETTINGS *aSettings, int aActiveCopperLayersCount=0)
 Create a default stackup, according to the current BOARD_DESIGN_SETTINGS settings. More...
 
void FormatBoardStackup (OUTPUTFORMATTER *aFormatter, const BOARD *aBoard, int aNestLevel) const
 Write the stackup info on board file. More...
 
int GetLayerDistance (PCB_LAYER_ID aFirstLayer, PCB_LAYER_ID aSecondLayer) const
 Calculate the distance (height) between the two given copper layers. More...
 

Static Public Member Functions

static LSET StackupAllowedBrdLayers ()
 

Public Attributes

wxString m_FinishType
 The name of external copper finish. More...
 
bool m_HasDielectricConstrains
 True if some layers have impedance controlled tracks or have specific constrains for micro-wave applications If the board has dielectric constrains, the .gbrjob will contain info about dielectric constrains: loss tangent and Epsilon rel. More...
 
bool m_HasThicknessConstrains
 True if some layers (copper and/or dielectric) have specific thickness. More...
 
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
 If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTOR_NONE = no edge connector BS_EDGE_CONNECTOR_IN_USE = board has edge connectors BS_EDGE_CONNECTOR_BEVELLED = edge connectors are beveled. More...
 
bool m_CastellatedPads
 True if castellated pads exist. More...
 
bool m_EdgePlating
 True if the edge board is plated. More...
 

Private Attributes

std::vector< BOARD_STACKUP_ITEM * > m_list
 

Detailed Description

Manage layers needed to make a physical board.

They are solder mask, silk screen, copper and dielectric. Some other layers, used in fabrication, are not managed here because they are not used to make a physical board itself.

Note
There are a few other parameters related to the physical stackup like finish type, impedance control and a few others.

Definition at line 210 of file board_stackup.h.

Constructor & Destructor Documentation

◆ BOARD_STACKUP() [1/2]

BOARD_STACKUP::BOARD_STACKUP ( )

Definition at line 293 of file board_stackup.cpp.

294{
295 m_HasDielectricConstrains = false; // True if some dielectric layers have constrains
296 // (Loss tg and Epison R)
297 m_HasThicknessConstrains = false; // True if some dielectric or copper layers have constrains
299 m_CastellatedPads = false; // True if some castellated pads exist
300 m_EdgePlating = false; // True if edge board is plated
301 m_FinishType = wxT( "None" ); // undefined finish type
302}
@ BS_EDGE_CONNECTOR_NONE
Definition: board_stackup.h:55
bool m_CastellatedPads
True if castellated pads exist.
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTO...
bool m_HasThicknessConstrains
True if some layers (copper and/or dielectric) have specific thickness.
wxString m_FinishType
The name of external copper finish.

References BS_EDGE_CONNECTOR_NONE, m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, and m_HasThicknessConstrains.

◆ BOARD_STACKUP() [2/2]

BOARD_STACKUP::BOARD_STACKUP ( const BOARD_STACKUP aOther)

Definition at line 305 of file board_stackup.cpp.

306{
312 m_FinishType = aOther.m_FinishType;
313
314 // All items in aOther.m_list have to be duplicated, because aOther.m_list
315 // manage pointers to these items
316 for( BOARD_STACKUP_ITEM* item : aOther.m_list )
317 {
318 BOARD_STACKUP_ITEM* dup_item = new BOARD_STACKUP_ITEM( *item );
319 Add( dup_item );
320 }
321}
Manage one layer needed to make a physical board.
Definition: board_stackup.h:90
void Add(BOARD_STACKUP_ITEM *aItem)
Add a new item in stackup layer.
std::vector< BOARD_STACKUP_ITEM * > m_list

References Add(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_HasThicknessConstrains, and m_list.

◆ ~BOARD_STACKUP()

BOARD_STACKUP::~BOARD_STACKUP ( )
inline

Definition at line 217 of file board_stackup.h.

217{ RemoveAll(); }
void RemoveAll()
Delete all items in list and clear the list.

References RemoveAll().

Member Function Documentation

◆ Add()

void BOARD_STACKUP::Add ( BOARD_STACKUP_ITEM aItem)
inline

Add a new item in stackup layer.

Definition at line 245 of file board_stackup.h.

245{ m_list.push_back( aItem ); }

References m_list.

Referenced by BOARD_STACKUP(), BuildDefaultStackupList(), operator=(), PCB_PARSER::parseBoardStackup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ BuildBoardThicknessFromStackup()

int BOARD_STACKUP::BuildBoardThicknessFromStackup ( ) const
Returns
the board thickness ( in UI) from the thickness of BOARD_STACKUP_ITEM list

Definition at line 365 of file board_stackup.cpp.

366{
367 // return the board thickness from the thickness of BOARD_STACKUP_ITEM list
368 int thickness = 0;
369
370 for( BOARD_STACKUP_ITEM* item : m_list )
371 {
372 if( item->IsThicknessEditable() && item->IsEnabled() )
373 {
374 thickness += item->GetThickness();
375
376 // dielectric layers can have more than one main layer
377 // add thickness of all sublayers
378 for( int idx = 1; idx < item->GetSublayersCount(); idx++ )
379 {
380 thickness += item->GetThickness( idx );
381 }
382 }
383 }
384
385 return thickness;
386}

References m_list.

Referenced by CADSTAR_PCB_ARCHIVE_LOADER::loadBoardStackup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ BuildDefaultStackupList()

void BOARD_STACKUP::BuildDefaultStackupList ( const BOARD_DESIGN_SETTINGS aSettings,
int  aActiveCopperLayersCount = 0 
)

Create a default stackup, according to the current BOARD_DESIGN_SETTINGS settings.

Parameters
aSettingsis the current board setting. if nullptr, build a full stackup (with 32 copper layers)
aActiveCopperLayersCountis used only if aSettings == nullptr is the number of copper layers to use to calculate a default dielectric thickness. ((<= 0 to use all copper layers)

Definition at line 483 of file board_stackup.cpp.

485{
486 // Creates a default stackup, according to the current BOARD_DESIGN_SETTINGS settings.
487 // Note: the m_TypeName string is made translatable using _HKI marker, but is not
488 // translated when building the stackup.
489 // It will be used as this in files, and can be translated only in dialog
490 // if aSettings == NULL, build a full stackup (with 32 copper layers)
491 LSET enabledLayer = aSettings ? aSettings->GetEnabledLayers() : StackupAllowedBrdLayers();
492 int copperLayerCount = aSettings ? aSettings->GetCopperLayerCount() : B_Cu+1;
493
494 // We need to calculate a suitable dielectric layer thickness.
495 // If no settings, and if aActiveCopperLayersCount is given, use it
496 // (If no settings, and no aActiveCopperLayersCount, the full 32 layers are used)
497 int activeCuLayerCount = copperLayerCount;
498
499 if( aSettings == nullptr && aActiveCopperLayersCount > 0 )
500 activeCuLayerCount = aActiveCopperLayersCount;
501
502 int brd__thickness = aSettings ? aSettings->GetBoardThickness() : pcbIUScale.mmToIU( 1.6 );
503 int diel_thickness = brd__thickness -
504 ( BOARD_STACKUP_ITEM::GetCopperDefaultThickness() * activeCuLayerCount );
505
506 // Take in account the solder mask thickness:
507 int sm_count = ( enabledLayer & LSET( 2, F_Mask, B_Mask) ).count();
508 diel_thickness -= BOARD_STACKUP_ITEM::GetMaskDefaultThickness() * sm_count;
509 diel_thickness /= std::max( 1, activeCuLayerCount - 1 );
510
511 int dielectric_idx = 0;
512
513 // Add silk screen, solder mask and solder paste layers on top
514 if( enabledLayer[F_SilkS] )
515 {
517 item->SetBrdLayerId( F_SilkS );
518 item->SetTypeName( _HKI( "Top Silk Screen" ) );
519 Add( item );
520 }
521
522 if( enabledLayer[F_Paste] )
523 {
525 item->SetBrdLayerId( F_Paste );
526 item->SetTypeName( _HKI( "Top Solder Paste" ) );
527 Add( item );
528 }
529
530 if( enabledLayer[F_Mask] )
531 {
533 item->SetBrdLayerId( F_Mask );
534 item->SetTypeName( _HKI( "Top Solder Mask" ) );
535 Add( item );
536 }
537
538 // Add copper and dielectric layers
539 for( int ii = 0; ii < copperLayerCount; ii++ )
540 {
542 item->SetBrdLayerId( ( PCB_LAYER_ID )ii );
543 item->SetTypeName( KEY_COPPER );
544 Add( item );
545
546 if( ii == copperLayerCount-1 )
547 {
548 item->SetBrdLayerId( B_Cu );
549 break;
550 }
551
552 // Add the dielectric layer:
554 item->SetThickness( diel_thickness );
555 item->SetDielectricLayerId( dielectric_idx + 1 );
556
557 // Display a dielectric default layer name:
558 if( (dielectric_idx & 1) == 0 )
559 {
560 item->SetTypeName( KEY_CORE );
561 item->SetMaterial( wxT( "FR4" ) );
562 }
563 else
564 {
565 item->SetTypeName( KEY_PREPREG );
566 item->SetMaterial( wxT( "FR4" ) );
567 }
568
569 Add( item );
570 dielectric_idx++;
571 }
572
573 // Add silk screen, solder mask and solder paste layers on bottom
574 if( enabledLayer[B_Mask] )
575 {
577 item->SetBrdLayerId( B_Mask );
578 item->SetTypeName( _HKI( "Bottom Solder Mask" ) );
579 Add( item );
580 }
581
582 if( enabledLayer[B_Paste] )
583 {
585 item->SetBrdLayerId( B_Paste );
586 item->SetTypeName( _HKI( "Bottom Solder Paste" ) );
587 Add( item );
588 }
589
590 if( enabledLayer[B_SilkS] )
591 {
593 item->SetBrdLayerId( B_SilkS );
594 item->SetTypeName( _HKI( "Bottom Silk Screen" ) );
595 Add( item );
596 }
597
598 // Transfer other stackup settings from aSettings
599 if( aSettings )
600 {
601 const BOARD_STACKUP& source_stackup = aSettings->GetStackupDescriptor();
603 m_CastellatedPads = source_stackup.m_CastellatedPads;
604 m_EdgePlating = source_stackup.m_EdgePlating;
605 m_FinishType = source_stackup.m_FinishType;
606 }
607}
constexpr EDA_IU_SCALE pcbIUScale
Definition: base_units.h:109
@ BS_ITEM_TYPE_COPPER
Definition: board_stackup.h:43
@ BS_ITEM_TYPE_SILKSCREEN
Definition: board_stackup.h:49
@ BS_ITEM_TYPE_DIELECTRIC
Definition: board_stackup.h:44
@ BS_ITEM_TYPE_SOLDERPASTE
Definition: board_stackup.h:46
@ BS_ITEM_TYPE_SOLDERMASK
Definition: board_stackup.h:47
LSET GetEnabledLayers() const
Return a bit-mask of all the layers that are enabled.
int GetBoardThickness() const
The full thickness of the board including copper and masks.
BOARD_STACKUP & GetStackupDescriptor()
void SetDielectricLayerId(int aLayerId)
void SetThickness(int aThickness, int aDielectricSubLayer=0)
void SetMaterial(const wxString &aName, int aDielectricSubLayer=0)
static int GetMaskDefaultThickness()
void SetBrdLayerId(PCB_LAYER_ID aBrdLayerId)
void SetTypeName(const wxString &aName)
static int GetCopperDefaultThickness()
Manage layers needed to make a physical board.
static LSET StackupAllowedBrdLayers()
LSET is a set of PCB_LAYER_IDs.
Definition: layer_ids.h:530
#define _HKI(x)
PCB_LAYER_ID
A quick note on layer IDs:
Definition: layer_ids.h:59
@ F_Paste
Definition: layer_ids.h:101
@ B_Mask
Definition: layer_ids.h:106
@ B_Cu
Definition: layer_ids.h:95
@ F_Mask
Definition: layer_ids.h:107
@ B_Paste
Definition: layer_ids.h:100
@ F_SilkS
Definition: layer_ids.h:104
@ B_SilkS
Definition: layer_ids.h:103
#define KEY_PREPREG
#define KEY_COPPER
#define KEY_CORE
constexpr int mmToIU(double mm) const
Definition: base_units.h:89

References _HKI, Add(), B_Cu, B_Mask, B_Paste, B_SilkS, BS_ITEM_TYPE_COPPER, BS_ITEM_TYPE_DIELECTRIC, BS_ITEM_TYPE_SILKSCREEN, BS_ITEM_TYPE_SOLDERMASK, BS_ITEM_TYPE_SOLDERPASTE, F_Mask, F_Paste, F_SilkS, BOARD_DESIGN_SETTINGS::GetBoardThickness(), BOARD_STACKUP_ITEM::GetCopperDefaultThickness(), BOARD_DESIGN_SETTINGS::GetCopperLayerCount(), BOARD_DESIGN_SETTINGS::GetEnabledLayers(), BOARD_STACKUP_ITEM::GetMaskDefaultThickness(), BOARD_DESIGN_SETTINGS::GetStackupDescriptor(), KEY_COPPER, KEY_CORE, KEY_PREPREG, m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, EDA_IU_SCALE::mmToIU(), pcbIUScale, BOARD_STACKUP_ITEM::SetBrdLayerId(), BOARD_STACKUP_ITEM::SetDielectricLayerId(), BOARD_STACKUP_ITEM::SetMaterial(), BOARD_STACKUP_ITEM::SetThickness(), BOARD_STACKUP_ITEM::SetTypeName(), and StackupAllowedBrdLayers().

Referenced by PANEL_SETUP_BOARD_STACKUP::buildLayerStackPanel(), CADSTAR_PCB_ARCHIVE_LOADER::loadBoardStackup(), PANEL_PREVIEW_3D_MODEL::PANEL_PREVIEW_3D_MODEL(), ALTIUM_PCB::ParseBoard6Data(), SynchronizeWithBoard(), and PANEL_PREVIEW_3D_MODEL::updateBoardThickness().

◆ FormatBoardStackup()

void BOARD_STACKUP::FormatBoardStackup ( OUTPUTFORMATTER aFormatter,
const BOARD aBoard,
int  aNestLevel 
) const

Write the stackup info on board file.

Parameters
aFormatteris the OUTPUTFORMATTER used to create the file
aBoardis the board
aNestLevelis the index to nest level to indent the lines in file

Definition at line 610 of file board_stackup.cpp.

612{
613 // Board stackup is the ordered list from top to bottom of
614 // physical layers and substrate used to build the board.
615 if( m_list.empty() )
616 return;
617
618 aFormatter->Print( aNestLevel, "(stackup\n" );
619 int nest_level = aNestLevel+1;
620
621 // Note:
622 // Unspecified parameters are not stored in file.
623 for( BOARD_STACKUP_ITEM* item: m_list )
624 {
625 wxString layer_name;
626
627 if( item->GetBrdLayerId() == UNDEFINED_LAYER )
628 layer_name.Printf( wxT( "dielectric %d" ), item->GetDielectricLayerId() );
629 else
630 layer_name = LSET::Name( item->GetBrdLayerId() );
631
632 aFormatter->Print( nest_level, "(layer %s (type %s)",
633 aFormatter->Quotew( layer_name ).c_str(),
634 aFormatter->Quotew( item->GetTypeName() ).c_str() );
635
636 if( item->IsColorEditable() && IsPrmSpecified( item->GetColor() ) )
637 {
638 aFormatter->Print( 0, " (color %s)",
639 aFormatter->Quotew( item->GetColor() ).c_str() );
640 }
641
642 for( int idx = 0; idx < item->GetSublayersCount(); idx++ )
643 {
644 if( idx ) // not for the main (first) layer.
645 {
646 aFormatter->Print( 0, "\n" );
647 aFormatter->Print( nest_level+1, "addsublayer" );
648 }
649
650 if( item->IsThicknessEditable() )
651 {
652 if( item->GetType() == BS_ITEM_TYPE_DIELECTRIC && item->IsThicknessLocked( idx ) )
653 aFormatter->Print( 0, " (thickness %s locked)",
654 EDA_UNIT_UTILS::FormatInternalUnits( pcbIUScale, item->GetThickness( idx ) ).c_str() );
655 else
656 aFormatter->Print( 0, " (thickness %s)",
657 EDA_UNIT_UTILS::FormatInternalUnits( pcbIUScale, item->GetThickness( idx ) ).c_str() );
658 }
659
660 if( item->HasMaterialValue( idx ) )
661 aFormatter->Print( 0, " (material %s)",
662 aFormatter->Quotew( item->GetMaterial( idx ) ).c_str() );
663
664 if( item->HasEpsilonRValue() && item->HasMaterialValue( idx ) )
665 aFormatter->Print( 0, " (epsilon_r %g)", item->GetEpsilonR( idx ) );
666
667 if( item->HasLossTangentValue() && item->HasMaterialValue( idx ) )
668 aFormatter->Print( 0, " (loss_tangent %s)",
669 FormatDouble2Str( item->GetLossTangent( idx ) ).c_str() );
670 }
671
672 aFormatter->Print( 0, ")\n" );
673 }
674
675 // Other infos about board, related to layers and other fabrication specifications
677 {
678 aFormatter->Print( nest_level, "(copper_finish %s)\n",
679 aFormatter->Quotew( m_FinishType ).c_str() );
680 }
681
682 aFormatter->Print( nest_level, "(dielectric_constraints %s)\n",
683 m_HasDielectricConstrains ? "yes" : "no" );
684
686 {
687 aFormatter->Print( nest_level, "(edge_connector %s)\n",
688 m_EdgeConnectorConstraints > 1 ? "bevelled": "yes" );
689 }
690
692 aFormatter->Print( nest_level, "(castellated_pads yes)\n" );
693
694 if( m_EdgePlating )
695 aFormatter->Print( nest_level, "(edge_plating yes)\n" );
696
697 aFormatter->Print( aNestLevel, ")\n" );
698}
bool IsPrmSpecified(const wxString &aPrmValue)
static const wxChar * Name(PCB_LAYER_ID aLayerId)
Return the fixed name association with aLayerId.
Definition: lset.cpp:82
std::string Quotew(const wxString &aWrapee) const
Definition: richio.cpp:499
int PRINTF_FUNC Print(int nestLevel, const char *fmt,...)
Format and write text to the output stream.
Definition: richio.cpp:431
@ UNDEFINED_LAYER
Definition: layer_ids.h:60
std::string FormatInternalUnits(const EDA_IU_SCALE &aIuScale, int aValue)
Converts aValue from internal units to a string appropriate for writing to file.
Definition: eda_units.cpp:143
std::string FormatDouble2Str(double aValue)
Print a float number without using scientific notation and no trailing 0 This function is intended in...

References BS_ITEM_TYPE_DIELECTRIC, FormatDouble2Str(), EDA_UNIT_UTILS::FormatInternalUnits(), IsPrmSpecified(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_list, LSET::Name(), pcbIUScale, OUTPUTFORMATTER::Print(), OUTPUTFORMATTER::Quotew(), and UNDEFINED_LAYER.

Referenced by PCB_PLUGIN::formatSetup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ GetCount()

int BOARD_STACKUP::GetCount ( ) const
inline
Returns
the number of layers in the stackup

Definition at line 239 of file board_stackup.h.

239{ return (int) m_list.size(); }

References m_list.

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup(), DRAWING_TOOL::DrawSpecificationStackup(), GetStackupLayer(), and BOARD_ADAPTER::InitSettings().

◆ GetLayerDistance()

int BOARD_STACKUP::GetLayerDistance ( PCB_LAYER_ID  aFirstLayer,
PCB_LAYER_ID  aSecondLayer 
) const

Calculate the distance (height) between the two given copper layers.

This factors in the thickness of any dielectric and copper layers between the two given layers, and half the height of the given start and end layers. This half-height calculation allows this to be used for consistent length measurements when calculating net length through a series of vias. A more advanced algorithm would be possible once we have a good concept of the start and end for a length measurement, but for now this will do. See https://gitlab.com/kicad/code/kicad/-/issues/8384 for more background.

Parameters
aFirstLayeris a copper layer
aSecondLayeris a different copper layer
Returns
the height (in IU) between the two layers

Definition at line 701 of file board_stackup.cpp.

702{
703 wxASSERT( IsCopperLayer( aFirstLayer ) && IsCopperLayer( aSecondLayer ) );
704
705 if( aFirstLayer == aSecondLayer )
706 return 0;
707
708 if( aSecondLayer < aFirstLayer )
709 std::swap( aFirstLayer, aSecondLayer );
710
711 int total = 0;
712 bool start = false;
713 bool half = false;
714
715 for( BOARD_STACKUP_ITEM* item : m_list )
716 {
717 // Will be UNDEFINED_LAYER for dielectrics
718 PCB_LAYER_ID layer = item->GetBrdLayerId();
719
720 if( layer != UNDEFINED_LAYER && !IsCopperLayer( layer ) )
721 continue; // Silk/mask layer
722
723 // Reached the start copper layer? Start counting the next dielectric after it
724 if( !start && ( layer != UNDEFINED_LAYER && layer >= aFirstLayer ) )
725 {
726 start = true;
727 half = true;
728 }
729 else if( !start )
730 continue;
731
732 // Reached the stop copper layer? we're done
733 if( start && ( layer != UNDEFINED_LAYER && layer >= aSecondLayer ) )
734 half = true;
735
736 for( int sublayer = 0; sublayer < item->GetSublayersCount(); sublayer++ )
737 {
738 int subThickness = item->GetThickness( sublayer );
739 total += half ? ( subThickness / 2 ) : subThickness;
740 }
741
742 half = false;
743
744 if( layer != UNDEFINED_LAYER && layer >= aSecondLayer )
745 break;
746 }
747
748 return total;
749}
bool IsCopperLayer(int aLayerId)
Tests whether a layer is a copper layer.
Definition: layer_ids.h:823

References IsCopperLayer(), m_list, and UNDEFINED_LAYER.

Referenced by DIALOG_NET_INSPECTOR::calculateViaLength(), BOARD::GetTrackLength(), DRC_TEST_PROVIDER_MATCHED_LENGTH::runInternal(), and PNS_KICAD_IFACE_BASE::StackupHeight().

◆ GetList()

◆ GetStackupLayer()

BOARD_STACKUP_ITEM * BOARD_STACKUP::GetStackupLayer ( int  aIndex)
Returns
a reference to the layer aIndex, or nullptr if not exists

Definition at line 356 of file board_stackup.cpp.

357{
358 if( aIndex < 0 || aIndex >= GetCount() )
359 return nullptr;
360
361 return GetList()[aIndex];
362}
const std::vector< BOARD_STACKUP_ITEM * > & GetList() const
int GetCount() const

References GetCount(), and GetList().

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup().

◆ operator=()

BOARD_STACKUP & BOARD_STACKUP::operator= ( const BOARD_STACKUP aOther)

Definition at line 324 of file board_stackup.cpp.

325{
331 m_FinishType = aOther.m_FinishType;
332
333 RemoveAll();
334
335 // All items in aOther.m_list have to be duplicated, because aOther.m_list
336 // manage pointers to these items
337 for( BOARD_STACKUP_ITEM* item : aOther.m_list )
338 {
339 BOARD_STACKUP_ITEM* dup_item = new BOARD_STACKUP_ITEM( *item );
340 Add( dup_item );
341 }
342
343 return *this;
344}

References Add(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_HasThicknessConstrains, m_list, and RemoveAll().

◆ RemoveAll()

void BOARD_STACKUP::RemoveAll ( )

◆ StackupAllowedBrdLayers()

static LSET BOARD_STACKUP::StackupAllowedBrdLayers ( )
inlinestatic
Returns
the board layers full mask allowed in the stackup list i.e. the SilkS, Mask, Paste and all copper layers

Definition at line 228 of file board_stackup.h.

229 {
232 }
static LSET ExternalCuMask()
Return a mask holding the Front and Bottom layers.
Definition: lset.cpp:801
static LSET InternalCuMask()
Return a complete set of internal copper layers which is all Cu layers except F_Cu and B_Cu.
Definition: lset.cpp:733

References B_Mask, B_Paste, B_SilkS, LSET::ExternalCuMask(), F_Mask, F_Paste, F_SilkS, and LSET::InternalCuMask().

Referenced by BuildDefaultStackupList(), PANEL_SETUP_BOARD_STACKUP::ImportSettingsFrom(), PANEL_SETUP_BOARD_STACKUP::OnLayersOptionsChanged(), and PANEL_SETUP_BOARD_STACKUP::PANEL_SETUP_BOARD_STACKUP().

◆ SynchronizeWithBoard()

bool BOARD_STACKUP::SynchronizeWithBoard ( BOARD_DESIGN_SETTINGS aSettings)

Synchronize the BOARD_STACKUP_ITEM* list with the board.

Not enabled layers are removed Missing layers are added

Parameters
aSettings,isthe current board setting.
Returns
true if changes are made

Definition at line 389 of file board_stackup.cpp.

390{
391 bool change = false;
392 // Build the suitable stackup:
393 BOARD_STACKUP stackup;
394 stackup.BuildDefaultStackupList( aSettings );
395
396 // First, find removed layers:
397 for( BOARD_STACKUP_ITEM* curr_item: m_list )
398 {
399 bool found = false;
400
401 for( BOARD_STACKUP_ITEM* item: stackup.GetList() )
402 {
403 if( curr_item->GetBrdLayerId() != UNDEFINED_LAYER )
404 {
405 if( item->GetBrdLayerId() == curr_item->GetBrdLayerId() )
406 {
407 found = true;
408 break;
409 }
410 }
411 else // curr_item = dielectric layer
412 {
413 if( item->GetBrdLayerId() != UNDEFINED_LAYER )
414 continue;
415
416 if( item->GetDielectricLayerId() == curr_item->GetDielectricLayerId() )
417 {
418 found = true;
419 break;
420 }
421 }
422 }
423
424 if( !found ) // a layer was removed: a change is found
425 {
426 change = true;
427 break;
428 }
429 }
430
431 // Now initialize all stackup items to the initial values, when exist
432 for( BOARD_STACKUP_ITEM* item : stackup.GetList() )
433 {
434 bool found = false;
435 // Search for initial settings:
436 for( const BOARD_STACKUP_ITEM* initial_item : m_list )
437 {
438 if( item->GetBrdLayerId() != UNDEFINED_LAYER )
439 {
440 if( item->GetBrdLayerId() == initial_item->GetBrdLayerId() )
441 {
442 *item = *initial_item;
443 found = true;
444 break;
445 }
446 }
447 else // dielectric layer: see m_DielectricLayerId for identification
448 {
449 // Compare dielectric layer with dielectric layer
450 if( initial_item->GetBrdLayerId() != UNDEFINED_LAYER )
451 continue;
452
453 if( item->GetDielectricLayerId() == initial_item->GetDielectricLayerId() )
454 {
455 *item = *initial_item;
456 found = true;
457 break;
458 }
459 }
460 }
461
462 if( !found )
463 {
464 change = true;
465 }
466 }
467
468 // Transfer layer settings:
469 *this = stackup;
470
471 // Transfer other stackup settings from aSettings
472 const BOARD_STACKUP& source_stackup = aSettings->GetStackupDescriptor();
475 m_CastellatedPads = source_stackup.m_CastellatedPads;
476 m_EdgePlating = source_stackup.m_EdgePlating;
477 m_FinishType = source_stackup.m_FinishType;
478
479 return change;
480}
void BuildDefaultStackupList(const BOARD_DESIGN_SETTINGS *aSettings, int aActiveCopperLayersCount=0)
Create a default stackup, according to the current BOARD_DESIGN_SETTINGS settings.

References BuildDefaultStackupList(), GetList(), BOARD_DESIGN_SETTINGS::GetStackupDescriptor(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_list, and UNDEFINED_LAYER.

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup(), and DRAWING_TOOL::DrawSpecificationStackup().

Member Data Documentation

◆ m_CastellatedPads

◆ m_EdgeConnectorConstraints

BS_EDGE_CONNECTOR_CONSTRAINTS BOARD_STACKUP::m_EdgeConnectorConstraints

If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTOR_NONE = no edge connector BS_EDGE_CONNECTOR_IN_USE = board has edge connectors BS_EDGE_CONNECTOR_BEVELLED = edge connectors are beveled.

Definition at line 318 of file board_stackup.h.

Referenced by GERBER_JOBFILE_WRITER::addJSONGeneralSpecs(), BOARD_STACKUP(), BuildDefaultStackupList(), BuildStackupReport(), DRAWING_TOOL::DrawBoardCharacteristics(), FormatBoardStackup(), operator=(), PCB_PARSER::parseBoardStackup(), PANEL_SETUP_BOARD_FINISH::synchronizeWithBoard(), SynchronizeWithBoard(), PANEL_SETUP_BOARD_FINISH::TransferDataFromWindow(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ m_EdgePlating

◆ m_FinishType

◆ m_HasDielectricConstrains

bool BOARD_STACKUP::m_HasDielectricConstrains

True if some layers have impedance controlled tracks or have specific constrains for micro-wave applications If the board has dielectric constrains, the .gbrjob will contain info about dielectric constrains: loss tangent and Epsilon rel.

If not, these values will be not specified in job file.

Definition at line 304 of file board_stackup.h.

Referenced by GERBER_JOBFILE_WRITER::addJSONGeneralSpecs(), GERBER_JOBFILE_WRITER::addJSONMaterialStackup(), BOARD_STACKUP(), BuildStackupReport(), DRAWING_TOOL::DrawBoardCharacteristics(), FormatBoardStackup(), operator=(), PCB_PARSER::parseBoardStackup(), SynchronizeWithBoard(), PANEL_SETUP_BOARD_STACKUP::synchronizeWithBoard(), PANEL_SETUP_BOARD_STACKUP::transferDataFromUIToStackup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ m_HasThicknessConstrains

bool BOARD_STACKUP::m_HasThicknessConstrains

True if some layers (copper and/or dielectric) have specific thickness.

Definition at line 309 of file board_stackup.h.

Referenced by BOARD_STACKUP(), and operator=().

◆ m_list


The documentation for this class was generated from the following files: