51#include <wx/numformatter.h>
52#include <wx/mstream.h>
69 catch(
const std::exception& e )
71 std::cerr << e.what() << std::endl;
81 { wxS(
"ODB_VERSION_MAJOR" ), wxS(
"8" ) },
82 { wxS(
"ODB_VERSION_MINOR" ), wxS(
"1" ) },
84 { wxS(
"CREATION_DATE" ), wxDateTime::Now().FormatISOCombined() },
85 { wxS(
"SAVE_DATE" ), wxDateTime::Now().FormatISOCombined() },
86 { wxS(
"SAVE_APP" ), wxS(
"Pcbnew" ) },
87 { wxS(
"SAVE_USER" ), wxS(
"" ) } };
124 std::vector<BOARD_STACKUP_ITEM*> layers = stackup.
GetList();
125 std::set<PCB_LAYER_ID> added_layers;
127 for(
int i = 0; i < stackup.
GetCount(); i++ )
131 for(
int sublayer_id = 0; sublayer_id < stackup_item->
GetSublayersCount(); sublayer_id++ )
135 if( ly_name.IsEmpty() )
141 ly_name = wxString::Format(
"DIELECTRIC_%d",
150 matrix.
m_diType.emplace( ODB_DIELECTRIC_TYPE::CORE );
152 matrix.
m_diType.emplace( ODB_DIELECTRIC_TYPE::PREPREG );
154 matrix.
m_type = ODB_TYPE::DIELECTRIC;
159 std::make_pair( PCB_LAYER_ID::UNDEFINED_LAYER, matrix.
m_layerName ) );
175 if( added_layers.find( layer ) != added_layers.end() )
179 added_layers.insert( layer );
196 case B_Paste: aMLayer.
m_type = ODB_TYPE::SOLDER_PASTE;
break;
200 case B_Mask: aMLayer.
m_type = ODB_TYPE::SOLDER_MASK;
break;
223 aMLayer.
m_type = ODB_TYPE::DOCUMENT;
229 aMLayer.
m_type = ODB_TYPE::SIGNAL;
234 aMLayer.
m_type = ODB_TYPE::UNDEFINED;
241 if( aMLayer.
m_type != ODB_TYPE::UNDEFINED )
251 std::map<std::pair<PCB_LAYER_ID, PCB_LAYER_ID>, std::vector<BOARD_ITEM*>>& drill_layers =
254 std::map<std::pair<PCB_LAYER_ID, PCB_LAYER_ID>, std::vector<BOARD_ITEM*>>& slot_holes =
257 bool has_pth_layer =
false;
258 bool has_npth_layer =
false;
265 drill_layers[std::make_pair(
via->TopLayer(),
via->BottomLayer() )].push_back(
via );
273 if( fp->IsFlipped() )
278 for(
PAD*
pad : fp->Pads() )
280 if( !has_pth_layer &&
pad->GetAttribute() == PAD_ATTRIB::PTH )
281 has_pth_layer =
true;
282 if( !has_npth_layer &&
pad->GetAttribute() == PAD_ATTRIB::NPTH )
283 has_npth_layer =
true;
285 if(
pad->HasHole() &&
pad->GetDrillSizeX() !=
pad->GetDrillSizeY() )
286 slot_holes[std::make_pair(
F_Cu,
B_Cu )].push_back(
pad );
287 else if(
pad->HasHole() )
288 drill_layers[std::make_pair(
F_Cu,
B_Cu )].push_back(
pad );
294 auto InitDrillMatrix =
295 [&](
const wxString& aHasPlated, std::pair<PCB_LAYER_ID, PCB_LAYER_ID> aLayerPair )
297 wxString dLayerName = wxString::Format(
"drill_%s_%s-%s", aHasPlated,
302 matrix.
m_type = ODB_TYPE::DRILL;
305 matrix.
m_span.emplace( std::make_pair(
310 std::make_pair( PCB_LAYER_ID::UNDEFINED_LAYER, matrix.
m_layerName ) );
313 if( drill_layers.find( std::make_pair(
F_Cu,
B_Cu ) ) != drill_layers.end()
314 || !slot_holes.empty() )
318 InitDrillMatrix(
"plated", std::make_pair(
F_Cu,
B_Cu ) );
320 InitDrillMatrix(
"non-plated", std::make_pair(
F_Cu,
B_Cu ) );
323 for(
const auto& [layer_pair, vec] : drill_layers )
325 if( layer_pair != std::make_pair(
F_Cu,
B_Cu ) )
326 InitDrillMatrix(
"plated", layer_pair );
334 matrix.
m_type = ODB_TYPE::COMPONENT;
339 std::make_pair( PCB_LAYER_ID::UNDEFINED_LAYER, matrix.
m_layerName ) );
347 std::make_pair( PCB_LAYER_ID::UNDEFINED_LAYER, matrix.
m_layerName ) );
372 if( layer.m_addType.has_value() )
381 if( layer.m_diType.has_value() )
391 if( layer.m_span.has_value() )
407 std::map<
int, std::vector<BOARD_ITEM*>>& aMap,
408 const PCB_LAYER_ID& aLayerID,
const wxString& aLayerName ) :
409 ODB_ENTITY_BASE( aBoard, aPlugin ), m_layerItems( aMap ), m_layerID( aLayerID ),
410 m_matrixLayerName( aLayerName )
412 m_featuresMgr = std::make_unique<FEATURES_MANAGER>( aBoard, aPlugin, aLayerName );
425 if(
m_layerID != PCB_LAYER_ID::UNDEFINED_LAYER )
440 std::vector<BOARD_ITEM*>& vec =
m_layerItems[net->GetNetCode()];
442 std::stable_sort( vec.begin(), vec.end(),
445 if( a->GetParentFootprint() == b->GetParentFootprint() )
446 return a->Type() < b->Type();
448 return a->GetParentFootprint() < b->GetParentFootprint();
468 return m_compBot.value().AddComponent( aFp, aPkg );
477 return m_compTop.value().AddComponent( aFp, aPkg );
484 std::map<std::pair<PCB_LAYER_ID, PCB_LAYER_ID>, std::vector<BOARD_ITEM*>>& drill_layers =
487 std::map<std::pair<PCB_LAYER_ID, PCB_LAYER_ID>, std::vector<BOARD_ITEM*>>& slot_holes =
497 bool is_npth_layer =
false;
498 wxString plated_name =
"plated";
502 is_npth_layer =
true;
503 plated_name =
"non-plated";
507 for(
const auto& [layer_pair, vec] : slot_holes )
509 wxString dLayerName = wxString::Format(
"drill_%s_%s-%s", plated_name,
521 if( ( is_npth_layer &&
pad->GetAttribute() == PAD_ATTRIB::PTH )
522 || ( !is_npth_layer &&
pad->GetAttribute() == PAD_ATTRIB::NPTH ) )
528 pad->GetAttribute() == PAD_ATTRIB::PTH ?
"PLATED" :
"NON_PLATED",
530 std::min(
pad->GetDrillSizeX(),
pad->GetDrillSizeY() ) ) );
541 for(
const auto& [layer_pair, vec] : drill_layers )
543 wxString dLayerName = wxString::Format(
"drill_%s_%s-%s", plated_name,
551 if( item->Type() ==
PCB_VIA_T && !is_npth_layer )
555 m_tools.value().AddDrillTools(
"VIA",
565 if( ( is_npth_layer &&
pad->GetAttribute() == PAD_ATTRIB::PTH )
566 || ( !is_npth_layer &&
pad->GetAttribute() == PAD_ATTRIB::NPTH ) )
572 pad->GetAttribute() == PAD_ATTRIB::PTH ?
"PLATED" :
"NON_PLATED",
595 layer_entity_ptr->InitEntityData();
624 m_compTop->Write( fileproxy.GetStream() );
628 m_compBot->Write( fileproxy.GetStream() );
651 m_tools.value().GenerateFile( fileproxy.GetStream() );
677 if( fp->IsFlipped() )
684 wxLogError(
_(
"Failed to add component data" ) );
696 ODB_COMPONENT& comp = iter->second->InitComponentData( fp, eda_pkg );
698 for(
int i = 0; i < fp->Pads().size(); ++i )
713 auto& toep = comp.
m_toeprints.emplace_back( pin_ref );
715 toep.m_net_num = eda_net.m_index;
716 toep.m_subnet_num = subnet.m_index;
721 (
ANGLE_360 -
pad->GetOrientation() ).Normalize().AsDegrees() );
723 if(
pad->IsFlipped() )
724 toep.m_mirror = wxT(
"M" );
726 toep.m_mirror = wxT(
"N" );
752 std::forward_as_tuple( layer, zone ),
753 std::forward_as_tuple( &subnet ) );
792 wxLogError(
"Failed to get board outline" );
795 if( !
m_profile->AddContour( board_outline, 0 ) )
797 wxLogError(
"Failed to add polygon to profile" );
800 m_profile->GenerateProfileFeatures( fileproxy.GetStream() );
814 {
"TOP_ACTIVE",
"0" },
815 {
"BOTTOM_ACTIVE",
"0" },
816 {
"RIGHT_ACTIVE",
"0" },
817 {
"LEFT_ACTIVE",
"0" },
818 {
"AFFECTING_BOM",
"" },
819 {
"AFFECTING_BOM_CHANGED",
"0" },
824 for(
const auto& [key, value] :
m_stephdr )
839 layerEntity->GenerateFiles( writer );
868 catch(
const std::exception& e )
870 std::cerr << e.what() << std::endl;
883 std::map<PCB_LAYER_ID, std::map<int, std::vector<BOARD_ITEM*>>>& elements =
887 [&layers, &elements](
PCB_TRACK* aTrack )
889 if( aTrack->Type() == PCB_VIA_T )
891 PCB_VIA* via = static_cast<PCB_VIA*>( aTrack );
893 for( PCB_LAYER_ID layer : layers )
895 if( via->FlashLayer( layer ) )
896 elements[layer][via->GetNetCode()].push_back( via );
901 elements[aTrack->GetLayer()][aTrack->GetNetCode()].push_back( aTrack );
905 std::for_each( m_board->Zones().begin(), m_board->Zones().end(),
906 [&elements](
ZONE* zone )
908 LSEQ zone_layers = zone->GetLayerSet().Seq();
910 for( PCB_LAYER_ID layer : zone_layers )
912 elements[layer][zone->GetNetCode()].push_back( zone );
919 elements[conn_it->GetLayer()][conn_it->GetNetCode()].push_back( conn_it );
921 elements[item->GetLayer()][0].push_back( item );
924 for(
FOOTPRINT* fp : m_board->Footprints() )
926 for(
PCB_FIELD* field : fp->GetFields() )
927 elements[field->GetLayer()][0].push_back( field );
929 for(
BOARD_ITEM* item : fp->GraphicalItems() )
930 elements[item->GetLayer()][0].push_back( item );
932 for(
PAD*
pad : fp->Pads() )
934 LSEQ pad_layers =
pad->GetLayerSet().Seq();
941 bool onSolderPasteLayer =
944 if( onSolderMaskLayer )
947 if( onSolderPasteLayer )
952 if( onCopperLayer && !
pad->IsOnCopperLayer() )
955 if( onCopperLayer && !
pad->FlashLayer( layer ) )
959 && ( padPlotsSize.
x <= 0 || padPlotsSize.
y <= 0 ) )
962 elements[layer][
pad->GetNetCode()].push_back(
pad );
967 for(
const auto& [layerID, layerName] : m_plugin->GetLayerNameList() )
969 std::shared_ptr<ODB_LAYER_ENTITY> layer_entity_ptr = std::make_shared<ODB_LAYER_ENTITY>(
970 m_board, m_plugin, elements[layerID], layerID, layerName );
972 m_layerEntityMap.emplace( layerName, layer_entity_ptr );
@ BS_ITEM_TYPE_DIELECTRIC
wxString GetMajorMinorPatchVersion()
Get the major, minor and patch version in a string major.minor.patch This is extracted by CMake from ...
A base class derived from BOARD_ITEM for items that can be connected and have a net,...
Container for design settings for a BOARD object.
BOARD_STACKUP & GetStackupDescriptor()
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Manage one layer needed to make a physical board.
wxString GetTypeName() const
int GetSublayersCount() const
wxString GetLayerName() const
PCB_LAYER_ID GetBrdLayerId() const
BOARD_STACKUP_ITEM_TYPE GetType() const
int GetDielectricLayerId() const
Manage layers needed to make a physical board.
const std::vector< BOARD_STACKUP_ITEM * > & GetList() const
bool SynchronizeWithBoard(BOARD_DESIGN_SETTINGS *aSettings)
Synchronize the BOARD_STACKUP_ITEM* list with the board.
Information pertinent to a Pcbnew printed circuit board.
bool GetBoardPolygonOutlines(SHAPE_POLY_SET &aOutlines, OUTLINE_ERROR_HANDLER *aErrorHandler=nullptr, bool aAllowUseArcsInPolygons=false, bool aIncludeNPTHAsOutlines=false)
Extract the board outlines and build a closed polygon from lines, arcs and circle items on edge cut l...
const NETINFO_LIST & GetNetInfo() const
LSET GetEnabledLayers() const
A proxy function that calls the corresponding function in m_BoardSettings.
const ZONES & Zones() const
const FOOTPRINTS & Footprints() const
const TRACKS & Tracks() const
const wxString GetLayerName(PCB_LAYER_ID aLayer) const
Return the name of a aLayer.
BOARD_DESIGN_SETTINGS & GetDesignSettings() const
T & AddSubnet(Args &&... args)
const std::shared_ptr< PIN > GetEdaPkgPin(size_t aPadIndex) const
NET & GetNet(size_t aNetcode)
const PACKAGE & GetPackage(size_t aHash) const
void AddNET(const NETINFO_ITEM *aNet)
void AddPackage(const FOOTPRINT *aFp)
void Write(std::ostream &ost) const
std::vector< std::shared_ptr< FOOTPRINT > > GetEdaFootprints() const
LSEQ is a sequence (and therefore also a set) of PCB_LAYER_IDs.
LSET is a set of PCB_LAYER_IDs.
static LSET AllCuMask(int aCuLayerCount=MAX_CU_LAYERS)
Return a mask holding the requested number of Cu PCB_LAYER_IDs.
LSEQ Seq(const LSEQ &aSequence) const
Return an LSEQ from the union of this LSET and a desired sequence.
Handle the data for a net.
Container for NETINFO_ITEM elements, which are the nets.
const size_t m_index
! CMP index number on board to be used in SNT(TOP), 0~n-1
std::list< TOEPRINT > m_toeprints
virtual std::string GetEntityName()=0
virtual bool CreateDirectoryTree(ODB_TREE_WRITER &writer)
void GenFeatures(ODB_TREE_WRITER &writer)
void GenComponents(ODB_TREE_WRITER &writer)
wxString m_matrixLayerName
std::optional< COMPONENTS_MANAGER > m_compTop
virtual void GenerateFiles(ODB_TREE_WRITER &writer) override
std::optional< COMPONENTS_MANAGER > m_compBot
std::optional< ODB_DRILL_TOOLS > m_tools
void GenTools(ODB_TREE_WRITER &writer)
std::map< int, std::vector< BOARD_ITEM * > > m_layerItems
ODB_LAYER_ENTITY(BOARD *aBoard, PCB_IO_ODBPP *aPlugin, std::map< int, std::vector< BOARD_ITEM * > > &aMap, const PCB_LAYER_ID &aLayerID, const wxString &aLayerName)
ODB_COMPONENT & InitComponentData(const FOOTPRINT *aFp, const EDA_DATA::PACKAGE &aPkg)
virtual void InitEntityData() override
void GenAttrList(ODB_TREE_WRITER &writer)
std::unique_ptr< FEATURES_MANAGER > m_featuresMgr
void AddStep(const wxString &aStepName)
void AddCOMPMatrixLayer()
void InitMatrixLayerData()
std::vector< MATRIX_LAYER > m_matrixLayers
void AddMatrixLayerField(MATRIX_LAYER &aMLayer, PCB_LAYER_ID aLayer)
virtual void GenerateFiles(ODB_TREE_WRITER &writer) override
std::map< wxString, unsigned int > m_matrixSteps
void AddDrillMatrixLayer()
virtual void InitEntityData() override
std::map< wxString, wxString > m_info
virtual void GenerateFiles(ODB_TREE_WRITER &writer) override
void Write(std::ostream &aStream)
virtual std::string GetEntityName() override
std::unordered_map< wxString, wxString > m_stephdr
void GenerateProfileFile(ODB_TREE_WRITER &writer)
void GenerateStepHeaderFile(ODB_TREE_WRITER &writer)
void GenerateEdaFiles(ODB_TREE_WRITER &writer)
virtual void InitEntityData() override
void GenerateLayerFiles(ODB_TREE_WRITER &writer)
std::map< wxString, std::shared_ptr< ODB_LAYER_ENTITY > > m_layerEntityMap
std::unique_ptr< FEATURES_MANAGER > m_profile
virtual bool CreateDirectoryTree(ODB_TREE_WRITER &writer) override
void GenerateNetlistsFiles(ODB_TREE_WRITER &writer)
virtual void GenerateFiles(ODB_TREE_WRITER &writer) override
void WriteEquationLine(const std::string &var, int value)
ARRAY_PROXY MakeArrayProxy(const std::string &aStr)
void write_line_enum(const std::string &var, const T &value)
const wxString GetRootPath() const
void CreateEntityDirectory(const wxString &aPareDir, const wxString &aSubDir=wxEmptyString)
ODB_FILE_WRITER CreateFileProxy(const wxString &aFileName)
void SetCurrentPath(const wxString &aDir)
const wxString GetCurrentPath() const
static constexpr PCB_LAYER_ID ALL_LAYERS
! Temporary layer identifier to identify code that is not padstack-aware
std::map< std::pair< PCB_LAYER_ID, ZONE * >, EDA_DATA::SUB_NET_PLANE * > & GetPlaneSubnetMap()
std::map< PCB_TRACK *, EDA_DATA::SUB_NET * > & GetViaTraceSubnetMap()
std::vector< std::pair< PCB_LAYER_ID, wxString > > & GetLayerNameList()
std::map< std::pair< PCB_LAYER_ID, PCB_LAYER_ID >, std::vector< BOARD_ITEM * > > & GetSlotHolesMap()
std::map< const PAD *, EDA_DATA::SUB_NET_TOEPRINT * > & GetPadSubnetMap()
std::map< PCB_LAYER_ID, std::map< int, std::vector< BOARD_ITEM * > > > & GetLayerElementsMap()
static std::string m_unitsStr
std::map< std::pair< PCB_LAYER_ID, PCB_LAYER_ID >, std::vector< BOARD_ITEM * > > & GetDrillLayerItemsMap()
Represent a set of closed polygons.
Handle a list of polygons defining a copper zone.
static constexpr EDA_ANGLE ANGLE_360
size_t hash_fp_item(const EDA_ITEM *aItem, int aFlags)
Calculate hash of an EDA_ITEM.
@ HASH_POS
use coordinates relative to the parent object
@ REL_COORD
use coordinates relative to the shape position
bool IsCopperLayer(int aLayerId)
Tests whether a layer is a copper layer.
PCB_LAYER_ID
A quick note on layer IDs:
bool IsValidLayer(int aLayerId)
Test whether a given integer is a valid layer index, i.e.
std::pair< wxString, wxString > AddXY(const VECTOR2I &aVec)
wxString GenLegalEntityName(const wxString &aStr)
wxString Double2String(double aVal)
wxString SymDouble2String(double aVal)
std::optional< ODB_DIELECTRIC_TYPE > m_diType
std::optional< std::pair< wxString, wxString > > m_span
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
@ PCB_PAD_T
class PAD, a pad in a footprint