24#ifndef DRC_RULE_PROTO_H
25#define DRC_RULE_PROTO_H
125 const wxString& aName = wxEmptyString ) :
185 wxString* aRuleName =
nullptr );
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
DRC_RULE_CONDITION * m_Test
SEVERITY GetSeverity() const
void SetParentRule(DRC_RULE *aParentRule)
MINOPTMAX< int > & Value()
const MINOPTMAX< int > & GetValue() const
ZONE_CONNECTION m_ZoneConnection
void SetName(const wxString &aName)
DRC_RULE * GetParentRule() const
DRC_CONSTRAINT(DRC_CONSTRAINT_T aType=NULL_CONSTRAINT, const wxString &aName=wxEmptyString)
DRC_RULE_CONDITION * m_Condition
virtual bool AppliesTo(const BOARD_ITEM *a, const BOARD_ITEM *b=nullptr) const
std::vector< DRC_CONSTRAINT > m_Constraints
void AddConstraint(DRC_CONSTRAINT &aConstraint)
std::optional< DRC_CONSTRAINT > FindConstraint(DRC_CONSTRAINT_T aType)
LSET is a set of PCB_LAYER_IDs.
const DRC_CONSTRAINT * GetConstraint(const BOARD_ITEM *aItem, const BOARD_ITEM *bItem, int aConstraint, PCB_LAYER_ID aLayer, wxString *aRuleName=nullptr)
@ DRC_DISALLOW_FOOTPRINTS
@ DRC_DISALLOW_MICRO_VIAS
@ ANNULAR_WIDTH_CONSTRAINT
@ COURTYARD_CLEARANCE_CONSTRAINT
@ VIA_DIAMETER_CONSTRAINT
@ ZONE_CONNECTION_CONSTRAINT
@ DIFF_PAIR_MAX_UNCOUPLED_CONSTRAINT
@ DIFF_PAIR_GAP_CONSTRAINT
@ SILK_CLEARANCE_CONSTRAINT
@ EDGE_CLEARANCE_CONSTRAINT
@ MIN_RESOLVED_SPOKES_CONSTRAINT
@ TEXT_THICKNESS_CONSTRAINT
@ PHYSICAL_HOLE_CLEARANCE_CONSTRAINT
@ THERMAL_SPOKE_WIDTH_CONSTRAINT
@ CONNECTION_WIDTH_CONSTRAINT
@ THERMAL_RELIEF_GAP_CONSTRAINT
@ HOLE_CLEARANCE_CONSTRAINT
@ DIFF_PAIR_INTRA_SKEW_CONSTRAINT
@ PHYSICAL_CLEARANCE_CONSTRAINT
@ HOLE_TO_HOLE_CONSTRAINT
PCB_LAYER_ID
A quick note on layer IDs:
void Format(OUTPUTFORMATTER *out, int aNestLevel, int aCtl, const CPTREE &aTree)
Output a PTREE into s-expression format via an OUTPUTFORMATTER derivative.
ZONE_CONNECTION
How pads are covered by copper in zone.