KiCad PCB EDA Suite
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drc_engine.cpp
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1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright (C) 2004-2019 Jean-Pierre Charras, jp.charras at wanadoo.fr
5 * Copyright (C) 2014 Dick Hollenbeck, [email protected]
6 * Copyright The KiCad Developers, see AUTHORS.txt for contributors.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <https://www.gnu.org/licenses/>.
20 */
21
22#include <atomic>
23#include <set>
24#include <wx/log.h>
25#include <reporter.h>
26#include <common.h>
27#include <progress_reporter.h>
28#include <string_utils.h>
29#include <board_design_settings.h>
30#include <project/net_settings.h>
31#include <component_classes/component_class_manager.h>
32#include <drc/drc_engine.h>
33#include <drc/drc_rtree.h>
34#include <drc/drc_rule_parser.h>
35#include <drc/drc_rule.h>
36#include <drc/drc_rule_condition.h>
37#include <drc/drc_test_provider.h>
38#include <drc/drc_item.h>
39#include <drc/drc_cache_generator.h>
40#include <board.h>
41#include <pcb_marker.h>
42#include <footprint.h>
43#include <pad.h>
44#include <pcb_track.h>
45#include <pcb_shape.h>
46#include <core/profile.h>
47#include <thread_pool.h>
48#include <zone.h>
49#include <project/project_file.h>
50#include <project/tuning_profiles.h>
51#include <connectivity/connectivity_data.h>
52#include <connectivity/from_to_cache.h>
53
54
55// wxListBox's performance degrades horrifically with very large datasets. It's not clear
56// they're useful to the user anyway.
57#define ERROR_LIMIT 199
58#define EXTENDED_ERROR_LIMIT 499
59
60
68static const wxChar* traceDrcProfile = wxT( "KICAD_DRC_PROFILE" );
69
70
71void drcPrintDebugMessage( int level, const wxString& msg, const char *function, int line )
72{
73 wxString valueStr;
74
75 if( wxGetEnv( wxT( "DRC_DEBUG" ), &valueStr ) )
76 {
77 int setLevel = wxAtoi( valueStr );
78
79 if( level <= setLevel )
80 printf( "%-30s:%d | %s\n", function, line, (const char *) msg.c_str() );
81 }
82}
83
84
85DRC_ENGINE::DRC_ENGINE( BOARD* aBoard, BOARD_DESIGN_SETTINGS *aSettings ) :
86 UNITS_PROVIDER( pcbIUScale, EDA_UNITS::MM ),
87 m_designSettings ( aSettings ),
88 m_board( aBoard ),
89 m_drawingSheet( nullptr ),
90 m_schematicNetlist( nullptr ),
91 m_rulesValid( false ),
92 m_reportAllTrackErrors( false ),
93 m_testFootprints( false ),
94 m_logReporter( nullptr ),
95 m_progressReporter( nullptr )
96{
97 m_errorLimits.resize( DRCE_LAST + 1 );
98
99 for( int ii = DRCE_FIRST; ii <= DRCE_LAST; ++ii )
100 m_errorLimits[ii] = ERROR_LIMIT;
101}
102
103
104DRC_ENGINE::~DRC_ENGINE()
105{
106 m_rules.clear();
107
108 for( std::pair<DRC_CONSTRAINT_T, std::vector<DRC_ENGINE_CONSTRAINT*>*> pair : m_constraintMap )
109 {
110 for( DRC_ENGINE_CONSTRAINT* constraint : *pair.second )
111 delete constraint;
112
113 delete pair.second;
114 }
115}
116
117
118static bool isKeepoutZone( const BOARD_ITEM* aItem, bool aCheckFlags )
119{
120 if( !aItem || aItem->Type() != PCB_ZONE_T )
121 return false;
122
123 const ZONE* zone = static_cast<const ZONE*>( aItem );
124
125 if( !zone->GetIsRuleArea() )
126 return false;
127
128 if( !zone->HasKeepoutParametersSet() )
129 return false;
130
131 if( aCheckFlags )
132 {
133 if( !zone->GetDoNotAllowTracks()
134 && !zone->GetDoNotAllowVias()
135 && !zone->GetDoNotAllowPads()
136 && !zone->GetDoNotAllowZoneFills()
137 && !zone->GetDoNotAllowFootprints() )
138 {
139 return false;
140 }
141 }
142
143 return true;
144}
145
146
147std::shared_ptr<DRC_RULE> DRC_ENGINE::createImplicitRule( const wxString& name,
148 const DRC_IMPLICIT_SOURCE aImplicitSource )
149{
150 std::shared_ptr<DRC_RULE> rule = std::make_shared<DRC_RULE>();
151
152 rule->m_Name = name;
153 rule->SetImplicitSource( aImplicitSource );
154
155 addRule( rule );
156
157 return rule;
158}
159
160
161void DRC_ENGINE::loadImplicitRules()
162{
163 BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
164 wxString expr, expr2, ncName;
165
166 // 1) global defaults
167
168 std::shared_ptr<DRC_RULE> rule = createImplicitRule( _( "board setup constraints" ),
169 DRC_IMPLICIT_SOURCE::BOARD_SETUP_CONSTRAINT );
170
171 DRC_CONSTRAINT widthConstraint( TRACK_WIDTH_CONSTRAINT );
172 widthConstraint.Value().SetMin( bds.m_TrackMinWidth );
173 rule->AddConstraint( widthConstraint );
174
175 DRC_CONSTRAINT connectionConstraint( CONNECTION_WIDTH_CONSTRAINT );
176 connectionConstraint.Value().SetMin( bds.m_MinConn );
177 rule->AddConstraint( connectionConstraint );
178
179 DRC_CONSTRAINT drillConstraint( HOLE_SIZE_CONSTRAINT );
180 drillConstraint.Value().SetMin( bds.m_MinThroughDrill );
181 rule->AddConstraint( drillConstraint );
182
183 DRC_CONSTRAINT annulusConstraint( ANNULAR_WIDTH_CONSTRAINT );
184 annulusConstraint.Value().SetMin( bds.m_ViasMinAnnularWidth );
185 rule->AddConstraint( annulusConstraint );
186
187 DRC_CONSTRAINT diameterConstraint( VIA_DIAMETER_CONSTRAINT );
188 diameterConstraint.Value().SetMin( bds.m_ViasMinSize );
189 rule->AddConstraint( diameterConstraint );
190
191 DRC_CONSTRAINT holeToHoleConstraint( HOLE_TO_HOLE_CONSTRAINT );
192 holeToHoleConstraint.Value().SetMin( bds.m_HoleToHoleMin );
193 rule->AddConstraint( holeToHoleConstraint );
194
195 rule = createImplicitRule( _( "board setup constraints zone fill strategy" ),
196 DRC_IMPLICIT_SOURCE::BOARD_SETUP_CONSTRAINT );
197 DRC_CONSTRAINT thermalSpokeCountConstraint( MIN_RESOLVED_SPOKES_CONSTRAINT );
198 thermalSpokeCountConstraint.Value().SetMin( bds.m_MinResolvedSpokes );
199 rule->AddConstraint( thermalSpokeCountConstraint );
200
201 rule = createImplicitRule( _( "board setup constraints silk" ), DRC_IMPLICIT_SOURCE::BOARD_SETUP_CONSTRAINT );
202 rule->m_LayerCondition = LSET( { F_SilkS, B_SilkS } );
203 DRC_CONSTRAINT silkClearanceConstraint( SILK_CLEARANCE_CONSTRAINT );
204 silkClearanceConstraint.Value().SetMin( bds.m_SilkClearance );
205 rule->AddConstraint( silkClearanceConstraint );
206
207 rule = createImplicitRule( _( "board setup constraints silk text height" ),
208 DRC_IMPLICIT_SOURCE::BOARD_SETUP_CONSTRAINT );
209 rule->m_LayerCondition = LSET( { F_SilkS, B_SilkS } );
210 DRC_CONSTRAINT silkTextHeightConstraint( TEXT_HEIGHT_CONSTRAINT );
211 silkTextHeightConstraint.Value().SetMin( bds.m_MinSilkTextHeight );
212 rule->AddConstraint( silkTextHeightConstraint );
213
214 rule = createImplicitRule( _( "board setup constraints silk text thickness" ),
215 DRC_IMPLICIT_SOURCE::BOARD_SETUP_CONSTRAINT );
216 rule->m_LayerCondition = LSET( { F_SilkS, B_SilkS } );
217 DRC_CONSTRAINT silkTextThicknessConstraint( TEXT_THICKNESS_CONSTRAINT );
218 silkTextThicknessConstraint.Value().SetMin( bds.m_MinSilkTextThickness );
219 rule->AddConstraint( silkTextThicknessConstraint );
220
221 rule = createImplicitRule( _( "board setup constraints hole" ), DRC_IMPLICIT_SOURCE::BOARD_SETUP_CONSTRAINT );
222 DRC_CONSTRAINT holeClearanceConstraint( HOLE_CLEARANCE_CONSTRAINT );
223 holeClearanceConstraint.Value().SetMin( bds.m_HoleClearance );
224 rule->AddConstraint( holeClearanceConstraint );
225
226 rule = createImplicitRule( _( "board setup constraints edge" ), DRC_IMPLICIT_SOURCE::BOARD_SETUP_CONSTRAINT );
227 DRC_CONSTRAINT edgeClearanceConstraint( EDGE_CLEARANCE_CONSTRAINT );
228 edgeClearanceConstraint.Value().SetMin( bds.m_CopperEdgeClearance );
229 rule->AddConstraint( edgeClearanceConstraint );
230
231 rule = createImplicitRule( _( "board setup constraints courtyard" ), DRC_IMPLICIT_SOURCE::BOARD_SETUP_CONSTRAINT );
232 DRC_CONSTRAINT courtyardClearanceConstraint( COURTYARD_CLEARANCE_CONSTRAINT );
233 holeToHoleConstraint.Value().SetMin( 0 );
234 rule->AddConstraint( courtyardClearanceConstraint );
235
236 // 2a) micro-via specific defaults (new DRC doesn't treat microvias in any special way)
237
238 std::shared_ptr<DRC_RULE> uViaRule = createImplicitRule( _( "board setup constraints micro-via" ),
239 DRC_IMPLICIT_SOURCE::BOARD_SETUP_CONSTRAINT );
240
241 uViaRule->m_Condition = new DRC_RULE_CONDITION( wxT( "A.Via_Type == 'Micro'" ) );
242
243 DRC_CONSTRAINT uViaDrillConstraint( HOLE_SIZE_CONSTRAINT );
244 uViaDrillConstraint.Value().SetMin( bds.m_MicroViasMinDrill );
245 uViaRule->AddConstraint( uViaDrillConstraint );
246
247 DRC_CONSTRAINT uViaDiameterConstraint( VIA_DIAMETER_CONSTRAINT );
248 uViaDiameterConstraint.Value().SetMin( bds.m_MicroViasMinSize );
249 uViaRule->AddConstraint( uViaDiameterConstraint );
250
251 // 2b) barcode-specific defaults
252
253 std::shared_ptr<DRC_RULE> barcodeRule = createImplicitRule( _( "barcode visual separation default" ),
254 DRC_IMPLICIT_SOURCE::BARCODE_DEFAULTS );
255 DRC_CONSTRAINT barcodeSeparationConstraint( PHYSICAL_CLEARANCE_CONSTRAINT );
256 barcodeSeparationConstraint.Value().SetMin( GetIuScale().mmToIU( 1.0 ) );
257 barcodeRule->AddConstraint( barcodeSeparationConstraint );
258 barcodeRule->m_Condition = new DRC_RULE_CONDITION( wxT( "A.Type == 'Barcode'" ) );
259
260 // 3) per-netclass rules
261
262 std::vector<std::shared_ptr<DRC_RULE>> netclassClearanceRules;
263 std::vector<std::shared_ptr<DRC_RULE>> netclassItemSpecificRules;
264
265 auto makeNetclassRules =
266 [&]( const std::shared_ptr<NETCLASS>& nc, bool isDefault )
267 {
268 ncName = nc->GetName();
269 ncName.Replace( "'", "\\'" );
270
271 if( nc->HasClearance() )
272 {
273 std::shared_ptr<DRC_RULE> netclassRule = std::make_shared<DRC_RULE>();
274 netclassRule->m_Name = wxString::Format( _( "netclass '%s'" ),
275 nc->GetClearanceParent()->GetHumanReadableName() );
276 netclassRule->SetImplicitSource( DRC_IMPLICIT_SOURCE::NET_CLASS );
277
278 expr = wxString::Format( wxT( "A.hasExactNetclass('%s')" ), ncName );
279 netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
280 netclassClearanceRules.push_back( netclassRule );
281
282 DRC_CONSTRAINT constraint( CLEARANCE_CONSTRAINT );
283 constraint.Value().SetMin( nc->GetClearance() );
284 netclassRule->AddConstraint( constraint );
285
286 {
287 std::unique_lock<std::shared_mutex> writeLock( m_clearanceCacheMutex );
288 m_netclassClearances[nc->GetName()] = nc->GetClearance();
289 }
290 }
291
292 if( nc->HasTrackWidth() )
293 {
294 std::shared_ptr<DRC_RULE> netclassRule = std::make_shared<DRC_RULE>();
295 netclassRule->m_Name = wxString::Format( _( "netclass '%s'" ),
296 nc->GetTrackWidthParent()->GetHumanReadableName() );
297 netclassRule->SetImplicitSource( DRC_IMPLICIT_SOURCE::NET_CLASS );
298
299 expr = wxString::Format( wxT( "A.hasExactNetclass('%s')" ), ncName );
300 netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
301 netclassClearanceRules.push_back( netclassRule );
302
303 DRC_CONSTRAINT constraint( TRACK_WIDTH_CONSTRAINT );
304 constraint.Value().SetMin( bds.m_TrackMinWidth );
305 constraint.Value().SetOpt( nc->GetTrackWidth() );
306 netclassRule->AddConstraint( constraint );
307 }
308
309 if( nc->HasDiffPairWidth() )
310 {
311 std::shared_ptr<DRC_RULE> netclassRule = std::make_shared<DRC_RULE>();
312 netclassRule->m_Name = wxString::Format( _( "netclass '%s' diff pair" ),
313 nc->GetDiffPairWidthParent()->GetHumanReadableName() );
314 netclassRule->SetImplicitSource( DRC_IMPLICIT_SOURCE::NET_CLASS );
315
316 expr = wxString::Format( wxT( "A.hasExactNetclass('%s') && A.inDiffPair('*')" ), ncName );
317 netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
318 netclassItemSpecificRules.push_back( netclassRule );
319
320 DRC_CONSTRAINT constraint( TRACK_WIDTH_CONSTRAINT );
321 constraint.Value().SetMin( bds.m_TrackMinWidth );
322 constraint.Value().SetOpt( nc->GetDiffPairWidth() );
323 netclassRule->AddConstraint( constraint );
324 }
325
326 if( nc->HasDiffPairGap() )
327 {
328 std::shared_ptr<DRC_RULE> netclassRule = std::make_shared<DRC_RULE>();
329 netclassRule->m_Name = wxString::Format( _( "netclass '%s'" ),
330 nc->GetDiffPairGapParent()->GetHumanReadableName() );
331 netclassRule->SetImplicitSource( DRC_IMPLICIT_SOURCE::NET_CLASS );
332
333 expr = wxString::Format( wxT( "A.hasExactNetclass('%s')" ), ncName );
334 netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
335 netclassItemSpecificRules.push_back( netclassRule );
336
337 DRC_CONSTRAINT constraint( DIFF_PAIR_GAP_CONSTRAINT );
338 constraint.Value().SetMin( bds.m_MinClearance );
339 constraint.Value().SetOpt( nc->GetDiffPairGap() );
340 netclassRule->AddConstraint( constraint );
341
342 // A narrower diffpair gap overrides the netclass min clearance
343 if( nc->GetDiffPairGap() < nc->GetClearance() )
344 {
345 netclassRule = std::make_shared<DRC_RULE>();
346 netclassRule->m_Name = wxString::Format( _( "netclass '%s' diff pair" ),
347 nc->GetDiffPairGapParent()->GetHumanReadableName() );
348 netclassRule->SetImplicitSource( DRC_IMPLICIT_SOURCE::NET_CLASS );
349
350 expr = wxString::Format( wxT( "A.hasExactNetclass('%s') && AB.isCoupledDiffPair()" ), ncName );
351 netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
352 netclassItemSpecificRules.push_back( netclassRule );
353
354 DRC_CONSTRAINT min_clearanceConstraint( CLEARANCE_CONSTRAINT );
355 min_clearanceConstraint.Value().SetMin( nc->GetDiffPairGap() );
356 netclassRule->AddConstraint( min_clearanceConstraint );
357
358 m_hasDiffPairClearanceOverrides = true;
359 }
360 }
361
362 if( nc->HasViaDiameter() )
363 {
364 std::shared_ptr<DRC_RULE> netclassRule = std::make_shared<DRC_RULE>();
365 netclassRule->m_Name = wxString::Format( _( "netclass '%s'" ),
366 nc->GetViaDiameterParent()->GetHumanReadableName() );
367 netclassRule->SetImplicitSource( DRC_IMPLICIT_SOURCE::NET_CLASS );
368
369 expr = wxString::Format( wxT( "A.hasExactNetclass('%s') && A.Via_Type != 'Micro'" ), ncName );
370 netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
371 netclassItemSpecificRules.push_back( netclassRule );
372
373 DRC_CONSTRAINT constraint( VIA_DIAMETER_CONSTRAINT );
374 constraint.Value().SetMin( bds.m_ViasMinSize );
375 constraint.Value().SetOpt( nc->GetViaDiameter() );
376 netclassRule->AddConstraint( constraint );
377 }
378
379 if( nc->HasViaDrill() )
380 {
381 std::shared_ptr<DRC_RULE> netclassRule = std::make_shared<DRC_RULE>();
382 netclassRule->m_Name = wxString::Format( _( "netclass '%s'" ),
383 nc->GetViaDrillParent()->GetHumanReadableName() );
384 netclassRule->SetImplicitSource( DRC_IMPLICIT_SOURCE::NET_CLASS );
385
386 expr = wxString::Format( wxT( "A.hasExactNetclass('%s') && A.Via_Type != 'Micro'" ), ncName );
387 netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
388 netclassItemSpecificRules.push_back( netclassRule );
389
390 DRC_CONSTRAINT constraint( HOLE_SIZE_CONSTRAINT );
391 constraint.Value().SetMin( bds.m_MinThroughDrill );
392 constraint.Value().SetOpt( nc->GetViaDrill() );
393 netclassRule->AddConstraint( constraint );
394 }
395
396 if( nc->HasuViaDiameter() )
397 {
398 std::shared_ptr<DRC_RULE> netclassRule = std::make_shared<DRC_RULE>();
399 netclassRule->m_Name = wxString::Format( _( "netclass '%s' uvia" ),
400 nc->GetuViaDiameterParent()->GetHumanReadableName() );
401 netclassRule->SetImplicitSource( DRC_IMPLICIT_SOURCE::NET_CLASS );
402
403 expr = wxString::Format( wxT( "A.hasExactNetclass('%s') && A.Via_Type == 'Micro'" ), ncName );
404 netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
405 netclassItemSpecificRules.push_back( netclassRule );
406
407 DRC_CONSTRAINT constraint( VIA_DIAMETER_CONSTRAINT );
408 constraint.Value().SetMin( bds.m_MicroViasMinSize );
409 constraint.Value().SetMin( nc->GetuViaDiameter() );
410 netclassRule->AddConstraint( constraint );
411 }
412
413 if( nc->HasuViaDrill() )
414 {
415 std::shared_ptr<DRC_RULE> netclassRule = std::make_shared<DRC_RULE>();
416 netclassRule->m_Name = wxString::Format( _( "netclass '%s' uvia" ),
417 nc->GetuViaDrillParent()->GetHumanReadableName() );
418 netclassRule->SetImplicitSource( DRC_IMPLICIT_SOURCE::NET_CLASS );
419
420 expr = wxString::Format( wxT( "A.hasExactNetclass('%s') && A.Via_Type == 'Micro'" ), ncName );
421 netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
422 netclassItemSpecificRules.push_back( netclassRule );
423
424 DRC_CONSTRAINT constraint( HOLE_SIZE_CONSTRAINT );
425 constraint.Value().SetMin( bds.m_MicroViasMinDrill );
426 constraint.Value().SetOpt( nc->GetuViaDrill() );
427 netclassRule->AddConstraint( constraint );
428 }
429 };
430
431 m_board->SynchronizeNetsAndNetClasses( false );
432 makeNetclassRules( bds.m_NetSettings->GetDefaultNetclass(), true );
433
434 for( const auto& [name, netclass] : bds.m_NetSettings->GetNetclasses() )
435 makeNetclassRules( netclass, false );
436
437 for( const auto& [name, netclass] : bds.m_NetSettings->GetCompositeNetclasses() )
438 makeNetclassRules( netclass, false );
439
440 // The netclass clearance rules have to be sorted by min clearance so the right one fires
441 // if 'A' and 'B' belong to two different netclasses.
442 //
443 // The item-specific netclass rules are all unary, so there's no 'A' vs 'B' issue.
444
445 std::sort( netclassClearanceRules.begin(), netclassClearanceRules.end(),
446 []( const std::shared_ptr<DRC_RULE>& lhs, const std::shared_ptr<DRC_RULE>& rhs )
447 {
448 return lhs->m_Constraints[0].m_Value.Min() < rhs->m_Constraints[0].m_Value.Min();
449 } );
450
451 for( std::shared_ptr<DRC_RULE>& ncRule : netclassClearanceRules )
452 addRule( ncRule );
453
454 for( std::shared_ptr<DRC_RULE>& ncRule : netclassItemSpecificRules )
455 addRule( ncRule );
456
457 // 4) tuning profile rules
458 auto addTuningSingleRule =
459 [&]( const DELAY_PROFILE_TRACK_PROPAGATION_ENTRY& aLayerEntry, const wxString& aProfileName,
460 const wxString& aNetclassName )
461 {
462 if( aLayerEntry.GetWidth() <= 0 )
463 return;
464
465 std::shared_ptr<DRC_RULE> tuningRule = std::make_shared<DRC_RULE>();
466 tuningRule->m_Severity = bds.m_DRCSeverities[DRCE_TUNING_PROFILE_IMPLICIT_RULES];
467 tuningRule->m_Name = wxString::Format( _( "tuning profile '%s'" ), aProfileName );
468 tuningRule->SetImplicitSource( DRC_IMPLICIT_SOURCE::TUNING_PROFILE );
469
470 expr = wxString::Format( wxT( "A.hasExactNetclass('%s') && A.Layer == '%s'" ),
471 aNetclassName,
472 LSET::Name( aLayerEntry.GetSignalLayer() ) );
473 tuningRule->m_Condition = new DRC_RULE_CONDITION( expr );
474
475 DRC_CONSTRAINT constraint( TRACK_WIDTH_CONSTRAINT );
476 constraint.Value().SetMin( std::max( bds.m_TrackMinWidth, aLayerEntry.GetWidth() ) );
477 constraint.Value().SetOpt( aLayerEntry.GetWidth() );
478 constraint.Value().SetMax( aLayerEntry.GetWidth() );
479 tuningRule->AddConstraint( constraint );
480
481 addRule( tuningRule );
482 };
483
484 auto addTuningDifferentialRules =
485 [&]( const DELAY_PROFILE_TRACK_PROPAGATION_ENTRY& aLayerEntry, const wxString& aProfileName,
486 const NETCLASS* aNetclass )
487 {
488 if( aLayerEntry.GetWidth() <= 0 || aLayerEntry.GetDiffPairGap() <= 0 )
489 return;
490
491 std::shared_ptr<DRC_RULE> tuningRule = std::make_shared<DRC_RULE>();
492 tuningRule->m_Severity = bds.m_DRCSeverities[DRCE_TUNING_PROFILE_IMPLICIT_RULES];
493 tuningRule->m_Name = wxString::Format( _( "tuning profile '%s'" ), aProfileName );
494 tuningRule->SetImplicitSource( DRC_IMPLICIT_SOURCE::TUNING_PROFILE );
495
496 expr = wxString::Format( wxT( "A.hasExactNetclass('%s') && A.Layer == '%s' && A.inDiffPair('*')" ),
497 aNetclass->GetName(),
498 LSET::Name( aLayerEntry.GetSignalLayer() ) );
499 tuningRule->m_Condition = new DRC_RULE_CONDITION( expr );
500
501 DRC_CONSTRAINT constraint( TRACK_WIDTH_CONSTRAINT );
502 constraint.Value().SetMin( std::max( bds.m_TrackMinWidth, aLayerEntry.GetWidth() ) );
503 constraint.Value().SetOpt( aLayerEntry.GetWidth() );
504 constraint.Value().SetMax( aLayerEntry.GetWidth() );
505 tuningRule->AddConstraint( constraint );
506
507 addRule( tuningRule );
508
509 std::shared_ptr<DRC_RULE> tuningRule2 = std::make_shared<DRC_RULE>();
510 tuningRule2->m_Severity = bds.m_DRCSeverities[DRCE_TUNING_PROFILE_IMPLICIT_RULES];
511 tuningRule2->m_Name = wxString::Format( _( "tuning profile '%s'" ), aProfileName );
512 tuningRule2->SetImplicitSource( DRC_IMPLICIT_SOURCE::TUNING_PROFILE );
513
514 expr2 = wxString::Format( wxT( "A.hasExactNetclass('%s') && A.Layer == '%s' && A.inDiffPair('*')" ),
515 aNetclass->GetName(),
516 LSET::Name( aLayerEntry.GetSignalLayer() ) );
517 tuningRule2->m_Condition = new DRC_RULE_CONDITION( expr2 );
518
519 DRC_CONSTRAINT constraint2( DIFF_PAIR_GAP_CONSTRAINT );
520 constraint2.Value().SetMin( std::max( bds.m_MinClearance, aLayerEntry.GetDiffPairGap() ) );
521 constraint2.Value().SetOpt( aLayerEntry.GetDiffPairGap() );
522 constraint2.Value().SetMax( aLayerEntry.GetDiffPairGap() );
523 tuningRule2->AddConstraint( constraint2 );
524
525 addRule( tuningRule2 );
526
527 // A narrower diffpair gap overrides the netclass min clearance
528 if( aLayerEntry.GetDiffPairGap() < aNetclass->GetClearance() )
529 {
530 std::shared_ptr<DRC_RULE> diffPairClearanceRule = std::make_shared<DRC_RULE>();
531 diffPairClearanceRule->m_Severity = bds.m_DRCSeverities[DRCE_TUNING_PROFILE_IMPLICIT_RULES];
532 diffPairClearanceRule->m_Name = wxString::Format( _( "tuning profile '%s'" ), aProfileName );
533 diffPairClearanceRule->SetImplicitSource( DRC_IMPLICIT_SOURCE::TUNING_PROFILE );
534
535 expr = wxString::Format(
536 wxT( "A.hasExactNetclass('%s') && A.Layer == '%s' && AB.isCoupledDiffPair()" ),
537 aNetclass->GetName(), LSET::Name( aLayerEntry.GetSignalLayer() ) );
538 diffPairClearanceRule->m_Condition = new DRC_RULE_CONDITION( expr );
539
540 DRC_CONSTRAINT min_clearanceConstraint( CLEARANCE_CONSTRAINT );
541 min_clearanceConstraint.Value().SetMin( aLayerEntry.GetDiffPairGap() );
542 diffPairClearanceRule->AddConstraint( min_clearanceConstraint );
543
544 addRule( diffPairClearanceRule );
545 }
546 };
547
548 if( PROJECT* project = m_board->GetProject() )
549 {
550 std::shared_ptr<TUNING_PROFILES> tuningParams = project->GetProjectFile().TuningProfileParameters();
551
552 auto addNetclassTuningProfileRules =
553 [&tuningParams, &addTuningSingleRule, &addTuningDifferentialRules]( NETCLASS* aNetclass )
554 {
555 if( aNetclass->HasTuningProfile() )
556 {
557 const wxString delayProfileName = aNetclass->GetTuningProfile();
558 const TUNING_PROFILE& profile = tuningParams->GetTuningProfile( delayProfileName );
559
560 for( const DELAY_PROFILE_TRACK_PROPAGATION_ENTRY& entry : profile.m_TrackPropagationEntries )
561 {
562 if( entry.GetWidth() <= 0 )
563 continue;
564
565 if( profile.m_Type == TUNING_PROFILE::PROFILE_TYPE::SINGLE )
566 addTuningSingleRule( entry, delayProfileName, aNetclass->GetName() );
567 else
568 addTuningDifferentialRules( entry, delayProfileName, aNetclass );
569 }
570 }
571 };
572
573 addNetclassTuningProfileRules( bds.m_NetSettings->GetDefaultNetclass().get() );
574
575 for( const auto& [netclassName, netclass] : bds.m_NetSettings->GetNetclasses() )
576 addNetclassTuningProfileRules( netclass.get() );
577
578 for( const auto& [netclassName, netclass] : bds.m_NetSettings->GetCompositeNetclasses() )
579 addNetclassTuningProfileRules( netclass.get() );
580 }
581
582 // 5) keepout area rules
583 auto addKeepoutZoneRule =
584 [&]( ZONE* zone, FOOTPRINT* parentFP )
585 {
586 const wxString& name = zone->GetZoneName();
587
588 if( name.IsEmpty() )
589 {
590 if( parentFP )
591 {
592 rule = createImplicitRule(
593 wxString::Format( _( "keepout area of %s" ), DescribeRef( parentFP->GetReference() ) ),
594 DRC_IMPLICIT_SOURCE::KEEPOUT );
595 }
596 else
597 {
598 rule = createImplicitRule( _( "keepout area" ), DRC_IMPLICIT_SOURCE::KEEPOUT );
599 }
600
601 }
602 else
603 {
604 if( parentFP )
605 {
606 rule = createImplicitRule( wxString::Format( _( "keepout area '%s' of %s" ), name,
607 DescribeRef( parentFP->GetReference() ) ),
608 DRC_IMPLICIT_SOURCE::KEEPOUT );
609 }
610 else
611 {
612 rule = createImplicitRule( wxString::Format( _( "keepout area '%s'" ), name ),
613 DRC_IMPLICIT_SOURCE::KEEPOUT );
614 }
615 }
616
617 rule->m_ImplicitItemId = zone->m_Uuid;
618 rule->m_ImplicitItem = zone;
619
620 rule->m_Condition = new DRC_RULE_CONDITION( wxString::Format( wxT( "A.intersectsArea('%s')" ),
621 zone->m_Uuid.AsString() ) );
622
623 rule->m_LayerCondition = zone->GetLayerSet();
624
625 int disallowFlags = 0;
626
627 if( zone->GetDoNotAllowTracks() )
628 disallowFlags |= DRC_DISALLOW_TRACKS;
629
630 if( zone->GetDoNotAllowVias() )
631 disallowFlags |= DRC_DISALLOW_VIAS;
632
633 if( zone->GetDoNotAllowPads() )
634 disallowFlags |= DRC_DISALLOW_PADS;
635
636 if( zone->GetDoNotAllowZoneFills() )
637 disallowFlags |= DRC_DISALLOW_ZONES;
638
639 if( zone->GetDoNotAllowFootprints() )
640 disallowFlags |= DRC_DISALLOW_FOOTPRINTS;
641
642 DRC_CONSTRAINT disallowConstraint( DISALLOW_CONSTRAINT );
643 disallowConstraint.m_DisallowFlags = disallowFlags;
644 rule->AddConstraint( disallowConstraint );
645 };
646
647 for( ZONE* zone : m_board->Zones() )
648 {
649 if( isKeepoutZone( zone, true ) )
650 addKeepoutZoneRule( zone, nullptr );
651 }
652
653 for( FOOTPRINT* footprint : m_board->Footprints() )
654 {
655 for( ZONE* zone : footprint->Zones() )
656 {
657 if( isKeepoutZone( zone, true ) )
658 addKeepoutZoneRule( zone, footprint );
659 }
660 }
661}
662
663
664void DRC_ENGINE::loadRules( const wxFileName& aPath )
665{
666 if( m_board && aPath.FileExists() )
667 {
668 std::vector<std::shared_ptr<DRC_RULE>> rules;
669
670 if( FILE* fp = wxFopen( aPath.GetFullPath(), wxT( "rt" ) ) )
671 {
672 FILE_LINE_READER lineReader( fp, aPath.GetFullPath() ); // Will close rules file
673 wxString rulesText;
674
675 std::function<bool( wxString* )> resolver =
676 [&]( wxString* token ) -> bool
677 {
678 if( IsComponentClassSelector( *token ) )
679 return false;
680
681 return m_board->ResolveTextVar( token, 0 );
682 };
683
684 while( char* line = lineReader.ReadLine() )
685 {
686 wxString str( line );
687 str = m_board->ConvertCrossReferencesToKIIDs( str );
688 str = ExpandTextVars( str, &resolver );
689
690 rulesText << str << '\n';
691 }
692
693 DRC_RULES_PARSER parser( rulesText, aPath.GetFullPath() );
694 parser.Parse( rules, m_logReporter );
695 }
696
697 // Copy the rules into the member variable afterwards so that if Parse() throws then
698 // the possibly malformed rules won't contaminate the current ruleset.
699
700 for( std::shared_ptr<DRC_RULE>& rule : rules )
701 m_rules.push_back( rule );
702 }
703}
704
705
706void DRC_ENGINE::compileRules()
707{
708 if( m_logReporter )
709 m_logReporter->Report( wxT( "Compiling Rules" ) );
710
711 REPORTER error_semaphore;
712
713 for( std::shared_ptr<DRC_RULE>& rule : m_rules )
714 {
715 DRC_RULE_CONDITION* condition = nullptr;
716
717 if( rule->m_Condition && !rule->m_Condition->GetExpression().IsEmpty() )
718 {
719 condition = rule->m_Condition;
720 condition->Compile( &error_semaphore );
721 }
722
723 if( error_semaphore.HasMessageOfSeverity( RPT_SEVERITY_ERROR ) )
724 THROW_PARSE_ERROR( wxT( "Parse error" ), rule->m_Name, TO_UTF8( rule->m_Condition->GetExpression() ), 0, 0 );
725
726 for( const DRC_CONSTRAINT& constraint : rule->m_Constraints )
727 {
728 auto& ruleVec = m_constraintMap[ constraint.m_Type ];
729
730 if( !ruleVec )
731 ruleVec = new std::vector<DRC_ENGINE_CONSTRAINT*>();
732
733 DRC_ENGINE_CONSTRAINT* engineConstraint = new DRC_ENGINE_CONSTRAINT;
734
735 engineConstraint->layerTest = rule->m_LayerCondition;
736 engineConstraint->condition = condition;
737 engineConstraint->constraint = constraint;
738 engineConstraint->parentRule = rule;
739
740 if( rule->IsImplicit() && constraint.m_Type == DISALLOW_CONSTRAINT
741 && rule->m_ImplicitItem && rule->m_ImplicitItem->Type() == PCB_ZONE_T )
742 {
743 // Duplicate zone UUIDs make an item-by-id lookup return the wrong same-UUID
744 // zone and defeat self-exclusion, so use the rule's own zone pointer
745 engineConstraint->implicitKeepoutZone = static_cast<ZONE*>( rule->m_ImplicitItem );
746 }
747
748 ruleVec->push_back( engineConstraint );
749 }
750 }
751
752 m_hasExplicitClearanceRules = false;
753 m_hasGeometryDependentRules = false;
754 m_explicitConstraints.clear();
755
756 for( auto& [constraintType, ruleList] : m_constraintMap )
757 {
758 for( DRC_ENGINE_CONSTRAINT* c : *ruleList )
759 {
760 if( c->parentRule && !c->parentRule->IsImplicit() )
761 {
762 m_explicitConstraints[constraintType].push_back( c );
763
764 if( constraintType == CLEARANCE_CONSTRAINT )
765 m_hasExplicitClearanceRules = true;
766
767 if( !m_hasGeometryDependentRules
768 && c->condition
769 && c->condition->HasGeometryDependentFunctions() )
770 {
771 m_hasGeometryDependentRules = true;
772 }
773 }
774 }
775 }
776}
777
778
779void DRC_ENGINE::InitEngine( const std::shared_ptr<DRC_RULE>& rule )
780{
781 m_testProviders = DRC_SHOWMATCHES_PROVIDER_REGISTRY::Instance().GetShowMatchesProviders();
782
783 for( DRC_TEST_PROVIDER* provider : m_testProviders )
784 {
785 if( m_logReporter )
786 m_logReporter->Report( wxString::Format( wxT( "Create DRC provider: '%s'" ), provider->GetName() ) );
787
788 provider->SetDRCEngine( this );
789 }
790
791 // Existing markers may hold raw pointers to DRC_RULEs we're about to destroy.
792 // Null them out so GetSeverity() falls back to the board design settings.
793 if( m_board )
794 {
795 for( PCB_MARKER* marker : m_board->Markers() )
796 {
797 DRC_ITEM* drcItem = static_cast<DRC_ITEM*>( marker->GetRCItem().get() );
798 drcItem->SetViolatingRule( nullptr );
799 }
800 }
801
802 m_rules.clear();
803 m_rulesValid = false;
804
805 for( std::pair<DRC_CONSTRAINT_T, std::vector<DRC_ENGINE_CONSTRAINT*>*> pair : m_constraintMap )
806 {
807 for( DRC_ENGINE_CONSTRAINT* constraint : *pair.second )
808 delete constraint;
809
810 delete pair.second;
811 }
812
813 m_constraintMap.clear();
814
815 m_board->IncrementTimeStamp(); // Clear board-level caches
816
817 try
818 {
819 m_rules.push_back( rule );
820 compileRules();
821 }
822 catch( PARSE_ERROR& original_parse_error )
823 {
824 throw original_parse_error;
825 }
826
827 for( int ii = DRCE_FIRST; ii <= DRCE_LAST; ++ii )
828 m_errorLimits[ii] = ERROR_LIMIT;
829
830 m_rulesValid = true;
831}
832
833
834void DRC_ENGINE::InitEngine( const wxFileName& aRulePath )
835{
836 m_testProviders = DRC_TEST_PROVIDER_REGISTRY::Instance().GetTestProviders();
837
838 for( DRC_TEST_PROVIDER* provider : m_testProviders )
839 {
840 if( m_logReporter )
841 m_logReporter->Report( wxString::Format( wxT( "Create DRC provider: '%s'" ), provider->GetName() ) );
842
843 provider->SetDRCEngine( this );
844 }
845
846 // Existing markers may hold raw pointers to DRC_RULEs we're about to destroy.
847 // Null them out so GetSeverity() falls back to the board design settings.
848 if( m_board )
849 {
850 for( PCB_MARKER* marker : m_board->Markers() )
851 {
852 DRC_ITEM* drcItem = static_cast<DRC_ITEM*>( marker->GetRCItem().get() );
853 drcItem->SetViolatingRule( nullptr );
854 }
855 }
856
857 m_rules.clear();
858 m_rulesValid = false;
859
860 for( std::pair<DRC_CONSTRAINT_T, std::vector<DRC_ENGINE_CONSTRAINT*>*> pair : m_constraintMap )
861 {
862 for( DRC_ENGINE_CONSTRAINT* constraint : *pair.second )
863 delete constraint;
864
865 delete pair.second;
866 }
867
868 m_constraintMap.clear();
869
870 {
871 std::unique_lock<std::shared_mutex> writeLock( m_clearanceCacheMutex );
872 m_ownClearanceCache.clear();
873 m_netclassClearances.clear();
874 }
875
876 m_hasExplicitClearanceRules = false;
877 m_hasDiffPairClearanceOverrides = false;
878 m_explicitConstraints.clear();
879
880 m_board->IncrementTimeStamp(); // Clear board-level caches
881
882 try // attempt to load full set of rules (implicit + user rules)
883 {
884 loadImplicitRules();
885 loadRules( aRulePath );
886 compileRules();
887 }
888 catch( PARSE_ERROR& original_parse_error )
889 {
890 m_rules.clear();
891
892 try // try again with just our implicit rules
893 {
894 loadImplicitRules();
895 compileRules();
896 }
897 catch( PARSE_ERROR& )
898 {
899 wxFAIL_MSG( wxT( "Compiling implicit rules failed." ) );
900 }
901
902 throw original_parse_error;
903 }
904
905 for( int ii = DRCE_FIRST; ii <= DRCE_LAST; ++ii )
906 m_errorLimits[ ii ] = ERROR_LIMIT;
907
908 m_rulesValid = true;
909}
910
911
912void DRC_ENGINE::RunTests( EDA_UNITS aUnits, bool aReportAllTrackErrors, bool aTestFootprints,
913 BOARD_COMMIT* aCommit )
914{
915 PROF_TIMER timer;
916
917 SetUserUnits( aUnits );
918
919 m_reportAllTrackErrors = aReportAllTrackErrors;
920 m_testFootprints = aTestFootprints;
921
922 for( int ii = DRCE_FIRST; ii <= DRCE_LAST; ++ii )
923 {
924 if( m_designSettings->Ignore( ii ) )
925 m_errorLimits[ ii ] = 0;
926 else if( ii == DRCE_CLEARANCE || ii == DRCE_UNCONNECTED_ITEMS )
927 m_errorLimits[ ii ] = EXTENDED_ERROR_LIMIT;
928 else
929 m_errorLimits[ ii ] = ERROR_LIMIT;
930 }
931
932 DRC_TEST_PROVIDER::Init();
933
934 m_board->IncrementTimeStamp(); // Invalidate all caches...
935
936 DRC_CACHE_GENERATOR cacheGenerator;
937 cacheGenerator.SetDRCEngine( this );
938
939 if( !cacheGenerator.Run() ) // ... and regenerate them.
940 return;
941
942 // Recompute component classes
943 m_board->GetComponentClassManager().ForceComponentClassRecalculation();
944
945 int timestamp = m_board->GetTimeStamp();
946
947 for( DRC_TEST_PROVIDER* provider : m_testProviders )
948 {
949 if( m_logReporter )
950 m_logReporter->Report( wxString::Format( wxT( "Run DRC provider: '%s'" ), provider->GetName() ) );
951
952 PROF_TIMER providerTimer;
953
954 if( !provider->RunTests( aUnits ) )
955 break;
956
957 providerTimer.Stop();
958 wxLogTrace( traceDrcProfile, "DRC provider '%s' took %0.3f ms", provider->GetName(), providerTimer.msecs() );
959 }
960
961 timer.Stop();
962 wxLogTrace( traceDrcProfile, "DRC took %0.3f ms", timer.msecs() );
963
964 // DRC tests are multi-threaded; anything that causes us to attempt to re-generate the
965 // caches while DRC is running is problematic.
966 wxASSERT( timestamp == m_board->GetTimeStamp() );
967}
968
969
970#define REPORT( s ) { if( aReporter ) { aReporter->Report( s ); } }
971
972DRC_CONSTRAINT DRC_ENGINE::EvalZoneConnection( const BOARD_ITEM* a, const BOARD_ITEM* b,
973 PCB_LAYER_ID aLayer, REPORTER* aReporter )
974{
975 DRC_CONSTRAINT constraint = EvalRules( ZONE_CONNECTION_CONSTRAINT, a, b, aLayer, aReporter );
976
977 REPORT( "" )
978 REPORT( wxString::Format( _( "Resolved zone connection type: %s." ),
979 PrintZoneConnection( constraint.m_ZoneConnection ) ) )
980
981 if( constraint.m_ZoneConnection == ZONE_CONNECTION::THT_THERMAL )
982 {
983 const PAD* pad = nullptr;
984
985 if( a->Type() == PCB_PAD_T )
986 pad = static_cast<const PAD*>( a );
987 else if( b->Type() == PCB_PAD_T )
988 pad = static_cast<const PAD*>( b );
989
990 if( pad && pad->GetAttribute() == PAD_ATTRIB::PTH )
991 {
992 constraint.m_ZoneConnection = ZONE_CONNECTION::THERMAL;
993 }
994 else
995 {
996 REPORT( wxString::Format( _( "Pad is not a through hole pad; connection will be: %s." ),
997 PrintZoneConnection( ZONE_CONNECTION::FULL ) ) )
998 constraint.m_ZoneConnection = ZONE_CONNECTION::FULL;
999 }
1000 }
1001
1002 return constraint;
1003}
1004
1005
1006DRC_CONSTRAINT DRC_ENGINE::EvalRules( DRC_CONSTRAINT_T aConstraintType, const BOARD_ITEM* a, const BOARD_ITEM* b,
1007 PCB_LAYER_ID aLayer, REPORTER* aReporter )
1008{
1009 /*
1010 * NOTE: all string manipulation MUST BE KEPT INSIDE the REPORT macro. It absolutely
1011 * kills performance when running bulk DRC tests (where aReporter is nullptr).
1012 */
1013
1014 const BOARD_CONNECTED_ITEM* ac = a && a->IsConnected() ? static_cast<const BOARD_CONNECTED_ITEM*>( a ) : nullptr;
1015 const BOARD_CONNECTED_ITEM* bc = b && b->IsConnected() ? static_cast<const BOARD_CONNECTED_ITEM*>( b ) : nullptr;
1016
1017 bool a_is_non_copper = a && ( !a->IsOnCopperLayer() || isKeepoutZone( a, false ) );
1018 bool b_is_non_copper = b && ( !b->IsOnCopperLayer() || isKeepoutZone( b, false ) );
1019
1020 const PAD* pad = nullptr;
1021 const ZONE* zone = nullptr;
1022 const FOOTPRINT* parentFootprint = nullptr;
1023
1024 if( aConstraintType == ZONE_CONNECTION_CONSTRAINT
1025 || aConstraintType == THERMAL_RELIEF_GAP_CONSTRAINT
1026 || aConstraintType == THERMAL_SPOKE_WIDTH_CONSTRAINT
1027 || aConstraintType == SOLDER_MASK_EXPANSION_CONSTRAINT
1028 || aConstraintType == SOLDER_PASTE_ABS_MARGIN_CONSTRAINT
1029 || aConstraintType == SOLDER_PASTE_REL_MARGIN_CONSTRAINT )
1030 {
1031 if( a && a->Type() == PCB_PAD_T )
1032 pad = static_cast<const PAD*>( a );
1033 else if( a && a->Type() == PCB_ZONE_T )
1034 zone = static_cast<const ZONE*>( a );
1035
1036 if( b && b->Type() == PCB_PAD_T )
1037 pad = static_cast<const PAD*>( b );
1038 else if( b && b->Type() == PCB_ZONE_T )
1039 zone = static_cast<const ZONE*>( b );
1040
1041 if( pad )
1042 parentFootprint = pad->GetParentFootprint();
1043 }
1044
1045 DRC_CONSTRAINT constraint;
1046 constraint.m_Type = aConstraintType;
1047
1048 auto applyConstraint =
1049 [&]( const DRC_ENGINE_CONSTRAINT* c )
1050 {
1051 if( c->constraint.m_Value.HasMin() )
1052 {
1053 if( c->parentRule && c->parentRule->IsImplicit() )
1054 constraint.m_ImplicitMin = true;
1055 else
1056 constraint.m_ImplicitMin = false;
1057
1058 constraint.m_Value.SetMin( c->constraint.m_Value.Min() );
1059 }
1060
1061 if( c->constraint.m_Value.HasOpt() )
1062 constraint.m_Value.SetOpt( c->constraint.m_Value.Opt() );
1063
1064 if( c->constraint.m_Value.HasMax() )
1065 constraint .m_Value.SetMax( c->constraint.m_Value.Max() );
1066
1067 switch( c->constraint.m_Type )
1068 {
1069 case CLEARANCE_CONSTRAINT:
1070 case COURTYARD_CLEARANCE_CONSTRAINT:
1071 case SILK_CLEARANCE_CONSTRAINT:
1072 case HOLE_CLEARANCE_CONSTRAINT:
1073 case EDGE_CLEARANCE_CONSTRAINT:
1074 case PHYSICAL_CLEARANCE_CONSTRAINT:
1075 case PHYSICAL_HOLE_CLEARANCE_CONSTRAINT:
1076 if( constraint.m_Value.Min() > MAXIMUM_CLEARANCE )
1077 constraint.m_Value.SetMin( MAXIMUM_CLEARANCE );
1078
1079 break;
1080
1081 default:
1082 break;
1083 }
1084
1085 // While the expectation would be to OR the disallow flags, we've already
1086 // masked them down to aItem's type -- so we're really only looking for a
1087 // boolean here.
1088 constraint.m_DisallowFlags = c->constraint.m_DisallowFlags;
1089
1090 constraint.m_ZoneConnection = c->constraint.m_ZoneConnection;
1091
1092 constraint.SetParentRule( c->constraint.GetParentRule() );
1093
1094 constraint.SetOptionsFromOther( c->constraint );
1095 };
1096
1097 const FOOTPRINT* footprints[2] = { a ? a->GetParentFootprint() : nullptr,
1098 b ? b->GetParentFootprint() : nullptr };
1099
1100 // Handle Footprint net ties, which will zero out the clearance for footprint objects
1101 if( aConstraintType == CLEARANCE_CONSTRAINT // Only zero clearance, other constraints still apply
1102 && ( ( ( !ac ) ^ ( !bc ) )// Only apply to cases where we are comparing a connected item to a non-connected item
1103 // and not both connected. Connected items of different nets still need to be checked
1104 // for their standard clearance value
1105 || ( ( footprints[0] == footprints[1] ) // Unless both items are in the same footprint
1106 && footprints[0] ) ) // And that footprint exists
1107 && !a_is_non_copper // Also, both elements need to be on copper layers
1108 && !b_is_non_copper )
1109 {
1110 const BOARD_ITEM* child_items[2] = {a, b};
1111
1112 // These are the items being compared against, so the order is reversed
1113 const BOARD_CONNECTED_ITEM* alt_items[2] = {bc, ac};
1114
1115 for( int ii = 0; ii < 2; ++ii )
1116 {
1117 // We need both a footprint item and a connected item to check for a net tie
1118 if( !footprints[ii] || !alt_items[ii] )
1119 continue;
1120
1121 const std::set<int>& netcodes = footprints[ii]->GetNetTieCache( child_items[ii] );
1122
1123 auto it = netcodes.find( alt_items[ii]->GetNetCode() );
1124
1125 if( it != netcodes.end() )
1126 {
1127 REPORT( "" )
1128 REPORT( wxString::Format( _( "Net tie on %s; clearance: 0." ),
1129 EscapeHTML( footprints[ii]->GetItemDescription( this, true ) ) ) )
1130
1131 constraint.SetName( _( "net tie" ) );
1132 constraint.m_Value.SetMin( 0 );
1133 return constraint;
1134 }
1135 }
1136 }
1137
1138 // Local overrides take precedence over everything *except* board min clearance
1139 if( aConstraintType == CLEARANCE_CONSTRAINT || aConstraintType == HOLE_CLEARANCE_CONSTRAINT )
1140 {
1141 int override_val = 0;
1142 std::optional<int> overrideA;
1143 std::optional<int> overrideB;
1144
1145 if( ac && !b_is_non_copper )
1146 overrideA = ac->GetClearanceOverrides( nullptr );
1147
1148 if( bc && !a_is_non_copper )
1149 overrideB = bc->GetClearanceOverrides( nullptr );
1150
1151 if( overrideA.has_value() || overrideB.has_value() )
1152 {
1153 wxString msg;
1154
1155 if( overrideA.has_value() )
1156 {
1157 REPORT( "" )
1158 REPORT( wxString::Format( _( "Local override on %s; clearance: %s." ),
1159 EscapeHTML( a->GetItemDescription( this, true ) ),
1160 MessageTextFromValue( overrideA.value() ) ) )
1161
1162 override_val = ac->GetClearanceOverrides( &msg ).value();
1163 }
1164
1165 if( overrideB.has_value() )
1166 {
1167 REPORT( "" )
1168 REPORT( wxString::Format( _( "Local override on %s; clearance: %s." ),
1169 EscapeHTML( b->GetItemDescription( this, true ) ),
1170 MessageTextFromValue( overrideB.value() ) ) )
1171
1172 if( overrideB > override_val )
1173 override_val = bc->GetClearanceOverrides( &msg ).value();
1174 }
1175
1176 if( override_val )
1177 {
1178 if( aConstraintType == CLEARANCE_CONSTRAINT )
1179 {
1180 if( override_val < m_designSettings->m_MinClearance )
1181 {
1182 override_val = m_designSettings->m_MinClearance;
1183 msg = _( "board minimum" );
1184
1185 REPORT( "" )
1186 REPORT( wxString::Format( _( "Board minimum clearance: %s." ),
1187 MessageTextFromValue( override_val ) ) )
1188 }
1189 }
1190 else
1191 {
1192 if( override_val < m_designSettings->m_HoleClearance )
1193 {
1194 override_val = m_designSettings->m_HoleClearance;
1195 msg = _( "board minimum hole" );
1196
1197 REPORT( "" )
1198 REPORT( wxString::Format( _( "Board minimum hole clearance: %s." ),
1199 MessageTextFromValue( override_val ) ) )
1200 }
1201 }
1202
1203 constraint.SetName( msg );
1204 constraint.m_Value.SetMin( override_val );
1205 return constraint;
1206 }
1207 }
1208 }
1209 else if( aConstraintType == ZONE_CONNECTION_CONSTRAINT )
1210 {
1211 if( pad && pad->GetLocalZoneConnection() != ZONE_CONNECTION::INHERITED )
1212 {
1213 wxString msg;
1214 ZONE_CONNECTION override = pad->GetZoneConnectionOverrides( &msg );
1215
1216 REPORT( "" )
1217 REPORT( wxString::Format( _( "Local override on %s; zone connection: %s." ),
1218 EscapeHTML( pad->GetItemDescription( this, true ) ),
1219 PrintZoneConnection( override ) ) )
1220
1221 constraint.SetName( msg );
1222 constraint.m_ZoneConnection = override;
1223 return constraint;
1224 }
1225 }
1226 else if( aConstraintType == THERMAL_RELIEF_GAP_CONSTRAINT )
1227 {
1228 if( pad && pad->GetLocalThermalGapOverride( nullptr ) > 0 )
1229 {
1230 wxString msg;
1231 int gap_override = pad->GetLocalThermalGapOverride( &msg );
1232
1233 REPORT( "" )
1234 REPORT( wxString::Format( _( "Local override on %s; thermal relief gap: %s." ),
1235 EscapeHTML( pad->GetItemDescription( this, true ) ),
1236 MessageTextFromValue( gap_override ) ) )
1237
1238 constraint.SetName( msg );
1239 constraint.m_Value.SetMin( gap_override );
1240 return constraint;
1241 }
1242 }
1243 else if( aConstraintType == THERMAL_SPOKE_WIDTH_CONSTRAINT )
1244 {
1245 if( pad && pad->GetLocalSpokeWidthOverride( nullptr ) > 0 )
1246 {
1247 wxString msg;
1248 int spoke_override = pad->GetLocalSpokeWidthOverride( &msg );
1249
1250 REPORT( "" )
1251 REPORT( wxString::Format( _( "Local override on %s; thermal spoke width: %s." ),
1252 EscapeHTML( pad->GetItemDescription( this, true ) ),
1253 MessageTextFromValue( spoke_override ) ) )
1254
1255 if( zone && zone->GetMinThickness() > spoke_override )
1256 {
1257 spoke_override = zone->GetMinThickness();
1258
1259 REPORT( "" )
1260 REPORT( wxString::Format( _( "%s min thickness: %s." ),
1261 EscapeHTML( zone->GetItemDescription( this, true ) ),
1262 MessageTextFromValue( spoke_override ) ) )
1263 }
1264
1265 constraint.SetName( msg );
1266 constraint.m_Value.SetMin( spoke_override );
1267 return constraint;
1268 }
1269 }
1270 else if( aConstraintType == SOLDER_MASK_EXPANSION_CONSTRAINT )
1271 {
1272 std::optional<int> override;
1273 const BOARD_ITEM* overrideItem = a;
1274
1275 if( pad )
1276 override = pad->GetLocalSolderMaskMargin();
1277 else if( a->Type() == PCB_SHAPE_T )
1278 override = static_cast<const PCB_SHAPE*>( a )->GetLocalSolderMaskMargin();
1279 else if( const PCB_TRACK* track = dynamic_cast<const PCB_TRACK*>( a ) )
1280 override = track->GetLocalSolderMaskMargin();
1281
1282 if( !override.has_value() && pad )
1283 {
1284 if( FOOTPRINT* overrideFootprint = pad->GetParentFootprint() )
1285 {
1286 override = overrideFootprint->GetLocalSolderMaskMargin();
1287 overrideItem = overrideFootprint;
1288 }
1289 }
1290
1291 if( override )
1292 {
1293 REPORT( "" )
1294 REPORT( wxString::Format( _( "Local override on %s; solder mask expansion: %s." ),
1295 EscapeHTML( overrideItem->GetItemDescription( this, true ) ),
1296 MessageTextFromValue( override.value() ) ) )
1297
1298 constraint.m_Value.SetOpt( override.value() );
1299 return constraint;
1300 }
1301 }
1302 else if( aConstraintType == SOLDER_PASTE_ABS_MARGIN_CONSTRAINT )
1303 {
1304 std::optional<int> override;
1305 const BOARD_ITEM* overrideItem = a;
1306
1307 if( pad )
1308 override = pad->GetLocalSolderPasteMargin();
1309
1310 if( !override.has_value() && pad )
1311 {
1312 if( FOOTPRINT* overrideFootprint = pad->GetParentFootprint() )
1313 {
1314 override = overrideFootprint->GetLocalSolderPasteMargin();
1315 overrideItem = overrideFootprint;
1316 }
1317 }
1318
1319 if( override )
1320 {
1321 REPORT( "" )
1322 REPORT( wxString::Format( _( "Local override on %s; solder paste absolute clearance: %s." ),
1323 EscapeHTML( overrideItem->GetItemDescription( this, true ) ),
1324 MessageTextFromValue( override.value() ) ) )
1325
1326 constraint.m_Value.SetOpt( override.value_or( 0 ) );
1327 return constraint;
1328 }
1329 }
1330 else if( aConstraintType == SOLDER_PASTE_REL_MARGIN_CONSTRAINT )
1331 {
1332 std::optional<double> overrideRatio;
1333 const BOARD_ITEM* overrideItem = a;
1334
1335 if( pad )
1336 overrideRatio = pad->GetLocalSolderPasteMarginRatio();
1337
1338 if( !overrideRatio.has_value() && pad )
1339 {
1340 if( FOOTPRINT* overrideFootprint = pad->GetParentFootprint() )
1341 {
1342 overrideRatio = overrideFootprint->GetLocalSolderPasteMarginRatio();
1343 overrideItem = overrideFootprint;
1344 }
1345 }
1346
1347 if( overrideRatio )
1348 {
1349 REPORT( "" )
1350 REPORT( wxString::Format( _( "Local override on %s; solder paste relative clearance: %s." ),
1351 EscapeHTML( overrideItem->GetItemDescription( this, true ) ),
1352 MessageTextFromValue( overrideRatio.value() * 100.0 ) ) )
1353
1354 constraint.m_Value.SetOpt( KiROUND( overrideRatio.value_or( 0 ) * 1000 ) );
1355 return constraint;
1356 }
1357 }
1358
1359 auto testAssertion =
1360 [&]( const DRC_ENGINE_CONSTRAINT* c )
1361 {
1362 REPORT( wxString::Format( _( "Checking assertion '%s'." ),
1363 EscapeHTML( c->constraint.m_Test->GetExpression() ) ) )
1364
1365 if( c->constraint.m_Test->EvaluateFor( a, b, c->constraint.m_Type, aLayer, aReporter ) )
1366 REPORT( _( "Assertion passed." ) )
1367 else
1368 REPORT( EscapeHTML( _( "--> Assertion failed. <--" ) ) )
1369 };
1370
1371 // Within a single EvalRules call a, b, aLayer and the constraint type are fixed, so a rule
1372 // condition's result depends only on its expression. Large rule sets contain many rules with
1373 // identical conditions; caching by expression collapses those duplicates into one evaluation
1374 // each and avoids re-running the (allocation-heavy) expression VM. Only used on the bulk path
1375 // with no reporter, since the reporter path has reporting side effects.
1376 std::unordered_map<wxString, bool> conditionCache;
1377
1378 auto reportConstraintHeader =
1379 [&]( const DRC_ENGINE_CONSTRAINT* c )
1380 {
1381 REPORT( "" )
1382
1383 bool implicit = c->parentRule && c->parentRule->IsImplicit();
1384
1385 switch( c->constraint.m_Type )
1386 {
1387 case CLEARANCE_CONSTRAINT:
1388 case COURTYARD_CLEARANCE_CONSTRAINT:
1389 case SILK_CLEARANCE_CONSTRAINT:
1390 case HOLE_CLEARANCE_CONSTRAINT:
1391 case EDGE_CLEARANCE_CONSTRAINT:
1392 case PHYSICAL_CLEARANCE_CONSTRAINT:
1393 case PHYSICAL_HOLE_CLEARANCE_CONSTRAINT:
1394 REPORT( wxString::Format( _( "Checking %s clearance: %s." ),
1395 EscapeHTML( c->constraint.GetName() ),
1396 MessageTextFromValue( c->constraint.m_Value.Min() ) ) )
1397 break;
1398 case CREEPAGE_CONSTRAINT:
1399 REPORT( wxString::Format( _( "Checking %s creepage: %s." ),
1400 EscapeHTML( c->constraint.GetName() ),
1401 MessageTextFromValue( c->constraint.m_Value.Min() ) ) )
1402 break;
1403 case MAX_UNCOUPLED_CONSTRAINT:
1404 REPORT( wxString::Format( _( "Checking %s max uncoupled length: %s." ),
1405 EscapeHTML( c->constraint.GetName() ),
1406 MessageTextFromValue( c->constraint.m_Value.Max() ) ) )
1407 break;
1408
1409 case SKEW_CONSTRAINT:
1410 REPORT( wxString::Format( _( "Checking %s max skew: %s." ),
1411 EscapeHTML( c->constraint.GetName() ),
1412 MessageTextFromValue( c->constraint.m_Value.Max() ) ) )
1413 break;
1414
1415 case THERMAL_RELIEF_GAP_CONSTRAINT:
1416 REPORT( wxString::Format( _( "Checking %s gap: %s." ),
1417 EscapeHTML( c->constraint.GetName() ),
1418 MessageTextFromValue( c->constraint.m_Value.Min() ) ) )
1419 break;
1420
1421 case THERMAL_SPOKE_WIDTH_CONSTRAINT:
1422 REPORT( wxString::Format( _( "Checking %s thermal spoke width: %s." ),
1423 EscapeHTML( c->constraint.GetName() ),
1424 MessageTextFromValue( c->constraint.m_Value.Opt() ) ) )
1425 break;
1426
1427 case SOLDER_MASK_EXPANSION_CONSTRAINT:
1428 REPORT( wxString::Format( _( "Checking %s solder mask expansion: %s." ),
1429 EscapeHTML( c->constraint.GetName() ),
1430 MessageTextFromValue( c->constraint.m_Value.Opt() ) ) )
1431 break;
1432
1433 case SOLDER_PASTE_ABS_MARGIN_CONSTRAINT:
1434 REPORT( wxString::Format( _( "Checking %s solder paste absolute clearance: %s." ),
1435 EscapeHTML( c->constraint.GetName() ),
1436 MessageTextFromValue( c->constraint.m_Value.Opt() ) ) )
1437 break;
1438
1439 case SOLDER_PASTE_REL_MARGIN_CONSTRAINT:
1440 REPORT( wxString::Format( _( "Checking %s solder paste relative clearance: %s." ),
1441 EscapeHTML( c->constraint.GetName() ),
1442 MessageTextFromValue( c->constraint.m_Value.Opt() ) ) )
1443 break;
1444
1445 case MIN_RESOLVED_SPOKES_CONSTRAINT:
1446 REPORT( wxString::Format( _( "Checking %s min spoke count: %s." ),
1447 EscapeHTML( c->constraint.GetName() ),
1448 MessageTextFromUnscaledValue( c->constraint.m_Value.Min() ) ) )
1449 break;
1450
1451 case ZONE_CONNECTION_CONSTRAINT:
1452 REPORT( wxString::Format( _( "Checking %s zone connection: %s." ),
1453 EscapeHTML( c->constraint.GetName() ),
1454 PrintZoneConnection( c->constraint.m_ZoneConnection ) ) )
1455 break;
1456
1457 case TRACK_WIDTH_CONSTRAINT:
1458 case ANNULAR_WIDTH_CONSTRAINT:
1459 case VIA_DIAMETER_CONSTRAINT:
1460 case HOLE_SIZE_CONSTRAINT:
1461 case TEXT_HEIGHT_CONSTRAINT:
1462 case TEXT_THICKNESS_CONSTRAINT:
1463 case DIFF_PAIR_GAP_CONSTRAINT:
1464 case LENGTH_CONSTRAINT:
1465 case NET_CHAIN_LENGTH_CONSTRAINT:
1466 case NET_CHAIN_STUB_LENGTH_CONSTRAINT:
1467 case NET_CHAIN_RETURN_PATH_CONSTRAINT:
1468 case CONNECTION_WIDTH_CONSTRAINT:
1469 case HOLE_TO_HOLE_CONSTRAINT:
1470 {
1471 if( implicit )
1472 {
1473 switch( c->constraint.m_Type )
1474 {
1475 case TRACK_WIDTH_CONSTRAINT:
1476 if( c->constraint.m_Value.HasOpt() )
1477 {
1478 REPORT( wxString::Format( _( "Checking %s track width: opt %s." ),
1479 EscapeHTML( c->constraint.GetName() ),
1480 MessageTextFromValue( c->constraint.m_Value.Opt() ) ) )
1481 }
1482 else if( c->constraint.m_Value.HasMin() )
1483 {
1484 REPORT( wxString::Format( _( "Checking %s track width: min %s." ),
1485 EscapeHTML( c->constraint.GetName() ),
1486 MessageTextFromValue( c->constraint.m_Value.Min() ) ) )
1487 }
1488
1489 break;
1490
1491 case ANNULAR_WIDTH_CONSTRAINT:
1492 REPORT( wxString::Format( _( "Checking %s annular width: min %s." ),
1493 EscapeHTML( c->constraint.GetName() ),
1494 MessageTextFromValue( c->constraint.m_Value.Opt() ) ) )
1495 break;
1496
1497 case VIA_DIAMETER_CONSTRAINT:
1498 if( c->constraint.m_Value.HasOpt() )
1499 {
1500 REPORT( wxString::Format( _( "Checking %s via diameter: opt %s." ),
1501 EscapeHTML( c->constraint.GetName() ),
1502 MessageTextFromValue( c->constraint.m_Value.Opt() ) ) )
1503 }
1504 else if( c->constraint.m_Value.HasMin() )
1505 {
1506 REPORT( wxString::Format( _( "Checking %s via diameter: min %s." ),
1507 EscapeHTML( c->constraint.GetName() ),
1508 MessageTextFromValue( c->constraint.m_Value.Min() ) ) )
1509 }
1510 break;
1511
1512 case HOLE_SIZE_CONSTRAINT:
1513 if( c->constraint.m_Value.HasOpt() )
1514 {
1515 REPORT( wxString::Format( _( "Checking %s hole size: opt %s." ),
1516 EscapeHTML( c->constraint.GetName() ),
1517 MessageTextFromValue( c->constraint.m_Value.Opt() ) ) )
1518 }
1519 else if( c->constraint.m_Value.HasMin() )
1520 {
1521 REPORT( wxString::Format( _( "Checking %s hole size: min %s." ),
1522 EscapeHTML( c->constraint.GetName() ),
1523 MessageTextFromValue( c->constraint.m_Value.Min() ) ) )
1524 }
1525
1526 break;
1527
1528 case TEXT_HEIGHT_CONSTRAINT:
1529 case TEXT_THICKNESS_CONSTRAINT:
1530 case CONNECTION_WIDTH_CONSTRAINT:
1531 REPORT( wxString::Format( _( "Checking %s: min %s." ),
1532 EscapeHTML( c->constraint.GetName() ),
1533 MessageTextFromValue( c->constraint.m_Value.Min() ) ) )
1534 break;
1535
1536 case DIFF_PAIR_GAP_CONSTRAINT:
1537 if( c->constraint.m_Value.HasOpt() )
1538 {
1539 REPORT( wxString::Format( _( "Checking %s diff pair gap: opt %s." ),
1540 EscapeHTML( c->constraint.GetName() ),
1541 MessageTextFromValue( c->constraint.m_Value.Opt() ) ) )
1542 }
1543 else if( c->constraint.m_Value.HasMin() )
1544 {
1545 REPORT( wxString::Format( _( "Checking %s clearance: min %s." ),
1546 EscapeHTML( c->constraint.GetName() ),
1547 MessageTextFromValue( c->constraint.m_Value.Min() ) ) )
1548 }
1549
1550 break;
1551
1552 case HOLE_TO_HOLE_CONSTRAINT:
1553 REPORT( wxString::Format( _( "Checking %s hole to hole: min %s." ),
1554 EscapeHTML( c->constraint.GetName() ),
1555 MessageTextFromValue( c->constraint.m_Value.Min() ) ) )
1556 break;
1557
1558 default:
1559 REPORT( wxString::Format( _( "Checking %s." ),
1560 EscapeHTML( c->constraint.GetName() ) ) )
1561 }
1562 }
1563 else
1564 {
1565 REPORT( wxString::Format( _( "Checking %s: min %s; opt %s; max %s." ),
1566 EscapeHTML( c->constraint.GetName() ),
1567 c->constraint.m_Value.HasMin()
1568 ? MessageTextFromValue( c->constraint.m_Value.Min() )
1569 : wxT( "<i>" ) + _( "undefined" ) + wxT( "</i>" ),
1570 c->constraint.m_Value.HasOpt()
1571 ? MessageTextFromValue( c->constraint.m_Value.Opt() )
1572 : wxT( "<i>" ) + _( "undefined" ) + wxT( "</i>" ),
1573 c->constraint.m_Value.HasMax()
1574 ? MessageTextFromValue( c->constraint.m_Value.Max() )
1575 : wxT( "<i>" ) + _( "undefined" ) + wxT( "</i>" ) ) )
1576 }
1577 break;
1578 }
1579
1580 default:
1581 REPORT( wxString::Format( _( "Checking %s." ), EscapeHTML( c->constraint.GetName() ) ) )
1582 }
1583 };
1584
1585 auto checkCondition =
1586 [&]( const DRC_ENGINE_CONSTRAINT* c, REPORTER* r )
1587 {
1588 bool condMatched = false;
1589
1590 if( r )
1591 {
1592 condMatched = c->condition->EvaluateFor( a, b, c->constraint.m_Type, aLayer, r );
1593 }
1594 else
1595 {
1596 const wxString& expr = c->condition->GetExpression();
1597 auto it = conditionCache.find( expr );
1598
1599 if( it != conditionCache.end() )
1600 {
1601 condMatched = it->second;
1602 }
1603 else
1604 {
1605 condMatched = c->condition->EvaluateFor( a, b, c->constraint.m_Type, aLayer, r );
1606 conditionCache[expr] = condMatched;
1607 }
1608 }
1609
1610 return condMatched;
1611 };
1612
1613 auto processConstraint =
1614 [&]( const DRC_ENGINE_CONSTRAINT* c )
1615 {
1616 bool implicit = c->parentRule && c->parentRule->IsImplicit();
1617
1618 if( implicit && c->parentRule->GetImplicitSource() == DRC_IMPLICIT_SOURCE::NET_CLASS )
1619 {
1620 if( c->constraint.m_Type == CLEARANCE_CONSTRAINT )
1621 {
1622 if( a_is_non_copper || b_is_non_copper )
1623 {
1624 reportConstraintHeader( c );
1625 REPORT( _( "Netclass clearances apply only between copper items." ) )
1626 return;
1627 }
1628 }
1629
1630 if( !checkCondition( c, nullptr ) )
1631 return;
1632 }
1633
1634 reportConstraintHeader( c );
1635
1636 if( c->constraint.m_Type == CLEARANCE_CONSTRAINT )
1637 {
1638 if( a_is_non_copper )
1639 {
1640 REPORT( wxString::Format( _( "%s contains no copper. Constraint ignored." ),
1641 EscapeHTML( a->GetItemDescription( this, true ) ) ) )
1642 return;
1643 }
1644 else if( b_is_non_copper )
1645 {
1646 REPORT( wxString::Format( _( "%s contains no copper. Constraint ignored." ),
1647 EscapeHTML( b->GetItemDescription( this, true ) ) ) )
1648 return;
1649 }
1650 }
1651 else if( c->constraint.m_Type == DISALLOW_CONSTRAINT )
1652 {
1653 // A footprint's own keepout never applies to that footprint; decide
1654 // ownership from the rule's zone so a hijacked UUID cache can't defeat it
1655 if( c->implicitKeepoutZone && a == c->implicitKeepoutZone->GetParentFootprint() )
1656 {
1657 REPORT( _( "Keepout belongs to the footprint under test; constraint ignored." ) )
1658 return;
1659 }
1660
1661 int mask;
1662
1663 if( a->GetFlags() & HOLE_PROXY )
1664 {
1665 mask = DRC_DISALLOW_HOLES;
1666 }
1667 else if( a->Type() == PCB_VIA_T )
1668 {
1669 const PCB_VIA* via = static_cast<const PCB_VIA*>( a );
1670
1671 if( via->IsMicroVia() )
1672 mask = DRC_DISALLOW_MICRO_VIAS;
1673 else if( via->IsBlindVia() )
1674 mask = DRC_DISALLOW_BLIND_VIAS;
1675 else if( via->IsBuriedVia() )
1676 mask = DRC_DISALLOW_BURIED_VIAS;
1677 else
1678 mask = DRC_DISALLOW_THROUGH_VIAS;
1679 }
1680 else
1681 {
1682 switch( a->Type() )
1683 {
1684 case PCB_TRACE_T: mask = DRC_DISALLOW_TRACKS; break;
1685 case PCB_ARC_T: mask = DRC_DISALLOW_TRACKS; break;
1686 case PCB_PAD_T: mask = DRC_DISALLOW_PADS; break;
1687 case PCB_FOOTPRINT_T: mask = DRC_DISALLOW_FOOTPRINTS; break;
1688 case PCB_SHAPE_T: mask = DRC_DISALLOW_GRAPHICS; break;
1689 case PCB_BARCODE_T: mask = DRC_DISALLOW_GRAPHICS; break;
1690 case PCB_FIELD_T: mask = DRC_DISALLOW_TEXTS; break;
1691 case PCB_TEXT_T: mask = DRC_DISALLOW_TEXTS; break;
1692 case PCB_TEXTBOX_T: mask = DRC_DISALLOW_TEXTS; break;
1693 case PCB_TABLE_T: mask = DRC_DISALLOW_TEXTS; break;
1694
1695 case PCB_ZONE_T:
1696 // Treat teardrop areas as tracks for DRC purposes
1697 if( static_cast<const ZONE*>( a )->IsTeardropArea() )
1698 mask = DRC_DISALLOW_TRACKS;
1699 else
1700 mask = DRC_DISALLOW_ZONES;
1701
1702 break;
1703
1704 case PCB_LOCATE_HOLE_T: mask = DRC_DISALLOW_HOLES; break;
1705 default: mask = 0; break;
1706 }
1707 }
1708
1709 if( ( c->constraint.m_DisallowFlags & mask ) == 0 )
1710 {
1711 if( implicit )
1712 REPORT( _( "Keepout constraint not met." ) )
1713 else
1714 REPORT( _( "Disallow constraint not met." ) )
1715
1716 return;
1717 }
1718
1719 LSET itemLayers = a->GetLayerSet();
1720
1721 if( a->Type() == PCB_FOOTPRINT_T )
1722 {
1723 const FOOTPRINT* footprint = static_cast<const FOOTPRINT*>( a );
1724
1725 if( !footprint->GetCourtyard( F_CrtYd ).IsEmpty() )
1726 itemLayers |= LSET::FrontMask();
1727
1728 if( !footprint->GetCourtyard( B_CrtYd ).IsEmpty() )
1729 itemLayers |= LSET::BackMask();
1730 }
1731
1732 if( !( c->layerTest & itemLayers ).any() )
1733 {
1734 if( implicit )
1735 {
1736 REPORT( _( "Keepout layer(s) not matched." ) )
1737 }
1738 else if( c->parentRule )
1739 {
1740 REPORT( wxString::Format( _( "Rule layer '%s' not matched; rule ignored." ),
1741 EscapeHTML( c->parentRule->m_LayerSource ) ) )
1742 }
1743 else
1744 {
1745 REPORT( _( "Rule layer not matched; rule ignored." ) )
1746 }
1747
1748 return;
1749 }
1750 }
1751
1752 if( ( IsPcbLayer( aLayer ) && !c->layerTest.test( aLayer ) )
1753 || ( m_board->GetEnabledLayers() & c->layerTest ).count() == 0 )
1754 {
1755 if( implicit )
1756 {
1757 REPORT( _( "Constraint layer not matched." ) )
1758 }
1759 else if( c->parentRule )
1760 {
1761 REPORT( wxString::Format( _( "Rule layer '%s' not matched; rule ignored." ),
1762 EscapeHTML( c->parentRule->m_LayerSource ) ) )
1763 }
1764 else
1765 {
1766 REPORT( _( "Rule layer not matched; rule ignored." ) )
1767 }
1768 }
1769 else if( c->constraint.m_Type == HOLE_TO_HOLE_CONSTRAINT
1770 && ( !a->HasHole() || !b->HasHole() ) )
1771 {
1772 // Hole-to-hole only applies between two mechanical holes; this covers both
1773 // round drilled holes and milled (oval) slots, but not a hole paired with
1774 // a non-hole item.
1775 const BOARD_ITEM* nonHole = a->HasHole() ? b : a;
1776
1777 REPORT( wxString::Format( _( "%s does not have a hole; rule ignored." ),
1778 nonHole->GetItemDescription( this, true ) ) )
1779 }
1780 else if( !c->condition || c->condition->GetExpression().IsEmpty() )
1781 {
1782 if( aReporter )
1783 {
1784 if( implicit )
1785 {
1786 REPORT( _( "Unconditional constraint applied." ) )
1787 }
1788 else if( constraint.m_Type == ASSERTION_CONSTRAINT )
1789 {
1790 REPORT( _( "Unconditional rule applied." ) )
1791 testAssertion( c );
1792 }
1793 else
1794 {
1795 REPORT( _( "Unconditional rule applied; overrides previous constraints." ) )
1796 }
1797 }
1798
1799 applyConstraint( c );
1800 }
1801 else
1802 {
1803 // For implicit keepout rules with a pre-resolved zone pointer, skip the
1804 // expensive expression evaluation when the item doesn't overlap the
1805 // zone's bounding box. This avoids UUID string parsing and cache lock
1806 // contention for the vast majority of item-keepout pairs.
1807 if( c->implicitKeepoutZone && !aReporter )
1808 {
1809 BOX2I itemBBox = a->GetBoundingBox();
1810 BOX2I zoneBBox = c->implicitKeepoutZone->GetBoundingBox();
1811
1812 if( !itemBBox.Intersects( zoneBBox ) )
1813 return;
1814 }
1815
1816 if( implicit )
1817 {
1818 // Don't report on implicit rule conditions; they're synthetic.
1819 }
1820 else
1821 {
1822 REPORT( wxString::Format( _( "Checking rule condition '%s'." ),
1823 EscapeHTML( c->condition->GetExpression() ) ) )
1824 }
1825
1826 bool condMatched;
1827
1828 if( implicit && c->parentRule->GetImplicitSource() == DRC_IMPLICIT_SOURCE::NET_CLASS )
1829 condMatched = true;
1830 else
1831 condMatched = checkCondition( c, aReporter );
1832
1833 if( condMatched )
1834 {
1835 if( aReporter )
1836 {
1837 if( implicit )
1838 {
1839 REPORT( _( "Constraint applied." ) )
1840 }
1841 else if( constraint.m_Type == ASSERTION_CONSTRAINT )
1842 {
1843 REPORT( _( "Rule applied." ) )
1844 testAssertion( c );
1845 }
1846 else
1847 {
1848 REPORT( _( "Rule applied; overrides previous constraints." ) )
1849 }
1850 }
1851
1852 applyConstraint( c );
1853 }
1854 else
1855 {
1856 REPORT( implicit ? _( "Membership not satisfied; constraint ignored." )
1857 : _( "Condition not satisfied; rule ignored." ) )
1858 }
1859 }
1860 };
1861
1862 // Fast-path for netclass clearance when no explicit or diff pair override rules exist
1863 if( aConstraintType == CLEARANCE_CONSTRAINT
1864 && !m_hasExplicitClearanceRules
1865 && !m_hasDiffPairClearanceOverrides
1866 && !aReporter
1867 && !a_is_non_copper
1868 && ( !b || !b_is_non_copper ) )
1869 {
1870 int clearance = 0;
1871
1872 // Get netclass names outside of the lock to minimize critical section
1873 wxString ncNameA;
1874 wxString ncNameB;
1875
1876 if( ac )
1877 {
1878 NETCLASS* ncA = ac->GetEffectiveNetClass();
1879
1880 if( ncA )
1881 ncNameA = ncA->GetName();
1882 }
1883
1884 if( bc )
1885 {
1886 NETCLASS* ncB = bc->GetEffectiveNetClass();
1887
1888 if( ncB )
1889 ncNameB = ncB->GetName();
1890 }
1891
1892 // Look up clearances with shared lock protection
1893 if( !ncNameA.empty() || !ncNameB.empty() )
1894 {
1895 std::shared_lock<std::shared_mutex> readLock( m_clearanceCacheMutex );
1896
1897 if( !ncNameA.empty() )
1898 {
1899 auto it = m_netclassClearances.find( ncNameA );
1900
1901 if( it != m_netclassClearances.end() )
1902 clearance = it->second;
1903 }
1904
1905 if( !ncNameB.empty() )
1906 {
1907 auto it = m_netclassClearances.find( ncNameB );
1908
1909 if( it != m_netclassClearances.end() )
1910 clearance = std::max( clearance, it->second );
1911 }
1912 }
1913
1914 if( clearance > 0 )
1915 {
1916 constraint.m_Value.SetMin( clearance );
1917 constraint.m_ImplicitMin = true;
1918 }
1919 }
1920 else
1921 {
1922 auto it = m_constraintMap.find( aConstraintType );
1923
1924 if( it != m_constraintMap.end() )
1925 {
1926 for( DRC_ENGINE_CONSTRAINT* rule : *it->second )
1927 processConstraint( rule );
1928 }
1929
1930 // DIFF_PAIR_GAP_CONSTRAINT must also respect CLEARANCE_CONSTRAINTs.
1931 if( aConstraintType == DIFF_PAIR_GAP_CONSTRAINT )
1932 {
1933 DRC_CONSTRAINT clearanceConstraint = EvalRules( CLEARANCE_CONSTRAINT, a, b, aLayer, nullptr );
1934
1935 REPORT( "" )
1936 REPORT( wxString::Format( _( "Resolved minimum clearance: %s." ),
1937 MessageTextFromValue( clearanceConstraint.m_Value.Min() ) ) )
1938
1939 if( constraint.m_Value.Min() < clearanceConstraint.m_Value.Min() )
1940 constraint.m_Value.SetMin( clearanceConstraint.m_Value.Min() );
1941
1942 return constraint;
1943 }
1944 }
1945
1946 if( constraint.GetParentRule() && !constraint.GetParentRule()->IsImplicit() )
1947 return constraint;
1948
1949 // Special case for properties which can be inherited from parent footprints. We've already
1950 // checked for local overrides, and there were no rules targetting the item itself, so we know
1951 // we're inheriting and need to see if there are any rules targetting the parent footprint.
1952 if( pad && parentFootprint && ( aConstraintType == ZONE_CONNECTION_CONSTRAINT
1953 || aConstraintType == THERMAL_RELIEF_GAP_CONSTRAINT
1954 || aConstraintType == THERMAL_SPOKE_WIDTH_CONSTRAINT
1955 || aConstraintType == SOLDER_MASK_EXPANSION_CONSTRAINT
1956 || aConstraintType == SOLDER_PASTE_ABS_MARGIN_CONSTRAINT
1957 || aConstraintType == SOLDER_PASTE_REL_MARGIN_CONSTRAINT ) )
1958 {
1959 REPORT( "" )
1960 REPORT( wxString::Format( _( "Inheriting from parent: %s." ),
1961 EscapeHTML( parentFootprint->GetItemDescription( this, true ) ) ) )
1962
1963 if( a == pad )
1964 a = parentFootprint;
1965 else
1966 b = parentFootprint;
1967
1968 // a/b just changed, so conditions evaluated against the pad must not be reused for the
1969 // parent footprint.
1970 conditionCache.clear();
1971
1972 auto it = m_constraintMap.find( aConstraintType );
1973
1974 if( it != m_constraintMap.end() )
1975 {
1976 for( DRC_ENGINE_CONSTRAINT* rule : *it->second )
1977 processConstraint( rule );
1978
1979 if( constraint.GetParentRule() && !constraint.GetParentRule()->IsImplicit() )
1980 return constraint;
1981 }
1982
1983 // Found nothing again? Return the defaults.
1984 if( aConstraintType == SOLDER_MASK_EXPANSION_CONSTRAINT )
1985 {
1986 constraint.SetParentRule( nullptr );
1987 constraint.SetName( _( "board setup" ) );
1988 constraint.m_Value.SetOpt( m_designSettings->m_SolderMaskExpansion );
1989 return constraint;
1990 }
1991 else if( aConstraintType == SOLDER_PASTE_ABS_MARGIN_CONSTRAINT )
1992 {
1993 constraint.SetParentRule( nullptr );
1994 constraint.SetName( _( "board setup" ) );
1995 constraint.m_Value.SetOpt( m_designSettings->m_SolderPasteMargin );
1996 return constraint;
1997 }
1998 else if( aConstraintType == SOLDER_PASTE_REL_MARGIN_CONSTRAINT )
1999 {
2000 constraint.SetParentRule( nullptr );
2001 constraint.SetName( _( "board setup" ) );
2002 constraint.m_Value.SetOpt( KiROUND( m_designSettings->m_SolderPasteMarginRatio * 1000 ) );
2003 return constraint;
2004 }
2005 }
2006
2007 // Unfortunately implicit rules don't work for local clearances (such as zones) because
2008 // they have to be max'ed with netclass values (which are already implicit rules), and our
2009 // rule selection paradigm is "winner takes all".
2010 if( aConstraintType == CLEARANCE_CONSTRAINT )
2011 {
2012 int global = constraint.m_Value.Min();
2013 int clearance = global;
2014 bool needBlankLine = true;
2015
2016 if( ac && ac->GetLocalClearance().has_value() )
2017 {
2018 int localA = ac->GetLocalClearance().value();
2019
2020 if( needBlankLine )
2021 {
2022 REPORT( "" )
2023 needBlankLine = false;
2024 }
2025
2026 REPORT( wxString::Format( _( "Local clearance on %s: %s." ),
2027 EscapeHTML( a->GetItemDescription( this, true ) ),
2028 MessageTextFromValue( localA ) ) )
2029
2030 if( localA > clearance )
2031 {
2032 wxString msg;
2033 clearance = ac->GetLocalClearance( &msg ).value();
2034 constraint.SetParentRule( nullptr );
2035 constraint.SetName( msg );
2036 constraint.m_Value.SetMin( clearance );
2037 }
2038 }
2039
2040 if( bc && bc->GetLocalClearance().has_value() )
2041 {
2042 int localB = bc->GetLocalClearance().value();
2043
2044 if( needBlankLine )
2045 {
2046 REPORT( "" )
2047 needBlankLine = false;
2048 }
2049
2050 REPORT( wxString::Format( _( "Local clearance on %s: %s." ),
2051 EscapeHTML( b->GetItemDescription( this, true ) ),
2052 MessageTextFromValue( localB ) ) )
2053
2054 if( localB > clearance )
2055 {
2056 wxString msg;
2057 clearance = bc->GetLocalClearance( &msg ).value();
2058 constraint.SetParentRule( nullptr );
2059 constraint.SetName( msg );
2060 constraint.m_Value.SetMin( clearance );
2061 }
2062 }
2063
2064 if( !a_is_non_copper && !b_is_non_copper )
2065 {
2066 if( needBlankLine )
2067 {
2068 REPORT( "" )
2069 needBlankLine = false;
2070 }
2071
2072 REPORT( wxString::Format( _( "Board minimum clearance: %s." ),
2073 MessageTextFromValue( m_designSettings->m_MinClearance ) ) )
2074
2075 if( clearance < m_designSettings->m_MinClearance )
2076 {
2077 constraint.SetParentRule( nullptr );
2078 constraint.SetName( _( "board minimum" ) );
2079 constraint.m_Value.SetMin( m_designSettings->m_MinClearance );
2080 }
2081 }
2082
2083 return constraint;
2084 }
2085 else if( aConstraintType == ZONE_CONNECTION_CONSTRAINT )
2086 {
2087 if( pad && parentFootprint )
2088 {
2089 ZONE_CONNECTION local = parentFootprint->GetLocalZoneConnection();
2090
2091 if( local != ZONE_CONNECTION::INHERITED )
2092 {
2093 REPORT( "" )
2094 REPORT( wxString::Format( _( "%s zone connection: %s." ),
2095 EscapeHTML( parentFootprint->GetItemDescription( this, true ) ),
2096 PrintZoneConnection( local ) ) )
2097
2098 constraint.SetParentRule( nullptr );
2099 constraint.SetName( _( "footprint" ) );
2100 constraint.m_ZoneConnection = local;
2101 return constraint;
2102 }
2103 }
2104
2105 if( zone )
2106 {
2107 ZONE_CONNECTION local = zone->GetPadConnection();
2108
2109 REPORT( "" )
2110 REPORT( wxString::Format( _( "%s pad connection: %s." ),
2111 EscapeHTML( zone->GetItemDescription( this, true ) ),
2112 PrintZoneConnection( local ) ) )
2113
2114 constraint.SetParentRule( nullptr );
2115 constraint.SetName( _( "zone" ) );
2116 constraint.m_ZoneConnection = local;
2117 return constraint;
2118 }
2119 }
2120 else if( aConstraintType == THERMAL_RELIEF_GAP_CONSTRAINT )
2121 {
2122 if( zone )
2123 {
2124 int local = zone->GetThermalReliefGap();
2125
2126 REPORT( "" )
2127 REPORT( wxString::Format( _( "%s thermal relief gap: %s." ),
2128 EscapeHTML( zone->GetItemDescription( this, true ) ),
2129 MessageTextFromValue( local ) ) )
2130
2131 constraint.SetParentRule( nullptr );
2132 constraint.SetName( _( "zone" ) );
2133 constraint.m_Value.SetMin( local );
2134 return constraint;
2135 }
2136 }
2137 else if( aConstraintType == THERMAL_SPOKE_WIDTH_CONSTRAINT )
2138 {
2139 if( zone )
2140 {
2141 int local = zone->GetThermalReliefSpokeWidth();
2142
2143 REPORT( "" )
2144 REPORT( wxString::Format( _( "%s thermal spoke width: %s." ),
2145 EscapeHTML( zone->GetItemDescription( this, true ) ),
2146 MessageTextFromValue( local ) ) )
2147
2148 constraint.SetParentRule( nullptr );
2149 constraint.SetName( _( "zone" ) );
2150 constraint.m_Value.SetMin( local );
2151 return constraint;
2152 }
2153 }
2154
2155 if( !constraint.GetParentRule() )
2156 {
2157 constraint.m_Type = NULL_CONSTRAINT;
2158 constraint.m_DisallowFlags = 0;
2159 }
2160
2161 return constraint;
2162}
2163
2164
2165DRC_CLEARANCE_BATCH DRC_ENGINE::EvalClearanceBatch( const BOARD_ITEM* a, const BOARD_ITEM* b,
2166 PCB_LAYER_ID aLayer )
2167{
2168 DRC_CLEARANCE_BATCH result;
2169 DRC_CONSTRAINT c;
2170
2171 c = EvalRules( CLEARANCE_CONSTRAINT, a, b, aLayer );
2172
2173 if( c.m_Value.HasMin() )
2174 result.clearance = c.m_Value.Min();
2175
2176 c = EvalRules( HOLE_CLEARANCE_CONSTRAINT, a, b, aLayer );
2177
2178 if( c.m_Value.HasMin() )
2179 result.holeClearance = c.m_Value.Min();
2180
2181 c = EvalRules( HOLE_TO_HOLE_CONSTRAINT, a, b, aLayer );
2182
2183 if( c.m_Value.HasMin() )
2184 result.holeToHole = c.m_Value.Min();
2185
2186 c = EvalRules( EDGE_CLEARANCE_CONSTRAINT, a, b, aLayer );
2187
2188 if( c.m_Value.HasMin() )
2189 result.edgeClearance = c.m_Value.Min();
2190
2191 c = EvalRules( PHYSICAL_CLEARANCE_CONSTRAINT, a, b, aLayer );
2192
2193 if( c.m_Value.HasMin() )
2194 result.physicalClearance = c.m_Value.Min();
2195
2196 return result;
2197}
2198
2199
2200void DRC_ENGINE::ProcessAssertions( const BOARD_ITEM* a,
2201 std::function<void( const DRC_CONSTRAINT* )> aFailureHandler,
2202 REPORTER* aReporter )
2203{
2204 /*
2205 * NOTE: all string manipulation MUST BE KEPT INSIDE the REPORT macro. It absolutely
2206 * kills performance when running bulk DRC tests (where aReporter is nullptr).
2207 */
2208
2209 auto testAssertion =
2210 [&]( const DRC_ENGINE_CONSTRAINT* c )
2211 {
2212 REPORT( wxString::Format( _( "Checking rule assertion '%s'." ),
2213 EscapeHTML( c->constraint.m_Test->GetExpression() ) ) )
2214
2215 if( c->constraint.m_Test->EvaluateFor( a, nullptr, c->constraint.m_Type,
2216 a->GetLayer(), aReporter ) )
2217 {
2218 REPORT( _( "Assertion passed." ) )
2219 }
2220 else
2221 {
2222 REPORT( EscapeHTML( _( "--> Assertion failed. <--" ) ) )
2223 aFailureHandler( &c->constraint );
2224 }
2225 };
2226
2227 auto processConstraint =
2228 [&]( const DRC_ENGINE_CONSTRAINT* c )
2229 {
2230 REPORT( "" )
2231 REPORT( wxString::Format( _( "Checking %s." ), c->constraint.GetName() ) )
2232
2233 if( !( a->GetLayerSet() & c->layerTest ).any() )
2234 {
2235 REPORT( wxString::Format( _( "Rule layer '%s' not matched; rule ignored." ),
2236 EscapeHTML( c->parentRule->m_LayerSource ) ) )
2237 }
2238
2239 if( !c->condition || c->condition->GetExpression().IsEmpty() )
2240 {
2241 REPORT( _( "Unconditional rule applied." ) )
2242 testAssertion( c );
2243 }
2244 else
2245 {
2246 REPORT( wxString::Format( _( "Checking rule condition '%s'." ),
2247 EscapeHTML( c->condition->GetExpression() ) ) )
2248
2249 if( c->condition->EvaluateFor( a, nullptr, c->constraint.m_Type,
2250 a->GetLayer(), aReporter ) )
2251 {
2252 REPORT( _( "Rule applied." ) )
2253 testAssertion( c );
2254 }
2255 else
2256 {
2257 REPORT( _( "Condition not satisfied; rule ignored." ) )
2258 }
2259 }
2260 };
2261
2262 auto it = m_constraintMap.find( ASSERTION_CONSTRAINT );
2263
2264 if( it != m_constraintMap.end() )
2265 {
2266 for( int ii = 0; ii < (int) it->second->size(); ++ii )
2267 processConstraint( it->second->at( ii ) );
2268 }
2269}
2270
2271
2272#undef REPORT
2273
2274
2275bool DRC_ENGINE::IsErrorLimitExceeded( int error_code )
2276{
2277 assert( error_code >= 0 && error_code <= DRCE_LAST );
2278 std::lock_guard<std::mutex> lock( m_errorLimitsMutex );
2279 return m_errorLimits[ error_code ] <= 0;
2280}
2281
2282
2283void DRC_ENGINE::ReportViolation( const std::shared_ptr<DRC_ITEM>& aItem, const VECTOR2I& aPos,
2284 int aMarkerLayer, const std::function<void( PCB_MARKER* )>& aPathGenerator )
2285{
2286 {
2287 std::lock_guard<std::mutex> lock( m_errorLimitsMutex );
2288
2289 // Providers pre-check IsErrorLimitExceeded(), but that check is racy when items
2290 // are processed in parallel, letting many threads slip past the cap and overshoot
2291 // it. Enforce the per-code limit atomically here so the reported count is exact
2292 // and reproducible regardless of worker scheduling.
2293 if( m_errorLimits[ aItem->GetErrorCode() ] <= 0 )
2294 return;
2295
2296 m_errorLimits[ aItem->GetErrorCode() ] -= 1;
2297 }
2298
2299 if( m_violationHandler )
2300 {
2301 static std::mutex handlerLock;
2302 std::lock_guard<std::mutex> guard( handlerLock );
2303 m_violationHandler( aItem, aPos, aMarkerLayer, aPathGenerator );
2304 }
2305
2306 if( m_logReporter )
2307 {
2308 wxString msg = wxString::Format( wxT( "Test '%s': %s (code %d)" ),
2309 aItem->GetViolatingTest()->GetName(),
2310 aItem->GetErrorMessage( false ),
2311 aItem->GetErrorCode() );
2312
2313 DRC_RULE* rule = aItem->GetViolatingRule();
2314
2315 if( rule )
2316 msg += wxString::Format( wxT( ", violating rule: '%s'" ), rule->m_Name );
2317
2318 m_logReporter->Report( msg );
2319
2320 wxString violatingItemsStr = wxT( "Violating items: " );
2321
2322 m_logReporter->Report( wxString::Format( wxT( " |- violating position (%d, %d)" ),
2323 aPos.x,
2324 aPos.y ) );
2325 }
2326}
2327
2328
2329bool DRC_ENGINE::KeepRefreshing( bool aWait )
2330{
2331 if( !m_progressReporter )
2332 return true;
2333
2334 return m_progressReporter->KeepRefreshing( aWait );
2335}
2336
2337
2338void DRC_ENGINE::AdvanceProgress()
2339{
2340 if( m_progressReporter )
2341 m_progressReporter->AdvanceProgress();
2342}
2343
2344
2345void DRC_ENGINE::SetMaxProgress( int aSize )
2346{
2347 if( m_progressReporter )
2348 m_progressReporter->SetMaxProgress( aSize );
2349}
2350
2351
2352bool DRC_ENGINE::ReportProgress( double aProgress )
2353{
2354 if( !m_progressReporter )
2355 return true;
2356
2357 m_progressReporter->SetCurrentProgress( aProgress );
2358 return m_progressReporter->KeepRefreshing( false );
2359}
2360
2361
2362bool DRC_ENGINE::ReportPhase( const wxString& aMessage )
2363{
2364 if( !m_progressReporter )
2365 return true;
2366
2367 m_progressReporter->AdvancePhase( aMessage );
2368 return m_progressReporter->KeepRefreshing( false );
2369}
2370
2371
2372bool DRC_ENGINE::IsCancelled() const
2373{
2374 return m_progressReporter && m_progressReporter->IsCancelled();
2375}
2376
2377
2378bool DRC_ENGINE::HasRulesForConstraintType( DRC_CONSTRAINT_T constraintID )
2379{
2380 auto it = m_constraintMap.find( constraintID );
2381 return it != m_constraintMap.end() && !it->second->empty();
2382}
2383
2384
2385bool DRC_ENGINE::QueryWorstConstraint( DRC_CONSTRAINT_T aConstraintId, DRC_CONSTRAINT& aConstraint,
2386 bool aUnconditionalOnly )
2387{
2388 int worst = 0;
2389 auto it = m_constraintMap.find( aConstraintId );
2390
2391 if( it != m_constraintMap.end() )
2392 {
2393 for( DRC_ENGINE_CONSTRAINT* c : *it->second )
2394 {
2395 if( aUnconditionalOnly && c->condition )
2396 continue;
2397
2398 int current = c->constraint.GetValue().Min();
2399
2400 if( current > worst )
2401 {
2402 worst = current;
2403 aConstraint = c->constraint;
2404 }
2405 }
2406 }
2407
2408 return worst > 0;
2409}
2410
2411
2412bool DRC_ENGINE::HasUserDefinedPhysicalConstraint()
2413{
2414 for( DRC_CONSTRAINT_T type : { PHYSICAL_CLEARANCE_CONSTRAINT, PHYSICAL_HOLE_CLEARANCE_CONSTRAINT } )
2415 {
2416 auto it = m_constraintMap.find( type );
2417
2418 if( it != m_constraintMap.end() )
2419 {
2420 for( DRC_ENGINE_CONSTRAINT* c : *it->second )
2421 {
2422 if( c->condition && c->parentRule && !c->parentRule->IsImplicit() )
2423 return true;
2424 }
2425 }
2426 }
2427
2428 return false;
2429}
2430
2431
2432std::set<int> DRC_ENGINE::QueryDistinctConstraints( DRC_CONSTRAINT_T aConstraintId )
2433{
2434 std::set<int> distinctMinimums;
2435 auto it = m_constraintMap.find( aConstraintId );
2436
2437 if( it != m_constraintMap.end() )
2438 {
2439 for( DRC_ENGINE_CONSTRAINT* c : *it->second )
2440 distinctMinimums.emplace( c->constraint.GetValue().Min() );
2441 }
2442
2443 return distinctMinimums;
2444}
2445
2446
2447// fixme: move two functions below to pcbcommon?
2448int DRC_ENGINE::MatchDpSuffix( const wxString& aNetName, wxString& aComplementNet, wxString& aBaseDpName )
2449{
2450 int rv = 0;
2451 int count = 0;
2452
2453 for( auto it = aNetName.rbegin(); it != aNetName.rend() && rv == 0; ++it, ++count )
2454 {
2455 int ch = *it;
2456
2457 if( ( ch >= '0' && ch <= '9' ) || ch == '_' )
2458 {
2459 continue;
2460 }
2461 else if( ch == '+' )
2462 {
2463 aComplementNet = wxT( "-" );
2464 rv = 1;
2465 }
2466 else if( ch == '-' )
2467 {
2468 aComplementNet = wxT( "+" );
2469 rv = -1;
2470 }
2471 else if( ch == 'N' )
2472 {
2473 aComplementNet = wxT( "P" );
2474 rv = -1;
2475 }
2476 else if ( ch == 'P' )
2477 {
2478 aComplementNet = wxT( "N" );
2479 rv = 1;
2480 }
2481 else
2482 {
2483 break;
2484 }
2485 }
2486
2487 if( rv != 0 && count >= 1 )
2488 {
2489 aBaseDpName = aNetName.Left( aNetName.Length() - count );
2490 aComplementNet = wxString( aBaseDpName ) << aComplementNet << aNetName.Right( count - 1 );
2491 }
2492
2493 return rv;
2494}
2495
2496
2497bool DRC_ENGINE::IsNetADiffPair( BOARD* aBoard, const NETINFO_ITEM* aNet, int& aNetP, int& aNetN )
2498{
2499 const wxString& refName = aNet->GetNetname();
2500 wxString dummy, coupledNetName;
2501
2502 if( int polarity = MatchDpSuffix( refName, coupledNetName, dummy ) )
2503 {
2504 NETINFO_ITEM* net = aBoard->FindNet( coupledNetName );
2505
2506 if( !net )
2507 return false;
2508
2509 if( polarity > 0 )
2510 {
2511 aNetP = aNet->GetNetCode();
2512 aNetN = net->GetNetCode();
2513 }
2514 else
2515 {
2516 aNetP = net->GetNetCode();
2517 aNetN = aNet->GetNetCode();
2518 }
2519
2520 return true;
2521 }
2522
2523 return false;
2524}
2525
2526
2531bool DRC_ENGINE::IsNetTieExclusion( int aTrackNetCode, PCB_LAYER_ID aTrackLayer,
2532 const VECTOR2I& aCollisionPos, BOARD_ITEM* aCollidingItem )
2533{
2534 FOOTPRINT* parentFootprint = aCollidingItem->GetParentFootprint();
2535
2536 if( parentFootprint && parentFootprint->IsNetTie() )
2537 {
2538 int epsilon = GetDesignSettings()->GetDRCEpsilon();
2539 std::map<wxString, int> padToNetTieGroupMap = parentFootprint->MapPadNumbersToNetTieGroups();
2540
2541 for( PAD* pad : parentFootprint->Pads() )
2542 {
2543 if( padToNetTieGroupMap[ pad->GetNumber() ] >= 0 && aTrackNetCode == pad->GetNetCode() )
2544 {
2545 if( pad->GetEffectiveShape( aTrackLayer )->Collide( aCollisionPos, epsilon ) )
2546 return true;
2547 }
2548 }
2549 }
2550
2551 return false;
2552}
2553
2554
2555namespace
2556{
2557enum class SHOWMATCH_DOMAIN
2558{
2559 ALL_ITEMS,
2560 COPPER_ITEMS,
2561 EDGE_ITEMS,
2562 FOOTPRINTS,
2563 HOLE_ITEMS,
2564 MASK_EXPANSION_ITEMS,
2565 MASK_ITEMS,
2566 PADS,
2567 PADS_AND_VIAS,
2568 PASTE_ITEMS,
2569 ROUTING_ITEMS,
2570 SILK_ITEMS,
2571 SILK_TARGET_ITEMS,
2572 TEXT_ITEMS,
2573 VIAS
2574};
2575
2576
2577struct SHOWMATCH_DOMAIN_SPEC
2578{
2579 SHOWMATCH_DOMAIN primary;
2580 SHOWMATCH_DOMAIN secondary = SHOWMATCH_DOMAIN::ALL_ITEMS;
2581 bool hasSecondary = false;
2582 bool secondaryUnary = false;
2583};
2584
2585
2586bool isShowMatchSkippable( const BOARD_ITEM* aItem )
2587{
2588 switch( aItem->Type() )
2589 {
2590 case PCB_NETINFO_T:
2591 case PCB_GENERATOR_T:
2592 case PCB_GROUP_T: return true;
2593
2594 default: return false;
2595 }
2596}
2597
2598
2599bool matchesShowMatchDomain( const BOARD_ITEM* aItem, SHOWMATCH_DOMAIN aDomain )
2600{
2601 if( !aItem || isShowMatchSkippable( aItem ) )
2602 return false;
2603
2604 switch( aDomain )
2605 {
2606 case SHOWMATCH_DOMAIN::ALL_ITEMS: return true;
2607
2608 case SHOWMATCH_DOMAIN::COPPER_ITEMS: return aItem->IsOnCopperLayer();
2609
2610 case SHOWMATCH_DOMAIN::EDGE_ITEMS:
2611 if( aItem->IsOnLayer( Edge_Cuts ) || aItem->IsOnLayer( Margin ) )
2612 return true;
2613
2614 if( aItem->Type() == PCB_PAD_T )
2615 {
2616 const PAD* pad = static_cast<const PAD*>( aItem );
2617 return pad->GetAttribute() == PAD_ATTRIB::NPTH && pad->HasHole();
2618 }
2619
2620 return false;
2621
2622 case SHOWMATCH_DOMAIN::FOOTPRINTS: return aItem->Type() == PCB_FOOTPRINT_T;
2623
2624 case SHOWMATCH_DOMAIN::HOLE_ITEMS: return aItem->HasHole();
2625
2626 case SHOWMATCH_DOMAIN::MASK_EXPANSION_ITEMS:
2627 switch( aItem->Type() )
2628 {
2629 case PCB_PAD_T:
2630 case PCB_TRACE_T:
2631 case PCB_ARC_T:
2632 case PCB_VIA_T:
2633 case PCB_SHAPE_T:
2634 case PCB_ZONE_T: return true;
2635
2636 default: return false;
2637 }
2638
2639 case SHOWMATCH_DOMAIN::MASK_ITEMS: return aItem->IsOnLayer( F_Mask ) || aItem->IsOnLayer( B_Mask );
2640
2641 case SHOWMATCH_DOMAIN::PADS: return aItem->Type() == PCB_PAD_T;
2642
2643 case SHOWMATCH_DOMAIN::PADS_AND_VIAS: return aItem->Type() == PCB_PAD_T || aItem->Type() == PCB_VIA_T;
2644
2645 case SHOWMATCH_DOMAIN::PASTE_ITEMS: return aItem->IsOnLayer( F_Paste ) || aItem->IsOnLayer( B_Paste );
2646
2647 case SHOWMATCH_DOMAIN::ROUTING_ITEMS:
2648 switch( aItem->Type() )
2649 {
2650 case PCB_TRACE_T:
2651 case PCB_ARC_T:
2652 case PCB_VIA_T:
2653 case PCB_PAD_T: return true;
2654
2655 default: return false;
2656 }
2657
2658 case SHOWMATCH_DOMAIN::SILK_ITEMS: return aItem->IsOnLayer( F_SilkS ) || aItem->IsOnLayer( B_SilkS );
2659
2660 case SHOWMATCH_DOMAIN::SILK_TARGET_ITEMS:
2661 return aItem->IsOnLayer( F_SilkS ) || aItem->IsOnLayer( B_SilkS ) || aItem->IsOnLayer( F_Mask )
2662 || aItem->IsOnLayer( B_Mask ) || aItem->IsOnLayer( F_Adhes ) || aItem->IsOnLayer( B_Adhes )
2663 || aItem->IsOnLayer( F_Paste ) || aItem->IsOnLayer( B_Paste ) || aItem->IsOnLayer( F_CrtYd )
2664 || aItem->IsOnLayer( B_CrtYd ) || aItem->IsOnLayer( F_Fab ) || aItem->IsOnLayer( B_Fab )
2665 || aItem->IsOnCopperLayer() || aItem->IsOnLayer( Edge_Cuts ) || aItem->IsOnLayer( Margin );
2666
2667 case SHOWMATCH_DOMAIN::TEXT_ITEMS:
2668 return aItem->Type() == PCB_FIELD_T || aItem->Type() == PCB_TEXT_T || aItem->Type() == PCB_TEXTBOX_T
2669 || aItem->Type() == PCB_TABLECELL_T || BaseType( aItem->Type() ) == PCB_DIMENSION_T;
2670
2671 case SHOWMATCH_DOMAIN::VIAS: return aItem->Type() == PCB_VIA_T;
2672 }
2673
2674 return false;
2675}
2676
2677
2678SHOWMATCH_DOMAIN_SPEC getShowMatchDomainSpec( DRC_CONSTRAINT_T aConstraint )
2679{
2680 switch( aConstraint )
2681 {
2682 case CLEARANCE_CONSTRAINT: return { SHOWMATCH_DOMAIN::COPPER_ITEMS };
2683
2684 case EDGE_CLEARANCE_CONSTRAINT: return { SHOWMATCH_DOMAIN::COPPER_ITEMS, SHOWMATCH_DOMAIN::EDGE_ITEMS, true, true };
2685
2686 case HOLE_CLEARANCE_CONSTRAINT: return { SHOWMATCH_DOMAIN::HOLE_ITEMS, SHOWMATCH_DOMAIN::ALL_ITEMS, true, false };
2687
2688 case HOLE_TO_HOLE_CONSTRAINT: return { SHOWMATCH_DOMAIN::HOLE_ITEMS };
2689
2690 case COURTYARD_CLEARANCE_CONSTRAINT: return { SHOWMATCH_DOMAIN::FOOTPRINTS };
2691
2692 case PHYSICAL_CLEARANCE_CONSTRAINT:
2693 case PHYSICAL_HOLE_CLEARANCE_CONSTRAINT:
2694 case CREEPAGE_CONSTRAINT: return { SHOWMATCH_DOMAIN::ALL_ITEMS };
2695
2696 case SILK_CLEARANCE_CONSTRAINT:
2697 return { SHOWMATCH_DOMAIN::SILK_ITEMS, SHOWMATCH_DOMAIN::SILK_TARGET_ITEMS, true, false };
2698
2699 case SOLDER_MASK_SLIVER_CONSTRAINT: return { SHOWMATCH_DOMAIN::MASK_ITEMS };
2700
2701 case TRACK_WIDTH_CONSTRAINT:
2702 case TRACK_ANGLE_CONSTRAINT:
2703 case TRACK_SEGMENT_LENGTH_CONSTRAINT:
2704 case CONNECTION_WIDTH_CONSTRAINT:
2705 case DIFF_PAIR_GAP_CONSTRAINT:
2706 case MAX_UNCOUPLED_CONSTRAINT:
2707 case LENGTH_CONSTRAINT:
2708 case SKEW_CONSTRAINT: return { SHOWMATCH_DOMAIN::ROUTING_ITEMS };
2709
2710 case VIA_DIAMETER_CONSTRAINT:
2711 case VIA_COUNT_CONSTRAINT: return { SHOWMATCH_DOMAIN::VIAS };
2712
2713 case HOLE_SIZE_CONSTRAINT: return { SHOWMATCH_DOMAIN::HOLE_ITEMS };
2714
2715 case ANNULAR_WIDTH_CONSTRAINT: return { SHOWMATCH_DOMAIN::PADS_AND_VIAS };
2716
2717 case MIN_RESOLVED_SPOKES_CONSTRAINT: return { SHOWMATCH_DOMAIN::PADS };
2718
2719 case TEXT_HEIGHT_CONSTRAINT:
2720 case TEXT_THICKNESS_CONSTRAINT: return { SHOWMATCH_DOMAIN::TEXT_ITEMS };
2721
2722 case SOLDER_MASK_EXPANSION_CONSTRAINT: return { SHOWMATCH_DOMAIN::MASK_EXPANSION_ITEMS };
2723
2724 case SOLDER_PASTE_ABS_MARGIN_CONSTRAINT:
2725 case SOLDER_PASTE_REL_MARGIN_CONSTRAINT: return { SHOWMATCH_DOMAIN::PASTE_ITEMS };
2726
2727 case ASSERTION_CONSTRAINT:
2728 case DISALLOW_CONSTRAINT:
2729 default: return { SHOWMATCH_DOMAIN::ALL_ITEMS };
2730 }
2731}
2732
2733
2734std::vector<BOARD_ITEM*> collectShowMatchCandidates( BOARD* aBoard, SHOWMATCH_DOMAIN aDomain )
2735{
2736 std::vector<BOARD_ITEM*> items;
2737
2738 if( !aBoard )
2739 return items;
2740
2741 for( const auto& [kiid, item] : aBoard->GetItemByIdCache() )
2742 {
2743 if( matchesShowMatchDomain( item, aDomain ) )
2744 items.push_back( item );
2745 }
2746
2747 return items;
2748}
2749
2750
2751std::vector<PCB_LAYER_ID> getShowMatchLayers( const BOARD_ITEM* aItem )
2752{
2753 std::vector<PCB_LAYER_ID> layers;
2754
2755 switch( aItem->Type() )
2756 {
2757 case PCB_PAD_T: layers = static_cast<const PAD*>( aItem )->Padstack().UniqueLayers(); break;
2758
2759 case PCB_VIA_T: layers = static_cast<const PCB_VIA*>( aItem )->Padstack().UniqueLayers(); break;
2760
2761 default:
2762 for( PCB_LAYER_ID layer : aItem->GetLayerSet() )
2763 layers.push_back( layer );
2764
2765 break;
2766 }
2767
2768 if( layers.empty() )
2769 layers.push_back( UNDEFINED_LAYER );
2770
2771 return layers;
2772}
2773
2774
2775bool ruleMatchesUnary( const DRC_RULE& aRule, const BOARD_ITEM* aItem, DRC_CONSTRAINT_T aConstraint,
2776 REPORTER* aReporter )
2777{
2778 bool testedLayer = false;
2779
2780 for( PCB_LAYER_ID layer : getShowMatchLayers( aItem ) )
2781 {
2782 if( layer != UNDEFINED_LAYER && !aRule.m_LayerCondition.test( layer ) )
2783 continue;
2784
2785 testedLayer = true;
2786
2787 if( !aRule.m_Condition
2788 || aRule.m_Condition->EvaluateFor( aItem, nullptr, static_cast<int>( aConstraint ), layer, aReporter ) )
2789 {
2790 return true;
2791 }
2792 }
2793
2794 if( !testedLayer && aItem->GetLayerSet().none() )
2795 {
2796 return !aRule.m_Condition
2797 || aRule.m_Condition->EvaluateFor( aItem, nullptr, static_cast<int>( aConstraint ), UNDEFINED_LAYER,
2798 aReporter );
2799 }
2800
2801 return false;
2802}
2803
2804
2805std::vector<PCB_LAYER_ID> getShowMatchPairLayers( const DRC_RULE& aRule, const BOARD_ITEM* aItemA,
2806 const BOARD_ITEM* aItemB, DRC_CONSTRAINT_T aConstraint )
2807{
2808 std::vector<PCB_LAYER_ID> layers;
2809 std::set<int> seenLayers;
2810
2811 auto addLayer =
2812 [&]( PCB_LAYER_ID aLayer )
2813 {
2814 if( aLayer != UNDEFINED_LAYER && !aRule.m_LayerCondition.test( aLayer ) )
2815 return;
2816
2817 if( seenLayers.insert( static_cast<int>( aLayer ) ).second )
2818 layers.push_back( aLayer );
2819 };
2820
2821 switch( aConstraint )
2822 {
2823 case EDGE_CLEARANCE_CONSTRAINT:
2824 for( PCB_LAYER_ID layer : getShowMatchLayers( aItemA ) )
2825 addLayer( layer );
2826
2827 break;
2828
2829 case COURTYARD_CLEARANCE_CONSTRAINT: addLayer( UNDEFINED_LAYER ); break;
2830
2831 default:
2832 for( PCB_LAYER_ID layer : getShowMatchLayers( aItemA ) )
2833 addLayer( layer );
2834
2835 for( PCB_LAYER_ID layer : getShowMatchLayers( aItemB ) )
2836 addLayer( layer );
2837
2838 break;
2839 }
2840
2841 if( layers.empty() )
2842 layers.push_back( UNDEFINED_LAYER );
2843
2844 return layers;
2845}
2846
2847
2848bool ruleMatchesPair( const DRC_RULE& aRule, const BOARD_ITEM* aItemA, const BOARD_ITEM* aItemB,
2849 DRC_CONSTRAINT_T aConstraint, REPORTER* aReporter )
2850{
2851 for( PCB_LAYER_ID layer : getShowMatchPairLayers( aRule, aItemA, aItemB, aConstraint ) )
2852 {
2853 if( !aRule.m_Condition
2854 || aRule.m_Condition->EvaluateFor( aItemA, aItemB, static_cast<int>( aConstraint ), layer, aReporter ) )
2855 {
2856 return true;
2857 }
2858 }
2859
2860 return false;
2861}
2862} // namespace
2863
2864
2865DRC_TEST_PROVIDER* DRC_ENGINE::GetTestProvider( const wxString& name ) const
2866{
2867 for( DRC_TEST_PROVIDER* prov : m_testProviders )
2868 {
2869 if( name == prov->GetName() )
2870 return prov;
2871 }
2872
2873 return nullptr;
2874}
2875
2876
2877std::vector<BOARD_ITEM*> DRC_ENGINE::GetItemsMatchingCondition( const wxString& aExpression,
2878 DRC_CONSTRAINT_T aConstraint,
2879 REPORTER* aReporter )
2880{
2881 wxLogTrace( wxS( "KI_TRACE_DRC_RULE_EDITOR" ), wxS( "[ShowMatches] engine enter: expr='%s', constraint=%d" ),
2882 aExpression, (int) aConstraint );
2883
2884 std::vector<BOARD_ITEM*> matches;
2885
2886 if( !m_board )
2887 return matches;
2888
2889 DRC_RULE_CONDITION condition( aExpression );
2890
2891 if( !condition.Compile( aReporter ? aReporter : m_logReporter ) )
2892 {
2893 wxLogTrace( wxS( "KI_TRACE_DRC_RULE_EDITOR" ), wxS( "[ShowMatches] engine: compile failed" ) );
2894 return matches;
2895 }
2896
2897 // Rebuild the from-to cache so that fromTo() expressions can be evaluated.
2898 // This cache requires explicit rebuilding before use since it depends on the full
2899 // connectivity graph being available.
2900 if( std::shared_ptr<CONNECTIVITY_DATA> connectivity = m_board->GetConnectivity() )
2901 {
2902 if( std::shared_ptr<FROM_TO_CACHE> ftCache = connectivity->GetFromToCache() )
2903 ftCache->Rebuild( m_board );
2904 }
2905
2906 BOARD_ITEM_SET items = m_board->GetItemSet();
2907 size_t totalItems = 0;
2908 size_t skippedItems = 0;
2909 size_t noLayerItems = 0;
2910 size_t checkedItems = 0;
2911
2912 for( auto& [kiid, item] : m_board->GetItemByIdCache() )
2913 {
2914 totalItems++;
2915
2916 // Skip items that don't have visible geometry or can't be meaningfully matched
2917 switch( item->Type() )
2918 {
2919 case PCB_NETINFO_T:
2920 case PCB_GENERATOR_T:
2921 case PCB_GROUP_T:
2922 case PCB_CONSTRAINT_T:
2923 skippedItems++;
2924 continue;
2925
2926 default:
2927 break;
2928 }
2929
2930 LSET itemLayers = item->GetLayerSet();
2931
2932 if( itemLayers.none() )
2933 {
2934 noLayerItems++;
2935 continue;
2936 }
2937
2938 checkedItems++;
2939 bool matched = false;
2940
2941 for( PCB_LAYER_ID layer : itemLayers )
2942 {
2943 if( condition.EvaluateFor( item, nullptr, static_cast<int>( aConstraint ), layer,
2944 aReporter ? aReporter : m_logReporter ) )
2945 {
2946 matches.push_back( item );
2947 wxLogTrace( wxS( "KI_TRACE_DRC_RULE_EDITOR" ),
2948 wxS( "[ShowMatches] engine: match type=%d kiid=%s layer=%d" ),
2949 (int) item->Type(), kiid.AsString(), (int) layer );
2950 matched = true;
2951 break; // No need to check other layers
2952 }
2953 }
2954
2955 // Log a few non-matching items to help debug condition issues
2956 if( !matched && matches.size() == 0 && checkedItems <= 5 )
2957 {
2958 wxLogTrace( wxS( "KI_TRACE_DRC_RULE_EDITOR" ),
2959 wxS( "[ShowMatches] engine: no-match sample type=%d kiid=%s layers=%s" ),
2960 (int) item->Type(), kiid.AsString(), itemLayers.FmtHex() );
2961 }
2962 }
2963
2964 wxLogTrace( wxS( "KI_TRACE_DRC_RULE_EDITOR" ),
2965 wxS( "[ShowMatches] engine stats: total=%zu skipped=%zu noLayer=%zu checked=%zu" ),
2966 totalItems, skippedItems, noLayerItems, checkedItems );
2967
2968 wxLogTrace( wxS( "KI_TRACE_DRC_RULE_EDITOR" ), wxS( "[ShowMatches] engine exit: total=%zu" ), matches.size() );
2969 return matches;
2970}
2971
2972
2973std::vector<BOARD_ITEM*> DRC_ENGINE::GetItemsMatchingRule( const std::shared_ptr<DRC_RULE>& aRule, REPORTER* aReporter )
2974{
2975 std::vector<BOARD_ITEM*> matches;
2976
2977 if( !m_board || !aRule )
2978 return matches;
2979
2980 const bool requiresPairwise = aRule->m_Condition && aRule->m_Condition->RequiresPairItems();
2981 std::set<BOARD_ITEM*> matchedItems;
2982
2983 if( std::shared_ptr<CONNECTIVITY_DATA> connectivity = m_board->GetConnectivity() )
2984 {
2985 if( std::shared_ptr<FROM_TO_CACHE> ftCache = connectivity->GetFromToCache() )
2986 ftCache->Rebuild( m_board );
2987 }
2988
2989 for( const DRC_CONSTRAINT& constraint : aRule->m_Constraints )
2990 {
2991 if( constraint.m_Type == NULL_CONSTRAINT )
2992 continue;
2993
2994 SHOWMATCH_DOMAIN_SPEC domainSpec = getShowMatchDomainSpec( constraint.m_Type );
2995 std::vector<BOARD_ITEM*> primaryItems = collectShowMatchCandidates( m_board, domainSpec.primary );
2996 std::vector<BOARD_ITEM*> secondaryItems;
2997
2998 if( domainSpec.hasSecondary )
2999 secondaryItems = collectShowMatchCandidates( m_board, domainSpec.secondary );
3000
3001 if( requiresPairwise )
3002 {
3003 if( secondaryItems.empty() )
3004 {
3005 for( size_t ii = 0; ii < primaryItems.size(); ++ii )
3006 {
3007 BOARD_ITEM* itemA = primaryItems[ii];
3008
3009 for( size_t jj = ii + 1; jj < primaryItems.size(); ++jj )
3010 {
3011 BOARD_ITEM* itemB = primaryItems[jj];
3012
3013 if( ruleMatchesPair( *aRule, itemA, itemB, constraint.m_Type,
3014 aReporter ? aReporter : m_logReporter ) )
3015 {
3016 matchedItems.insert( itemA );
3017 matchedItems.insert( itemB );
3018 }
3019 }
3020 }
3021 }
3022 else
3023 {
3024 for( BOARD_ITEM* itemA : primaryItems )
3025 {
3026 for( BOARD_ITEM* itemB : secondaryItems )
3027 {
3028 if( itemA == itemB )
3029 continue;
3030
3031 if( ruleMatchesPair( *aRule, itemA, itemB, constraint.m_Type,
3032 aReporter ? aReporter : m_logReporter ) )
3033 {
3034 matchedItems.insert( itemA );
3035 matchedItems.insert( itemB );
3036 }
3037 }
3038 }
3039 }
3040 }
3041 else
3042 {
3043 for( BOARD_ITEM* item : primaryItems )
3044 {
3045 if( ruleMatchesUnary( *aRule, item, constraint.m_Type, aReporter ? aReporter : m_logReporter ) )
3046 {
3047 matchedItems.insert( item );
3048 }
3049 }
3050
3051 if( domainSpec.hasSecondary && domainSpec.secondaryUnary )
3052 {
3053 for( BOARD_ITEM* item : secondaryItems )
3054 {
3055 if( ruleMatchesUnary( *aRule, item, constraint.m_Type, aReporter ? aReporter : m_logReporter ) )
3056 {
3057 matchedItems.insert( item );
3058 }
3059 }
3060 }
3061 }
3062 }
3063
3064 matches.assign( matchedItems.begin(), matchedItems.end() );
3065
3066 return matches;
3067}
3068
3069
3070int DRC_ENGINE::GetCachedOwnClearance( const BOARD_ITEM* aItem, PCB_LAYER_ID aLayer,
3071 wxString* aSource )
3072{
3073 DRC_OWN_CLEARANCE_CACHE_KEY key{ aItem->m_Uuid, aLayer };
3074
3075 // Fast path: check cache with shared (read) lock
3076 {
3077 std::shared_lock<std::shared_mutex> readLock( m_clearanceCacheMutex );
3078
3079 auto it = m_ownClearanceCache.find( key );
3080
3081 if( it != m_ownClearanceCache.end() )
3082 {
3083 // Cache hit. We don't cache the source string since it's rarely requested
3084 // and caching it would add complexity.
3085 return it->second;
3086 }
3087 }
3088
3089 // Cache miss - evaluate the constraint (outside lock to avoid blocking other threads)
3090 DRC_CONSTRAINT_T constraintType = CLEARANCE_CONSTRAINT;
3091
3092 if( aItem->Type() == PCB_PAD_T )
3093 {
3094 const PAD* pad = static_cast<const PAD*>( aItem );
3095
3096 if( pad->GetAttribute() == PAD_ATTRIB::NPTH )
3097 constraintType = HOLE_CLEARANCE_CONSTRAINT;
3098 }
3099
3100 DRC_CONSTRAINT constraint = EvalRules( constraintType, aItem, nullptr, aLayer );
3101
3102 int clearance = 0;
3103
3104 if( constraint.Value().HasMin() )
3105 {
3106 clearance = constraint.Value().Min();
3107
3108 if( aSource )
3109 *aSource = constraint.GetName();
3110 }
3111
3112 // Store in cache with exclusive (write) lock using double-checked locking
3113 {
3114 std::unique_lock<std::shared_mutex> writeLock( m_clearanceCacheMutex );
3115
3116 auto it = m_ownClearanceCache.find( key );
3117
3118 if( it == m_ownClearanceCache.end() )
3119 m_ownClearanceCache[key] = clearance;
3120 }
3121
3122 return clearance;
3123}
3124
3125
3126void DRC_ENGINE::InvalidateClearanceCache( const KIID& aUuid )
3127{
3128 std::unique_lock<std::shared_mutex> writeLock( m_clearanceCacheMutex );
3129
3130 if( m_board )
3131 {
3132 LSET copperLayers = m_board->GetEnabledLayers() & LSET::AllCuMask();
3133
3134 for( PCB_LAYER_ID layer : copperLayers.Seq() )
3135 m_ownClearanceCache.erase( DRC_OWN_CLEARANCE_CACHE_KEY{ aUuid, layer } );
3136 }
3137 else
3138 {
3139 auto it = m_ownClearanceCache.begin();
3140
3141 while( it != m_ownClearanceCache.end() )
3142 {
3143 if( it->first.m_uuid == aUuid )
3144 it = m_ownClearanceCache.erase( it );
3145 else
3146 ++it;
3147 }
3148 }
3149}
3150
3151
3152void DRC_ENGINE::ClearClearanceCache()
3153{
3154 std::unique_lock<std::shared_mutex> writeLock( m_clearanceCacheMutex );
3155 m_ownClearanceCache.clear();
3156}
3157
3158
3159void DRC_ENGINE::InitializeClearanceCache()
3160{
3161 if( !m_board )
3162 return;
3163
3164 // Pre-populate the cache for all connected items to avoid delays during first render.
3165 // We only need to cache copper layers since clearance outlines are only drawn on copper.
3166
3167 LSET copperLayers = m_board->GetEnabledLayers() & LSET::AllCuMask();
3168
3169 using CLEARANCE_MAP = std::unordered_map<DRC_OWN_CLEARANCE_CACHE_KEY, int>;
3170
3171 // Build flat list of (item, layer) pairs to process.
3172 // Estimate size based on tracks + pads * average layers (2 for typical TH pads).
3173 std::vector<std::pair<const BOARD_ITEM*, PCB_LAYER_ID>> itemsToProcess;
3174 size_t estimatedPads = 0;
3175
3176 for( FOOTPRINT* footprint : m_board->Footprints() )
3177 estimatedPads += footprint->Pads().size();
3178
3179 itemsToProcess.reserve( m_board->Tracks().size() + estimatedPads * 2 );
3180
3181 for( PCB_TRACK* track : m_board->Tracks() )
3182 {
3183 if( track->Type() == PCB_VIA_T )
3184 {
3185 for( PCB_LAYER_ID layer : LSET( track->GetLayerSet() & copperLayers ).Seq() )
3186 itemsToProcess.emplace_back( track, layer );
3187 }
3188 else
3189 {
3190 itemsToProcess.emplace_back( track, track->GetLayer() );
3191 }
3192 }
3193
3194 for( FOOTPRINT* footprint : m_board->Footprints() )
3195 {
3196 for( PAD* pad : footprint->Pads() )
3197 {
3198 for( PCB_LAYER_ID layer : LSET( pad->GetLayerSet() & copperLayers ).Seq() )
3199 itemsToProcess.emplace_back( pad, layer );
3200 }
3201 }
3202
3203 if( itemsToProcess.empty() )
3204 return;
3205
3206 {
3207 std::unique_lock<std::shared_mutex> writeLock( m_clearanceCacheMutex );
3208 m_ownClearanceCache.reserve( itemsToProcess.size() );
3209 }
3210
3211 thread_pool& tp = GetKiCadThreadPool();
3212
3213 auto processItems =
3214 [this]( size_t aStart, size_t aEnd, const std::vector<std::pair<const BOARD_ITEM*, PCB_LAYER_ID>>& aItems )
3215 -> CLEARANCE_MAP
3216 {
3217 CLEARANCE_MAP localCache;
3218
3219 for( size_t i = aStart; i < aEnd; ++i )
3220 {
3221 const BOARD_ITEM* item = aItems[i].first;
3222 PCB_LAYER_ID layer = aItems[i].second;
3223
3224 DRC_CONSTRAINT_T constraintType = CLEARANCE_CONSTRAINT;
3225
3226 if( item->Type() == PCB_PAD_T )
3227 {
3228 const PAD* pad = static_cast<const PAD*>( item );
3229
3230 if( pad->GetAttribute() == PAD_ATTRIB::NPTH )
3231 constraintType = HOLE_CLEARANCE_CONSTRAINT;
3232 }
3233
3234 DRC_CONSTRAINT constraint = EvalRules( constraintType, item, nullptr, layer );
3235
3236 int clearance = 0;
3237
3238 if( constraint.Value().HasMin() )
3239 clearance = constraint.Value().Min();
3240
3241 localCache[{ item->m_Uuid, layer }] = clearance;
3242 }
3243
3244 return localCache;
3245 };
3246
3247 auto results = tp.submit_blocks( 0, itemsToProcess.size(),
3248 [&]( size_t aStart, size_t aEnd ) -> CLEARANCE_MAP
3249 {
3250 return processItems( aStart, aEnd, itemsToProcess );
3251 } );
3252
3253 // Collect all results first WITHOUT holding the lock to avoid deadlock.
3254 // Worker threads call EvalRules() which needs a read lock on m_clearanceCacheMutex.
3255 // If we held a write lock while calling .get(), workers would block on the read lock
3256 // while we block waiting for them to complete.
3257 std::vector<CLEARANCE_MAP> collectedResults;
3258 collectedResults.reserve( results.size() );
3259
3260 for( size_t i = 0; i < results.size(); ++i )
3261 {
3262 if( results[i].valid() )
3263 collectedResults.push_back( results[i].get() );
3264 }
3265
3266 // Now merge with write lock held, but no blocking on futures
3267 {
3268 std::unique_lock<std::shared_mutex> writeLock( m_clearanceCacheMutex );
3269
3270 for( const auto& localCache : collectedResults )
3271 m_ownClearanceCache.insert( localCache.begin(), localCache.end() );
3272 }
3273}
name
const char * name
Definition DXF_plotter.cpp:60
pcbIUScale
constexpr EDA_IU_SCALE pcbIUScale
Definition base_units.h:121
BITMAPS::via
@ via
Definition bitmaps_list.h:658
BITMAPS::project
@ project
Definition bitmaps_list.h:478
BITMAPS::pad
@ pad
Definition bitmaps_list.h:412
BOARD_ITEM_SET
std::set< BOARD_ITEM *, CompareByUuid > BOARD_ITEM_SET
Set of BOARD_ITEMs ordered by UUID.
Definition board.h:357
board_design_settings.h
MAXIMUM_CLEARANCE
#define MAXIMUM_CLEARANCE
Definition board_design_settings.h:103
BOX2I
BOX2< VECTOR2I > BOX2I
Definition box2.h:918
KiROUND
constexpr BOX2I KiROUND(const BOX2D &aBoxD)
Definition box2.h:986
BASE_SET::FmtHex
std::string FmtHex() const
Return a hex string showing contents of this set.
Definition base_set.h:302
BOARD_COMMIT
Definition board_commit.h:45
BOARD_CONNECTED_ITEM
A base class derived from BOARD_ITEM for items that can be connected and have a net,...
Definition board_connected_item.h:42
BOARD_CONNECTED_ITEM::GetClearanceOverrides
virtual std::optional< int > GetClearanceOverrides(wxString *aSource) const
Return any clearance overrides set in the "classic" (ie: pre-rule) system.
Definition board_connected_item.h:169
BOARD_CONNECTED_ITEM::GetEffectiveNetClass
virtual NETCLASS * GetEffectiveNetClass() const
Return the NETCLASS for this item.
Definition board_connected_item.cpp:137
BOARD_CONNECTED_ITEM::GetLocalClearance
virtual std::optional< int > GetLocalClearance() const
Return any local clearances set in the "classic" (ie: pre-rule) system.
Definition board_connected_item.h:179
BOARD_DESIGN_SETTINGS
Container for design settings for a BOARD object.
Definition board_design_settings.h:249
BOARD_DESIGN_SETTINGS::m_MinConn
int m_MinConn
Definition board_design_settings.h:680
BOARD_DESIGN_SETTINGS::m_NetSettings
std::shared_ptr< NET_SETTINGS > m_NetSettings
Definition board_design_settings.h:735
BOARD_DESIGN_SETTINGS::m_CopperEdgeClearance
int m_CopperEdgeClearance
Definition board_design_settings.h:687
BOARD_DESIGN_SETTINGS::m_DRCSeverities
std::map< int, SEVERITY > m_DRCSeverities
Definition board_design_settings.h:696
BOARD_DESIGN_SETTINGS::m_ViasMinSize
int m_ViasMinSize
Definition board_design_settings.h:683
BOARD_DESIGN_SETTINGS::m_MicroViasMinSize
int m_MicroViasMinSize
Definition board_design_settings.h:685
BOARD_DESIGN_SETTINGS::m_MicroViasMinDrill
int m_MicroViasMinDrill
Definition board_design_settings.h:686
BOARD_DESIGN_SETTINGS::m_MinClearance
int m_MinClearance
Definition board_design_settings.h:678
BOARD_DESIGN_SETTINGS::m_MinSilkTextThickness
int m_MinSilkTextThickness
Definition board_design_settings.h:693
BOARD_DESIGN_SETTINGS::m_MinThroughDrill
int m_MinThroughDrill
Definition board_design_settings.h:684
BOARD_DESIGN_SETTINGS::m_MinResolvedSpokes
int m_MinResolvedSpokes
Definition board_design_settings.h:691
BOARD_DESIGN_SETTINGS::GetDRCEpsilon
int GetDRCEpsilon() const
Return an epsilon which accounts for rounding errors, etc.
Definition board_design_settings.cpp:1878
BOARD_DESIGN_SETTINGS::m_HoleToHoleMin
int m_HoleToHoleMin
Definition board_design_settings.h:689
BOARD_DESIGN_SETTINGS::m_MinSilkTextHeight
int m_MinSilkTextHeight
Definition board_design_settings.h:692
BOARD_DESIGN_SETTINGS::m_HoleClearance
int m_HoleClearance
Definition board_design_settings.h:688
BOARD_DESIGN_SETTINGS::m_SilkClearance
int m_SilkClearance
Definition board_design_settings.h:690
BOARD_DESIGN_SETTINGS::m_TrackMinWidth
int m_TrackMinWidth
Definition board_design_settings.h:681
BOARD_DESIGN_SETTINGS::m_ViasMinAnnularWidth
int m_ViasMinAnnularWidth
Definition board_design_settings.h:682
BOARD_ITEM
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition board_item.h:83
BOARD_ITEM::GetLayer
virtual PCB_LAYER_ID GetLayer() const
Return the primary layer this item is on.
Definition board_item.h:295
BOARD_ITEM::IsConnected
virtual bool IsConnected() const
Returns information if the object is derived from BOARD_CONNECTED_ITEM.
Definition board_item.h:159
BOARD_ITEM::IsOnLayer
virtual bool IsOnLayer(PCB_LAYER_ID aLayer) const
Test to see if this object is on the given layer.
Definition board_item.h:377
BOARD_ITEM::GetParentFootprint
FOOTPRINT * GetParentFootprint() const
Definition board_item.cpp:112
BOARD_ITEM::GetLayerSet
virtual LSET GetLayerSet() const
Return a std::bitset of all layers on which the item physically resides.
Definition board_item.h:315
BOARD_ITEM::IsOnCopperLayer
virtual bool IsOnCopperLayer() const
Definition board_item.h:176
BOARD_ITEM::HasHole
virtual bool HasHole() const
Definition board_item.h:181
BOARD
Information pertinent to a Pcbnew printed circuit board.
Definition board.h:373
BOARD::FindNet
NETINFO_ITEM * FindNet(int aNetcode) const
Search for a net with the given netcode.
Definition board.cpp:2777
BOARD::GetItemByIdCache
const std::unordered_map< KIID, BOARD_ITEM * > & GetItemByIdCache() const
Definition board.h:1564
BOX2::Intersects
constexpr bool Intersects(const BOX2< Vec > &aRect) const
Definition box2.h:307
DELAY_PROFILE_TRACK_PROPAGATION_ENTRY
Represents a single line in a time domain profile track propagation setup.
Definition tuning_profiles.h:82
DELAY_PROFILE_TRACK_PROPAGATION_ENTRY::GetDiffPairGap
int GetDiffPairGap() const
Definition tuning_profiles.h:100
DELAY_PROFILE_TRACK_PROPAGATION_ENTRY::GetWidth
int GetWidth() const
Definition tuning_profiles.h:99
DELAY_PROFILE_TRACK_PROPAGATION_ENTRY::GetSignalLayer
PCB_LAYER_ID GetSignalLayer() const
Definition tuning_profiles.h:95
DRC_CACHE_GENERATOR
Definition drc_cache_generator.h:29
DRC_CACHE_GENERATOR::Run
virtual bool Run() override
Run this provider against the given PCB with configured options (if any).
Definition drc_cache_generator.cpp:33
DRC_CONSTRAINT
Definition drc_rule.h:166
DRC_CONSTRAINT::GetName
wxString GetName() const
Definition drc_rule.h:204
DRC_CONSTRAINT::m_DisallowFlags
int m_DisallowFlags
Definition drc_rule.h:241
DRC_CONSTRAINT::SetParentRule
void SetParentRule(DRC_RULE *aParentRule)
Definition drc_rule.h:199
DRC_CONSTRAINT::Value
MINOPTMAX< int > & Value()
Definition drc_rule.h:197
DRC_CONSTRAINT::GetValue
const MINOPTMAX< int > & GetValue() const
Definition drc_rule.h:196
DRC_CONSTRAINT::m_ZoneConnection
ZONE_CONNECTION m_ZoneConnection
Definition drc_rule.h:242
DRC_CONSTRAINT::SetName
void SetName(const wxString &aName)
Definition drc_rule.h:202
DRC_CONSTRAINT::m_Value
MINOPTMAX< int > m_Value
Definition drc_rule.h:240
DRC_CONSTRAINT::m_Type
DRC_CONSTRAINT_T m_Type
Definition drc_rule.h:239
DRC_CONSTRAINT::SetOptionsFromOther
void SetOptionsFromOther(const DRC_CONSTRAINT &aOther)
Definition drc_rule.h:234
DRC_CONSTRAINT::GetParentRule
DRC_RULE * GetParentRule() const
Definition drc_rule.h:200
DRC_CONSTRAINT::m_ImplicitMin
bool m_ImplicitMin
Definition drc_rule.h:244
DRC_ENGINE::m_constraintMap
std::map< DRC_CONSTRAINT_T, std::vector< DRC_ENGINE_CONSTRAINT * > * > m_constraintMap
Definition drc_engine.h:376
DRC_ENGINE::EvalClearanceBatch
DRC_CLEARANCE_BATCH EvalClearanceBatch(const BOARD_ITEM *a, const BOARD_ITEM *b, PCB_LAYER_ID aLayer)
Evaluate all clearance-related constraints in a single batch call.
Definition drc_engine.cpp:2165
DRC_ENGINE::AdvanceProgress
void AdvanceProgress()
Definition drc_engine.cpp:2338
DRC_ENGINE::createImplicitRule
std::shared_ptr< DRC_RULE > createImplicitRule(const wxString &name, DRC_IMPLICIT_SOURCE aImplicitSource)
Definition drc_engine.cpp:147
DRC_ENGINE::RunTests
void RunTests(EDA_UNITS aUnits, bool aReportAllTrackErrors, bool aTestFootprints, BOARD_COMMIT *aCommit=nullptr)
Run the DRC tests.
Definition drc_engine.cpp:912
DRC_ENGINE::m_ownClearanceCache
std::unordered_map< DRC_OWN_CLEARANCE_CACHE_KEY, int > m_ownClearanceCache
Definition drc_engine.h:387
DRC_ENGINE::m_hasDiffPairClearanceOverrides
bool m_hasDiffPairClearanceOverrides
Definition drc_engine.h:399
DRC_ENGINE::m_testFootprints
bool m_testFootprints
Definition drc_engine.h:373
DRC_ENGINE::addRule
void addRule(std::shared_ptr< DRC_RULE > &rule)
Definition drc_engine.h:330
DRC_ENGINE::m_progressReporter
PROGRESS_REPORTER * m_progressReporter
Definition drc_engine.h:380
DRC_ENGINE::ClearClearanceCache
void ClearClearanceCache()
Clear the entire clearance cache.
Definition drc_engine.cpp:3152
DRC_ENGINE::loadRules
void loadRules(const wxFileName &aPath)
Load and parse a rule set from an sexpr text file.
Definition drc_engine.cpp:664
DRC_ENGINE::m_testProviders
std::vector< DRC_TEST_PROVIDER * > m_testProviders
Definition drc_engine.h:368
DRC_ENGINE::m_logReporter
REPORTER * m_logReporter
Definition drc_engine.h:379
DRC_ENGINE::m_explicitConstraints
std::map< DRC_CONSTRAINT_T, std::vector< DRC_ENGINE_CONSTRAINT * > > m_explicitConstraints
Definition drc_engine.h:400
DRC_ENGINE::compileRules
void compileRules()
Definition drc_engine.cpp:706
DRC_ENGINE::QueryDistinctConstraints
std::set< int > QueryDistinctConstraints(DRC_CONSTRAINT_T aConstraintId)
Definition drc_engine.cpp:2432
DRC_ENGINE::m_hasGeometryDependentRules
bool m_hasGeometryDependentRules
Definition drc_engine.h:398
DRC_ENGINE::m_drawingSheet
DS_PROXY_VIEW_ITEM * m_drawingSheet
Definition drc_engine.h:363
DRC_ENGINE::m_schematicNetlist
NETLIST * m_schematicNetlist
Definition drc_engine.h:364
DRC_ENGINE::m_clearanceCacheMutex
std::shared_mutex m_clearanceCacheMutex
Definition drc_engine.h:396
DRC_ENGINE::KeepRefreshing
bool KeepRefreshing(bool aWait=false)
Definition drc_engine.cpp:2329
DRC_ENGINE::GetItemsMatchingRule
std::vector< BOARD_ITEM * > GetItemsMatchingRule(const std::shared_ptr< DRC_RULE > &aRule, REPORTER *aReporter=nullptr)
Definition drc_engine.cpp:2973
DRC_ENGINE::m_board
BOARD * m_board
Definition drc_engine.h:362
DRC_ENGINE::GetCachedOwnClearance
int GetCachedOwnClearance(const BOARD_ITEM *aItem, PCB_LAYER_ID aLayer, wxString *aSource=nullptr)
Get the cached own clearance for an item on a specific layer.
Definition drc_engine.cpp:3070
DRC_ENGINE::m_reportAllTrackErrors
bool m_reportAllTrackErrors
Definition drc_engine.h:372
DRC_ENGINE::ReportProgress
bool ReportProgress(double aProgress)
Definition drc_engine.cpp:2352
DRC_ENGINE::GetTestProvider
DRC_TEST_PROVIDER * GetTestProvider(const wxString &name) const
Definition drc_engine.cpp:2865
DRC_ENGINE::HasRulesForConstraintType
bool HasRulesForConstraintType(DRC_CONSTRAINT_T constraintID)
Definition drc_engine.cpp:2378
DRC_ENGINE::GetDesignSettings
BOARD_DESIGN_SETTINGS * GetDesignSettings() const
Definition drc_engine.h:146
DRC_ENGINE::SetMaxProgress
void SetMaxProgress(int aSize)
Definition drc_engine.cpp:2345
DRC_ENGINE::DRC_ENGINE
DRC_ENGINE(BOARD *aBoard=nullptr, BOARD_DESIGN_SETTINGS *aSettings=nullptr)
Definition drc_engine.cpp:85
DRC_ENGINE::m_hasExplicitClearanceRules
bool m_hasExplicitClearanceRules
Definition drc_engine.h:397
DRC_ENGINE::m_errorLimits
std::vector< int > m_errorLimits
Definition drc_engine.h:370
DRC_ENGINE::IsErrorLimitExceeded
bool IsErrorLimitExceeded(int error_code)
Definition drc_engine.cpp:2275
DRC_ENGINE::ProcessAssertions
void ProcessAssertions(const BOARD_ITEM *a, std::function< void(const DRC_CONSTRAINT *)> aFailureHandler, REPORTER *aReporter=nullptr)
Definition drc_engine.cpp:2200
DRC_ENGINE::loadImplicitRules
void loadImplicitRules()
Definition drc_engine.cpp:161
DRC_ENGINE::m_violationHandler
DRC_VIOLATION_HANDLER m_violationHandler
Definition drc_engine.h:378
DRC_ENGINE::EvalRules
DRC_CONSTRAINT EvalRules(DRC_CONSTRAINT_T aConstraintType, const BOARD_ITEM *a, const BOARD_ITEM *b, PCB_LAYER_ID aLayer, REPORTER *aReporter=nullptr)
Definition drc_engine.cpp:1006
DRC_ENGINE::m_rules
std::vector< std::shared_ptr< DRC_RULE > > m_rules
Definition drc_engine.h:366
DRC_ENGINE::QueryWorstConstraint
bool QueryWorstConstraint(DRC_CONSTRAINT_T aRuleId, DRC_CONSTRAINT &aConstraint, bool aUnconditionalOnly=false)
Definition drc_engine.cpp:2385
DRC_ENGINE::IsCancelled
bool IsCancelled() const
Definition drc_engine.cpp:2372
DRC_ENGINE::m_netclassClearances
std::unordered_map< wxString, int > m_netclassClearances
Definition drc_engine.h:392
DRC_ENGINE::IsNetTieExclusion
bool IsNetTieExclusion(int aTrackNetCode, PCB_LAYER_ID aTrackLayer, const VECTOR2I &aCollisionPos, BOARD_ITEM *aCollidingItem)
Check if the given collision between a track and another item occurs during the track's entry into a ...
Definition drc_engine.cpp:2531
DRC_ENGINE::~DRC_ENGINE
virtual ~DRC_ENGINE()
Definition drc_engine.cpp:104
DRC_ENGINE::GetItemsMatchingCondition
std::vector< BOARD_ITEM * > GetItemsMatchingCondition(const wxString &aExpression, DRC_CONSTRAINT_T aConstraint=ASSERTION_CONSTRAINT, REPORTER *aReporter=nullptr)
Evaluate a DRC condition against all board items and return matches.
Definition drc_engine.cpp:2877
DRC_ENGINE::InitEngine
void InitEngine(const wxFileName &aRulePath)
Initialize the DRC engine.
Definition drc_engine.cpp:834
DRC_ENGINE::EvalZoneConnection
DRC_CONSTRAINT EvalZoneConnection(const BOARD_ITEM *a, const BOARD_ITEM *b, PCB_LAYER_ID aLayer, REPORTER *aReporter=nullptr)
Definition drc_engine.cpp:972
DRC_ENGINE::MatchDpSuffix
static int MatchDpSuffix(const wxString &aNetName, wxString &aComplementNet, wxString &aBaseDpName)
Check if the given net is a diff pair, returning its polarity and complement if so.
Definition drc_engine.cpp:2448
DRC_ENGINE::ReportPhase
bool ReportPhase(const wxString &aMessage)
Definition drc_engine.cpp:2362
DRC_ENGINE::IsNetADiffPair
static bool IsNetADiffPair(BOARD *aBoard, const NETINFO_ITEM *aNet, int &aNetP, int &aNetN)
Definition drc_engine.cpp:2497
DRC_ENGINE::InitializeClearanceCache
void InitializeClearanceCache()
Initialize the clearance cache for all items on the board.
Definition drc_engine.cpp:3159
DRC_ENGINE::m_rulesValid
bool m_rulesValid
Definition drc_engine.h:367
DRC_ENGINE::InvalidateClearanceCache
void InvalidateClearanceCache(const KIID &aUuid)
Invalidate the clearance cache for a specific item.
Definition drc_engine.cpp:3126
DRC_ENGINE::m_designSettings
BOARD_DESIGN_SETTINGS * m_designSettings
Definition drc_engine.h:361
DRC_ENGINE::HasUserDefinedPhysicalConstraint
bool HasUserDefinedPhysicalConstraint()
Definition drc_engine.cpp:2412
DRC_ENGINE::ReportViolation
void ReportViolation(const std::shared_ptr< DRC_ITEM > &aItem, const VECTOR2I &aPos, int aMarkerLayer, const std::function< void(PCB_MARKER *)> &aPathGenerator={})
Definition drc_engine.cpp:2283
DRC_ENGINE::m_errorLimitsMutex
std::mutex m_errorLimitsMutex
Definition drc_engine.h:371
DRC_ITEM
Definition drc_item.h:128
DRC_ITEM::SetViolatingRule
void SetViolatingRule(DRC_RULE *aRule)
Definition drc_item.h:169
DRC_RULES_PARSER
Definition drc_rule_parser.h:38
DRC_RULES_PARSER::Parse
void Parse(std::vector< std::shared_ptr< DRC_RULE > > &aRules, REPORTER *aReporter)
Definition drc_rule_parser.cpp:166
DRC_RULE_CONDITION
Definition drc_rule_condition.h:32
DRC_RULE_CONDITION::Compile
bool Compile(REPORTER *aReporter, int aSourceLine=0, int aSourceOffset=0)
Definition drc_rule_condition.cpp:123
DRC_RULE_CONDITION::GetExpression
wxString GetExpression() const
Definition drc_rule_condition.h:43
DRC_RULE_CONDITION::EvaluateFor
bool EvaluateFor(const BOARD_ITEM *aItemA, const BOARD_ITEM *aItemB, int aConstraint, PCB_LAYER_ID aLayer, REPORTER *aReporter=nullptr)
Definition drc_rule_condition.cpp:39
DRC_RULE
Definition drc_rule.h:125
DRC_RULE::m_Condition
DRC_RULE_CONDITION * m_Condition
Definition drc_rule.h:156
DRC_RULE::IsImplicit
bool IsImplicit() const
Definition drc_rule.h:143
DRC_RULE::m_LayerCondition
LSET m_LayerCondition
Definition drc_rule.h:155
DRC_RULE::m_Name
wxString m_Name
Definition drc_rule.h:153
DRC_RULE::m_LayerSource
wxString m_LayerSource
Definition drc_rule.h:154
DRC_RULE::GetImplicitSource
DRC_IMPLICIT_SOURCE GetImplicitSource() const
Definition drc_rule.h:147
DRC_SHOWMATCHES_PROVIDER_REGISTRY::GetShowMatchesProviders
std::vector< DRC_TEST_PROVIDER * > GetShowMatchesProviders() const
Definition drc_test_provider.h:81
DRC_SHOWMATCHES_PROVIDER_REGISTRY::Instance
static DRC_SHOWMATCHES_PROVIDER_REGISTRY & Instance()
Definition drc_test_provider.h:74
DRC_TEST_PROVIDER_REGISTRY::GetTestProviders
std::vector< DRC_TEST_PROVIDER * > GetTestProviders() const
Definition drc_test_provider.h:50
DRC_TEST_PROVIDER_REGISTRY::Instance
static DRC_TEST_PROVIDER_REGISTRY & Instance()
Definition drc_test_provider.h:43
DRC_TEST_PROVIDER
Represent a DRC "provider" which runs some DRC functions over a BOARD and spits out DRC_ITEM and posi...
Definition drc_test_provider.h:103
DRC_TEST_PROVIDER::Init
static void Init()
Definition drc_test_provider.cpp:59
DRC_TEST_PROVIDER::SetDRCEngine
void SetDRCEngine(DRC_ENGINE *engine)
Definition drc_test_provider.h:110
EDA_ITEM::GetBoundingBox
virtual const BOX2I GetBoundingBox() const
Return the orthogonal bounding box of this object for display purposes.
Definition eda_item.cpp:135
EDA_ITEM::GetItemDescription
virtual wxString GetItemDescription(UNITS_PROVIDER *aUnitsProvider, bool aFull) const
Return a user-visible description string of this item.
Definition eda_item.cpp:169
EDA_ITEM::m_Uuid
const KIID m_Uuid
Definition eda_item.h:531
EDA_ITEM::Type
KICAD_T Type() const
Returns the type of object.
Definition eda_item.h:108
EDA_ITEM::GetFlags
EDA_ITEM_FLAGS GetFlags() const
Definition eda_item.h:155
FILE_LINE_READER
A LINE_READER that reads from an open file.
Definition richio.h:154
FILE_LINE_READER::ReadLine
char * ReadLine() override
Read a line of text into the buffer and increments the line number counter.
Definition richio.cpp:204
FOOTPRINT::GetLocalZoneConnection
ZONE_CONNECTION GetLocalZoneConnection() const
Definition footprint.h:492
FOOTPRINT::MapPadNumbersToNetTieGroups
std::map< wxString, int > MapPadNumbersToNetTieGroups() const
Definition footprint.cpp:4078
FOOTPRINT::Pads
std::deque< PAD * > & Pads()
Definition footprint.h:375
FOOTPRINT::GetNetTieCache
const std::set< int > & GetNetTieCache(const BOARD_ITEM *aItem) const
Get the set of net codes that are allowed to connect to a footprint item.
Definition footprint.h:752
FOOTPRINT::IsNetTie
bool IsNetTie() const
Definition footprint.h:523
FOOTPRINT::GetItemDescription
wxString GetItemDescription(UNITS_PROVIDER *aUnitsProvider, bool aFull) const override
Return a user-visible description string of this item.
Definition footprint.cpp:2806
FOOTPRINT::GetCourtyard
const SHAPE_POLY_SET & GetCourtyard(PCB_LAYER_ID aLayer) const
Used in DRC to test the courtyard area (a complex polygon).
Definition footprint.cpp:3867
KIID
Definition kiid.h:46
KIID::AsString
wxString AsString() const
Definition kiid.cpp:264
LSET
LSET is a set of PCB_LAYER_IDs.
Definition lset.h:37
LSET::FrontMask
static const LSET & FrontMask()
Return a mask holding all technical layers and the external CU layer on front side.
Definition lset.cpp:718
LSET::AllCuMask
static const LSET & AllCuMask()
return AllCuMask( MAX_CU_LAYERS );
Definition lset.cpp:604
LSET::BackMask
static const LSET & BackMask()
Return a mask holding all technical layers and the external CU layer on back side.
Definition lset.cpp:725
LSET::Seq
LSEQ Seq(const LSEQ &aSequence) const
Return an LSEQ from the union of this LSET and a desired sequence.
Definition lset.cpp:309
LSET::Name
static wxString Name(PCB_LAYER_ID aLayerId)
Return the fixed name association with aLayerId.
Definition lset.cpp:184
MINOPTMAX::Min
T Min() const
Definition minoptmax.h:29
MINOPTMAX::SetMin
void SetMin(T v)
Definition minoptmax.h:38
MINOPTMAX::SetOpt
void SetOpt(T v)
Definition minoptmax.h:40
MINOPTMAX::HasMin
bool HasMin() const
Definition minoptmax.h:34
MINOPTMAX::SetMax
void SetMax(T v)
Definition minoptmax.h:39
NETCLASS
A collection of nets and the parameters used to route or test these nets.
Definition netclass.h:38
NETCLASS::GetName
const wxString GetName() const
Gets the name of this (maybe aggregate) netclass in a format for internal usage or for export to exte...
Definition netclass.cpp:354
NETINFO_ITEM
Handle the data for a net.
Definition netinfo.h:46
NETINFO_ITEM::GetNetname
const wxString & GetNetname() const
Definition netinfo.h:100
NETINFO_ITEM::GetNetCode
int GetNetCode() const
Definition netinfo.h:94
NET_SETTINGS::GetCompositeNetclasses
const std::map< wxString, std::shared_ptr< NETCLASS > > & GetCompositeNetclasses() const
Gets all composite (multiple assignment / missing defaults) netclasses.
Definition net_settings.cpp:692
NET_SETTINGS::GetNetclasses
const std::map< wxString, std::shared_ptr< NETCLASS > > & GetNetclasses() const
Gets all netclasses.
Definition net_settings.cpp:686
NET_SETTINGS::GetDefaultNetclass
std::shared_ptr< NETCLASS > GetDefaultNetclass() const
Gets the default netclass for the project.
Definition net_settings.cpp:661
PAD
Definition pad.h:61
PCB_MARKER
Definition pcb_marker.h:34
PCB_SHAPE
Definition pcb_shape.h:35
PCB_SHAPE::GetLocalSolderMaskMargin
std::optional< int > GetLocalSolderMaskMargin() const
Definition pcb_shape.h:332
PCB_TRACK
Definition pcb_track.h:57
PCB_VIA
Definition pcb_track.h:355
PROF_TIMER
A small class to help profiling.
Definition profile.h:46
PROF_TIMER::Stop
void Stop()
Save the time when this function was called, and set the counter stane to stop.
Definition profile.h:86
PROF_TIMER::msecs
double msecs(bool aSinceLast=false)
Definition profile.h:147
PROJECT
Container for project specific data.
Definition project.h:63
REPORTER
A pure virtual class used to derive REPORTER objects from.
Definition reporter.h:72
REPORTER::HasMessageOfSeverity
virtual bool HasMessageOfSeverity(int aSeverityMask) const
Returns true if the reporter has one or more messages matching the specified severity mask.
Definition reporter.h:142
SHAPE_POLY_SET::IsEmpty
bool IsEmpty() const
Return true if the set is empty (no polygons at all)
Definition shape_poly_set.h:1292
UNITS_PROVIDER::GetIuScale
const EDA_IU_SCALE & GetIuScale() const
Definition units_provider.h:51
UNITS_PROVIDER::MessageTextFromUnscaledValue
wxString MessageTextFromUnscaledValue(double aValue, bool aAddUnitLabel=true, EDA_DATA_TYPE aType=EDA_DATA_TYPE::DISTANCE) const
Definition units_provider.h:137
UNITS_PROVIDER::UNITS_PROVIDER
UNITS_PROVIDER(const EDA_IU_SCALE &aIuScale, EDA_UNITS aUnits)
Definition units_provider.h:33
UNITS_PROVIDER::MessageTextFromValue
wxString MessageTextFromValue(double aValue, bool aAddUnitLabel=true, EDA_DATA_TYPE aType=EDA_DATA_TYPE::DISTANCE) const
A lower-precision version of StringFromValue().
Definition units_provider.h:123
UNITS_PROVIDER::SetUserUnits
void SetUserUnits(EDA_UNITS aUnits)
Definition units_provider.h:42
ZONE
Handle a list of polygons defining a copper zone.
Definition zone.h:70
ZONE::GetItemDescription
wxString GetItemDescription(UNITS_PROVIDER *aUnitsProvider, bool aFull) const override
Return a user-visible description string of this item.
Definition zone.cpp:1430
ZONE::GetIsRuleArea
bool GetIsRuleArea() const
Accessors to parameters used in Rule Area zones:
Definition zone.h:813
ZONE::GetDoNotAllowVias
bool GetDoNotAllowVias() const
Definition zone.h:824
ZONE::GetDoNotAllowPads
bool GetDoNotAllowPads() const
Definition zone.h:826
ZONE::GetBoundingBox
const BOX2I GetBoundingBox() const override
Definition zone.cpp:766
ZONE::GetDoNotAllowTracks
bool GetDoNotAllowTracks() const
Definition zone.h:825
ZONE::GetZoneName
const wxString & GetZoneName() const
Definition zone.h:160
ZONE::GetMinThickness
int GetMinThickness() const
Definition zone.h:315
ZONE::GetPadConnection
ZONE_CONNECTION GetPadConnection() const
Definition zone.h:312
ZONE::GetThermalReliefSpokeWidth
int GetThermalReliefSpokeWidth() const
Definition zone.h:259
ZONE::GetDoNotAllowFootprints
bool GetDoNotAllowFootprints() const
Definition zone.h:827
ZONE::GetLayerSet
virtual LSET GetLayerSet() const override
Return a std::bitset of all layers on which the item physically resides.
Definition zone.h:133
ZONE::HasKeepoutParametersSet
bool HasKeepoutParametersSet() const
Accessor to determine if any keepout parameters are set.
Definition zone.h:804
ZONE::GetDoNotAllowZoneFills
bool GetDoNotAllowZoneFills() const
Definition zone.h:823
ZONE::GetThermalReliefGap
int GetThermalReliefGap() const
Definition zone.h:248
ExpandTextVars
wxString ExpandTextVars(const wxString &aSource, const PROJECT *aProject, int aFlags)
Definition common.cpp:59
DescribeRef
wxString DescribeRef(const wxString &aRef)
Returns a user-visible HTML string describing a footprint reference designator.
Definition common.cpp:478
common.h
The common library.
component_class_manager.h
connectivity_data.h
drc_cache_generator.h
drcPrintDebugMessage
void drcPrintDebugMessage(int level, const wxString &msg, const char *function, int line)
Definition drc_engine.cpp:71
EXTENDED_ERROR_LIMIT
#define EXTENDED_ERROR_LIMIT
Definition drc_engine.cpp:58
isKeepoutZone
static bool isKeepoutZone(const BOARD_ITEM *aItem, bool aCheckFlags)
Definition drc_engine.cpp:118
ERROR_LIMIT
#define ERROR_LIMIT
Definition drc_engine.cpp:57
drc_engine.h
drc_item.h
DRCE_TUNING_PROFILE_IMPLICIT_RULES
@ DRCE_TUNING_PROFILE_IMPLICIT_RULES
Definition drc_item.h:115
DRCE_UNCONNECTED_ITEMS
@ DRCE_UNCONNECTED_ITEMS
Definition drc_item.h:37
DRCE_CLEARANCE
@ DRCE_CLEARANCE
Definition drc_item.h:41
DRCE_FIRST
@ DRCE_FIRST
Definition drc_item.h:36
DRCE_LAST
@ DRCE_LAST
Definition drc_item.h:123
drc_rtree.h
IsComponentClassSelector
bool IsComponentClassSelector(const wxString &aToken)
${Class:X} inside a DRC rule is a component-class selector consumed by testFootprintSelector(),...
Definition drc_rule.cpp:30
drc_rule.h
DRC_IMPLICIT_SOURCE
DRC_IMPLICIT_SOURCE
Definition drc_rule.h:110
DRC_IMPLICIT_SOURCE::BARCODE_DEFAULTS
@ BARCODE_DEFAULTS
Definition drc_rule.h:113
DRC_IMPLICIT_SOURCE::TUNING_PROFILE
@ TUNING_PROFILE
Definition drc_rule.h:116
DRC_IMPLICIT_SOURCE::NET_CLASS
@ NET_CLASS
Definition drc_rule.h:115
DRC_IMPLICIT_SOURCE::KEEPOUT
@ KEEPOUT
Definition drc_rule.h:114
DRC_IMPLICIT_SOURCE::BOARD_SETUP_CONSTRAINT
@ BOARD_SETUP_CONSTRAINT
Definition drc_rule.h:112
DRC_DISALLOW_PADS
@ DRC_DISALLOW_PADS
Definition drc_rule.h:100
DRC_DISALLOW_BURIED_VIAS
@ DRC_DISALLOW_BURIED_VIAS
Definition drc_rule.h:98
DRC_DISALLOW_BLIND_VIAS
@ DRC_DISALLOW_BLIND_VIAS
Definition drc_rule.h:97
DRC_DISALLOW_TEXTS
@ DRC_DISALLOW_TEXTS
Definition drc_rule.h:102
DRC_DISALLOW_ZONES
@ DRC_DISALLOW_ZONES
Definition drc_rule.h:101
DRC_DISALLOW_HOLES
@ DRC_DISALLOW_HOLES
Definition drc_rule.h:104
DRC_DISALLOW_GRAPHICS
@ DRC_DISALLOW_GRAPHICS
Definition drc_rule.h:103
DRC_DISALLOW_THROUGH_VIAS
@ DRC_DISALLOW_THROUGH_VIAS
Definition drc_rule.h:95
DRC_DISALLOW_FOOTPRINTS
@ DRC_DISALLOW_FOOTPRINTS
Definition drc_rule.h:105
DRC_DISALLOW_TRACKS
@ DRC_DISALLOW_TRACKS
Definition drc_rule.h:99
DRC_DISALLOW_MICRO_VIAS
@ DRC_DISALLOW_MICRO_VIAS
Definition drc_rule.h:96
DRC_CONSTRAINT_T
DRC_CONSTRAINT_T
Definition drc_rule.h:49
ANNULAR_WIDTH_CONSTRAINT
@ ANNULAR_WIDTH_CONSTRAINT
Definition drc_rule.h:63
COURTYARD_CLEARANCE_CONSTRAINT
@ COURTYARD_CLEARANCE_CONSTRAINT
Definition drc_rule.h:57
VIA_DIAMETER_CONSTRAINT
@ VIA_DIAMETER_CONSTRAINT
Definition drc_rule.h:72
ZONE_CONNECTION_CONSTRAINT
@ ZONE_CONNECTION_CONSTRAINT
Definition drc_rule.h:64
DIFF_PAIR_GAP_CONSTRAINT
@ DIFF_PAIR_GAP_CONSTRAINT
Definition drc_rule.h:78
NET_CHAIN_LENGTH_CONSTRAINT
@ NET_CHAIN_LENGTH_CONSTRAINT
Definition drc_rule.h:74
SOLDER_MASK_SLIVER_CONSTRAINT
@ SOLDER_MASK_SLIVER_CONSTRAINT
Definition drc_rule.h:89
NET_CHAIN_STUB_LENGTH_CONSTRAINT
@ NET_CHAIN_STUB_LENGTH_CONSTRAINT
Definition drc_rule.h:75
DISALLOW_CONSTRAINT
@ DISALLOW_CONSTRAINT
Definition drc_rule.h:71
TRACK_WIDTH_CONSTRAINT
@ TRACK_WIDTH_CONSTRAINT
Definition drc_rule.h:61
SILK_CLEARANCE_CONSTRAINT
@ SILK_CLEARANCE_CONSTRAINT
Definition drc_rule.h:58
EDGE_CLEARANCE_CONSTRAINT
@ EDGE_CLEARANCE_CONSTRAINT
Definition drc_rule.h:55
MIN_RESOLVED_SPOKES_CONSTRAINT
@ MIN_RESOLVED_SPOKES_CONSTRAINT
Definition drc_rule.h:67
TRACK_SEGMENT_LENGTH_CONSTRAINT
@ TRACK_SEGMENT_LENGTH_CONSTRAINT
Definition drc_rule.h:62
TEXT_THICKNESS_CONSTRAINT
@ TEXT_THICKNESS_CONSTRAINT
Definition drc_rule.h:60
LENGTH_CONSTRAINT
@ LENGTH_CONSTRAINT
Definition drc_rule.h:73
VIA_COUNT_CONSTRAINT
@ VIA_COUNT_CONSTRAINT
Definition drc_rule.h:81
NET_CHAIN_RETURN_PATH_CONSTRAINT
@ NET_CHAIN_RETURN_PATH_CONSTRAINT
Definition drc_rule.h:76
PHYSICAL_HOLE_CLEARANCE_CONSTRAINT
@ PHYSICAL_HOLE_CLEARANCE_CONSTRAINT
Definition drc_rule.h:83
CLEARANCE_CONSTRAINT
@ CLEARANCE_CONSTRAINT
Definition drc_rule.h:51
NULL_CONSTRAINT
@ NULL_CONSTRAINT
Definition drc_rule.h:50
THERMAL_SPOKE_WIDTH_CONSTRAINT
@ THERMAL_SPOKE_WIDTH_CONSTRAINT
Definition drc_rule.h:66
CONNECTION_WIDTH_CONSTRAINT
@ CONNECTION_WIDTH_CONSTRAINT
Definition drc_rule.h:85
THERMAL_RELIEF_GAP_CONSTRAINT
@ THERMAL_RELIEF_GAP_CONSTRAINT
Definition drc_rule.h:65
MAX_UNCOUPLED_CONSTRAINT
@ MAX_UNCOUPLED_CONSTRAINT
Definition drc_rule.h:79
ASSERTION_CONSTRAINT
@ ASSERTION_CONSTRAINT
Definition drc_rule.h:84
SKEW_CONSTRAINT
@ SKEW_CONSTRAINT
Definition drc_rule.h:77
HOLE_CLEARANCE_CONSTRAINT
@ HOLE_CLEARANCE_CONSTRAINT
Definition drc_rule.h:53
SOLDER_PASTE_ABS_MARGIN_CONSTRAINT
@ SOLDER_PASTE_ABS_MARGIN_CONSTRAINT
Definition drc_rule.h:69
SOLDER_MASK_EXPANSION_CONSTRAINT
@ SOLDER_MASK_EXPANSION_CONSTRAINT
Definition drc_rule.h:68
TRACK_ANGLE_CONSTRAINT
@ TRACK_ANGLE_CONSTRAINT
Definition drc_rule.h:86
HOLE_SIZE_CONSTRAINT
@ HOLE_SIZE_CONSTRAINT
Definition drc_rule.h:56
TEXT_HEIGHT_CONSTRAINT
@ TEXT_HEIGHT_CONSTRAINT
Definition drc_rule.h:59
CREEPAGE_CONSTRAINT
@ CREEPAGE_CONSTRAINT
Definition drc_rule.h:52
PHYSICAL_CLEARANCE_CONSTRAINT
@ PHYSICAL_CLEARANCE_CONSTRAINT
Definition drc_rule.h:82
SOLDER_PASTE_REL_MARGIN_CONSTRAINT
@ SOLDER_PASTE_REL_MARGIN_CONSTRAINT
Definition drc_rule.h:70
HOLE_TO_HOLE_CONSTRAINT
@ HOLE_TO_HOLE_CONSTRAINT
Definition drc_rule.h:54
DRC_DISALLOW_VIAS
constexpr int DRC_DISALLOW_VIAS
Definition drc_rule.h:120
drc_rule_condition.h
drc_rule_parser.h
drc_test_provider.h
_
#define _(s)
Definition eda_3d_actions.cpp:36
HOLE_PROXY
#define HOLE_PROXY
Indicates the BOARD_ITEM is a proxy for its hole.
Definition eda_item_flags.h:61
EDA_UNITS
EDA_UNITS
Definition eda_units.h:44
resolver
static FILENAME_RESOLVER * resolver
Definition export_idf.cpp:49
from_to_cache.h
traceDrcProfile
static const wxChar * traceDrcProfile
Flag to enable DRC profile timing logging.
Definition drc_engine.cpp:68
THROW_PARSE_ERROR
#define THROW_PARSE_ERROR(aProblem, aSource, aInputLine, aLineNumber, aByteIndex)
Definition ki_exception.h:163
IsPcbLayer
bool IsPcbLayer(int aLayer)
Test whether a layer is a valid layer for Pcbnew.
Definition layer_ids.h:672
PCB_LAYER_ID
PCB_LAYER_ID
A quick note on layer IDs:
Definition layer_ids.h:56
F_CrtYd
@ F_CrtYd
Definition layer_ids.h:112
B_Adhes
@ B_Adhes
Definition layer_ids.h:99
Edge_Cuts
@ Edge_Cuts
Definition layer_ids.h:108
F_Paste
@ F_Paste
Definition layer_ids.h:100
F_Adhes
@ F_Adhes
Definition layer_ids.h:98
B_Mask
@ B_Mask
Definition layer_ids.h:94
F_Mask
@ F_Mask
Definition layer_ids.h:93
B_Paste
@ B_Paste
Definition layer_ids.h:101
F_Fab
@ F_Fab
Definition layer_ids.h:115
Margin
@ Margin
Definition layer_ids.h:109
F_SilkS
@ F_SilkS
Definition layer_ids.h:96
B_CrtYd
@ B_CrtYd
Definition layer_ids.h:111
UNDEFINED_LAYER
@ UNDEFINED_LAYER
Definition layer_ids.h:57
B_SilkS
@ B_SilkS
Definition layer_ids.h:97
B_Fab
@ B_Fab
Definition layer_ids.h:114
VISIBILITY_LAYER::VIAS
@ VIAS
Definition layer_settings_utils.h:35
REPORT
#define REPORT(msg)
Definition lib_symbol.cpp:2131
net_settings.h
PAD_ATTRIB::NPTH
@ NPTH
like PAD_PTH, but not plated mechanical use only, no connection allowed
Definition padstack.h:103
PAD_ATTRIB::PTH
@ PTH
Plated through hole pad.
Definition padstack.h:98
PADS
std::deque< PAD * > PADS
Definition pcb_item_containers.h:55
FOOTPRINTS
std::deque< FOOTPRINT * > FOOTPRINTS
Definition pcb_item_containers.h:39
pcb_marker.h
pcb_shape.h
pcb_track.h
progress_reporter.h
project_file.h
RPT_SEVERITY_ERROR
@ RPT_SEVERITY_ERROR
Definition report_severity.h:35
epsilon
const double epsilon
Definition resistor_substitution_utils.h:30
dummy
std::vector< FAB_LAYER_COLOR > dummy
Definition stackup_predefined_prms.cpp:93
EscapeHTML
wxString EscapeHTML(const wxString &aString)
Return a new wxString escaped for embedding in HTML.
Definition string_utils.cpp:569
string_utils.h
TO_UTF8
#define TO_UTF8(wxstring)
Convert a wxString to a UTF8 encoded C string for all wxWidgets build modes.
Definition string_utils.h:451
DRC_CLEARANCE_BATCH
Batch result for clearance-related constraints to reduce per-query overhead during PNS routing.
Definition drc_engine.h:109
DRC_ENGINE::DRC_ENGINE_CONSTRAINT
Definition drc_engine.h:345
DRC_ENGINE::DRC_ENGINE_CONSTRAINT::implicitKeepoutZone
ZONE * implicitKeepoutZone
Definition drc_engine.h:354
DRC_ENGINE::DRC_ENGINE_CONSTRAINT::parentRule
std::shared_ptr< DRC_RULE > parentRule
Definition drc_engine.h:348
DRC_ENGINE::DRC_ENGINE_CONSTRAINT::layerTest
LSET layerTest
Definition drc_engine.h:346
DRC_ENGINE::DRC_ENGINE_CONSTRAINT::condition
DRC_RULE_CONDITION * condition
Definition drc_engine.h:347
DRC_ENGINE::DRC_ENGINE_CONSTRAINT::constraint
DRC_CONSTRAINT constraint
Definition drc_engine.h:349
DRC_OWN_CLEARANCE_CACHE_KEY
Cache key for own clearance lookups, combining item UUID and layer.
Definition drc_engine.h:39
PARSE_ERROR
A filename or source description, a problem input line, a line number, a byte offset,...
Definition ki_exception.h:118
TUNING_PROFILE
Represents a single line in the tuning profile configuration grid.
Definition tuning_profiles.h:146
TUNING_PROFILE::PROFILE_TYPE::SINGLE
@ SINGLE
Definition tuning_profiles.h:149
TUNING_PROFILE::m_Type
PROFILE_TYPE m_Type
Definition tuning_profiles.h:154
TUNING_PROFILE::m_TrackPropagationEntries
std::vector< DELAY_PROFILE_TRACK_PROPAGATION_ENTRY > m_TrackPropagationEntries
Definition tuning_profiles.h:159
MM
static const long long MM
Definition test_net_chain_total_length.cpp:25
clearance
int clearance
Definition test_shape_arc.cpp:972
result
wxString result
Test unit parsing edge cases and error handling.
Definition test_text_eval_numeric_compat.cpp:598
GetKiCadThreadPool
thread_pool & GetKiCadThreadPool()
Get a reference to the current thread pool.
Definition thread_pool.cpp:27
tp
static thread_pool * tp
Definition thread_pool.cpp:24
thread_pool.h
thread_pool
BS::priority_thread_pool thread_pool
Definition thread_pool.h:27
tuning_profiles.h
BaseType
constexpr KICAD_T BaseType(const KICAD_T aType)
Return the underlying type of the given type.
Definition typeinfo.h:257
PCB_CONSTRAINT_T
@ PCB_CONSTRAINT_T
class PCB_CONSTRAINT, a geometric constraint between board items
Definition typeinfo.h:238
PCB_SHAPE_T
@ PCB_SHAPE_T
class PCB_SHAPE, a segment not on copper layers
Definition typeinfo.h:81
PCB_GENERATOR_T
@ PCB_GENERATOR_T
class PCB_GENERATOR, generator on a layer
Definition typeinfo.h:84
PCB_VIA_T
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
Definition typeinfo.h:90
PCB_GROUP_T
@ PCB_GROUP_T
class PCB_GROUP, a set of BOARD_ITEMs
Definition typeinfo.h:104
PCB_TEXTBOX_T
@ PCB_TEXTBOX_T
class PCB_TEXTBOX, wrapped text on a layer
Definition typeinfo.h:86
PCB_ZONE_T
@ PCB_ZONE_T
class ZONE, a copper pour area
Definition typeinfo.h:101
PCB_TEXT_T
@ PCB_TEXT_T
class PCB_TEXT, text on a layer
Definition typeinfo.h:85
PCB_FIELD_T
@ PCB_FIELD_T
class PCB_FIELD, text associated with a footprint property
Definition typeinfo.h:83
PCB_BARCODE_T
@ PCB_BARCODE_T
class PCB_BARCODE, a barcode (graphic item)
Definition typeinfo.h:94
PCB_TABLECELL_T
@ PCB_TABLECELL_T
class PCB_TABLECELL, PCB_TEXTBOX for use in tables
Definition typeinfo.h:88
PCB_FOOTPRINT_T
@ PCB_FOOTPRINT_T
class FOOTPRINT, a footprint
Definition typeinfo.h:79
PCB_PAD_T
@ PCB_PAD_T
class PAD, a pad in a footprint
Definition typeinfo.h:80
PCB_ARC_T
@ PCB_ARC_T
class PCB_ARC, an arc track segment on a copper layer
Definition typeinfo.h:91
PCB_DIMENSION_T
@ PCB_DIMENSION_T
class PCB_DIMENSION_BASE: abstract dimension meta-type
Definition typeinfo.h:93
PCB_TABLE_T
@ PCB_TABLE_T
class PCB_TABLE, table of PCB_TABLECELLs
Definition typeinfo.h:87
PCB_NETINFO_T
@ PCB_NETINFO_T
class NETINFO_ITEM, a description of a net
Definition typeinfo.h:103
PCB_LOCATE_HOLE_T
@ PCB_LOCATE_HOLE_T
Definition typeinfo.h:124
PCB_TRACE_T
@ PCB_TRACE_T
class PCB_TRACK, a track segment (segment on a copper layer)
Definition typeinfo.h:89
VECTOR2I
VECTOR2< int32_t > VECTOR2I
Definition vector2d.h:683
PrintZoneConnection
wxString PrintZoneConnection(ZONE_CONNECTION aConnection)
Definition zones.h:52
ZONE_CONNECTION
ZONE_CONNECTION
How pads are covered by copper in zone.
Definition zones.h:43
ZONE_CONNECTION::THERMAL
@ THERMAL
Use thermal relief for pads.
Definition zones.h:46
ZONE_CONNECTION::THT_THERMAL
@ THT_THERMAL
Thermal relief only for THT pads.
Definition zones.h:48
ZONE_CONNECTION::FULL
@ FULL
pads are covered by copper
Definition zones.h:47