KiCad PCB EDA Suite
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drc_engine.cpp
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1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright (C) 2004-2019 Jean-Pierre Charras, jp.charras at wanadoo.fr
5 * Copyright (C) 2014 Dick Hollenbeck, [email protected]
6 * Copyright The KiCad Developers, see AUTHORS.txt for contributors.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, you may find one here:
20 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
21 * or you may search the http://www.gnu.org website for the version 2 license,
22 * or you may write to the Free Software Foundation, Inc.,
23 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
24 */
25
26#include <atomic>
27#include <wx/log.h>
28#include <reporter.h>
29#include <common.h>
30#include <progress_reporter.h>
31#include <string_utils.h>
32#include <board_design_settings.h>
33#include <drc/drc_engine.h>
34#include <drc/drc_rtree.h>
35#include <drc/drc_rule_parser.h>
36#include <drc/drc_rule.h>
37#include <drc/drc_rule_condition.h>
38#include <drc/drc_test_provider.h>
39#include <drc/drc_item.h>
40#include <drc/drc_cache_generator.h>
41#include <footprint.h>
42#include <pad.h>
43#include <pcb_track.h>
44#include <pcb_shape.h>
45#include <core/profile.h>
46#include <thread_pool.h>
47#include <zone.h>
48#include <project/project_file.h>
49#include <project/tuning_profiles.h>
50#include <connectivity/connectivity_data.h>
51#include <connectivity/from_to_cache.h>
52
53
54// wxListBox's performance degrades horrifically with very large datasets. It's not clear
55// they're useful to the user anyway.
56#define ERROR_LIMIT 199
57#define EXTENDED_ERROR_LIMIT 499
58
59
67static const wxChar* traceDrcProfile = wxT( "KICAD_DRC_PROFILE" );
68
69
70void drcPrintDebugMessage( int level, const wxString& msg, const char *function, int line )
71{
72 wxString valueStr;
73
74 if( wxGetEnv( wxT( "DRC_DEBUG" ), &valueStr ) )
75 {
76 int setLevel = wxAtoi( valueStr );
77
78 if( level <= setLevel )
79 printf( "%-30s:%d | %s\n", function, line, (const char *) msg.c_str() );
80 }
81}
82
83
84DRC_ENGINE::DRC_ENGINE( BOARD* aBoard, BOARD_DESIGN_SETTINGS *aSettings ) :
85 UNITS_PROVIDER( pcbIUScale, EDA_UNITS::MM ),
86 m_designSettings ( aSettings ),
87 m_board( aBoard ),
88 m_drawingSheet( nullptr ),
89 m_schematicNetlist( nullptr ),
90 m_rulesValid( false ),
91 m_reportAllTrackErrors( false ),
92 m_testFootprints( false ),
93 m_logReporter( nullptr ),
94 m_progressReporter( nullptr )
95{
96 m_errorLimits.resize( DRCE_LAST + 1 );
97
98 for( int ii = DRCE_FIRST; ii <= DRCE_LAST; ++ii )
99 m_errorLimits[ii] = ERROR_LIMIT;
100}
101
102
103DRC_ENGINE::~DRC_ENGINE()
104{
105 m_rules.clear();
106
107 for( std::pair<DRC_CONSTRAINT_T, std::vector<DRC_ENGINE_CONSTRAINT*>*> pair : m_constraintMap )
108 {
109 for( DRC_ENGINE_CONSTRAINT* constraint : *pair.second )
110 delete constraint;
111
112 delete pair.second;
113 }
114}
115
116
117static bool isKeepoutZone( const BOARD_ITEM* aItem, bool aCheckFlags )
118{
119 if( !aItem || aItem->Type() != PCB_ZONE_T )
120 return false;
121
122 const ZONE* zone = static_cast<const ZONE*>( aItem );
123
124 if( !zone->GetIsRuleArea() )
125 return false;
126
127 if( !zone->HasKeepoutParametersSet() )
128 return false;
129
130 if( aCheckFlags )
131 {
132 if( !zone->GetDoNotAllowTracks()
133 && !zone->GetDoNotAllowVias()
134 && !zone->GetDoNotAllowPads()
135 && !zone->GetDoNotAllowZoneFills()
136 && !zone->GetDoNotAllowFootprints() )
137 {
138 return false;
139 }
140 }
141
142 return true;
143}
144
145
146std::shared_ptr<DRC_RULE> DRC_ENGINE::createImplicitRule( const wxString& name,
147 const DRC_IMPLICIT_SOURCE aImplicitSource )
148{
149 std::shared_ptr<DRC_RULE> rule = std::make_shared<DRC_RULE>();
150
151 rule->m_Name = name;
152 rule->SetImplicitSource( aImplicitSource );
153
154 addRule( rule );
155
156 return rule;
157}
158
159
160void DRC_ENGINE::loadImplicitRules()
161{
162 BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
163 wxString expr, expr2, ncName;
164
165 // 1) global defaults
166
167 std::shared_ptr<DRC_RULE> rule =
168 createImplicitRule( _( "board setup constraints" ), DRC_IMPLICIT_SOURCE::BOARD_SETUP_CONSTRAINT );
169
170 DRC_CONSTRAINT widthConstraint( TRACK_WIDTH_CONSTRAINT );
171 widthConstraint.Value().SetMin( bds.m_TrackMinWidth );
172 rule->AddConstraint( widthConstraint );
173
174 DRC_CONSTRAINT connectionConstraint( CONNECTION_WIDTH_CONSTRAINT );
175 connectionConstraint.Value().SetMin( bds.m_MinConn );
176 rule->AddConstraint( connectionConstraint );
177
178 DRC_CONSTRAINT drillConstraint( HOLE_SIZE_CONSTRAINT );
179 drillConstraint.Value().SetMin( bds.m_MinThroughDrill );
180 rule->AddConstraint( drillConstraint );
181
182 DRC_CONSTRAINT annulusConstraint( ANNULAR_WIDTH_CONSTRAINT );
183 annulusConstraint.Value().SetMin( bds.m_ViasMinAnnularWidth );
184 rule->AddConstraint( annulusConstraint );
185
186 DRC_CONSTRAINT diameterConstraint( VIA_DIAMETER_CONSTRAINT );
187 diameterConstraint.Value().SetMin( bds.m_ViasMinSize );
188 rule->AddConstraint( diameterConstraint );
189
190 DRC_CONSTRAINT holeToHoleConstraint( HOLE_TO_HOLE_CONSTRAINT );
191 holeToHoleConstraint.Value().SetMin( bds.m_HoleToHoleMin );
192 rule->AddConstraint( holeToHoleConstraint );
193
194 rule = createImplicitRule( _( "board setup constraints zone fill strategy" ),
195 DRC_IMPLICIT_SOURCE::BOARD_SETUP_CONSTRAINT );
196 DRC_CONSTRAINT thermalSpokeCountConstraint( MIN_RESOLVED_SPOKES_CONSTRAINT );
197 thermalSpokeCountConstraint.Value().SetMin( bds.m_MinResolvedSpokes );
198 rule->AddConstraint( thermalSpokeCountConstraint );
199
200 rule = createImplicitRule( _( "board setup constraints silk" ), DRC_IMPLICIT_SOURCE::BOARD_SETUP_CONSTRAINT );
201 rule->m_LayerCondition = LSET( { F_SilkS, B_SilkS } );
202 DRC_CONSTRAINT silkClearanceConstraint( SILK_CLEARANCE_CONSTRAINT );
203 silkClearanceConstraint.Value().SetMin( bds.m_SilkClearance );
204 rule->AddConstraint( silkClearanceConstraint );
205
206 rule = createImplicitRule( _( "board setup constraints silk text height" ),
207 DRC_IMPLICIT_SOURCE::BOARD_SETUP_CONSTRAINT );
208 rule->m_LayerCondition = LSET( { F_SilkS, B_SilkS } );
209 DRC_CONSTRAINT silkTextHeightConstraint( TEXT_HEIGHT_CONSTRAINT );
210 silkTextHeightConstraint.Value().SetMin( bds.m_MinSilkTextHeight );
211 rule->AddConstraint( silkTextHeightConstraint );
212
213 rule = createImplicitRule( _( "board setup constraints silk text thickness" ),
214 DRC_IMPLICIT_SOURCE::BOARD_SETUP_CONSTRAINT );
215 rule->m_LayerCondition = LSET( { F_SilkS, B_SilkS } );
216 DRC_CONSTRAINT silkTextThicknessConstraint( TEXT_THICKNESS_CONSTRAINT );
217 silkTextThicknessConstraint.Value().SetMin( bds.m_MinSilkTextThickness );
218 rule->AddConstraint( silkTextThicknessConstraint );
219
220 rule = createImplicitRule( _( "board setup constraints hole" ), DRC_IMPLICIT_SOURCE::BOARD_SETUP_CONSTRAINT );
221 DRC_CONSTRAINT holeClearanceConstraint( HOLE_CLEARANCE_CONSTRAINT );
222 holeClearanceConstraint.Value().SetMin( bds.m_HoleClearance );
223 rule->AddConstraint( holeClearanceConstraint );
224
225 rule = createImplicitRule( _( "board setup constraints edge" ), DRC_IMPLICIT_SOURCE::BOARD_SETUP_CONSTRAINT );
226 DRC_CONSTRAINT edgeClearanceConstraint( EDGE_CLEARANCE_CONSTRAINT );
227 edgeClearanceConstraint.Value().SetMin( bds.m_CopperEdgeClearance );
228 rule->AddConstraint( edgeClearanceConstraint );
229
230 rule = createImplicitRule( _( "board setup constraints courtyard" ), DRC_IMPLICIT_SOURCE::BOARD_SETUP_CONSTRAINT );
231 DRC_CONSTRAINT courtyardClearanceConstraint( COURTYARD_CLEARANCE_CONSTRAINT );
232 holeToHoleConstraint.Value().SetMin( 0 );
233 rule->AddConstraint( courtyardClearanceConstraint );
234
235 // 2a) micro-via specific defaults (new DRC doesn't treat microvias in any special way)
236
237 std::shared_ptr<DRC_RULE> uViaRule =
238 createImplicitRule( _( "board setup micro-via constraints" ), DRC_IMPLICIT_SOURCE::BOARD_SETUP_CONSTRAINT );
239
240 uViaRule->m_Condition = new DRC_RULE_CONDITION( wxT( "A.Via_Type == 'Micro'" ) );
241
242 DRC_CONSTRAINT uViaDrillConstraint( HOLE_SIZE_CONSTRAINT );
243 uViaDrillConstraint.Value().SetMin( bds.m_MicroViasMinDrill );
244 uViaRule->AddConstraint( uViaDrillConstraint );
245
246 DRC_CONSTRAINT uViaDiameterConstraint( VIA_DIAMETER_CONSTRAINT );
247 uViaDiameterConstraint.Value().SetMin( bds.m_MicroViasMinSize );
248 uViaRule->AddConstraint( uViaDiameterConstraint );
249
250 // 2b) barcode-specific defaults
251
252 std::shared_ptr<DRC_RULE> barcodeRule =
253 createImplicitRule( _( "barcode visual separation default" ), DRC_IMPLICIT_SOURCE::BARCODE_DEFAULTS );
254 DRC_CONSTRAINT barcodeSeparationConstraint( PHYSICAL_CLEARANCE_CONSTRAINT );
255 barcodeSeparationConstraint.Value().SetMin( GetIuScale().mmToIU( 1.0 ) );
256 barcodeRule->AddConstraint( barcodeSeparationConstraint );
257 barcodeRule->m_Condition = new DRC_RULE_CONDITION( wxT( "A.Type == 'Barcode'" ) );
258
259 // 3) per-netclass rules
260
261 std::vector<std::shared_ptr<DRC_RULE>> netclassClearanceRules;
262 std::vector<std::shared_ptr<DRC_RULE>> netclassItemSpecificRules;
263
264 auto makeNetclassRules =
265 [&]( const std::shared_ptr<NETCLASS>& nc, bool isDefault )
266 {
267 ncName = nc->GetName();
268 ncName.Replace( "'", "\\'" );
269
270 if( nc->HasClearance() )
271 {
272 std::shared_ptr<DRC_RULE> netclassRule = std::make_shared<DRC_RULE>();
273 netclassRule->m_Name = wxString::Format( _( "netclass '%s'" ),
274 nc->GetClearanceParent()->GetHumanReadableName() );
275 netclassRule->SetImplicitSource( DRC_IMPLICIT_SOURCE::NET_CLASS );
276
277 expr = wxString::Format( wxT( "A.hasExactNetclass('%s')" ), ncName );
278 netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
279 netclassClearanceRules.push_back( netclassRule );
280
281 DRC_CONSTRAINT constraint( CLEARANCE_CONSTRAINT );
282 constraint.Value().SetMin( nc->GetClearance() );
283 netclassRule->AddConstraint( constraint );
284
285 {
286 std::unique_lock<std::shared_mutex> writeLock( m_clearanceCacheMutex );
287 m_netclassClearances[nc->GetName()] = nc->GetClearance();
288 }
289 }
290
291 if( nc->HasTrackWidth() )
292 {
293 std::shared_ptr<DRC_RULE> netclassRule = std::make_shared<DRC_RULE>();
294 netclassRule->m_Name = wxString::Format( _( "netclass '%s'" ),
295 nc->GetTrackWidthParent()->GetHumanReadableName() );
296 netclassRule->SetImplicitSource( DRC_IMPLICIT_SOURCE::NET_CLASS );
297
298 expr = wxString::Format( wxT( "A.hasExactNetclass('%s')" ), ncName );
299 netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
300 netclassClearanceRules.push_back( netclassRule );
301
302 DRC_CONSTRAINT constraint( TRACK_WIDTH_CONSTRAINT );
303 constraint.Value().SetMin( bds.m_TrackMinWidth );
304 constraint.Value().SetOpt( nc->GetTrackWidth() );
305 netclassRule->AddConstraint( constraint );
306 }
307
308 if( nc->HasDiffPairWidth() )
309 {
310 std::shared_ptr<DRC_RULE> netclassRule = std::make_shared<DRC_RULE>();
311 netclassRule->m_Name = wxString::Format( _( "netclass '%s' (diff pair)" ),
312 nc->GetDiffPairWidthParent()->GetHumanReadableName() );
313 netclassRule->SetImplicitSource( DRC_IMPLICIT_SOURCE::NET_CLASS );
314
315 expr = wxString::Format( wxT( "A.hasExactNetclass('%s') && A.inDiffPair('*')" ), ncName );
316 netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
317 netclassItemSpecificRules.push_back( netclassRule );
318
319 DRC_CONSTRAINT constraint( TRACK_WIDTH_CONSTRAINT );
320 constraint.Value().SetMin( bds.m_TrackMinWidth );
321 constraint.Value().SetOpt( nc->GetDiffPairWidth() );
322 netclassRule->AddConstraint( constraint );
323 }
324
325 if( nc->HasDiffPairGap() )
326 {
327 std::shared_ptr<DRC_RULE> netclassRule = std::make_shared<DRC_RULE>();
328 netclassRule->m_Name = wxString::Format( _( "netclass '%s' (diff pair)" ),
329 nc->GetDiffPairGapParent()->GetHumanReadableName() );
330 netclassRule->SetImplicitSource( DRC_IMPLICIT_SOURCE::NET_CLASS );
331
332 expr = wxString::Format( wxT( "A.hasExactNetclass('%s')" ), ncName );
333 netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
334 netclassItemSpecificRules.push_back( netclassRule );
335
336 DRC_CONSTRAINT constraint( DIFF_PAIR_GAP_CONSTRAINT );
337 constraint.Value().SetMin( bds.m_MinClearance );
338 constraint.Value().SetOpt( nc->GetDiffPairGap() );
339 netclassRule->AddConstraint( constraint );
340
341 // A narrower diffpair gap overrides the netclass min clearance
342 if( nc->GetDiffPairGap() < nc->GetClearance() )
343 {
344 netclassRule = std::make_shared<DRC_RULE>();
345 netclassRule->m_Name = wxString::Format( _( "netclass '%s' (diff pair)" ),
346 nc->GetDiffPairGapParent()->GetHumanReadableName() );
347 netclassRule->SetImplicitSource( DRC_IMPLICIT_SOURCE::NET_CLASS );
348
349 expr = wxString::Format( wxT( "A.hasExactNetclass('%s') && AB.isCoupledDiffPair()" ), ncName );
350 netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
351 netclassItemSpecificRules.push_back( netclassRule );
352
353 DRC_CONSTRAINT min_clearanceConstraint( CLEARANCE_CONSTRAINT );
354 min_clearanceConstraint.Value().SetMin( nc->GetDiffPairGap() );
355 netclassRule->AddConstraint( min_clearanceConstraint );
356
357 m_hasDiffPairClearanceOverrides = true;
358 }
359 }
360
361 if( nc->HasViaDiameter() )
362 {
363 std::shared_ptr<DRC_RULE> netclassRule = std::make_shared<DRC_RULE>();
364 netclassRule->m_Name = wxString::Format( _( "netclass '%s'" ),
365 nc->GetViaDiameterParent()->GetHumanReadableName() );
366 netclassRule->SetImplicitSource( DRC_IMPLICIT_SOURCE::NET_CLASS );
367
368 expr = wxString::Format( wxT( "A.hasExactNetclass('%s') && A.Via_Type != 'Micro'" ), ncName );
369 netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
370 netclassItemSpecificRules.push_back( netclassRule );
371
372 DRC_CONSTRAINT constraint( VIA_DIAMETER_CONSTRAINT );
373 constraint.Value().SetMin( bds.m_ViasMinSize );
374 constraint.Value().SetOpt( nc->GetViaDiameter() );
375 netclassRule->AddConstraint( constraint );
376 }
377
378 if( nc->HasViaDrill() )
379 {
380 std::shared_ptr<DRC_RULE> netclassRule = std::make_shared<DRC_RULE>();
381 netclassRule->m_Name = wxString::Format( _( "netclass '%s'" ),
382 nc->GetViaDrillParent()->GetHumanReadableName() );
383 netclassRule->SetImplicitSource( DRC_IMPLICIT_SOURCE::NET_CLASS );
384
385 expr = wxString::Format( wxT( "A.hasExactNetclass('%s') && A.Via_Type != 'Micro'" ), ncName );
386 netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
387 netclassItemSpecificRules.push_back( netclassRule );
388
389 DRC_CONSTRAINT constraint( HOLE_SIZE_CONSTRAINT );
390 constraint.Value().SetMin( bds.m_MinThroughDrill );
391 constraint.Value().SetOpt( nc->GetViaDrill() );
392 netclassRule->AddConstraint( constraint );
393 }
394
395 if( nc->HasuViaDiameter() )
396 {
397 std::shared_ptr<DRC_RULE> netclassRule = std::make_shared<DRC_RULE>();
398 netclassRule->m_Name = wxString::Format( _( "netclass '%s' (uvia)" ),
399 nc->GetuViaDiameterParent()->GetHumanReadableName() );
400 netclassRule->SetImplicitSource( DRC_IMPLICIT_SOURCE::NET_CLASS );
401
402 expr = wxString::Format( wxT( "A.hasExactNetclass('%s') && A.Via_Type == 'Micro'" ), ncName );
403 netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
404 netclassItemSpecificRules.push_back( netclassRule );
405
406 DRC_CONSTRAINT constraint( VIA_DIAMETER_CONSTRAINT );
407 constraint.Value().SetMin( bds.m_MicroViasMinSize );
408 constraint.Value().SetMin( nc->GetuViaDiameter() );
409 netclassRule->AddConstraint( constraint );
410 }
411
412 if( nc->HasuViaDrill() )
413 {
414 std::shared_ptr<DRC_RULE> netclassRule = std::make_shared<DRC_RULE>();
415 netclassRule->m_Name = wxString::Format( _( "netclass '%s' (uvia)" ),
416 nc->GetuViaDrillParent()->GetHumanReadableName() );
417 netclassRule->SetImplicitSource( DRC_IMPLICIT_SOURCE::NET_CLASS );
418
419 expr = wxString::Format( wxT( "A.hasExactNetclass('%s') && A.Via_Type == 'Micro'" ), ncName );
420 netclassRule->m_Condition = new DRC_RULE_CONDITION( expr );
421 netclassItemSpecificRules.push_back( netclassRule );
422
423 DRC_CONSTRAINT constraint( HOLE_SIZE_CONSTRAINT );
424 constraint.Value().SetMin( bds.m_MicroViasMinDrill );
425 constraint.Value().SetOpt( nc->GetuViaDrill() );
426 netclassRule->AddConstraint( constraint );
427 }
428 };
429
430 m_board->SynchronizeNetsAndNetClasses( false );
431 makeNetclassRules( bds.m_NetSettings->GetDefaultNetclass(), true );
432
433 for( const auto& [name, netclass] : bds.m_NetSettings->GetNetclasses() )
434 makeNetclassRules( netclass, false );
435
436 for( const auto& [name, netclass] : bds.m_NetSettings->GetCompositeNetclasses() )
437 makeNetclassRules( netclass, false );
438
439 // The netclass clearance rules have to be sorted by min clearance so the right one fires
440 // if 'A' and 'B' belong to two different netclasses.
441 //
442 // The item-specific netclass rules are all unary, so there's no 'A' vs 'B' issue.
443
444 std::sort( netclassClearanceRules.begin(), netclassClearanceRules.end(),
445 []( const std::shared_ptr<DRC_RULE>& lhs, const std::shared_ptr<DRC_RULE>& rhs )
446 {
447 return lhs->m_Constraints[0].m_Value.Min()
448 < rhs->m_Constraints[0].m_Value.Min();
449 } );
450
451 for( std::shared_ptr<DRC_RULE>& ncRule : netclassClearanceRules )
452 addRule( ncRule );
453
454 for( std::shared_ptr<DRC_RULE>& ncRule : netclassItemSpecificRules )
455 addRule( ncRule );
456
457 // 4) tuning profile rules
458 auto addTuningSingleRule =
459 [&]( const DELAY_PROFILE_TRACK_PROPAGATION_ENTRY& aLayerEntry, const wxString& aProfileName,
460 const wxString& aNetclassName )
461 {
462 if( aLayerEntry.GetWidth() <= 0 )
463 return;
464
465 std::shared_ptr<DRC_RULE> tuningRule = std::make_shared<DRC_RULE>();
466 tuningRule->m_Severity = bds.m_DRCSeverities[DRCE_TUNING_PROFILE_IMPLICIT_RULES];
467 tuningRule->m_Name = wxString::Format( _( "tuning profile '%s'" ), aProfileName );
468 tuningRule->SetImplicitSource( DRC_IMPLICIT_SOURCE::TUNING_PROFILE );
469
470 expr = wxString::Format( wxT( "A.hasExactNetclass('%s') && A.Layer == '%s'" ),
471 aNetclassName,
472 LSET::Name( aLayerEntry.GetSignalLayer() ) );
473 tuningRule->m_Condition = new DRC_RULE_CONDITION( expr );
474
475 DRC_CONSTRAINT constraint( TRACK_WIDTH_CONSTRAINT );
476 constraint.Value().SetMin( std::max( bds.m_TrackMinWidth, aLayerEntry.GetWidth() ) );
477 constraint.Value().SetOpt( aLayerEntry.GetWidth() );
478 constraint.Value().SetMax( aLayerEntry.GetWidth() );
479 tuningRule->AddConstraint( constraint );
480
481 addRule( tuningRule );
482 };
483
484 auto addTuningDifferentialRules =
485 [&]( const DELAY_PROFILE_TRACK_PROPAGATION_ENTRY& aLayerEntry, const wxString& aProfileName,
486 const NETCLASS* aNetclass )
487 {
488 if( aLayerEntry.GetWidth() <= 0 || aLayerEntry.GetDiffPairGap() <= 0 )
489 return;
490
491 std::shared_ptr<DRC_RULE> tuningRule = std::make_shared<DRC_RULE>();
492 tuningRule->m_Severity = bds.m_DRCSeverities[DRCE_TUNING_PROFILE_IMPLICIT_RULES];
493 tuningRule->m_Name = wxString::Format( _( "tuning profile '%s'" ), aProfileName );
494 tuningRule->SetImplicitSource( DRC_IMPLICIT_SOURCE::TUNING_PROFILE );
495
496 expr = wxString::Format( wxT( "A.hasExactNetclass('%s') && A.Layer == '%s' && A.inDiffPair('*')" ),
497 aNetclass->GetName(),
498 LSET::Name( aLayerEntry.GetSignalLayer() ) );
499 tuningRule->m_Condition = new DRC_RULE_CONDITION( expr );
500
501 DRC_CONSTRAINT constraint( TRACK_WIDTH_CONSTRAINT );
502 constraint.Value().SetMin( std::max( bds.m_TrackMinWidth, aLayerEntry.GetWidth() ) );
503 constraint.Value().SetOpt( aLayerEntry.GetWidth() );
504 constraint.Value().SetMax( aLayerEntry.GetWidth() );
505 tuningRule->AddConstraint( constraint );
506
507 addRule( tuningRule );
508
509 std::shared_ptr<DRC_RULE> tuningRule2 = std::make_shared<DRC_RULE>();
510 tuningRule2->m_Severity = bds.m_DRCSeverities[DRCE_TUNING_PROFILE_IMPLICIT_RULES];
511 tuningRule2->m_Name = wxString::Format( _( "tuning profile '%s'" ), aProfileName );
512 tuningRule2->SetImplicitSource( DRC_IMPLICIT_SOURCE::TUNING_PROFILE );
513
514 expr2 = wxString::Format( wxT( "A.hasExactNetclass('%s') && A.Layer == '%s' && A.inDiffPair('*')" ),
515 aNetclass->GetName(),
516 LSET::Name( aLayerEntry.GetSignalLayer() ) );
517 tuningRule2->m_Condition = new DRC_RULE_CONDITION( expr2 );
518
519 DRC_CONSTRAINT constraint2( DIFF_PAIR_GAP_CONSTRAINT );
520 constraint2.Value().SetMin( std::max( bds.m_MinClearance, aLayerEntry.GetDiffPairGap() ) );
521 constraint2.Value().SetOpt( aLayerEntry.GetDiffPairGap() );
522 constraint2.Value().SetMax( aLayerEntry.GetDiffPairGap() );
523 tuningRule2->AddConstraint( constraint2 );
524
525 addRule( tuningRule2 );
526
527 // A narrower diffpair gap overrides the netclass min clearance
528 if( aLayerEntry.GetDiffPairGap() < aNetclass->GetClearance() )
529 {
530 std::shared_ptr<DRC_RULE> diffPairClearanceRule = std::make_shared<DRC_RULE>();
531 diffPairClearanceRule->m_Severity = bds.m_DRCSeverities[DRCE_TUNING_PROFILE_IMPLICIT_RULES];
532 diffPairClearanceRule->m_Name = wxString::Format( _( "tuning profile '%s'" ), aProfileName );
533 diffPairClearanceRule->SetImplicitSource( DRC_IMPLICIT_SOURCE::TUNING_PROFILE );
534
535 expr = wxString::Format( wxT( "A.hasExactNetclass('%s') && A.Layer == '%s' && A.inDiffPair('*')" ),
536 aNetclass->GetName(),
537 LSET::Name( aLayerEntry.GetSignalLayer() ) );
538 diffPairClearanceRule->m_Condition = new DRC_RULE_CONDITION( expr );
539
540 DRC_CONSTRAINT min_clearanceConstraint( CLEARANCE_CONSTRAINT );
541 min_clearanceConstraint.Value().SetMin( aLayerEntry.GetDiffPairGap() );
542 diffPairClearanceRule->AddConstraint( min_clearanceConstraint );
543
544 addRule( diffPairClearanceRule );
545 }
546 };
547
548 if( PROJECT* project = m_board->GetProject() )
549 {
550 std::shared_ptr<TUNING_PROFILES> tuningParams = project->GetProjectFile().TuningProfileParameters();
551
552 auto addNetclassTuningProfileRules =
553 [&tuningParams, &addTuningSingleRule, &addTuningDifferentialRules]( NETCLASS* aNetclass )
554 {
555 if( aNetclass->HasTuningProfile() )
556 {
557 const wxString delayProfileName = aNetclass->GetTuningProfile();
558 const TUNING_PROFILE& profile = tuningParams->GetTuningProfile( delayProfileName );
559
560 for( const DELAY_PROFILE_TRACK_PROPAGATION_ENTRY& entry : profile.m_TrackPropagationEntries )
561 {
562 if( entry.GetWidth() <= 0 )
563 continue;
564
565 if( profile.m_Type == TUNING_PROFILE::PROFILE_TYPE::SINGLE )
566 addTuningSingleRule( entry, delayProfileName, aNetclass->GetName() );
567 else
568 addTuningDifferentialRules( entry, delayProfileName, aNetclass );
569 }
570 }
571 };
572
573 addNetclassTuningProfileRules( bds.m_NetSettings->GetDefaultNetclass().get() );
574
575 for( const auto& [netclassName, netclass] : bds.m_NetSettings->GetNetclasses() )
576 addNetclassTuningProfileRules( netclass.get() );
577
578 for( const auto& [netclassName, netclass] : bds.m_NetSettings->GetCompositeNetclasses() )
579 addNetclassTuningProfileRules( netclass.get() );
580 }
581
582 // 5) keepout area rules
583 auto addKeepoutZoneRule =
584 [&]( ZONE* zone, FOOTPRINT* parentFP )
585 {
586 const wxString& name = zone->GetZoneName();
587
588 if( name.IsEmpty() )
589 {
590 if( parentFP )
591 {
592 rule = createImplicitRule(
593 wxString::Format( _( "keepout area of %s" ), DescribeRef( parentFP->GetReference() ) ),
594 DRC_IMPLICIT_SOURCE::KEEPOUT );
595 }
596 else
597 {
598 rule = createImplicitRule( _( "keepout area" ), DRC_IMPLICIT_SOURCE::KEEPOUT );
599 }
600
601 }
602 else
603 {
604 if( parentFP )
605 {
606 rule = createImplicitRule( wxString::Format( _( "keepout area '%s' of %s" ), name,
607 DescribeRef( parentFP->GetReference() ) ),
608 DRC_IMPLICIT_SOURCE::KEEPOUT );
609 }
610 else
611 {
612 rule = createImplicitRule( wxString::Format( _( "keepout area '%s'" ), name ),
613 DRC_IMPLICIT_SOURCE::KEEPOUT );
614 }
615 }
616
617 rule->m_ImplicitItemId = zone->m_Uuid;
618
619 rule->m_Condition = new DRC_RULE_CONDITION( wxString::Format( wxT( "A.intersectsArea('%s')" ),
620 zone->m_Uuid.AsString() ) );
621
622 rule->m_LayerCondition = zone->GetLayerSet();
623
624 int disallowFlags = 0;
625
626 if( zone->GetDoNotAllowTracks() )
627 disallowFlags |= DRC_DISALLOW_TRACKS;
628
629 if( zone->GetDoNotAllowVias() )
630 disallowFlags |= DRC_DISALLOW_VIAS;
631
632 if( zone->GetDoNotAllowPads() )
633 disallowFlags |= DRC_DISALLOW_PADS;
634
635 if( zone->GetDoNotAllowZoneFills() )
636 disallowFlags |= DRC_DISALLOW_ZONES;
637
638 if( zone->GetDoNotAllowFootprints() )
639 disallowFlags |= DRC_DISALLOW_FOOTPRINTS;
640
641 DRC_CONSTRAINT disallowConstraint( DISALLOW_CONSTRAINT );
642 disallowConstraint.m_DisallowFlags = disallowFlags;
643 rule->AddConstraint( disallowConstraint );
644 };
645
646 for( ZONE* zone : m_board->Zones() )
647 {
648 if( isKeepoutZone( zone, true ) )
649 addKeepoutZoneRule( zone, nullptr );
650 }
651
652 for( FOOTPRINT* footprint : m_board->Footprints() )
653 {
654 for( ZONE* zone : footprint->Zones() )
655 {
656 if( isKeepoutZone( zone, true ) )
657 addKeepoutZoneRule( zone, footprint );
658 }
659 }
660}
661
662
663void DRC_ENGINE::loadRules( const wxFileName& aPath )
664{
665 if( m_board && aPath.FileExists() )
666 {
667 std::vector<std::shared_ptr<DRC_RULE>> rules;
668
669 if( FILE* fp = wxFopen( aPath.GetFullPath(), wxT( "rt" ) ) )
670 {
671 FILE_LINE_READER lineReader( fp, aPath.GetFullPath() ); // Will close rules file
672 wxString rulesText;
673
674 std::function<bool( wxString* )> resolver =
675 [&]( wxString* token ) -> bool
676 {
677 return m_board->ResolveTextVar( token, 0 );
678 };
679
680 while( char* line = lineReader.ReadLine() )
681 {
682 wxString str( line );
683 str = m_board->ConvertCrossReferencesToKIIDs( str );
684 str = ExpandTextVars( str, &resolver );
685
686 rulesText << str << '\n';
687 }
688
689 DRC_RULES_PARSER parser( rulesText, aPath.GetFullPath() );
690 parser.Parse( rules, m_logReporter );
691 }
692
693 // Copy the rules into the member variable afterwards so that if Parse() throws then
694 // the possibly malformed rules won't contaminate the current ruleset.
695
696 for( std::shared_ptr<DRC_RULE>& rule : rules )
697 m_rules.push_back( rule );
698 }
699}
700
701
702void DRC_ENGINE::compileRules()
703{
704 if( m_logReporter )
705 m_logReporter->Report( wxT( "Compiling Rules" ) );
706
707 REPORTER error_semaphore;
708
709 for( std::shared_ptr<DRC_RULE>& rule : m_rules )
710 {
711 DRC_RULE_CONDITION* condition = nullptr;
712
713 if( rule->m_Condition && !rule->m_Condition->GetExpression().IsEmpty() )
714 {
715 condition = rule->m_Condition;
716 condition->Compile( &error_semaphore );
717 }
718
719 if( error_semaphore.HasMessageOfSeverity( RPT_SEVERITY_ERROR ) )
720 THROW_PARSE_ERROR( wxT( "Parse error" ), rule->m_Name,
721 TO_UTF8( rule->m_Condition->GetExpression() ), 0, 0 );
722
723 for( const DRC_CONSTRAINT& constraint : rule->m_Constraints )
724 {
725 auto& ruleVec = m_constraintMap[ constraint.m_Type ];
726
727 if( !ruleVec )
728 ruleVec = new std::vector<DRC_ENGINE_CONSTRAINT*>();
729
730 DRC_ENGINE_CONSTRAINT* engineConstraint = new DRC_ENGINE_CONSTRAINT;
731
732 engineConstraint->layerTest = rule->m_LayerCondition;
733 engineConstraint->condition = condition;
734 engineConstraint->constraint = constraint;
735 engineConstraint->parentRule = rule;
736 ruleVec->push_back( engineConstraint );
737 }
738 }
739
740 m_hasExplicitClearanceRules = false;
741 m_explicitConstraints.clear();
742
743 for( auto& [constraintType, ruleList] : m_constraintMap )
744 {
745 for( DRC_ENGINE_CONSTRAINT* c : *ruleList )
746 {
747 if( c->parentRule && !c->parentRule->IsImplicit() )
748 {
749 m_explicitConstraints[constraintType].push_back( c );
750
751 if( constraintType == CLEARANCE_CONSTRAINT )
752 m_hasExplicitClearanceRules = true;
753 }
754 }
755 }
756}
757
758
759void DRC_ENGINE::InitEngine( const std::shared_ptr<DRC_RULE>& rule )
760{
761 m_testProviders = DRC_SHOWMATCHES_PROVIDER_REGISTRY::Instance().GetShowMatchesProviders();
762
763 for( DRC_TEST_PROVIDER* provider : m_testProviders )
764 {
765 if( m_logReporter )
766 m_logReporter->Report( wxString::Format( wxT( "Create DRC provider: '%s'" ), provider->GetName() ) );
767
768 provider->SetDRCEngine( this );
769 }
770
771 m_rules.clear();
772 m_rulesValid = false;
773
774 for( std::pair<DRC_CONSTRAINT_T, std::vector<DRC_ENGINE_CONSTRAINT*>*> pair : m_constraintMap )
775 {
776 for( DRC_ENGINE_CONSTRAINT* constraint : *pair.second )
777 delete constraint;
778
779 delete pair.second;
780 }
781
782 m_constraintMap.clear();
783
784 m_board->IncrementTimeStamp(); // Clear board-level caches
785
786 try
787 {
788 m_rules.push_back( rule );
789 compileRules();
790 }
791 catch( PARSE_ERROR& original_parse_error )
792 {
793 throw original_parse_error;
794 }
795
796 for( int ii = DRCE_FIRST; ii < DRCE_LAST; ++ii )
797 m_errorLimits[ii] = ERROR_LIMIT;
798
799 m_rulesValid = true;
800}
801
802
803void DRC_ENGINE::InitEngine( const wxFileName& aRulePath )
804{
805 m_testProviders = DRC_TEST_PROVIDER_REGISTRY::Instance().GetTestProviders();
806
807 for( DRC_TEST_PROVIDER* provider : m_testProviders )
808 {
809 if( m_logReporter )
810 m_logReporter->Report( wxString::Format( wxT( "Create DRC provider: '%s'" ), provider->GetName() ) );
811
812 provider->SetDRCEngine( this );
813 }
814
815 m_rules.clear();
816 m_rulesValid = false;
817
818 for( std::pair<DRC_CONSTRAINT_T, std::vector<DRC_ENGINE_CONSTRAINT*>*> pair : m_constraintMap )
819 {
820 for( DRC_ENGINE_CONSTRAINT* constraint : *pair.second )
821 delete constraint;
822
823 delete pair.second;
824 }
825
826 m_constraintMap.clear();
827
828 {
829 std::unique_lock<std::shared_mutex> writeLock( m_clearanceCacheMutex );
830 m_ownClearanceCache.clear();
831 m_netclassClearances.clear();
832 }
833
834 m_hasExplicitClearanceRules = false;
835 m_hasDiffPairClearanceOverrides = false;
836 m_explicitConstraints.clear();
837
838 m_board->IncrementTimeStamp(); // Clear board-level caches
839
840 try // attempt to load full set of rules (implicit + user rules)
841 {
842 loadImplicitRules();
843 loadRules( aRulePath );
844 compileRules();
845 }
846 catch( PARSE_ERROR& original_parse_error )
847 {
848 m_rules.clear();
849
850 try // try again with just our implicit rules
851 {
852 loadImplicitRules();
853 compileRules();
854 }
855 catch( PARSE_ERROR& )
856 {
857 wxFAIL_MSG( wxT( "Compiling implicit rules failed." ) );
858 }
859
860 throw original_parse_error;
861 }
862
863 for( int ii = DRCE_FIRST; ii <= DRCE_LAST; ++ii )
864 m_errorLimits[ ii ] = ERROR_LIMIT;
865
866 m_rulesValid = true;
867}
868
869
870void DRC_ENGINE::RunTests( EDA_UNITS aUnits, bool aReportAllTrackErrors, bool aTestFootprints,
871 BOARD_COMMIT* aCommit )
872{
873 PROF_TIMER timer;
874
875 SetUserUnits( aUnits );
876
877 m_reportAllTrackErrors = aReportAllTrackErrors;
878 m_testFootprints = aTestFootprints;
879
880 for( int ii = DRCE_FIRST; ii <= DRCE_LAST; ++ii )
881 {
882 if( m_designSettings->Ignore( ii ) )
883 m_errorLimits[ ii ] = 0;
884 else if( ii == DRCE_CLEARANCE || ii == DRCE_UNCONNECTED_ITEMS )
885 m_errorLimits[ ii ] = EXTENDED_ERROR_LIMIT;
886 else
887 m_errorLimits[ ii ] = ERROR_LIMIT;
888 }
889
890 DRC_TEST_PROVIDER::Init();
891
892 m_board->IncrementTimeStamp(); // Invalidate all caches...
893
894 DRC_CACHE_GENERATOR cacheGenerator;
895 cacheGenerator.SetDRCEngine( this );
896
897 if( !cacheGenerator.Run() ) // ... and regenerate them.
898 return;
899
900 // Recompute component classes
901 m_board->GetComponentClassManager().ForceComponentClassRecalculation();
902
903 int timestamp = m_board->GetTimeStamp();
904
905 for( DRC_TEST_PROVIDER* provider : m_testProviders )
906 {
907 if( m_logReporter )
908 m_logReporter->Report( wxString::Format( wxT( "Run DRC provider: '%s'" ), provider->GetName() ) );
909
910 if( !provider->RunTests( aUnits ) )
911 break;
912 }
913
914 timer.Stop();
915 wxLogTrace( traceDrcProfile, "DRC took %0.3f ms", timer.msecs() );
916
917 // DRC tests are multi-threaded; anything that causes us to attempt to re-generate the
918 // caches while DRC is running is problematic.
919 wxASSERT( timestamp == m_board->GetTimeStamp() );
920}
921
922
923#define REPORT( s ) { if( aReporter ) { aReporter->Report( s ); } }
924
925DRC_CONSTRAINT DRC_ENGINE::EvalZoneConnection( const BOARD_ITEM* a, const BOARD_ITEM* b,
926 PCB_LAYER_ID aLayer, REPORTER* aReporter )
927{
928 DRC_CONSTRAINT constraint = EvalRules( ZONE_CONNECTION_CONSTRAINT, a, b, aLayer, aReporter );
929
930 REPORT( "" )
931 REPORT( wxString::Format( _( "Resolved zone connection type: %s." ),
932 PrintZoneConnection( constraint.m_ZoneConnection ) ) )
933
934 if( constraint.m_ZoneConnection == ZONE_CONNECTION::THT_THERMAL )
935 {
936 const PAD* pad = nullptr;
937
938 if( a->Type() == PCB_PAD_T )
939 pad = static_cast<const PAD*>( a );
940 else if( b->Type() == PCB_PAD_T )
941 pad = static_cast<const PAD*>( b );
942
943 if( pad && pad->GetAttribute() == PAD_ATTRIB::PTH )
944 {
945 constraint.m_ZoneConnection = ZONE_CONNECTION::THERMAL;
946 }
947 else
948 {
949 REPORT( wxString::Format( _( "Pad is not a through hole pad; connection will be: %s." ),
950 PrintZoneConnection( ZONE_CONNECTION::FULL ) ) )
951 constraint.m_ZoneConnection = ZONE_CONNECTION::FULL;
952 }
953 }
954
955 return constraint;
956}
957
958
959DRC_CONSTRAINT DRC_ENGINE::EvalRules( DRC_CONSTRAINT_T aConstraintType, const BOARD_ITEM* a,
960 const BOARD_ITEM* b, PCB_LAYER_ID aLayer,
961 REPORTER* aReporter )
962{
963 /*
964 * NOTE: all string manipulation MUST BE KEPT INSIDE the REPORT macro. It absolutely
965 * kills performance when running bulk DRC tests (where aReporter is nullptr).
966 */
967
968 const BOARD_CONNECTED_ITEM* ac = a && a->IsConnected() ? static_cast<const BOARD_CONNECTED_ITEM*>( a ) : nullptr;
969 const BOARD_CONNECTED_ITEM* bc = b && b->IsConnected() ? static_cast<const BOARD_CONNECTED_ITEM*>( b ) : nullptr;
970
971 bool a_is_non_copper = a && ( !a->IsOnCopperLayer() || isKeepoutZone( a, false ) );
972 bool b_is_non_copper = b && ( !b->IsOnCopperLayer() || isKeepoutZone( b, false ) );
973
974 const PAD* pad = nullptr;
975 const ZONE* zone = nullptr;
976 const FOOTPRINT* parentFootprint = nullptr;
977
978 if( aConstraintType == ZONE_CONNECTION_CONSTRAINT
979 || aConstraintType == THERMAL_RELIEF_GAP_CONSTRAINT
980 || aConstraintType == THERMAL_SPOKE_WIDTH_CONSTRAINT
981 || aConstraintType == SOLDER_MASK_EXPANSION_CONSTRAINT
982 || aConstraintType == SOLDER_PASTE_ABS_MARGIN_CONSTRAINT
983 || aConstraintType == SOLDER_PASTE_REL_MARGIN_CONSTRAINT )
984 {
985 if( a && a->Type() == PCB_PAD_T )
986 pad = static_cast<const PAD*>( a );
987 else if( a && a->Type() == PCB_ZONE_T )
988 zone = static_cast<const ZONE*>( a );
989
990 if( b && b->Type() == PCB_PAD_T )
991 pad = static_cast<const PAD*>( b );
992 else if( b && b->Type() == PCB_ZONE_T )
993 zone = static_cast<const ZONE*>( b );
994
995 if( pad )
996 parentFootprint = pad->GetParentFootprint();
997 }
998
999 DRC_CONSTRAINT constraint;
1000 constraint.m_Type = aConstraintType;
1001
1002 auto applyConstraint =
1003 [&]( const DRC_ENGINE_CONSTRAINT* c )
1004 {
1005 if( c->constraint.m_Value.HasMin() )
1006 {
1007 if( c->parentRule && c->parentRule->IsImplicit() )
1008 constraint.m_ImplicitMin = true;
1009
1010 constraint.m_Value.SetMin( c->constraint.m_Value.Min() );
1011 }
1012
1013 if( c->constraint.m_Value.HasOpt() )
1014 constraint.m_Value.SetOpt( c->constraint.m_Value.Opt() );
1015
1016 if( c->constraint.m_Value.HasMax() )
1017 constraint .m_Value.SetMax( c->constraint.m_Value.Max() );
1018
1019 switch( c->constraint.m_Type )
1020 {
1021 case CLEARANCE_CONSTRAINT:
1022 case COURTYARD_CLEARANCE_CONSTRAINT:
1023 case SILK_CLEARANCE_CONSTRAINT:
1024 case HOLE_CLEARANCE_CONSTRAINT:
1025 case EDGE_CLEARANCE_CONSTRAINT:
1026 case PHYSICAL_CLEARANCE_CONSTRAINT:
1027 case PHYSICAL_HOLE_CLEARANCE_CONSTRAINT:
1028 if( constraint.m_Value.Min() > MAXIMUM_CLEARANCE )
1029 constraint.m_Value.SetMin( MAXIMUM_CLEARANCE );
1030
1031 break;
1032
1033 default:
1034 break;
1035 }
1036
1037 // While the expectation would be to OR the disallow flags, we've already
1038 // masked them down to aItem's type -- so we're really only looking for a
1039 // boolean here.
1040 constraint.m_DisallowFlags = c->constraint.m_DisallowFlags;
1041
1042 constraint.m_ZoneConnection = c->constraint.m_ZoneConnection;
1043
1044 constraint.SetParentRule( c->constraint.GetParentRule() );
1045
1046 constraint.SetOptionsFromOther( c->constraint );
1047 };
1048
1049 const FOOTPRINT* footprints[2] = { a ? a->GetParentFootprint() : nullptr,
1050 b ? b->GetParentFootprint() : nullptr };
1051
1052 // Handle Footprint net ties, which will zero out the clearance for footprint objects
1053 if( aConstraintType == CLEARANCE_CONSTRAINT // Only zero clearance, other constraints still apply
1054 && ( ( ( !ac ) ^ ( !bc ) )// Only apply to cases where we are comparing a connected item to a non-connected item
1055 // and not both connected. Connected items of different nets still need to be checked
1056 // for their standard clearance value
1057 || ( ( footprints[0] == footprints[1] ) // Unless both items are in the same footprint
1058 && footprints[0] ) ) // And that footprint exists
1059 && !a_is_non_copper // Also, both elements need to be on copper layers
1060 && !b_is_non_copper )
1061 {
1062 const BOARD_ITEM* child_items[2] = {a, b};
1063
1064 // These are the items being compared against, so the order is reversed
1065 const BOARD_CONNECTED_ITEM* alt_items[2] = {bc, ac};
1066
1067 for( int ii = 0; ii < 2; ++ii )
1068 {
1069 // We need both a footprint item and a connected item to check for a net tie
1070 if( !footprints[ii] || !alt_items[ii] )
1071 continue;
1072
1073 const std::set<int>& netcodes = footprints[ii]->GetNetTieCache( child_items[ii] );
1074
1075 auto it = netcodes.find( alt_items[ii]->GetNetCode() );
1076
1077 if( it != netcodes.end() )
1078 {
1079 REPORT( "" )
1080 REPORT( wxString::Format( _( "Net tie on %s; clearance: 0." ),
1081 EscapeHTML( footprints[ii]->GetItemDescription( this, true ) ) ) )
1082
1083 constraint.SetName( _( "net tie" ) );
1084 constraint.m_Value.SetMin( 0 );
1085 return constraint;
1086 }
1087 }
1088 }
1089
1090 // Local overrides take precedence over everything *except* board min clearance
1091 if( aConstraintType == CLEARANCE_CONSTRAINT || aConstraintType == HOLE_CLEARANCE_CONSTRAINT )
1092 {
1093 int override_val = 0;
1094 std::optional<int> overrideA;
1095 std::optional<int> overrideB;
1096
1097 if( ac && !b_is_non_copper )
1098 overrideA = ac->GetClearanceOverrides( nullptr );
1099
1100 if( bc && !a_is_non_copper )
1101 overrideB = bc->GetClearanceOverrides( nullptr );
1102
1103 if( overrideA.has_value() || overrideB.has_value() )
1104 {
1105 wxString msg;
1106
1107 if( overrideA.has_value() )
1108 {
1109 REPORT( "" )
1110 REPORT( wxString::Format( _( "Local override on %s; clearance: %s." ),
1111 EscapeHTML( a->GetItemDescription( this, true ) ),
1112 MessageTextFromValue( overrideA.value() ) ) )
1113
1114 override_val = ac->GetClearanceOverrides( &msg ).value();
1115 }
1116
1117 if( overrideB.has_value() )
1118 {
1119 REPORT( "" )
1120 REPORT( wxString::Format( _( "Local override on %s; clearance: %s." ),
1121 EscapeHTML( b->GetItemDescription( this, true ) ),
1122 MessageTextFromValue( overrideB.value() ) ) )
1123
1124 if( overrideB > override_val )
1125 override_val = bc->GetClearanceOverrides( &msg ).value();
1126 }
1127
1128 if( override_val )
1129 {
1130 if( aConstraintType == CLEARANCE_CONSTRAINT )
1131 {
1132 if( override_val < m_designSettings->m_MinClearance )
1133 {
1134 override_val = m_designSettings->m_MinClearance;
1135 msg = _( "board minimum" );
1136
1137 REPORT( "" )
1138 REPORT( wxString::Format( _( "Board minimum clearance: %s." ),
1139 MessageTextFromValue( override_val ) ) )
1140 }
1141 }
1142 else
1143 {
1144 if( override_val < m_designSettings->m_HoleClearance )
1145 {
1146 override_val = m_designSettings->m_HoleClearance;
1147 msg = _( "board minimum hole" );
1148
1149 REPORT( "" )
1150 REPORT( wxString::Format( _( "Board minimum hole clearance: %s." ),
1151 MessageTextFromValue( override_val ) ) )
1152 }
1153 }
1154
1155 constraint.SetName( msg );
1156 constraint.m_Value.SetMin( override_val );
1157 return constraint;
1158 }
1159 }
1160 }
1161 else if( aConstraintType == ZONE_CONNECTION_CONSTRAINT )
1162 {
1163 if( pad && pad->GetLocalZoneConnection() != ZONE_CONNECTION::INHERITED )
1164 {
1165 wxString msg;
1166 ZONE_CONNECTION override = pad->GetZoneConnectionOverrides( &msg );
1167
1168 REPORT( "" )
1169 REPORT( wxString::Format( _( "Local override on %s; zone connection: %s." ),
1170 EscapeHTML( pad->GetItemDescription( this, true ) ),
1171 PrintZoneConnection( override ) ) )
1172
1173 constraint.SetName( msg );
1174 constraint.m_ZoneConnection = override;
1175 return constraint;
1176 }
1177 }
1178 else if( aConstraintType == THERMAL_RELIEF_GAP_CONSTRAINT )
1179 {
1180 if( pad && pad->GetLocalThermalGapOverride( nullptr ) > 0 )
1181 {
1182 wxString msg;
1183 int gap_override = pad->GetLocalThermalGapOverride( &msg );
1184
1185 REPORT( "" )
1186 REPORT( wxString::Format( _( "Local override on %s; thermal relief gap: %s." ),
1187 EscapeHTML( pad->GetItemDescription( this, true ) ),
1188 MessageTextFromValue( gap_override ) ) )
1189
1190 constraint.SetName( msg );
1191 constraint.m_Value.SetMin( gap_override );
1192 return constraint;
1193 }
1194 }
1195 else if( aConstraintType == THERMAL_SPOKE_WIDTH_CONSTRAINT )
1196 {
1197 if( pad && pad->GetLocalSpokeWidthOverride( nullptr ) > 0 )
1198 {
1199 wxString msg;
1200 int spoke_override = pad->GetLocalSpokeWidthOverride( &msg );
1201
1202 REPORT( "" )
1203 REPORT( wxString::Format( _( "Local override on %s; thermal spoke width: %s." ),
1204 EscapeHTML( pad->GetItemDescription( this, true ) ),
1205 MessageTextFromValue( spoke_override ) ) )
1206
1207 if( zone && zone->GetMinThickness() > spoke_override )
1208 {
1209 spoke_override = zone->GetMinThickness();
1210
1211 REPORT( "" )
1212 REPORT( wxString::Format( _( "%s min thickness: %s." ),
1213 EscapeHTML( zone->GetItemDescription( this, true ) ),
1214 MessageTextFromValue( spoke_override ) ) )
1215 }
1216
1217 constraint.SetName( msg );
1218 constraint.m_Value.SetMin( spoke_override );
1219 return constraint;
1220 }
1221 }
1222 else if( aConstraintType == SOLDER_MASK_EXPANSION_CONSTRAINT )
1223 {
1224 std::optional<int> override;
1225
1226 if( pad )
1227 override = pad->GetLocalSolderMaskMargin();
1228 else if( a->Type() == PCB_SHAPE_T )
1229 override = static_cast<const PCB_SHAPE*>( a )->GetLocalSolderMaskMargin();
1230 else if( const PCB_TRACK* track = dynamic_cast<const PCB_TRACK*>( a ) )
1231 override = track->GetLocalSolderMaskMargin();
1232
1233 if( override )
1234 {
1235 REPORT( "" )
1236 REPORT( wxString::Format( _( "Local override on %s; solder mask expansion: %s." ),
1237 EscapeHTML( pad->GetItemDescription( this, true ) ),
1238 MessageTextFromValue( override.value() ) ) )
1239
1240 constraint.m_Value.SetOpt( override.value() );
1241 return constraint;
1242 }
1243 }
1244 else if( aConstraintType == SOLDER_PASTE_ABS_MARGIN_CONSTRAINT )
1245 {
1246 std::optional<int> override;
1247
1248 if( pad )
1249 override = pad->GetLocalSolderPasteMargin();
1250
1251 if( override )
1252 {
1253 REPORT( "" )
1254 REPORT( wxString::Format( _( "Local override on %s; solder paste absolute clearance: %s." ),
1255 EscapeHTML( pad->GetItemDescription( this, true ) ),
1256 MessageTextFromValue( override.value() ) ) )
1257
1258 constraint.m_Value.SetOpt( override.value_or( 0 ) );
1259 return constraint;
1260 }
1261 }
1262 else if( aConstraintType == SOLDER_PASTE_REL_MARGIN_CONSTRAINT )
1263 {
1264 std::optional<double> overrideRatio;
1265
1266 if( pad )
1267 overrideRatio = pad->GetLocalSolderPasteMarginRatio();
1268
1269 if( overrideRatio )
1270 {
1271 REPORT( "" )
1272 REPORT( wxString::Format( _( "Local override on %s; solder paste relative clearance: %s." ),
1273 EscapeHTML( pad->GetItemDescription( this, true ) ),
1274 MessageTextFromValue( overrideRatio.value() * 100.0 ) ) )
1275
1276 constraint.m_Value.SetOpt( KiROUND( overrideRatio.value_or( 0 ) * 1000 ) );
1277 return constraint;
1278 }
1279 }
1280
1281 auto testAssertion =
1282 [&]( const DRC_ENGINE_CONSTRAINT* c )
1283 {
1284 REPORT( wxString::Format( _( "Checking assertion '%s'." ),
1285 EscapeHTML( c->constraint.m_Test->GetExpression() ) ) )
1286
1287 if( c->constraint.m_Test->EvaluateFor( a, b, c->constraint.m_Type, aLayer, aReporter ) )
1288 REPORT( _( "Assertion passed." ) )
1289 else
1290 REPORT( EscapeHTML( _( "--> Assertion failed. <--" ) ) )
1291 };
1292
1293 auto processConstraint =
1294 [&]( const DRC_ENGINE_CONSTRAINT* c )
1295 {
1296 bool implicit = c->parentRule && c->parentRule->IsImplicit();
1297
1298 REPORT( "" )
1299
1300 switch( c->constraint.m_Type )
1301 {
1302 case CLEARANCE_CONSTRAINT:
1303 case COURTYARD_CLEARANCE_CONSTRAINT:
1304 case SILK_CLEARANCE_CONSTRAINT:
1305 case HOLE_CLEARANCE_CONSTRAINT:
1306 case EDGE_CLEARANCE_CONSTRAINT:
1307 case PHYSICAL_CLEARANCE_CONSTRAINT:
1308 case PHYSICAL_HOLE_CLEARANCE_CONSTRAINT:
1309 REPORT( wxString::Format( _( "Checking %s clearance: %s." ),
1310 EscapeHTML( c->constraint.GetName() ),
1311 MessageTextFromValue( c->constraint.m_Value.Min() ) ) )
1312 break;
1313 case CREEPAGE_CONSTRAINT:
1314 REPORT( wxString::Format( _( "Checking %s creepage: %s." ),
1315 EscapeHTML( c->constraint.GetName() ),
1316 MessageTextFromValue( c->constraint.m_Value.Min() ) ) )
1317 break;
1318 case MAX_UNCOUPLED_CONSTRAINT:
1319 REPORT( wxString::Format( _( "Checking %s max uncoupled length: %s." ),
1320 EscapeHTML( c->constraint.GetName() ),
1321 MessageTextFromValue( c->constraint.m_Value.Max() ) ) )
1322 break;
1323
1324 case SKEW_CONSTRAINT:
1325 REPORT( wxString::Format( _( "Checking %s max skew: %s." ),
1326 EscapeHTML( c->constraint.GetName() ),
1327 MessageTextFromValue( c->constraint.m_Value.Max() ) ) )
1328 break;
1329
1330 case THERMAL_RELIEF_GAP_CONSTRAINT:
1331 REPORT( wxString::Format( _( "Checking %s gap: %s." ),
1332 EscapeHTML( c->constraint.GetName() ),
1333 MessageTextFromValue( c->constraint.m_Value.Min() ) ) )
1334 break;
1335
1336 case THERMAL_SPOKE_WIDTH_CONSTRAINT:
1337 REPORT( wxString::Format( _( "Checking %s thermal spoke width: %s." ),
1338 EscapeHTML( c->constraint.GetName() ),
1339 MessageTextFromValue( c->constraint.m_Value.Opt() ) ) )
1340 break;
1341
1342 case SOLDER_MASK_EXPANSION_CONSTRAINT:
1343 REPORT( wxString::Format( _( "Checking %s solder mask expansion: %s." ),
1344 EscapeHTML( c->constraint.GetName() ),
1345 MessageTextFromValue( c->constraint.m_Value.Opt() ) ) )
1346 break;
1347
1348 case SOLDER_PASTE_ABS_MARGIN_CONSTRAINT:
1349 REPORT( wxString::Format( _( "Checking %s solder paste absolute clearance: %s." ),
1350 EscapeHTML( c->constraint.GetName() ),
1351 MessageTextFromValue( c->constraint.m_Value.Opt() ) ) )
1352 break;
1353
1354 case SOLDER_PASTE_REL_MARGIN_CONSTRAINT:
1355 REPORT( wxString::Format( _( "Checking %s solder paste relative clearance: %s." ),
1356 EscapeHTML( c->constraint.GetName() ),
1357 MessageTextFromValue( c->constraint.m_Value.Opt() ) ) )
1358 break;
1359
1360 case MIN_RESOLVED_SPOKES_CONSTRAINT:
1361 REPORT( wxString::Format( _( "Checking %s min spoke count: %s." ),
1362 EscapeHTML( c->constraint.GetName() ),
1363 MessageTextFromUnscaledValue( c->constraint.m_Value.Min() ) ) )
1364 break;
1365
1366 case ZONE_CONNECTION_CONSTRAINT:
1367 REPORT( wxString::Format( _( "Checking %s zone connection: %s." ),
1368 EscapeHTML( c->constraint.GetName() ),
1369 PrintZoneConnection( c->constraint.m_ZoneConnection ) ) )
1370 break;
1371
1372 case TRACK_WIDTH_CONSTRAINT:
1373 case ANNULAR_WIDTH_CONSTRAINT:
1374 case VIA_DIAMETER_CONSTRAINT:
1375 case HOLE_SIZE_CONSTRAINT:
1376 case TEXT_HEIGHT_CONSTRAINT:
1377 case TEXT_THICKNESS_CONSTRAINT:
1378 case DIFF_PAIR_GAP_CONSTRAINT:
1379 case LENGTH_CONSTRAINT:
1380 case CONNECTION_WIDTH_CONSTRAINT:
1381 case HOLE_TO_HOLE_CONSTRAINT:
1382 {
1383 if( implicit )
1384 {
1385 switch( c->constraint.m_Type )
1386 {
1387 case TRACK_WIDTH_CONSTRAINT:
1388 if( c->constraint.m_Value.HasOpt() )
1389 {
1390 REPORT( wxString::Format( _( "Checking %s track width: opt %s." ),
1391 EscapeHTML( c->constraint.GetName() ),
1392 MessageTextFromValue( c->constraint.m_Value.Opt() ) ) )
1393 }
1394 else if( c->constraint.m_Value.HasMin() )
1395 {
1396 REPORT( wxString::Format( _( "Checking %s track width: min %s." ),
1397 EscapeHTML( c->constraint.GetName() ),
1398 MessageTextFromValue( c->constraint.m_Value.Min() ) ) )
1399 }
1400
1401 break;
1402
1403 case ANNULAR_WIDTH_CONSTRAINT:
1404 REPORT( wxString::Format( _( "Checking %s annular width: min %s." ),
1405 EscapeHTML( c->constraint.GetName() ),
1406 MessageTextFromValue( c->constraint.m_Value.Opt() ) ) )
1407 break;
1408
1409 case VIA_DIAMETER_CONSTRAINT:
1410 if( c->constraint.m_Value.HasOpt() )
1411 {
1412 REPORT( wxString::Format( _( "Checking %s via diameter: opt %s." ),
1413 EscapeHTML( c->constraint.GetName() ),
1414 MessageTextFromValue( c->constraint.m_Value.Opt() ) ) )
1415 }
1416 else if( c->constraint.m_Value.HasMin() )
1417 {
1418 REPORT( wxString::Format( _( "Checking %s via diameter: min %s." ),
1419 EscapeHTML( c->constraint.GetName() ),
1420 MessageTextFromValue( c->constraint.m_Value.Min() ) ) )
1421 }
1422 break;
1423
1424 case HOLE_SIZE_CONSTRAINT:
1425 if( c->constraint.m_Value.HasOpt() )
1426 {
1427 REPORT( wxString::Format( _( "Checking %s hole size: opt %s." ),
1428 EscapeHTML( c->constraint.GetName() ),
1429 MessageTextFromValue( c->constraint.m_Value.Opt() ) ) )
1430 }
1431 else if( c->constraint.m_Value.HasMin() )
1432 {
1433 REPORT( wxString::Format( _( "Checking %s hole size: min %s." ),
1434 EscapeHTML( c->constraint.GetName() ),
1435 MessageTextFromValue( c->constraint.m_Value.Min() ) ) )
1436 }
1437
1438 break;
1439
1440 case TEXT_HEIGHT_CONSTRAINT:
1441 case TEXT_THICKNESS_CONSTRAINT:
1442 case CONNECTION_WIDTH_CONSTRAINT:
1443 REPORT( wxString::Format( _( "Checking %s: min %s." ),
1444 EscapeHTML( c->constraint.GetName() ),
1445 MessageTextFromValue( c->constraint.m_Value.Min() ) ) )
1446 break;
1447
1448 case DIFF_PAIR_GAP_CONSTRAINT:
1449 if( c->constraint.m_Value.HasOpt() )
1450 {
1451 REPORT( wxString::Format( _( "Checking %s diff pair gap: opt %s." ),
1452 EscapeHTML( c->constraint.GetName() ),
1453 MessageTextFromValue( c->constraint.m_Value.Opt() ) ) )
1454 }
1455 else if( c->constraint.m_Value.HasMin() )
1456 {
1457 REPORT( wxString::Format( _( "Checking %s clearance: min %s." ),
1458 EscapeHTML( c->constraint.GetName() ),
1459 MessageTextFromValue( c->constraint.m_Value.Min() ) ) )
1460 }
1461
1462 break;
1463
1464 case HOLE_TO_HOLE_CONSTRAINT:
1465 REPORT( wxString::Format( _( "Checking %s hole to hole: min %s." ),
1466 EscapeHTML( c->constraint.GetName() ),
1467 MessageTextFromValue( c->constraint.m_Value.Min() ) ) )
1468 break;
1469
1470 default:
1471 REPORT( wxString::Format( _( "Checking %s." ),
1472 EscapeHTML( c->constraint.GetName() ) ) )
1473 }
1474 }
1475 else
1476 {
1477 REPORT( wxString::Format( _( "Checking %s: min %s; opt %s; max %s." ),
1478 EscapeHTML( c->constraint.GetName() ),
1479 c->constraint.m_Value.HasMin()
1480 ? MessageTextFromValue( c->constraint.m_Value.Min() )
1481 : wxT( "<i>" ) + _( "undefined" ) + wxT( "</i>" ),
1482 c->constraint.m_Value.HasOpt()
1483 ? MessageTextFromValue( c->constraint.m_Value.Opt() )
1484 : wxT( "<i>" ) + _( "undefined" ) + wxT( "</i>" ),
1485 c->constraint.m_Value.HasMax()
1486 ? MessageTextFromValue( c->constraint.m_Value.Max() )
1487 : wxT( "<i>" ) + _( "undefined" ) + wxT( "</i>" ) ) )
1488 }
1489 break;
1490 }
1491
1492 default:
1493 REPORT( wxString::Format( _( "Checking %s." ),
1494 EscapeHTML( c->constraint.GetName() ) ) )
1495 }
1496
1497 if( c->constraint.m_Type == CLEARANCE_CONSTRAINT )
1498 {
1499 if( a_is_non_copper || b_is_non_copper )
1500 {
1501 if( implicit )
1502 {
1503 REPORT( _( "Netclass clearances apply only between copper items." ) )
1504 }
1505 else if( a_is_non_copper )
1506 {
1507 REPORT( wxString::Format( _( "%s contains no copper. Rule ignored." ),
1508 EscapeHTML( a->GetItemDescription( this, true ) ) ) )
1509 }
1510 else if( b_is_non_copper )
1511 {
1512 REPORT( wxString::Format( _( "%s contains no copper. Rule ignored." ),
1513 EscapeHTML( b->GetItemDescription( this, true ) ) ) )
1514 }
1515
1516 return;
1517 }
1518 }
1519 else if( c->constraint.m_Type == DISALLOW_CONSTRAINT )
1520 {
1521 int mask;
1522
1523 if( a->GetFlags() & HOLE_PROXY )
1524 {
1525 mask = DRC_DISALLOW_HOLES;
1526 }
1527 else if( a->Type() == PCB_VIA_T )
1528 {
1529 const PCB_VIA* via = static_cast<const PCB_VIA*>( a );
1530
1531 if( via->IsMicroVia() )
1532 mask = DRC_DISALLOW_MICRO_VIAS;
1533 else if( via->IsBlindVia() )
1534 mask = DRC_DISALLOW_BLIND_VIAS;
1535 else if( via->IsBuriedVia() )
1536 mask = DRC_DISALLOW_BURIED_VIAS;
1537 else
1538 mask = DRC_DISALLOW_THROUGH_VIAS;
1539 }
1540 else
1541 {
1542 switch( a->Type() )
1543 {
1544 case PCB_TRACE_T: mask = DRC_DISALLOW_TRACKS; break;
1545 case PCB_ARC_T: mask = DRC_DISALLOW_TRACKS; break;
1546 case PCB_PAD_T: mask = DRC_DISALLOW_PADS; break;
1547 case PCB_FOOTPRINT_T: mask = DRC_DISALLOW_FOOTPRINTS; break;
1548 case PCB_SHAPE_T: mask = DRC_DISALLOW_GRAPHICS; break;
1549 case PCB_BARCODE_T: mask = DRC_DISALLOW_GRAPHICS; break;
1550 case PCB_FIELD_T: mask = DRC_DISALLOW_TEXTS; break;
1551 case PCB_TEXT_T: mask = DRC_DISALLOW_TEXTS; break;
1552 case PCB_TEXTBOX_T: mask = DRC_DISALLOW_TEXTS; break;
1553 case PCB_TABLE_T: mask = DRC_DISALLOW_TEXTS; break;
1554
1555 case PCB_ZONE_T:
1556 // Treat teardrop areas as tracks for DRC purposes
1557 if( static_cast<const ZONE*>( a )->IsTeardropArea() )
1558 mask = DRC_DISALLOW_TRACKS;
1559 else
1560 mask = DRC_DISALLOW_ZONES;
1561
1562 break;
1563
1564 case PCB_LOCATE_HOLE_T: mask = DRC_DISALLOW_HOLES; break;
1565 default: mask = 0; break;
1566 }
1567 }
1568
1569 if( ( c->constraint.m_DisallowFlags & mask ) == 0 )
1570 {
1571 if( implicit )
1572 REPORT( _( "Keepout constraint not met." ) )
1573 else
1574 REPORT( _( "Disallow constraint not met." ) )
1575
1576 return;
1577 }
1578
1579 LSET itemLayers = a->GetLayerSet();
1580
1581 if( a->Type() == PCB_FOOTPRINT_T )
1582 {
1583 const FOOTPRINT* footprint = static_cast<const FOOTPRINT*>( a );
1584
1585 if( !footprint->GetCourtyard( F_CrtYd ).IsEmpty() )
1586 itemLayers |= LSET::FrontMask();
1587
1588 if( !footprint->GetCourtyard( B_CrtYd ).IsEmpty() )
1589 itemLayers |= LSET::BackMask();
1590 }
1591
1592 if( !( c->layerTest & itemLayers ).any() )
1593 {
1594 if( implicit )
1595 {
1596 REPORT( _( "Keepout layer(s) not matched." ) )
1597 }
1598 else if( c->parentRule )
1599 {
1600 REPORT( wxString::Format( _( "Rule layer '%s' not matched; rule ignored." ),
1601 EscapeHTML( c->parentRule->m_LayerSource ) ) )
1602 }
1603 else
1604 {
1605 REPORT( _( "Rule layer not matched; rule ignored." ) )
1606 }
1607
1608 return;
1609 }
1610 }
1611
1612 if( ( IsPcbLayer( aLayer ) && !c->layerTest.test( aLayer ) )
1613 || ( m_board->GetEnabledLayers() & c->layerTest ).count() == 0 )
1614 {
1615 if( implicit )
1616 {
1617 REPORT( _( "Constraint layer not matched." ) )
1618 }
1619 else if( c->parentRule )
1620 {
1621 REPORT( wxString::Format( _( "Rule layer '%s' not matched; rule ignored." ),
1622 EscapeHTML( c->parentRule->m_LayerSource ) ) )
1623 }
1624 else
1625 {
1626 REPORT( _( "Rule layer not matched; rule ignored." ) )
1627 }
1628 }
1629 else if( c->constraint.m_Type == HOLE_TO_HOLE_CONSTRAINT
1630 && ( !a->HasDrilledHole() && !b->HasDrilledHole() ) )
1631 {
1632 // Report non-drilled-holes as an implicit condition
1633 REPORT( wxString::Format( _( "%s is not a drilled hole; rule ignored." ),
1634 a->GetItemDescription( this, true ) ) )
1635 }
1636 else if( !c->condition || c->condition->GetExpression().IsEmpty() )
1637 {
1638 if( aReporter )
1639 {
1640 if( implicit )
1641 {
1642 REPORT( _( "Unconditional constraint applied." ) )
1643 }
1644 else if( constraint.m_Type == ASSERTION_CONSTRAINT )
1645 {
1646 REPORT( _( "Unconditional rule applied." ) )
1647 testAssertion( c );
1648 }
1649 else
1650 {
1651 REPORT( _( "Unconditional rule applied; overrides previous constraints." ) )
1652 }
1653 }
1654
1655 applyConstraint( c );
1656 }
1657 else
1658 {
1659 if( implicit )
1660 {
1661 // Don't report on implicit rule conditions; they're synthetic.
1662 }
1663 else
1664 {
1665 REPORT( wxString::Format( _( "Checking rule condition '%s'." ),
1666 EscapeHTML( c->condition->GetExpression() ) ) )
1667 }
1668
1669 if( c->condition->EvaluateFor( a, b, c->constraint.m_Type, aLayer, aReporter ) )
1670 {
1671 if( aReporter )
1672 {
1673 if( implicit )
1674 {
1675 REPORT( _( "Constraint applied." ) )
1676 }
1677 else if( constraint.m_Type == ASSERTION_CONSTRAINT )
1678 {
1679 REPORT( _( "Rule applied." ) )
1680 testAssertion( c );
1681 }
1682 else
1683 {
1684 REPORT( _( "Rule applied; overrides previous constraints." ) )
1685 }
1686 }
1687
1688 applyConstraint( c );
1689 }
1690 else
1691 {
1692 REPORT( implicit ? _( "Membership not satisfied; constraint ignored." )
1693 : _( "Condition not satisfied; rule ignored." ) )
1694 }
1695 }
1696 };
1697
1698 // Fast-path for netclass clearance when no explicit or diff pair override rules exist
1699 if( aConstraintType == CLEARANCE_CONSTRAINT
1700 && !m_hasExplicitClearanceRules
1701 && !m_hasDiffPairClearanceOverrides
1702 && !aReporter
1703 && !a_is_non_copper
1704 && ( !b || !b_is_non_copper ) )
1705 {
1706 int clearance = 0;
1707
1708 // Get netclass names outside of the lock to minimize critical section
1709 wxString ncNameA;
1710 wxString ncNameB;
1711
1712 if( ac )
1713 {
1714 NETCLASS* ncA = ac->GetEffectiveNetClass();
1715
1716 if( ncA )
1717 ncNameA = ncA->GetName();
1718 }
1719
1720 if( bc )
1721 {
1722 NETCLASS* ncB = bc->GetEffectiveNetClass();
1723
1724 if( ncB )
1725 ncNameB = ncB->GetName();
1726 }
1727
1728 // Look up clearances with shared lock protection
1729 if( !ncNameA.empty() || !ncNameB.empty() )
1730 {
1731 std::shared_lock<std::shared_mutex> readLock( m_clearanceCacheMutex );
1732
1733 if( !ncNameA.empty() )
1734 {
1735 auto it = m_netclassClearances.find( ncNameA );
1736
1737 if( it != m_netclassClearances.end() )
1738 clearance = it->second;
1739 }
1740
1741 if( !ncNameB.empty() )
1742 {
1743 auto it = m_netclassClearances.find( ncNameB );
1744
1745 if( it != m_netclassClearances.end() )
1746 clearance = std::max( clearance, it->second );
1747 }
1748 }
1749
1750 if( clearance > 0 )
1751 {
1752 constraint.m_Value.SetMin( clearance );
1753 constraint.m_ImplicitMin = true;
1754 }
1755 }
1756 else
1757 {
1758 auto it = m_constraintMap.find( aConstraintType );
1759
1760 if( it != m_constraintMap.end() )
1761 {
1762 for( DRC_ENGINE_CONSTRAINT* rule : *it->second )
1763 processConstraint( rule );
1764 }
1765 }
1766
1767 if( constraint.GetParentRule() && !constraint.GetParentRule()->IsImplicit() )
1768 return constraint;
1769
1770 // Special case for properties which can be inherited from parent footprints. We've already
1771 // checked for local overrides, and there were no rules targetting the item itself, so we know
1772 // we're inheriting and need to see if there are any rules targetting the parent footprint.
1773 if( pad && parentFootprint && ( aConstraintType == ZONE_CONNECTION_CONSTRAINT
1774 || aConstraintType == THERMAL_RELIEF_GAP_CONSTRAINT
1775 || aConstraintType == THERMAL_SPOKE_WIDTH_CONSTRAINT
1776 || aConstraintType == SOLDER_MASK_EXPANSION_CONSTRAINT
1777 || aConstraintType == SOLDER_PASTE_ABS_MARGIN_CONSTRAINT
1778 || aConstraintType == SOLDER_PASTE_REL_MARGIN_CONSTRAINT ) )
1779 {
1780 REPORT( "" )
1781 REPORT( wxString::Format( _( "Inheriting from parent: %s." ),
1782 EscapeHTML( parentFootprint->GetItemDescription( this, true ) ) ) )
1783
1784 if( a == pad )
1785 a = parentFootprint;
1786 else
1787 b = parentFootprint;
1788
1789 auto it = m_constraintMap.find( aConstraintType );
1790
1791 if( it != m_constraintMap.end() )
1792 {
1793 for( DRC_ENGINE_CONSTRAINT* rule : *it->second )
1794 processConstraint( rule );
1795
1796 if( constraint.GetParentRule() && !constraint.GetParentRule()->IsImplicit() )
1797 return constraint;
1798 }
1799
1800 // Found nothing again? Return the defaults.
1801 if( aConstraintType == SOLDER_MASK_EXPANSION_CONSTRAINT )
1802 {
1803 constraint.SetParentRule( nullptr );
1804 constraint.SetName( _( "board setup" ) );
1805 constraint.m_Value.SetOpt( m_designSettings->m_SolderMaskExpansion );
1806 return constraint;
1807 }
1808 else if( aConstraintType == SOLDER_PASTE_ABS_MARGIN_CONSTRAINT )
1809 {
1810 constraint.SetParentRule( nullptr );
1811 constraint.SetName( _( "board setup" ) );
1812 constraint.m_Value.SetOpt( m_designSettings->m_SolderPasteMargin );
1813 return constraint;
1814 }
1815 else if( aConstraintType == SOLDER_PASTE_REL_MARGIN_CONSTRAINT )
1816 {
1817 constraint.SetParentRule( nullptr );
1818 constraint.SetName( _( "board setup" ) );
1819 constraint.m_Value.SetOpt( KiROUND( m_designSettings->m_SolderPasteMarginRatio * 1000 ) );
1820 return constraint;
1821 }
1822 }
1823
1824 // Unfortunately implicit rules don't work for local clearances (such as zones) because
1825 // they have to be max'ed with netclass values (which are already implicit rules), and our
1826 // rule selection paradigm is "winner takes all".
1827 if( aConstraintType == CLEARANCE_CONSTRAINT )
1828 {
1829 int global = constraint.m_Value.Min();
1830 int clearance = global;
1831 bool needBlankLine = true;
1832
1833 if( ac && ac->GetLocalClearance().has_value() )
1834 {
1835 int localA = ac->GetLocalClearance().value();
1836
1837 if( needBlankLine )
1838 {
1839 REPORT( "" )
1840 needBlankLine = false;
1841 }
1842
1843 REPORT( wxString::Format( _( "Local clearance on %s: %s." ),
1844 EscapeHTML( a->GetItemDescription( this, true ) ),
1845 MessageTextFromValue( localA ) ) )
1846
1847 if( localA > clearance )
1848 {
1849 wxString msg;
1850 clearance = ac->GetLocalClearance( &msg ).value();
1851 constraint.SetParentRule( nullptr );
1852 constraint.SetName( msg );
1853 constraint.m_Value.SetMin( clearance );
1854 }
1855 }
1856
1857 if( bc && bc->GetLocalClearance().has_value() )
1858 {
1859 int localB = bc->GetLocalClearance().value();
1860
1861 if( needBlankLine )
1862 {
1863 REPORT( "" )
1864 needBlankLine = false;
1865 }
1866
1867 REPORT( wxString::Format( _( "Local clearance on %s: %s." ),
1868 EscapeHTML( b->GetItemDescription( this, true ) ),
1869 MessageTextFromValue( localB ) ) )
1870
1871 if( localB > clearance )
1872 {
1873 wxString msg;
1874 clearance = bc->GetLocalClearance( &msg ).value();
1875 constraint.SetParentRule( nullptr );
1876 constraint.SetName( msg );
1877 constraint.m_Value.SetMin( clearance );
1878 }
1879 }
1880
1881 if( !a_is_non_copper && !b_is_non_copper )
1882 {
1883 if( needBlankLine )
1884 {
1885 REPORT( "" )
1886 needBlankLine = false;
1887 }
1888
1889 REPORT( wxString::Format( _( "Board minimum clearance: %s." ),
1890 MessageTextFromValue( m_designSettings->m_MinClearance ) ) )
1891
1892 if( clearance < m_designSettings->m_MinClearance )
1893 {
1894 constraint.SetParentRule( nullptr );
1895 constraint.SetName( _( "board minimum" ) );
1896 constraint.m_Value.SetMin( m_designSettings->m_MinClearance );
1897 }
1898 }
1899
1900 return constraint;
1901 }
1902 else if( aConstraintType == DIFF_PAIR_GAP_CONSTRAINT )
1903 {
1904 REPORT( "" )
1905 REPORT( wxString::Format( _( "Board minimum clearance: %s." ),
1906 MessageTextFromValue( m_designSettings->m_MinClearance ) ) )
1907
1908 if( constraint.m_Value.Min() < m_designSettings->m_MinClearance )
1909 {
1910 constraint.SetParentRule( nullptr );
1911 constraint.SetName( _( "board minimum" ) );
1912 constraint.m_Value.SetMin( m_designSettings->m_MinClearance );
1913 }
1914
1915 return constraint;
1916 }
1917 else if( aConstraintType == ZONE_CONNECTION_CONSTRAINT )
1918 {
1919 if( pad && parentFootprint )
1920 {
1921 ZONE_CONNECTION local = parentFootprint->GetLocalZoneConnection();
1922
1923 if( local != ZONE_CONNECTION::INHERITED )
1924 {
1925 REPORT( "" )
1926 REPORT( wxString::Format( _( "%s zone connection: %s." ),
1927 EscapeHTML( parentFootprint->GetItemDescription( this, true ) ),
1928 PrintZoneConnection( local ) ) )
1929
1930 constraint.SetParentRule( nullptr );
1931 constraint.SetName( _( "footprint" ) );
1932 constraint.m_ZoneConnection = local;
1933 return constraint;
1934 }
1935 }
1936
1937 if( zone )
1938 {
1939 ZONE_CONNECTION local = zone->GetPadConnection();
1940
1941 REPORT( "" )
1942 REPORT( wxString::Format( _( "%s pad connection: %s." ),
1943 EscapeHTML( zone->GetItemDescription( this, true ) ),
1944 PrintZoneConnection( local ) ) )
1945
1946 constraint.SetParentRule( nullptr );
1947 constraint.SetName( _( "zone" ) );
1948 constraint.m_ZoneConnection = local;
1949 return constraint;
1950 }
1951 }
1952 else if( aConstraintType == THERMAL_RELIEF_GAP_CONSTRAINT )
1953 {
1954 if( zone )
1955 {
1956 int local = zone->GetThermalReliefGap();
1957
1958 REPORT( "" )
1959 REPORT( wxString::Format( _( "%s thermal relief gap: %s." ),
1960 EscapeHTML( zone->GetItemDescription( this, true ) ),
1961 MessageTextFromValue( local ) ) )
1962
1963 constraint.SetParentRule( nullptr );
1964 constraint.SetName( _( "zone" ) );
1965 constraint.m_Value.SetMin( local );
1966 return constraint;
1967 }
1968 }
1969 else if( aConstraintType == THERMAL_SPOKE_WIDTH_CONSTRAINT )
1970 {
1971 if( zone )
1972 {
1973 int local = zone->GetThermalReliefSpokeWidth();
1974
1975 REPORT( "" )
1976 REPORT( wxString::Format( _( "%s thermal spoke width: %s." ),
1977 EscapeHTML( zone->GetItemDescription( this, true ) ),
1978 MessageTextFromValue( local ) ) )
1979
1980 constraint.SetParentRule( nullptr );
1981 constraint.SetName( _( "zone" ) );
1982 constraint.m_Value.SetMin( local );
1983 return constraint;
1984 }
1985 }
1986
1987 if( !constraint.GetParentRule() )
1988 {
1989 constraint.m_Type = NULL_CONSTRAINT;
1990 constraint.m_DisallowFlags = 0;
1991 }
1992
1993 return constraint;
1994}
1995
1996
1997DRC_CLEARANCE_BATCH DRC_ENGINE::EvalClearanceBatch( const BOARD_ITEM* a, const BOARD_ITEM* b,
1998 PCB_LAYER_ID aLayer )
1999{
2000 DRC_CLEARANCE_BATCH result;
2001 DRC_CONSTRAINT c;
2002
2003 c = EvalRules( CLEARANCE_CONSTRAINT, a, b, aLayer );
2004
2005 if( c.m_Value.HasMin() )
2006 result.clearance = c.m_Value.Min();
2007
2008 c = EvalRules( HOLE_CLEARANCE_CONSTRAINT, a, b, aLayer );
2009
2010 if( c.m_Value.HasMin() )
2011 result.holeClearance = c.m_Value.Min();
2012
2013 c = EvalRules( HOLE_TO_HOLE_CONSTRAINT, a, b, aLayer );
2014
2015 if( c.m_Value.HasMin() )
2016 result.holeToHole = c.m_Value.Min();
2017
2018 c = EvalRules( EDGE_CLEARANCE_CONSTRAINT, a, b, aLayer );
2019
2020 if( c.m_Value.HasMin() )
2021 result.edgeClearance = c.m_Value.Min();
2022
2023 c = EvalRules( PHYSICAL_CLEARANCE_CONSTRAINT, a, b, aLayer );
2024
2025 if( c.m_Value.HasMin() )
2026 result.physicalClearance = c.m_Value.Min();
2027
2028 return result;
2029}
2030
2031
2032void DRC_ENGINE::ProcessAssertions( const BOARD_ITEM* a,
2033 std::function<void( const DRC_CONSTRAINT* )> aFailureHandler,
2034 REPORTER* aReporter )
2035{
2036 /*
2037 * NOTE: all string manipulation MUST BE KEPT INSIDE the REPORT macro. It absolutely
2038 * kills performance when running bulk DRC tests (where aReporter is nullptr).
2039 */
2040
2041 auto testAssertion =
2042 [&]( const DRC_ENGINE_CONSTRAINT* c )
2043 {
2044 REPORT( wxString::Format( _( "Checking rule assertion '%s'." ),
2045 EscapeHTML( c->constraint.m_Test->GetExpression() ) ) )
2046
2047 if( c->constraint.m_Test->EvaluateFor( a, nullptr, c->constraint.m_Type,
2048 a->GetLayer(), aReporter ) )
2049 {
2050 REPORT( _( "Assertion passed." ) )
2051 }
2052 else
2053 {
2054 REPORT( EscapeHTML( _( "--> Assertion failed. <--" ) ) )
2055 aFailureHandler( &c->constraint );
2056 }
2057 };
2058
2059 auto processConstraint =
2060 [&]( const DRC_ENGINE_CONSTRAINT* c )
2061 {
2062 REPORT( "" )
2063 REPORT( wxString::Format( _( "Checking %s." ), c->constraint.GetName() ) )
2064
2065 if( !( a->GetLayerSet() & c->layerTest ).any() )
2066 {
2067 REPORT( wxString::Format( _( "Rule layer '%s' not matched; rule ignored." ),
2068 EscapeHTML( c->parentRule->m_LayerSource ) ) )
2069 }
2070
2071 if( !c->condition || c->condition->GetExpression().IsEmpty() )
2072 {
2073 REPORT( _( "Unconditional rule applied." ) )
2074 testAssertion( c );
2075 }
2076 else
2077 {
2078 REPORT( wxString::Format( _( "Checking rule condition '%s'." ),
2079 EscapeHTML( c->condition->GetExpression() ) ) )
2080
2081 if( c->condition->EvaluateFor( a, nullptr, c->constraint.m_Type,
2082 a->GetLayer(), aReporter ) )
2083 {
2084 REPORT( _( "Rule applied." ) )
2085 testAssertion( c );
2086 }
2087 else
2088 {
2089 REPORT( _( "Condition not satisfied; rule ignored." ) )
2090 }
2091 }
2092 };
2093
2094 auto it = m_constraintMap.find( ASSERTION_CONSTRAINT );
2095
2096 if( it != m_constraintMap.end() )
2097 {
2098 for( int ii = 0; ii < (int) it->second->size(); ++ii )
2099 processConstraint( it->second->at( ii ) );
2100 }
2101}
2102
2103
2104#undef REPORT
2105
2106
2107bool DRC_ENGINE::IsErrorLimitExceeded( int error_code )
2108{
2109 assert( error_code >= 0 && error_code <= DRCE_LAST );
2110 return m_errorLimits[ error_code ] <= 0;
2111}
2112
2113
2114void DRC_ENGINE::ReportViolation( const std::shared_ptr<DRC_ITEM>& aItem, const VECTOR2I& aPos,
2115 int aMarkerLayer, const std::function<void( PCB_MARKER* )>& aPathGenerator )
2116{
2117 static std::mutex globalLock;
2118
2119 m_errorLimits[ aItem->GetErrorCode() ] -= 1;
2120
2121 if( m_violationHandler )
2122 {
2123 std::lock_guard<std::mutex> guard( globalLock );
2124 m_violationHandler( aItem, aPos, aMarkerLayer, aPathGenerator );
2125 }
2126
2127 if( m_logReporter )
2128 {
2129 wxString msg = wxString::Format( wxT( "Test '%s': %s (code %d)" ),
2130 aItem->GetViolatingTest()->GetName(),
2131 aItem->GetErrorMessage( false ),
2132 aItem->GetErrorCode() );
2133
2134 DRC_RULE* rule = aItem->GetViolatingRule();
2135
2136 if( rule )
2137 msg += wxString::Format( wxT( ", violating rule: '%s'" ), rule->m_Name );
2138
2139 m_logReporter->Report( msg );
2140
2141 wxString violatingItemsStr = wxT( "Violating items: " );
2142
2143 m_logReporter->Report( wxString::Format( wxT( " |- violating position (%d, %d)" ),
2144 aPos.x,
2145 aPos.y ) );
2146 }
2147}
2148
2149
2150bool DRC_ENGINE::KeepRefreshing( bool aWait )
2151{
2152 if( !m_progressReporter )
2153 return true;
2154
2155 return m_progressReporter->KeepRefreshing( aWait );
2156}
2157
2158
2159void DRC_ENGINE::AdvanceProgress()
2160{
2161 if( m_progressReporter )
2162 m_progressReporter->AdvanceProgress();
2163}
2164
2165
2166void DRC_ENGINE::SetMaxProgress( int aSize )
2167{
2168 if( m_progressReporter )
2169 m_progressReporter->SetMaxProgress( aSize );
2170}
2171
2172
2173bool DRC_ENGINE::ReportProgress( double aProgress )
2174{
2175 if( !m_progressReporter )
2176 return true;
2177
2178 m_progressReporter->SetCurrentProgress( aProgress );
2179 return m_progressReporter->KeepRefreshing( false );
2180}
2181
2182
2183bool DRC_ENGINE::ReportPhase( const wxString& aMessage )
2184{
2185 if( !m_progressReporter )
2186 return true;
2187
2188 m_progressReporter->AdvancePhase( aMessage );
2189 bool retval = m_progressReporter->KeepRefreshing( false );
2190 wxSafeYield( nullptr, true ); // Force an update for the message
2191 return retval;
2192}
2193
2194
2195bool DRC_ENGINE::IsCancelled() const
2196{
2197 return m_progressReporter && m_progressReporter->IsCancelled();
2198}
2199
2200
2201bool DRC_ENGINE::HasRulesForConstraintType( DRC_CONSTRAINT_T constraintID )
2202{
2203 auto it = m_constraintMap.find( constraintID );
2204 return it != m_constraintMap.end() && !it->second->empty();
2205}
2206
2207
2208bool DRC_ENGINE::QueryWorstConstraint( DRC_CONSTRAINT_T aConstraintId, DRC_CONSTRAINT& aConstraint )
2209{
2210 int worst = 0;
2211 auto it = m_constraintMap.find( aConstraintId );
2212
2213 if( it != m_constraintMap.end() )
2214 {
2215 for( DRC_ENGINE_CONSTRAINT* c : *it->second )
2216 {
2217 int current = c->constraint.GetValue().Min();
2218
2219 if( current > worst )
2220 {
2221 worst = current;
2222 aConstraint = c->constraint;
2223 }
2224 }
2225 }
2226
2227 return worst > 0;
2228}
2229
2230
2231std::set<int> DRC_ENGINE::QueryDistinctConstraints( DRC_CONSTRAINT_T aConstraintId )
2232{
2233 std::set<int> distinctMinimums;
2234 auto it = m_constraintMap.find( aConstraintId );
2235
2236 if( it != m_constraintMap.end() )
2237 {
2238 for( DRC_ENGINE_CONSTRAINT* c : *it->second )
2239 distinctMinimums.emplace( c->constraint.GetValue().Min() );
2240 }
2241
2242 return distinctMinimums;
2243}
2244
2245
2246// fixme: move two functions below to pcbcommon?
2247int DRC_ENGINE::MatchDpSuffix( const wxString& aNetName, wxString& aComplementNet,
2248 wxString& aBaseDpName )
2249{
2250 int rv = 0;
2251 int count = 0;
2252
2253 for( auto it = aNetName.rbegin(); it != aNetName.rend() && rv == 0; ++it, ++count )
2254 {
2255 int ch = *it;
2256
2257 if( ( ch >= '0' && ch <= '9' ) || ch == '_' )
2258 {
2259 continue;
2260 }
2261 else if( ch == '+' )
2262 {
2263 aComplementNet = wxT( "-" );
2264 rv = 1;
2265 }
2266 else if( ch == '-' )
2267 {
2268 aComplementNet = wxT( "+" );
2269 rv = -1;
2270 }
2271 else if( ch == 'N' )
2272 {
2273 aComplementNet = wxT( "P" );
2274 rv = -1;
2275 }
2276 else if ( ch == 'P' )
2277 {
2278 aComplementNet = wxT( "N" );
2279 rv = 1;
2280 }
2281 else
2282 {
2283 break;
2284 }
2285 }
2286
2287 if( rv != 0 && count >= 1 )
2288 {
2289 aBaseDpName = aNetName.Left( aNetName.Length() - count );
2290 aComplementNet = wxString( aBaseDpName ) << aComplementNet << aNetName.Right( count - 1 );
2291 }
2292
2293 return rv;
2294}
2295
2296
2297bool DRC_ENGINE::IsNetADiffPair( BOARD* aBoard, NETINFO_ITEM* aNet, int& aNetP, int& aNetN )
2298{
2299 wxString refName = aNet->GetNetname();
2300 wxString dummy, coupledNetName;
2301
2302 if( int polarity = MatchDpSuffix( refName, coupledNetName, dummy ) )
2303 {
2304 NETINFO_ITEM* net = aBoard->FindNet( coupledNetName );
2305
2306 if( !net )
2307 return false;
2308
2309 if( polarity > 0 )
2310 {
2311 aNetP = aNet->GetNetCode();
2312 aNetN = net->GetNetCode();
2313 }
2314 else
2315 {
2316 aNetP = net->GetNetCode();
2317 aNetN = aNet->GetNetCode();
2318 }
2319
2320 return true;
2321 }
2322
2323 return false;
2324}
2325
2326
2331bool DRC_ENGINE::IsNetTieExclusion( int aTrackNetCode, PCB_LAYER_ID aTrackLayer,
2332 const VECTOR2I& aCollisionPos, BOARD_ITEM* aCollidingItem )
2333{
2334 FOOTPRINT* parentFootprint = aCollidingItem->GetParentFootprint();
2335
2336 if( parentFootprint && parentFootprint->IsNetTie() )
2337 {
2338 int epsilon = GetDesignSettings()->GetDRCEpsilon();
2339 std::map<wxString, int> padToNetTieGroupMap = parentFootprint->MapPadNumbersToNetTieGroups();
2340
2341 for( PAD* pad : parentFootprint->Pads() )
2342 {
2343 if( padToNetTieGroupMap[ pad->GetNumber() ] >= 0 && aTrackNetCode == pad->GetNetCode() )
2344 {
2345 if( pad->GetEffectiveShape( aTrackLayer )->Collide( aCollisionPos, epsilon ) )
2346 return true;
2347 }
2348 }
2349 }
2350
2351 return false;
2352}
2353
2354
2355DRC_TEST_PROVIDER* DRC_ENGINE::GetTestProvider( const wxString& name ) const
2356{
2357 for( DRC_TEST_PROVIDER* prov : m_testProviders )
2358 {
2359 if( name == prov->GetName() )
2360 return prov;
2361 }
2362
2363 return nullptr;
2364}
2365
2366
2367std::vector<BOARD_ITEM*> DRC_ENGINE::GetItemsMatchingCondition( const wxString& aExpression,
2368 DRC_CONSTRAINT_T aConstraint,
2369 REPORTER* aReporter )
2370{
2371 wxLogTrace( wxS( "KI_TRACE_DRC_RULE_EDITOR" ),
2372 wxS( "[ShowMatches] engine enter: expr='%s', constraint=%d" ), aExpression, (int) aConstraint );
2373 std::vector<BOARD_ITEM*> matches;
2374
2375 if( !m_board )
2376 return matches;
2377
2378 DRC_RULE_CONDITION condition( aExpression );
2379
2380 if( !condition.Compile( aReporter ? aReporter : m_logReporter ) )
2381 {
2382 wxLogTrace( wxS( "KI_TRACE_DRC_RULE_EDITOR" ), wxS( "[ShowMatches] engine: compile failed" ) );
2383 return matches;
2384 }
2385
2386 // Rebuild the from-to cache so that fromTo() expressions can be evaluated.
2387 // This cache requires explicit rebuilding before use since it depends on the full
2388 // connectivity graph being available.
2389 if( auto connectivity = m_board->GetConnectivity() )
2390 {
2391 if( auto ftCache = connectivity->GetFromToCache() )
2392 ftCache->Rebuild( m_board );
2393 }
2394
2395 BOARD_ITEM_SET items = m_board->GetItemSet();
2396 size_t totalItems = 0;
2397 size_t skippedItems = 0;
2398 size_t noLayerItems = 0;
2399 size_t checkedItems = 0;
2400
2401 for( auto& [kiid, item] : m_board->GetItemByIdCache() )
2402 {
2403 totalItems++;
2404
2405 // Skip items that don't have visible geometry or can't be meaningfully matched
2406 switch( item->Type() )
2407 {
2408 case PCB_NETINFO_T:
2409 case PCB_GENERATOR_T:
2410 case PCB_GROUP_T:
2411 skippedItems++;
2412 continue;
2413
2414 default:
2415 break;
2416 }
2417
2418 LSET itemLayers = item->GetLayerSet();
2419
2420 if( itemLayers.none() )
2421 {
2422 noLayerItems++;
2423 continue;
2424 }
2425
2426 checkedItems++;
2427 bool matched = false;
2428
2429 for( PCB_LAYER_ID layer : itemLayers )
2430 {
2431 if( condition.EvaluateFor( item, nullptr, static_cast<int>( aConstraint ), layer,
2432 aReporter ? aReporter : m_logReporter ) )
2433 {
2434 matches.push_back( item );
2435 wxLogTrace( wxS( "KI_TRACE_DRC_RULE_EDITOR" ),
2436 wxS( "[ShowMatches] engine: match type=%d kiid=%s layer=%d" ),
2437 (int) item->Type(), kiid.AsString(), (int) layer );
2438 matched = true;
2439 break; // No need to check other layers
2440 }
2441 }
2442
2443 // Log a few non-matching items to help debug condition issues
2444 if( !matched && matches.size() == 0 && checkedItems <= 5 )
2445 {
2446 wxLogTrace( wxS( "KI_TRACE_DRC_RULE_EDITOR" ),
2447 wxS( "[ShowMatches] engine: no-match sample type=%d kiid=%s layers=%s" ),
2448 (int) item->Type(), kiid.AsString(), itemLayers.FmtHex() );
2449 }
2450 }
2451
2452 wxLogTrace( wxS( "KI_TRACE_DRC_RULE_EDITOR" ),
2453 wxS( "[ShowMatches] engine stats: total=%zu skipped=%zu noLayer=%zu checked=%zu" ),
2454 totalItems, skippedItems, noLayerItems, checkedItems );
2455
2456 wxLogTrace( wxS( "KI_TRACE_DRC_RULE_EDITOR" ), wxS( "[ShowMatches] engine exit: total=%zu" ), matches.size() );
2457 return matches;
2458}
2459
2460
2461int DRC_ENGINE::GetCachedOwnClearance( const BOARD_ITEM* aItem, PCB_LAYER_ID aLayer,
2462 wxString* aSource )
2463{
2464 DRC_OWN_CLEARANCE_CACHE_KEY key{ aItem->m_Uuid, aLayer };
2465
2466 // Fast path: check cache with shared (read) lock
2467 {
2468 std::shared_lock<std::shared_mutex> readLock( m_clearanceCacheMutex );
2469
2470 auto it = m_ownClearanceCache.find( key );
2471
2472 if( it != m_ownClearanceCache.end() )
2473 {
2474 // Cache hit. We don't cache the source string since it's rarely requested
2475 // and caching it would add complexity.
2476 return it->second;
2477 }
2478 }
2479
2480 // Cache miss - evaluate the constraint (outside lock to avoid blocking other threads)
2481 DRC_CONSTRAINT_T constraintType = CLEARANCE_CONSTRAINT;
2482
2483 if( aItem->Type() == PCB_PAD_T )
2484 {
2485 const PAD* pad = static_cast<const PAD*>( aItem );
2486
2487 if( pad->GetAttribute() == PAD_ATTRIB::NPTH )
2488 constraintType = HOLE_CLEARANCE_CONSTRAINT;
2489 }
2490
2491 DRC_CONSTRAINT constraint = EvalRules( constraintType, aItem, nullptr, aLayer );
2492
2493 int clearance = 0;
2494
2495 if( constraint.Value().HasMin() )
2496 {
2497 clearance = constraint.Value().Min();
2498
2499 if( aSource )
2500 *aSource = constraint.GetName();
2501 }
2502
2503 // Store in cache with exclusive (write) lock using double-checked locking
2504 {
2505 std::unique_lock<std::shared_mutex> writeLock( m_clearanceCacheMutex );
2506
2507 auto it = m_ownClearanceCache.find( key );
2508
2509 if( it == m_ownClearanceCache.end() )
2510 m_ownClearanceCache[key] = clearance;
2511 }
2512
2513 return clearance;
2514}
2515
2516
2517void DRC_ENGINE::InvalidateClearanceCache( const KIID& aUuid )
2518{
2519 std::unique_lock<std::shared_mutex> writeLock( m_clearanceCacheMutex );
2520
2521 // Remove all entries for this item (across all layers)
2522 auto it = m_ownClearanceCache.begin();
2523
2524 while( it != m_ownClearanceCache.end() )
2525 {
2526 if( it->first.m_uuid == aUuid )
2527 it = m_ownClearanceCache.erase( it );
2528 else
2529 ++it;
2530 }
2531}
2532
2533
2534void DRC_ENGINE::ClearClearanceCache()
2535{
2536 std::unique_lock<std::shared_mutex> writeLock( m_clearanceCacheMutex );
2537 m_ownClearanceCache.clear();
2538}
2539
2540
2541void DRC_ENGINE::InitializeClearanceCache()
2542{
2543 if( !m_board )
2544 return;
2545
2546 // Pre-populate the cache for all connected items to avoid delays during first render.
2547 // We only need to cache copper layers since clearance outlines are only drawn on copper.
2548
2549 LSET copperLayers = m_board->GetEnabledLayers() & LSET::AllCuMask();
2550
2551 using CLEARANCE_MAP = std::unordered_map<DRC_OWN_CLEARANCE_CACHE_KEY, int>;
2552
2553 // Build flat list of (item, layer) pairs to process.
2554 // Estimate size based on tracks + pads * average layers (2 for typical TH pads).
2555 std::vector<std::pair<const BOARD_ITEM*, PCB_LAYER_ID>> itemsToProcess;
2556 size_t estimatedPads = 0;
2557
2558 for( FOOTPRINT* footprint : m_board->Footprints() )
2559 estimatedPads += footprint->Pads().size();
2560
2561 itemsToProcess.reserve( m_board->Tracks().size() + estimatedPads * 2 );
2562
2563 for( PCB_TRACK* track : m_board->Tracks() )
2564 {
2565 if( track->Type() == PCB_VIA_T )
2566 {
2567 for( PCB_LAYER_ID layer : LSET( track->GetLayerSet() & copperLayers ).Seq() )
2568 itemsToProcess.emplace_back( track, layer );
2569 }
2570 else
2571 {
2572 itemsToProcess.emplace_back( track, track->GetLayer() );
2573 }
2574 }
2575
2576 for( FOOTPRINT* footprint : m_board->Footprints() )
2577 {
2578 for( PAD* pad : footprint->Pads() )
2579 {
2580 for( PCB_LAYER_ID layer : LSET( pad->GetLayerSet() & copperLayers ).Seq() )
2581 itemsToProcess.emplace_back( pad, layer );
2582 }
2583 }
2584
2585 if( itemsToProcess.empty() )
2586 return;
2587
2588 {
2589 std::unique_lock<std::shared_mutex> writeLock( m_clearanceCacheMutex );
2590 m_ownClearanceCache.reserve( itemsToProcess.size() );
2591 }
2592
2593 thread_pool& tp = GetKiCadThreadPool();
2594
2595 auto processItems = [this]( size_t aStart, size_t aEnd,
2596 const std::vector<std::pair<const BOARD_ITEM*, PCB_LAYER_ID>>& aItems )
2597 -> CLEARANCE_MAP
2598 {
2599 CLEARANCE_MAP localCache;
2600
2601 for( size_t i = aStart; i < aEnd; ++i )
2602 {
2603 const BOARD_ITEM* item = aItems[i].first;
2604 PCB_LAYER_ID layer = aItems[i].second;
2605
2606 DRC_CONSTRAINT_T constraintType = CLEARANCE_CONSTRAINT;
2607
2608 if( item->Type() == PCB_PAD_T )
2609 {
2610 const PAD* pad = static_cast<const PAD*>( item );
2611
2612 if( pad->GetAttribute() == PAD_ATTRIB::NPTH )
2613 constraintType = HOLE_CLEARANCE_CONSTRAINT;
2614 }
2615
2616 DRC_CONSTRAINT constraint = EvalRules( constraintType, item, nullptr, layer );
2617
2618 int clearance = 0;
2619
2620 if( constraint.Value().HasMin() )
2621 clearance = constraint.Value().Min();
2622
2623 localCache[{ item->m_Uuid, layer }] = clearance;
2624 }
2625
2626 return localCache;
2627 };
2628
2629 auto results = tp.submit_blocks( 0, itemsToProcess.size(),
2630 [&]( size_t aStart, size_t aEnd ) -> CLEARANCE_MAP
2631 {
2632 return processItems( aStart, aEnd, itemsToProcess );
2633 } );
2634
2635 // Collect all results first WITHOUT holding the lock to avoid deadlock.
2636 // Worker threads call EvalRules() which needs a read lock on m_clearanceCacheMutex.
2637 // If we held a write lock while calling .get(), workers would block on the read lock
2638 // while we block waiting for them to complete.
2639 std::vector<CLEARANCE_MAP> collectedResults;
2640 collectedResults.reserve( results.size() );
2641
2642 for( size_t i = 0; i < results.size(); ++i )
2643 {
2644 if( results[i].valid() )
2645 collectedResults.push_back( results[i].get() );
2646 }
2647
2648 // Now merge with write lock held, but no blocking on futures
2649 {
2650 std::unique_lock<std::shared_mutex> writeLock( m_clearanceCacheMutex );
2651
2652 for( const auto& localCache : collectedResults )
2653 m_ownClearanceCache.insert( localCache.begin(), localCache.end() );
2654 }
2655}
name
const char * name
Definition DXF_plotter.cpp:65
pcbIUScale
constexpr EDA_IU_SCALE pcbIUScale
Definition base_units.h:112
BITMAPS::via
@ via
Definition bitmaps_list.h:658
BITMAPS::project
@ project
Definition bitmaps_list.h:481
BITMAPS::pad
@ pad
Definition bitmaps_list.h:415
BOARD_ITEM_SET
std::set< BOARD_ITEM *, CompareByUuid > BOARD_ITEM_SET
Set of BOARD_ITEMs ordered by UUID.
Definition board.h:306
board_design_settings.h
MAXIMUM_CLEARANCE
#define MAXIMUM_CLEARANCE
Definition board_design_settings.h:103
KiROUND
constexpr BOX2I KiROUND(const BOX2D &aBoxD)
Definition box2.h:990
BASE_SET::FmtHex
std::string FmtHex() const
Return a hex string showing contents of this set.
Definition base_set.h:302
BOARD_COMMIT
Definition board_commit.h:49
BOARD_CONNECTED_ITEM
A base class derived from BOARD_ITEM for items that can be connected and have a net,...
Definition board_connected_item.h:46
BOARD_CONNECTED_ITEM::GetClearanceOverrides
virtual std::optional< int > GetClearanceOverrides(wxString *aSource) const
Return any clearance overrides set in the "classic" (ie: pre-rule) system.
Definition board_connected_item.h:164
BOARD_CONNECTED_ITEM::GetEffectiveNetClass
virtual NETCLASS * GetEffectiveNetClass() const
Return the NETCLASS for this item.
Definition board_connected_item.cpp:136
BOARD_CONNECTED_ITEM::GetLocalClearance
virtual std::optional< int > GetLocalClearance() const
Return any local clearances set in the "classic" (ie: pre-rule) system.
Definition board_connected_item.h:174
BOARD_DESIGN_SETTINGS
Container for design settings for a BOARD object.
Definition board_design_settings.h:249
BOARD_DESIGN_SETTINGS::m_MinConn
int m_MinConn
Definition board_design_settings.h:692
BOARD_DESIGN_SETTINGS::m_NetSettings
std::shared_ptr< NET_SETTINGS > m_NetSettings
Definition board_design_settings.h:747
BOARD_DESIGN_SETTINGS::m_CopperEdgeClearance
int m_CopperEdgeClearance
Definition board_design_settings.h:699
BOARD_DESIGN_SETTINGS::m_DRCSeverities
std::map< int, SEVERITY > m_DRCSeverities
Definition board_design_settings.h:708
BOARD_DESIGN_SETTINGS::m_ViasMinSize
int m_ViasMinSize
Definition board_design_settings.h:695
BOARD_DESIGN_SETTINGS::m_MicroViasMinSize
int m_MicroViasMinSize
Definition board_design_settings.h:697
BOARD_DESIGN_SETTINGS::m_MicroViasMinDrill
int m_MicroViasMinDrill
Definition board_design_settings.h:698
BOARD_DESIGN_SETTINGS::m_MinClearance
int m_MinClearance
Definition board_design_settings.h:690
BOARD_DESIGN_SETTINGS::m_MinSilkTextThickness
int m_MinSilkTextThickness
Definition board_design_settings.h:705
BOARD_DESIGN_SETTINGS::m_MinThroughDrill
int m_MinThroughDrill
Definition board_design_settings.h:696
BOARD_DESIGN_SETTINGS::m_MinResolvedSpokes
int m_MinResolvedSpokes
Definition board_design_settings.h:703
BOARD_DESIGN_SETTINGS::GetDRCEpsilon
int GetDRCEpsilon() const
Return an epsilon which accounts for rounding errors, etc.
Definition board_design_settings.cpp:1546
BOARD_DESIGN_SETTINGS::m_HoleToHoleMin
int m_HoleToHoleMin
Definition board_design_settings.h:701
BOARD_DESIGN_SETTINGS::m_MinSilkTextHeight
int m_MinSilkTextHeight
Definition board_design_settings.h:704
BOARD_DESIGN_SETTINGS::m_HoleClearance
int m_HoleClearance
Definition board_design_settings.h:700
BOARD_DESIGN_SETTINGS::m_SilkClearance
int m_SilkClearance
Definition board_design_settings.h:702
BOARD_DESIGN_SETTINGS::m_TrackMinWidth
int m_TrackMinWidth
Definition board_design_settings.h:693
BOARD_DESIGN_SETTINGS::m_ViasMinAnnularWidth
int m_ViasMinAnnularWidth
Definition board_design_settings.h:694
BOARD_ITEM
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition board_item.h:83
BOARD_ITEM::GetLayer
virtual PCB_LAYER_ID GetLayer() const
Return the primary layer this item is on.
Definition board_item.h:236
BOARD_ITEM::IsConnected
virtual bool IsConnected() const
Returns information if the object is derived from BOARD_CONNECTED_ITEM.
Definition board_item.h:138
BOARD_ITEM::GetParentFootprint
FOOTPRINT * GetParentFootprint() const
Definition board_item.cpp:98
BOARD_ITEM::GetLayerSet
virtual LSET GetLayerSet() const
Return a std::bitset of all layers on which the item physically resides.
Definition board_item.h:256
BOARD_ITEM::HasDrilledHole
virtual bool HasDrilledHole() const
Definition board_item.h:165
BOARD_ITEM::IsOnCopperLayer
virtual bool IsOnCopperLayer() const
Definition board_item.h:155
BOARD
Information pertinent to a Pcbnew printed circuit board.
Definition board.h:322
BOARD::FindNet
NETINFO_ITEM * FindNet(int aNetcode) const
Search for a net with the given netcode.
Definition board.cpp:2359
DELAY_PROFILE_TRACK_PROPAGATION_ENTRY
Represents a single line in a time domain profile track propagation setup.
Definition tuning_profiles.h:82
DELAY_PROFILE_TRACK_PROPAGATION_ENTRY::GetDiffPairGap
int GetDiffPairGap() const
Definition tuning_profiles.h:100
DELAY_PROFILE_TRACK_PROPAGATION_ENTRY::GetWidth
int GetWidth() const
Definition tuning_profiles.h:99
DELAY_PROFILE_TRACK_PROPAGATION_ENTRY::GetSignalLayer
PCB_LAYER_ID GetSignalLayer() const
Definition tuning_profiles.h:95
DRC_CACHE_GENERATOR
Definition drc_cache_generator.h:33
DRC_CACHE_GENERATOR::Run
virtual bool Run() override
Run this provider against the given PCB with configured options (if any).
Definition drc_cache_generator.cpp:36
DRC_CONSTRAINT
Definition drc_rule.h:156
DRC_CONSTRAINT::GetName
wxString GetName() const
Definition drc_rule.h:194
DRC_CONSTRAINT::m_DisallowFlags
int m_DisallowFlags
Definition drc_rule.h:229
DRC_CONSTRAINT::SetParentRule
void SetParentRule(DRC_RULE *aParentRule)
Definition drc_rule.h:189
DRC_CONSTRAINT::Value
MINOPTMAX< int > & Value()
Definition drc_rule.h:187
DRC_CONSTRAINT::GetValue
const MINOPTMAX< int > & GetValue() const
Definition drc_rule.h:186
DRC_CONSTRAINT::m_ZoneConnection
ZONE_CONNECTION m_ZoneConnection
Definition drc_rule.h:230
DRC_CONSTRAINT::SetName
void SetName(const wxString &aName)
Definition drc_rule.h:192
DRC_CONSTRAINT::m_Value
MINOPTMAX< int > m_Value
Definition drc_rule.h:228
DRC_CONSTRAINT::m_Type
DRC_CONSTRAINT_T m_Type
Definition drc_rule.h:227
DRC_CONSTRAINT::SetOptionsFromOther
void SetOptionsFromOther(const DRC_CONSTRAINT &aOther)
Definition drc_rule.h:224
DRC_CONSTRAINT::GetParentRule
DRC_RULE * GetParentRule() const
Definition drc_rule.h:190
DRC_CONSTRAINT::m_ImplicitMin
bool m_ImplicitMin
Definition drc_rule.h:232
DRC_ENGINE::m_constraintMap
std::map< DRC_CONSTRAINT_T, std::vector< DRC_ENGINE_CONSTRAINT * > * > m_constraintMap
Definition drc_engine.h:367
DRC_ENGINE::EvalClearanceBatch
DRC_CLEARANCE_BATCH EvalClearanceBatch(const BOARD_ITEM *a, const BOARD_ITEM *b, PCB_LAYER_ID aLayer)
Evaluate all clearance-related constraints in a single batch call.
Definition drc_engine.cpp:1997
DRC_ENGINE::AdvanceProgress
void AdvanceProgress()
Definition drc_engine.cpp:2159
DRC_ENGINE::createImplicitRule
std::shared_ptr< DRC_RULE > createImplicitRule(const wxString &name, DRC_IMPLICIT_SOURCE aImplicitSource)
Definition drc_engine.cpp:146
DRC_ENGINE::RunTests
void RunTests(EDA_UNITS aUnits, bool aReportAllTrackErrors, bool aTestFootprints, BOARD_COMMIT *aCommit=nullptr)
Run the DRC tests.
Definition drc_engine.cpp:870
DRC_ENGINE::m_ownClearanceCache
std::unordered_map< DRC_OWN_CLEARANCE_CACHE_KEY, int > m_ownClearanceCache
Definition drc_engine.h:378
DRC_ENGINE::m_hasDiffPairClearanceOverrides
bool m_hasDiffPairClearanceOverrides
Definition drc_engine.h:389
DRC_ENGINE::m_testFootprints
bool m_testFootprints
Definition drc_engine.h:364
DRC_ENGINE::addRule
void addRule(std::shared_ptr< DRC_RULE > &rule)
Definition drc_engine.h:327
DRC_ENGINE::m_progressReporter
PROGRESS_REPORTER * m_progressReporter
Definition drc_engine.h:371
DRC_ENGINE::ClearClearanceCache
void ClearClearanceCache()
Clear the entire clearance cache.
Definition drc_engine.cpp:2534
DRC_ENGINE::loadRules
void loadRules(const wxFileName &aPath)
Load and parse a rule set from an sexpr text file.
Definition drc_engine.cpp:663
DRC_ENGINE::m_testProviders
std::vector< DRC_TEST_PROVIDER * > m_testProviders
Definition drc_engine.h:360
DRC_ENGINE::m_logReporter
REPORTER * m_logReporter
Definition drc_engine.h:370
DRC_ENGINE::m_explicitConstraints
std::map< DRC_CONSTRAINT_T, std::vector< DRC_ENGINE_CONSTRAINT * > > m_explicitConstraints
Definition drc_engine.h:390
DRC_ENGINE::compileRules
void compileRules()
Definition drc_engine.cpp:702
DRC_ENGINE::QueryDistinctConstraints
std::set< int > QueryDistinctConstraints(DRC_CONSTRAINT_T aConstraintId)
Definition drc_engine.cpp:2231
DRC_ENGINE::m_drawingSheet
DS_PROXY_VIEW_ITEM * m_drawingSheet
Definition drc_engine.h:355
DRC_ENGINE::m_schematicNetlist
NETLIST * m_schematicNetlist
Definition drc_engine.h:356
DRC_ENGINE::m_clearanceCacheMutex
std::shared_mutex m_clearanceCacheMutex
Definition drc_engine.h:387
DRC_ENGINE::KeepRefreshing
bool KeepRefreshing(bool aWait=false)
Definition drc_engine.cpp:2150
DRC_ENGINE::m_board
BOARD * m_board
Definition drc_engine.h:354
DRC_ENGINE::GetCachedOwnClearance
int GetCachedOwnClearance(const BOARD_ITEM *aItem, PCB_LAYER_ID aLayer, wxString *aSource=nullptr)
Get the cached own clearance for an item on a specific layer.
Definition drc_engine.cpp:2461
DRC_ENGINE::m_reportAllTrackErrors
bool m_reportAllTrackErrors
Definition drc_engine.h:363
DRC_ENGINE::ReportProgress
bool ReportProgress(double aProgress)
Definition drc_engine.cpp:2173
DRC_ENGINE::GetTestProvider
DRC_TEST_PROVIDER * GetTestProvider(const wxString &name) const
Definition drc_engine.cpp:2355
DRC_ENGINE::HasRulesForConstraintType
bool HasRulesForConstraintType(DRC_CONSTRAINT_T constraintID)
Definition drc_engine.cpp:2201
DRC_ENGINE::GetDesignSettings
BOARD_DESIGN_SETTINGS * GetDesignSettings() const
Definition drc_engine.h:149
DRC_ENGINE::SetMaxProgress
void SetMaxProgress(int aSize)
Definition drc_engine.cpp:2166
DRC_ENGINE::DRC_ENGINE
DRC_ENGINE(BOARD *aBoard=nullptr, BOARD_DESIGN_SETTINGS *aSettings=nullptr)
Definition drc_engine.cpp:84
DRC_ENGINE::m_hasExplicitClearanceRules
bool m_hasExplicitClearanceRules
Definition drc_engine.h:388
DRC_ENGINE::m_errorLimits
std::vector< int > m_errorLimits
Definition drc_engine.h:362
DRC_ENGINE::IsErrorLimitExceeded
bool IsErrorLimitExceeded(int error_code)
Definition drc_engine.cpp:2107
DRC_ENGINE::ProcessAssertions
void ProcessAssertions(const BOARD_ITEM *a, std::function< void(const DRC_CONSTRAINT *)> aFailureHandler, REPORTER *aReporter=nullptr)
Definition drc_engine.cpp:2032
DRC_ENGINE::loadImplicitRules
void loadImplicitRules()
Definition drc_engine.cpp:160
DRC_ENGINE::m_violationHandler
DRC_VIOLATION_HANDLER m_violationHandler
Definition drc_engine.h:369
DRC_ENGINE::EvalRules
DRC_CONSTRAINT EvalRules(DRC_CONSTRAINT_T aConstraintType, const BOARD_ITEM *a, const BOARD_ITEM *b, PCB_LAYER_ID aLayer, REPORTER *aReporter=nullptr)
Definition drc_engine.cpp:959
DRC_ENGINE::m_rules
std::vector< std::shared_ptr< DRC_RULE > > m_rules
Definition drc_engine.h:358
DRC_ENGINE::IsCancelled
bool IsCancelled() const
Definition drc_engine.cpp:2195
DRC_ENGINE::m_netclassClearances
std::unordered_map< wxString, int > m_netclassClearances
Definition drc_engine.h:383
DRC_ENGINE::IsNetADiffPair
static bool IsNetADiffPair(BOARD *aBoard, NETINFO_ITEM *aNet, int &aNetP, int &aNetN)
Definition drc_engine.cpp:2297
DRC_ENGINE::IsNetTieExclusion
bool IsNetTieExclusion(int aTrackNetCode, PCB_LAYER_ID aTrackLayer, const VECTOR2I &aCollisionPos, BOARD_ITEM *aCollidingItem)
Check if the given collision between a track and another item occurs during the track's entry into a ...
Definition drc_engine.cpp:2331
DRC_ENGINE::~DRC_ENGINE
virtual ~DRC_ENGINE()
Definition drc_engine.cpp:103
DRC_ENGINE::QueryWorstConstraint
bool QueryWorstConstraint(DRC_CONSTRAINT_T aRuleId, DRC_CONSTRAINT &aConstraint)
Definition drc_engine.cpp:2208
DRC_ENGINE::GetItemsMatchingCondition
std::vector< BOARD_ITEM * > GetItemsMatchingCondition(const wxString &aExpression, DRC_CONSTRAINT_T aConstraint=ASSERTION_CONSTRAINT, REPORTER *aReporter=nullptr)
Evaluate a DRC condition against all board items and return matches.
Definition drc_engine.cpp:2367
DRC_ENGINE::InitEngine
void InitEngine(const wxFileName &aRulePath)
Initialize the DRC engine.
Definition drc_engine.cpp:803
DRC_ENGINE::EvalZoneConnection
DRC_CONSTRAINT EvalZoneConnection(const BOARD_ITEM *a, const BOARD_ITEM *b, PCB_LAYER_ID aLayer, REPORTER *aReporter=nullptr)
Definition drc_engine.cpp:925
DRC_ENGINE::MatchDpSuffix
static int MatchDpSuffix(const wxString &aNetName, wxString &aComplementNet, wxString &aBaseDpName)
Check if the given net is a diff pair, returning its polarity and complement if so.
Definition drc_engine.cpp:2247
DRC_ENGINE::ReportPhase
bool ReportPhase(const wxString &aMessage)
Definition drc_engine.cpp:2183
DRC_ENGINE::InitializeClearanceCache
void InitializeClearanceCache()
Initialize the clearance cache for all items on the board.
Definition drc_engine.cpp:2541
DRC_ENGINE::m_rulesValid
bool m_rulesValid
Definition drc_engine.h:359
DRC_ENGINE::InvalidateClearanceCache
void InvalidateClearanceCache(const KIID &aUuid)
Invalidate the clearance cache for a specific item.
Definition drc_engine.cpp:2517
DRC_ENGINE::m_designSettings
BOARD_DESIGN_SETTINGS * m_designSettings
Definition drc_engine.h:353
DRC_ENGINE::ReportViolation
void ReportViolation(const std::shared_ptr< DRC_ITEM > &aItem, const VECTOR2I &aPos, int aMarkerLayer, const std::function< void(PCB_MARKER *)> &aPathGenerator={})
Definition drc_engine.cpp:2114
DRC_RULES_PARSER
Definition drc_rule_parser.h:41
DRC_RULES_PARSER::Parse
void Parse(std::vector< std::shared_ptr< DRC_RULE > > &aRules, REPORTER *aReporter)
Definition drc_rule_parser.cpp:155
DRC_RULE_CONDITION
Definition drc_rule_condition.h:36
DRC_RULE_CONDITION::Compile
bool Compile(REPORTER *aReporter, int aSourceLine=0, int aSourceOffset=0)
Definition drc_rule_condition.cpp:89
DRC_RULE_CONDITION::EvaluateFor
bool EvaluateFor(const BOARD_ITEM *aItemA, const BOARD_ITEM *aItemB, int aConstraint, PCB_LAYER_ID aLayer, REPORTER *aReporter=nullptr)
Definition drc_rule_condition.cpp:43
DRC_RULE
Definition drc_rule.h:119
DRC_RULE::IsImplicit
bool IsImplicit() const
Definition drc_rule.h:134
DRC_RULE::m_Name
wxString m_Name
Definition drc_rule.h:143
DRC_SHOWMATCHES_PROVIDER_REGISTRY::GetShowMatchesProviders
std::vector< DRC_TEST_PROVIDER * > GetShowMatchesProviders() const
Definition drc_test_provider.h:85
DRC_SHOWMATCHES_PROVIDER_REGISTRY::Instance
static DRC_SHOWMATCHES_PROVIDER_REGISTRY & Instance()
Definition drc_test_provider.h:78
DRC_TEST_PROVIDER_REGISTRY::GetTestProviders
std::vector< DRC_TEST_PROVIDER * > GetTestProviders() const
Definition drc_test_provider.h:54
DRC_TEST_PROVIDER_REGISTRY::Instance
static DRC_TEST_PROVIDER_REGISTRY & Instance()
Definition drc_test_provider.h:47
DRC_TEST_PROVIDER
Represent a DRC "provider" which runs some DRC functions over a BOARD and spits out DRC_ITEM and posi...
Definition drc_test_provider.h:107
DRC_TEST_PROVIDER::Init
static void Init()
Definition drc_test_provider.cpp:61
DRC_TEST_PROVIDER::SetDRCEngine
void SetDRCEngine(DRC_ENGINE *engine)
Definition drc_test_provider.h:114
EDA_ITEM::GetItemDescription
virtual wxString GetItemDescription(UNITS_PROVIDER *aUnitsProvider, bool aFull) const
Return a user-visible description string of this item.
Definition eda_item.cpp:144
EDA_ITEM::m_Uuid
const KIID m_Uuid
Definition eda_item.h:522
EDA_ITEM::Type
KICAD_T Type() const
Returns the type of object.
Definition eda_item.h:110
EDA_ITEM::GetFlags
EDA_ITEM_FLAGS GetFlags() const
Definition eda_item.h:151
FILE_LINE_READER
A LINE_READER that reads from an open file.
Definition richio.h:158
FILE_LINE_READER::ReadLine
char * ReadLine() override
Read a line of text into the buffer and increments the line number counter.
Definition richio.cpp:208
FOOTPRINT::GetLocalZoneConnection
ZONE_CONNECTION GetLocalZoneConnection() const
Definition footprint.h:389
FOOTPRINT::MapPadNumbersToNetTieGroups
std::map< wxString, int > MapPadNumbersToNetTieGroups() const
Definition footprint.cpp:3643
FOOTPRINT::Pads
std::deque< PAD * > & Pads()
Definition footprint.h:304
FOOTPRINT::GetNetTieCache
const std::set< int > & GetNetTieCache(const BOARD_ITEM *aItem) const
Get the set of net codes that are allowed to connect to a footprint item.
Definition footprint.h:636
FOOTPRINT::IsNetTie
bool IsNetTie() const
Definition footprint.h:420
FOOTPRINT::GetItemDescription
wxString GetItemDescription(UNITS_PROVIDER *aUnitsProvider, bool aFull) const override
Return a user-visible description string of this item.
Definition footprint.cpp:2568
FOOTPRINT::GetCourtyard
const SHAPE_POLY_SET & GetCourtyard(PCB_LAYER_ID aLayer) const
Used in DRC to test the courtyard area (a complex polygon).
Definition footprint.cpp:3442
KIID
Definition kiid.h:49
KIID::AsString
wxString AsString() const
Definition kiid.cpp:247
LSET
LSET is a set of PCB_LAYER_IDs.
Definition lset.h:37
LSET::FrontMask
static const LSET & FrontMask()
Return a mask holding all technical layers and the external CU layer on front side.
Definition lset.cpp:705
LSET::BackMask
static const LSET & BackMask()
Return a mask holding all technical layers and the external CU layer on back side.
Definition lset.cpp:712
LSET::Seq
LSEQ Seq(const LSEQ &aSequence) const
Return an LSEQ from the union of this LSET and a desired sequence.
Definition lset.cpp:296
LSET::AllCuMask
static LSET AllCuMask()
return AllCuMask( MAX_CU_LAYERS );
Definition lset.cpp:591
LSET::Name
static wxString Name(PCB_LAYER_ID aLayerId)
Return the fixed name association with aLayerId.
Definition lset.cpp:188
MINOPTMAX::Min
T Min() const
Definition minoptmax.h:33
MINOPTMAX::SetMin
void SetMin(T v)
Definition minoptmax.h:41
MINOPTMAX::SetOpt
void SetOpt(T v)
Definition minoptmax.h:43
MINOPTMAX::HasMin
bool HasMin() const
Definition minoptmax.h:37
MINOPTMAX::SetMax
void SetMax(T v)
Definition minoptmax.h:42
NETCLASS
A collection of nets and the parameters used to route or test these nets.
Definition netclass.h:45
NETCLASS::GetName
const wxString GetName() const
Gets the name of this (maybe aggregate) netclass in a format for internal usage or for export to exte...
Definition netclass.cpp:328
NETINFO_ITEM
Handle the data for a net.
Definition netinfo.h:54
NETINFO_ITEM::GetNetname
const wxString & GetNetname() const
Definition netinfo.h:112
NETINFO_ITEM::GetNetCode
int GetNetCode() const
Definition netinfo.h:106
NET_SETTINGS::GetCompositeNetclasses
const std::map< wxString, std::shared_ptr< NETCLASS > > & GetCompositeNetclasses() const
Gets all composite (multiple assignment / missing defaults) netclasses.
Definition net_settings.cpp:530
NET_SETTINGS::GetNetclasses
const std::map< wxString, std::shared_ptr< NETCLASS > > & GetNetclasses() const
Gets all netclasses.
Definition net_settings.cpp:524
NET_SETTINGS::GetDefaultNetclass
std::shared_ptr< NETCLASS > GetDefaultNetclass()
Gets the default netclass for the project.
Definition net_settings.cpp:499
PAD
Definition pad.h:55
PCB_MARKER
Definition pcb_marker.h:38
PCB_SHAPE
Definition pcb_shape.h:38
PCB_SHAPE::GetLocalSolderMaskMargin
std::optional< int > GetLocalSolderMaskMargin() const
Definition pcb_shape.h:210
PCB_TRACK
Definition pcb_track.h:118
PCB_VIA
Definition pcb_track.h:416
PROF_TIMER
A small class to help profiling.
Definition profile.h:49
PROF_TIMER::Stop
void Stop()
Save the time when this function was called, and set the counter stane to stop.
Definition profile.h:88
PROF_TIMER::msecs
double msecs(bool aSinceLast=false)
Definition profile.h:149
PROJECT
Container for project specific data.
Definition project.h:65
REPORTER
A pure virtual class used to derive REPORTER objects from.
Definition reporter.h:73
REPORTER::HasMessageOfSeverity
virtual bool HasMessageOfSeverity(int aSeverityMask) const
Returns true if the reporter has one or more messages matching the specified severity mask.
Definition reporter.h:143
SHAPE_POLY_SET::IsEmpty
bool IsEmpty() const
Return true if the set is empty (no polygons at all)
Definition shape_poly_set.h:1284
UNITS_PROVIDER::GetIuScale
const EDA_IU_SCALE & GetIuScale() const
Definition units_provider.h:55
UNITS_PROVIDER::MessageTextFromUnscaledValue
wxString MessageTextFromUnscaledValue(double aValue, bool aAddUnitLabel=true, EDA_DATA_TYPE aType=EDA_DATA_TYPE::DISTANCE) const
Definition units_provider.h:141
UNITS_PROVIDER::UNITS_PROVIDER
UNITS_PROVIDER(const EDA_IU_SCALE &aIuScale, EDA_UNITS aUnits)
Definition units_provider.h:37
UNITS_PROVIDER::MessageTextFromValue
wxString MessageTextFromValue(double aValue, bool aAddUnitLabel=true, EDA_DATA_TYPE aType=EDA_DATA_TYPE::DISTANCE) const
A lower-precision version of StringFromValue().
Definition units_provider.h:127
UNITS_PROVIDER::SetUserUnits
void SetUserUnits(EDA_UNITS aUnits)
Definition units_provider.h:46
ZONE
Handle a list of polygons defining a copper zone.
Definition zone.h:74
ZONE::GetItemDescription
wxString GetItemDescription(UNITS_PROVIDER *aUnitsProvider, bool aFull) const override
Return a user-visible description string of this item.
Definition zone.cpp:1155
ZONE::GetIsRuleArea
bool GetIsRuleArea() const
Accessors to parameters used in Rule Area zones:
Definition zone.h:701
ZONE::GetDoNotAllowVias
bool GetDoNotAllowVias() const
Definition zone.h:712
ZONE::GetDoNotAllowPads
bool GetDoNotAllowPads() const
Definition zone.h:714
ZONE::GetDoNotAllowTracks
bool GetDoNotAllowTracks() const
Definition zone.h:713
ZONE::GetZoneName
const wxString & GetZoneName() const
Definition zone.h:159
ZONE::GetMinThickness
int GetMinThickness() const
Definition zone.h:297
ZONE::GetPadConnection
ZONE_CONNECTION GetPadConnection() const
Definition zone.h:294
ZONE::GetThermalReliefSpokeWidth
int GetThermalReliefSpokeWidth() const
Definition zone.h:241
ZONE::GetDoNotAllowFootprints
bool GetDoNotAllowFootprints() const
Definition zone.h:715
ZONE::GetLayerSet
virtual LSET GetLayerSet() const override
Return a std::bitset of all layers on which the item physically resides.
Definition zone.h:136
ZONE::HasKeepoutParametersSet
bool HasKeepoutParametersSet() const
Accessor to determine if any keepout parameters are set.
Definition zone.h:692
ZONE::GetDoNotAllowZoneFills
bool GetDoNotAllowZoneFills() const
Definition zone.h:711
ZONE::GetThermalReliefGap
int GetThermalReliefGap() const
Definition zone.h:230
ExpandTextVars
wxString ExpandTextVars(const wxString &aSource, const PROJECT *aProject, int aFlags)
Definition common.cpp:61
DescribeRef
wxString DescribeRef(const wxString &aRef)
Returns a user-visible HTML string describing a footprint reference designator.
Definition common.cpp:341
common.h
The common library.
connectivity_data.h
SIZE_UNITS::MM
@ MM
Definition dialog_export_3d_image.h:37
drc_cache_generator.h
drcPrintDebugMessage
void drcPrintDebugMessage(int level, const wxString &msg, const char *function, int line)
Definition drc_engine.cpp:70
EXTENDED_ERROR_LIMIT
#define EXTENDED_ERROR_LIMIT
Definition drc_engine.cpp:57
isKeepoutZone
static bool isKeepoutZone(const BOARD_ITEM *aItem, bool aCheckFlags)
Definition drc_engine.cpp:117
ERROR_LIMIT
#define ERROR_LIMIT
Definition drc_engine.cpp:56
drc_engine.h
drc_item.h
DRCE_TUNING_PROFILE_IMPLICIT_RULES
@ DRCE_TUNING_PROFILE_IMPLICIT_RULES
Definition drc_item.h:114
DRCE_UNCONNECTED_ITEMS
@ DRCE_UNCONNECTED_ITEMS
Definition drc_item.h:40
DRCE_CLEARANCE
@ DRCE_CLEARANCE
Definition drc_item.h:44
DRCE_FIRST
@ DRCE_FIRST
Definition drc_item.h:39
DRCE_LAST
@ DRCE_LAST
Definition drc_item.h:120
drc_rtree.h
drc_rule.h
DRC_IMPLICIT_SOURCE
DRC_IMPLICIT_SOURCE
Definition drc_rule.h:104
DRC_IMPLICIT_SOURCE::BARCODE_DEFAULTS
@ BARCODE_DEFAULTS
Definition drc_rule.h:107
DRC_IMPLICIT_SOURCE::TUNING_PROFILE
@ TUNING_PROFILE
Definition drc_rule.h:110
DRC_IMPLICIT_SOURCE::NET_CLASS
@ NET_CLASS
Definition drc_rule.h:109
DRC_IMPLICIT_SOURCE::KEEPOUT
@ KEEPOUT
Definition drc_rule.h:108
DRC_IMPLICIT_SOURCE::BOARD_SETUP_CONSTRAINT
@ BOARD_SETUP_CONSTRAINT
Definition drc_rule.h:106
DRC_DISALLOW_PADS
@ DRC_DISALLOW_PADS
Definition drc_rule.h:94
DRC_DISALLOW_BURIED_VIAS
@ DRC_DISALLOW_BURIED_VIAS
Definition drc_rule.h:92
DRC_DISALLOW_BLIND_VIAS
@ DRC_DISALLOW_BLIND_VIAS
Definition drc_rule.h:91
DRC_DISALLOW_TEXTS
@ DRC_DISALLOW_TEXTS
Definition drc_rule.h:96
DRC_DISALLOW_ZONES
@ DRC_DISALLOW_ZONES
Definition drc_rule.h:95
DRC_DISALLOW_HOLES
@ DRC_DISALLOW_HOLES
Definition drc_rule.h:98
DRC_DISALLOW_GRAPHICS
@ DRC_DISALLOW_GRAPHICS
Definition drc_rule.h:97
DRC_DISALLOW_THROUGH_VIAS
@ DRC_DISALLOW_THROUGH_VIAS
Definition drc_rule.h:89
DRC_DISALLOW_FOOTPRINTS
@ DRC_DISALLOW_FOOTPRINTS
Definition drc_rule.h:99
DRC_DISALLOW_TRACKS
@ DRC_DISALLOW_TRACKS
Definition drc_rule.h:93
DRC_DISALLOW_MICRO_VIAS
@ DRC_DISALLOW_MICRO_VIAS
Definition drc_rule.h:90
DRC_CONSTRAINT_T
DRC_CONSTRAINT_T
Definition drc_rule.h:47
ANNULAR_WIDTH_CONSTRAINT
@ ANNULAR_WIDTH_CONSTRAINT
Definition drc_rule.h:61
COURTYARD_CLEARANCE_CONSTRAINT
@ COURTYARD_CLEARANCE_CONSTRAINT
Definition drc_rule.h:55
VIA_DIAMETER_CONSTRAINT
@ VIA_DIAMETER_CONSTRAINT
Definition drc_rule.h:70
ZONE_CONNECTION_CONSTRAINT
@ ZONE_CONNECTION_CONSTRAINT
Definition drc_rule.h:62
DIFF_PAIR_GAP_CONSTRAINT
@ DIFF_PAIR_GAP_CONSTRAINT
Definition drc_rule.h:73
DISALLOW_CONSTRAINT
@ DISALLOW_CONSTRAINT
Definition drc_rule.h:69
TRACK_WIDTH_CONSTRAINT
@ TRACK_WIDTH_CONSTRAINT
Definition drc_rule.h:59
SILK_CLEARANCE_CONSTRAINT
@ SILK_CLEARANCE_CONSTRAINT
Definition drc_rule.h:56
EDGE_CLEARANCE_CONSTRAINT
@ EDGE_CLEARANCE_CONSTRAINT
Definition drc_rule.h:53
MIN_RESOLVED_SPOKES_CONSTRAINT
@ MIN_RESOLVED_SPOKES_CONSTRAINT
Definition drc_rule.h:65
TEXT_THICKNESS_CONSTRAINT
@ TEXT_THICKNESS_CONSTRAINT
Definition drc_rule.h:58
LENGTH_CONSTRAINT
@ LENGTH_CONSTRAINT
Definition drc_rule.h:71
PHYSICAL_HOLE_CLEARANCE_CONSTRAINT
@ PHYSICAL_HOLE_CLEARANCE_CONSTRAINT
Definition drc_rule.h:78
CLEARANCE_CONSTRAINT
@ CLEARANCE_CONSTRAINT
Definition drc_rule.h:49
NULL_CONSTRAINT
@ NULL_CONSTRAINT
Definition drc_rule.h:48
THERMAL_SPOKE_WIDTH_CONSTRAINT
@ THERMAL_SPOKE_WIDTH_CONSTRAINT
Definition drc_rule.h:64
CONNECTION_WIDTH_CONSTRAINT
@ CONNECTION_WIDTH_CONSTRAINT
Definition drc_rule.h:80
THERMAL_RELIEF_GAP_CONSTRAINT
@ THERMAL_RELIEF_GAP_CONSTRAINT
Definition drc_rule.h:63
MAX_UNCOUPLED_CONSTRAINT
@ MAX_UNCOUPLED_CONSTRAINT
Definition drc_rule.h:74
ASSERTION_CONSTRAINT
@ ASSERTION_CONSTRAINT
Definition drc_rule.h:79
SKEW_CONSTRAINT
@ SKEW_CONSTRAINT
Definition drc_rule.h:72
HOLE_CLEARANCE_CONSTRAINT
@ HOLE_CLEARANCE_CONSTRAINT
Definition drc_rule.h:51
SOLDER_PASTE_ABS_MARGIN_CONSTRAINT
@ SOLDER_PASTE_ABS_MARGIN_CONSTRAINT
Definition drc_rule.h:67
SOLDER_MASK_EXPANSION_CONSTRAINT
@ SOLDER_MASK_EXPANSION_CONSTRAINT
Definition drc_rule.h:66
HOLE_SIZE_CONSTRAINT
@ HOLE_SIZE_CONSTRAINT
Definition drc_rule.h:54
TEXT_HEIGHT_CONSTRAINT
@ TEXT_HEIGHT_CONSTRAINT
Definition drc_rule.h:57
CREEPAGE_CONSTRAINT
@ CREEPAGE_CONSTRAINT
Definition drc_rule.h:50
PHYSICAL_CLEARANCE_CONSTRAINT
@ PHYSICAL_CLEARANCE_CONSTRAINT
Definition drc_rule.h:77
SOLDER_PASTE_REL_MARGIN_CONSTRAINT
@ SOLDER_PASTE_REL_MARGIN_CONSTRAINT
Definition drc_rule.h:68
HOLE_TO_HOLE_CONSTRAINT
@ HOLE_TO_HOLE_CONSTRAINT
Definition drc_rule.h:52
DRC_DISALLOW_VIAS
constexpr int DRC_DISALLOW_VIAS
Definition drc_rule.h:114
drc_rule_condition.h
drc_rule_parser.h
drc_test_provider.h
_
#define _(s)
Definition eda_3d_actions.cpp:36
HOLE_PROXY
#define HOLE_PROXY
Indicates the BOARD_ITEM is a proxy for its hole.
Definition eda_item_flags.h:65
EDA_UNITS
EDA_UNITS
Definition eda_units.h:48
resolver
static FILENAME_RESOLVER * resolver
Definition export_idf.cpp:53
from_to_cache.h
traceDrcProfile
static const wxChar * traceDrcProfile
Flag to enable DRC profile timing logging.
Definition drc_engine.cpp:67
THROW_PARSE_ERROR
#define THROW_PARSE_ERROR(aProblem, aSource, aInputLine, aLineNumber, aByteIndex)
Definition ki_exception.h:165
IsPcbLayer
bool IsPcbLayer(int aLayer)
Test whether a layer is a valid layer for Pcbnew.
Definition layer_ids.h:666
PCB_LAYER_ID
PCB_LAYER_ID
A quick note on layer IDs:
Definition layer_ids.h:60
F_CrtYd
@ F_CrtYd
Definition layer_ids.h:116
F_SilkS
@ F_SilkS
Definition layer_ids.h:100
B_CrtYd
@ B_CrtYd
Definition layer_ids.h:115
B_SilkS
@ B_SilkS
Definition layer_ids.h:101
REPORT
#define REPORT(msg)
Definition lib_symbol.cpp:1844
PAD_ATTRIB::NPTH
@ NPTH
like PAD_PTH, but not plated mechanical use only, no connection allowed
Definition padstack.h:103
PAD_ATTRIB::PTH
@ PTH
Plated through hole pad.
Definition padstack.h:98
pcb_shape.h
pcb_track.h
progress_reporter.h
project_file.h
RPT_SEVERITY_ERROR
@ RPT_SEVERITY_ERROR
Definition report_severity.h:35
epsilon
const double epsilon
Definition resistor_substitution_utils.h:30
dummy
std::vector< FAB_LAYER_COLOR > dummy
Definition stackup_predefined_prms.cpp:97
EscapeHTML
wxString EscapeHTML(const wxString &aString)
Return a new wxString escaped for embedding in HTML.
Definition string_utils.cpp:570
string_utils.h
TO_UTF8
#define TO_UTF8(wxstring)
Convert a wxString to a UTF8 encoded C string for all wxWidgets build modes.
Definition string_utils.h:453
DRC_CLEARANCE_BATCH
Batch result for clearance-related constraints to reduce per-query overhead during PNS routing.
Definition drc_engine.h:112
DRC_ENGINE::DRC_ENGINE_CONSTRAINT
Definition drc_engine.h:342
DRC_ENGINE::DRC_ENGINE_CONSTRAINT::parentRule
std::shared_ptr< DRC_RULE > parentRule
Definition drc_engine.h:345
DRC_ENGINE::DRC_ENGINE_CONSTRAINT::layerTest
LSET layerTest
Definition drc_engine.h:343
DRC_ENGINE::DRC_ENGINE_CONSTRAINT::condition
DRC_RULE_CONDITION * condition
Definition drc_engine.h:344
DRC_ENGINE::DRC_ENGINE_CONSTRAINT::constraint
DRC_CONSTRAINT constraint
Definition drc_engine.h:346
DRC_OWN_CLEARANCE_CACHE_KEY
Cache key for own clearance lookups, combining item UUID and layer.
Definition drc_engine.h:43
PARSE_ERROR
A filename or source description, a problem input line, a line number, a byte offset,...
Definition ki_exception.h:120
TUNING_PROFILE
Represents a single line in the tuning profile configuration grid.
Definition tuning_profiles.h:146
TUNING_PROFILE::PROFILE_TYPE::SINGLE
@ SINGLE
Definition tuning_profiles.h:149
TUNING_PROFILE::m_Type
PROFILE_TYPE m_Type
Definition tuning_profiles.h:154
TUNING_PROFILE::m_TrackPropagationEntries
std::vector< DELAY_PROFILE_TRACK_PROPAGATION_ENTRY > m_TrackPropagationEntries
Definition tuning_profiles.h:157
clearance
int clearance
Definition test_shape_arc.cpp:974
result
wxString result
Test unit parsing edge cases and error handling.
Definition test_text_eval_numeric_compat.cpp:602
GetKiCadThreadPool
thread_pool & GetKiCadThreadPool()
Get a reference to the current thread pool.
Definition thread_pool.cpp:31
tp
static thread_pool * tp
Definition thread_pool.cpp:28
thread_pool.h
thread_pool
BS::priority_thread_pool thread_pool
Definition thread_pool.h:31
tuning_profiles.h
PCB_SHAPE_T
@ PCB_SHAPE_T
class PCB_SHAPE, a segment not on copper layers
Definition typeinfo.h:88
PCB_GENERATOR_T
@ PCB_GENERATOR_T
class PCB_GENERATOR, generator on a layer
Definition typeinfo.h:91
PCB_VIA_T
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
Definition typeinfo.h:97
PCB_GROUP_T
@ PCB_GROUP_T
class PCB_GROUP, a set of BOARD_ITEMs
Definition typeinfo.h:111
PCB_TEXTBOX_T
@ PCB_TEXTBOX_T
class PCB_TEXTBOX, wrapped text on a layer
Definition typeinfo.h:93
PCB_ZONE_T
@ PCB_ZONE_T
class ZONE, a copper pour area
Definition typeinfo.h:108
PCB_TEXT_T
@ PCB_TEXT_T
class PCB_TEXT, text on a layer
Definition typeinfo.h:92
PCB_FIELD_T
@ PCB_FIELD_T
class PCB_FIELD, text associated with a footprint property
Definition typeinfo.h:90
PCB_BARCODE_T
@ PCB_BARCODE_T
class PCB_BARCODE, a barcode (graphic item)
Definition typeinfo.h:101
PCB_FOOTPRINT_T
@ PCB_FOOTPRINT_T
class FOOTPRINT, a footprint
Definition typeinfo.h:86
PCB_PAD_T
@ PCB_PAD_T
class PAD, a pad in a footprint
Definition typeinfo.h:87
PCB_ARC_T
@ PCB_ARC_T
class PCB_ARC, an arc track segment on a copper layer
Definition typeinfo.h:98
PCB_TABLE_T
@ PCB_TABLE_T
class PCB_TABLE, table of PCB_TABLECELLs
Definition typeinfo.h:94
PCB_NETINFO_T
@ PCB_NETINFO_T
class NETINFO_ITEM, a description of a net
Definition typeinfo.h:110
PCB_LOCATE_HOLE_T
@ PCB_LOCATE_HOLE_T
Definition typeinfo.h:131
PCB_TRACE_T
@ PCB_TRACE_T
class PCB_TRACK, a track segment (segment on a copper layer)
Definition typeinfo.h:96
VECTOR2I
VECTOR2< int32_t > VECTOR2I
Definition vector2d.h:695
PrintZoneConnection
wxString PrintZoneConnection(ZONE_CONNECTION aConnection)
Definition zones.h:56
ZONE_CONNECTION
ZONE_CONNECTION
How pads are covered by copper in zone.
Definition zones.h:47
ZONE_CONNECTION::THERMAL
@ THERMAL
Use thermal relief for pads.
Definition zones.h:50
ZONE_CONNECTION::THT_THERMAL
@ THT_THERMAL
Thermal relief only for THT pads.
Definition zones.h:52
ZONE_CONNECTION::FULL
@ FULL
pads are covered by copper
Definition zones.h:51