KiCad PCB EDA Suite
drc_cache_generator.cpp
Go to the documentation of this file.
1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright (C) 2022 KiCad Developers.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, you may find one here:
18 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
19 * or you may search the http://www.gnu.org website for the version 2 license,
20 * or you may write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
22 */
23
24#include <common.h>
26#include <footprint.h>
27#include <thread_pool.h>
28#include <zone.h>
29
30#include <drc/drc_engine.h>
31#include <drc/drc_rtree.h>
33
35{
37
38 int& m_largestClearance = m_board->m_DRCMaxClearance;
39 int& m_largestPhysicalClearance = m_board->m_DRCMaxPhysicalClearance;
40 DRC_CONSTRAINT worstConstraint;
41
43 m_largestClearance = worstConstraint.GetValue().Min();
44
46 m_largestClearance = std::max( m_largestClearance, worstConstraint.GetValue().Min() );
47
49 m_largestPhysicalClearance = worstConstraint.GetValue().Min();
50
52 m_largestPhysicalClearance = std::max( m_largestPhysicalClearance, worstConstraint.GetValue().Min() );
53
54 std::set<ZONE*> allZones;
55
56 for( ZONE* zone : m_board->Zones() )
57 {
58 allZones.insert( zone );
59
60 if( !zone->GetIsRuleArea() )
61 {
62 m_board->m_DRCZones.push_back( zone );
63
64 if( ( zone->GetLayerSet() & LSET::AllCuMask() ).any() )
65 {
66 m_board->m_DRCCopperZones.push_back( zone );
67 m_largestClearance = std::max( m_largestClearance, zone->GetLocalClearance() );
68 }
69 }
70 }
71
72 for( FOOTPRINT* footprint : m_board->Footprints() )
73 {
74 for( PAD* pad : footprint->Pads() )
75 m_largestClearance = std::max( m_largestClearance, pad->GetLocalClearance() );
76
77 for( ZONE* zone : footprint->Zones() )
78 {
79 allZones.insert( zone );
80
81 if( !zone->GetIsRuleArea() )
82 {
83 m_board->m_DRCZones.push_back( zone );
84
85 if( ( zone->GetLayerSet() & LSET::AllCuMask() ).any() )
86 {
87 m_board->m_DRCCopperZones.push_back( zone );
88 m_largestClearance = std::max( m_largestClearance, zone->GetLocalClearance() );
89 }
90 }
91 }
92 }
93
94 // This is the number of tests between 2 calls to the progress bar
95 size_t progressDelta = 200;
96 size_t count = 0;
97 size_t ii = 0;
98
99 auto countItems =
100 [&]( BOARD_ITEM* item ) -> bool
101 {
102 ++count;
103 return true;
104 };
105
106 auto addToCopperTree =
107 [&]( BOARD_ITEM* item ) -> bool
108 {
109 if( !reportProgress( ii++, count, progressDelta ) )
110 return false;
111
112 LSET layers = item->GetLayerSet();
113
114 // Special-case pad holes which pierce all the copper layers
115 if( item->Type() == PCB_PAD_T )
116 {
117 PAD* pad = static_cast<PAD*>( item );
118
119 if( pad->HasHole() )
120 layers |= LSET::AllCuMask();
121 }
122
123 for( PCB_LAYER_ID layer : layers.Seq() )
124 {
125 if( IsCopperLayer( layer ) )
126 m_board->m_CopperItemRTreeCache->Insert( item, layer, m_largestClearance );
127 }
128
129 return true;
130 };
131
132 if( !reportPhase( _( "Gathering copper items..." ) ) )
133 return false; // DRC cancelled
134
135 static const std::vector<KICAD_T> itemTypes = {
137 PCB_PAD_T,
141 };
142
143 forEachGeometryItem( itemTypes, LSET::AllCuMask(), countItems );
144 forEachGeometryItem( itemTypes, LSET::AllCuMask(), addToCopperTree );
145
146 if( !reportPhase( _( "Tessellating copper zones..." ) ) )
147 return false; // DRC cancelled
148
149 // Cache zone bounding boxes, triangulation, copper zone rtrees, and footprint courtyards
150 // before we start.
151
152 for( FOOTPRINT* footprint : m_board->Footprints() )
153 footprint->BuildCourtyardCaches();
154
156 std::vector<std::future<size_t>> returns;
157 std::atomic<size_t> done( 1 );
158
159 returns.reserve( allZones.size() );
160
161 auto cache_zones =
162 [this, &done]( ZONE* aZone ) -> size_t
163 {
164 if( m_drcEngine->IsCancelled() )
165 return 0;
166
167 aZone->CacheBoundingBox();
168 aZone->CacheTriangulation();
169
170 if( !aZone->GetIsRuleArea() && aZone->IsOnCopperLayer() )
171 {
172 std::unique_ptr<DRC_RTREE> rtree = std::make_unique<DRC_RTREE>();
173
174 for( PCB_LAYER_ID layer : aZone->GetLayerSet().Seq() )
175 {
176 if( IsCopperLayer( layer ) )
177 rtree->Insert( aZone, layer );
178 }
179
180 std::unique_lock<std::mutex> cacheLock( m_board->m_CachesMutex );
181 m_board->m_CopperZoneRTreeCache[ aZone ] = std::move( rtree );
182
183 done.fetch_add( 1 );
184 }
185
186 return 1;
187 };
188
189 for( ZONE* zone : allZones )
190 returns.emplace_back( tp.submit( cache_zones, zone ) );
191
192 for( const std::future<size_t>& ret : returns )
193 {
194 std::future_status status = ret.wait_for( std::chrono::milliseconds( 250 ) );
195
196 while( status != std::future_status::ready )
197 {
198 m_drcEngine->ReportProgress( static_cast<double>( done ) / allZones.size() );
199 status = ret.wait_for( std::chrono::milliseconds( 250 ) );
200 }
201 }
202
203 return !m_drcEngine->IsCancelled();
204}
205
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition: board_item.h:50
std::vector< ZONE * > m_DRCCopperZones
Definition: board.h:1157
ZONES & Zones()
Definition: board.h:313
FOOTPRINTS & Footprints()
Definition: board.h:307
std::unique_ptr< DRC_RTREE > m_CopperItemRTreeCache
Definition: board.h:1153
int m_DRCMaxPhysicalClearance
Definition: board.h:1159
int m_DRCMaxClearance
Definition: board.h:1158
std::unordered_map< ZONE *, std::unique_ptr< DRC_RTREE > > m_CopperZoneRTreeCache
Definition: board.h:1152
std::vector< ZONE * > m_DRCZones
Definition: board.h:1156
std::mutex m_CachesMutex
Definition: board.h:1145
virtual bool Run() override
Run this provider against the given PCB with configured options (if any).
const MINOPTMAX< int > & GetValue() const
Definition: drc_rule.h:139
BOARD * GetBoard() const
Definition: drc_engine.h:89
bool ReportProgress(double aProgress)
bool IsCancelled() const
bool QueryWorstConstraint(DRC_CONSTRAINT_T aRuleId, DRC_CONSTRAINT &aConstraint)
virtual bool reportPhase(const wxString &aStageName)
int forEachGeometryItem(const std::vector< KICAD_T > &aTypes, LSET aLayers, const std::function< bool(BOARD_ITEM *)> &aFunc)
virtual bool reportProgress(int aCount, int aSize, int aDelta)
DRC_ENGINE * m_drcEngine
LSET is a set of PCB_LAYER_IDs.
Definition: layer_ids.h:530
LSEQ Seq(const PCB_LAYER_ID *aWishListSequence, unsigned aCount) const
Return an LSEQ from the union of this LSET and a desired sequence.
Definition: lset.cpp:411
static LSET AllCuMask(int aCuLayerCount=MAX_CU_LAYERS)
Return a mask holding the requested number of Cu PCB_LAYER_IDs.
Definition: lset.cpp:773
T Min() const
Definition: minoptmax.h:33
Definition: pad.h:58
Handle a list of polygons defining a copper zone.
Definition: zone.h:57
The common library.
@ PHYSICAL_HOLE_CLEARANCE_CONSTRAINT
Definition: drc_rule.h:70
@ CLEARANCE_CONSTRAINT
Definition: drc_rule.h:46
@ HOLE_CLEARANCE_CONSTRAINT
Definition: drc_rule.h:47
@ PHYSICAL_CLEARANCE_CONSTRAINT
Definition: drc_rule.h:69
#define _(s)
bool IsCopperLayer(int aLayerId)
Tests whether a layer is a copper layer.
Definition: layer_ids.h:823
PCB_LAYER_ID
A quick note on layer IDs:
Definition: layer_ids.h:59
thread_pool & GetKiCadThreadPool()
Get a reference to the current thread pool.
Definition: thread_pool.cpp:32
static thread_pool * tp
Definition: thread_pool.cpp:30
BS::thread_pool thread_pool
Definition: thread_pool.h:30
@ PCB_SHAPE_T
class PCB_SHAPE, a segment not on copper layers
Definition: typeinfo.h:88
@ PCB_FP_SHAPE_T
class FP_SHAPE, a footprint edge
Definition: typeinfo.h:94
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
Definition: typeinfo.h:102
@ PCB_FP_TEXTBOX_T
class FP_TEXTBOX, wrapped text in a footprint
Definition: typeinfo.h:93
@ PCB_TEXTBOX_T
class PCB_TEXTBOX, wrapped text on a layer
Definition: typeinfo.h:91
@ PCB_TEXT_T
class PCB_TEXT, text on a layer
Definition: typeinfo.h:90
@ PCB_PAD_T
class PAD, a pad in a footprint
Definition: typeinfo.h:87
@ PCB_FP_TEXT_T
class FP_TEXT, text in a footprint
Definition: typeinfo.h:92
@ PCB_ARC_T
class PCB_ARC, an arc track segment on a copper layer
Definition: typeinfo.h:103
@ PCB_DIMENSION_T
class PCB_DIMENSION_BASE: abstract dimension meta-type
Definition: typeinfo.h:105
@ PCB_TRACE_T
class PCB_TRACK, a track segment (segment on a copper layer)
Definition: typeinfo.h:101