KiCad PCB EDA Suite
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drc_test_provider_solder_mask.cpp
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1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright The KiCad Developers.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, you may find one here:
18 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
19 * or you may search the http://www.gnu.org website for the version 2 license,
20 * or you may write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
22 */
23
24#include <common.h>
27#include <footprint.h>
28#include <pad.h>
29#include <pcb_track.h>
30#include <pcb_text.h>
31#include <thread_pool.h>
32#include <zone.h>
33#include <geometry/seg.h>
34#include <drc/drc_engine.h>
35#include <drc/drc_item.h>
36#include <drc/drc_rule.h>
38#include <drc/drc_rtree.h>
39
40/*
41 Solder mask tests. Checks for silkscreen which is clipped by mask openings and for bridges
42 between mask apertures with different nets.
43 Errors generated:
44 - DRCE_SILK_MASK_CLEARANCE
45 - DRCE_SOLDERMASK_BRIDGE
46*/
47
49{
50public:
52 m_board( nullptr ),
53 m_webWidth( 0 ),
54 m_maxError( 0 ),
56 {
57 m_bridgeRule.m_Name = _( "board setup solder mask min width" );
58 }
59
60 virtual ~DRC_TEST_PROVIDER_SOLDER_MASK() = default;
61
62 virtual bool Run() override;
63
64 virtual const wxString GetName() const override { return wxT( "solder_mask_issues" ); };
65
66private:
67 void addItemToRTrees( BOARD_ITEM* aItem );
68 void buildRTrees();
69
71 void testMaskBridges();
72
73 void testItemAgainstItems( BOARD_ITEM* aItem, const BOX2I& aItemBBox,
74 PCB_LAYER_ID aRefLayer, PCB_LAYER_ID aTargetLayer );
75 void testMaskItemAgainstZones( BOARD_ITEM* item, const BOX2I& itemBBox,
76 PCB_LAYER_ID refLayer, PCB_LAYER_ID targetLayer );
77
78 bool checkMaskAperture( BOARD_ITEM* aMaskItem, BOARD_ITEM* aTestItem, PCB_LAYER_ID aTestLayer,
79 int aTestNet, BOARD_ITEM** aCollidingItem );
80
81 bool checkItemMask( BOARD_ITEM* aItem, int aTestNet );
82
83private:
85
90
91 std::unique_ptr<DRC_RTREE> m_fullSolderMaskRTree;
92 std::unique_ptr<DRC_RTREE> m_itemTree;
93
95 std::unordered_map<PTR_PTR_CACHE_KEY, LSET> m_checkedPairs;
96
97 // Shapes used to define solder mask apertures don't have nets, so we assign them the
98 // first object+net that bridges their aperture (after which any other nets will generate
99 // violations).
100 std::unordered_map<PTR_LAYER_CACHE_KEY, std::pair<BOARD_ITEM*, int>> m_maskApertureNetMap;
101};
102
103
105{
106 for( PCB_LAYER_ID layer : { F_Mask, B_Mask } )
107 {
108 if( !aItem->IsOnLayer( layer ) )
109 continue;
110
111 SHAPE_POLY_SET* solderMask = m_board->m_SolderMaskBridges->GetFill( layer );
112
113 if( aItem->Type() == PCB_ZONE_T )
114 {
115 ZONE* zone = static_cast<ZONE*>( aItem );
116
117 solderMask->BooleanAdd( *zone->GetFilledPolysList( layer ) );
118 }
119 else
120 {
121 int clearance = m_webWidth / 2;
122
123 if( aItem->Type() == PCB_PAD_T )
124 clearance += static_cast<PAD*>( aItem )->GetSolderMaskExpansion( layer );
125 else if( aItem->Type() == PCB_VIA_T )
126 clearance += static_cast<PCB_VIA*>( aItem )->GetSolderMaskExpansion();
127 else if( aItem->Type() == PCB_SHAPE_T )
128 clearance += static_cast<PCB_SHAPE*>( aItem )->GetSolderMaskExpansion();
129
130 if( aItem->Type() == PCB_FIELD_T || aItem->Type() == PCB_TEXT_T )
131 {
132 PCB_TEXT* text = static_cast<PCB_TEXT*>( aItem );
133
134 text->TransformTextToPolySet( *solderMask, clearance, m_maxError, ERROR_OUTSIDE );
135 }
136 else
137 {
138 aItem->TransformShapeToPolygon( *solderMask, layer, clearance, m_maxError, ERROR_OUTSIDE );
139 }
140
141 m_itemTree->Insert( aItem, layer, m_largestClearance );
142 }
143 }
144}
145
146
148{
149 ZONE* solderMask = m_board->m_SolderMaskBridges;
150 LSET layers( { F_Mask, B_Mask, F_Cu, B_Cu } );
151
152 const size_t progressDelta = 500;
153 int count = 0;
154 int ii = 0;
155
156 solderMask->GetFill( F_Mask )->RemoveAllContours();
157 solderMask->GetFill( B_Mask )->RemoveAllContours();
158
159 m_fullSolderMaskRTree = std::make_unique<DRC_RTREE>();
160 m_itemTree = std::make_unique<DRC_RTREE>();
161
163 [&]( BOARD_ITEM* item ) -> bool
164 {
165 ++count;
166 return true;
167 } );
168
170 [&]( BOARD_ITEM* item ) -> bool
171 {
172 if( !reportProgress( ii++, count, progressDelta ) )
173 return false;
174
175 addItemToRTrees( item );
176 return true;
177 } );
178
179 solderMask->GetFill( F_Mask )->Simplify();
180 solderMask->GetFill( B_Mask )->Simplify();
181
182 if( m_webWidth > 0 )
183 {
186 }
187
188 solderMask->SetFillFlag( F_Mask, true );
189 solderMask->SetFillFlag( B_Mask, true );
190 solderMask->SetIsFilled( true );
191
192 solderMask->CacheTriangulation();
193
194 m_fullSolderMaskRTree->Insert( solderMask, F_Mask );
195 m_fullSolderMaskRTree->Insert( solderMask, B_Mask );
196
197 m_checkedPairs.clear();
198}
199
200
202{
203 LSET silkLayers( { F_SilkS, B_SilkS } );
204
205 // If we have no minimum web width then we delegate to the silk checker which does object-to-object
206 // testing (instead of object-to-solder-mask-zone-fill checking that we do here).
207 if( m_webWidth <= 0 )
208 return;
209
210 const size_t progressDelta = 250;
211 int count = 0;
212 int ii = 0;
213
215 [&]( BOARD_ITEM* item ) -> bool
216 {
217 ++count;
218 return true;
219 } );
220
222 [&]( BOARD_ITEM* item ) -> bool
223 {
224 if( m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_MASK_CLEARANCE ) )
225 return false;
226
227 if( !reportProgress( ii++, count, progressDelta ) )
228 return false;
229
230 if( isInvisibleText( item ) )
231 return true;
232
233 for( PCB_LAYER_ID layer : silkLayers )
234 {
235 if( !item->IsOnLayer( layer ) )
236 continue;
237
238 PCB_LAYER_ID maskLayer = layer == F_SilkS ? F_Mask : B_Mask;
239 BOX2I itemBBox = item->GetBoundingBox();
241 item, nullptr, maskLayer );
242 int clearance = constraint.GetValue().Min();
243 int actual;
244 VECTOR2I pos;
245
246 if( constraint.GetSeverity() == RPT_SEVERITY_IGNORE || clearance < 0 )
247 return true;
248
249 std::shared_ptr<SHAPE> itemShape = item->GetEffectiveShape( layer );
250
251 if( m_fullSolderMaskRTree->QueryColliding( itemBBox, itemShape.get(), maskLayer,
252 clearance, &actual, &pos ) )
253 {
254 std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_SILK_MASK_CLEARANCE );
255
256 if( clearance > 0 )
257 {
258 wxString msg = formatMsg( _( "(%s clearance %s; actual %s)" ),
259 constraint.GetName(),
260 clearance,
261 actual );
262
263 drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
264 }
265
266 drce->SetItems( item );
267 drce->SetViolatingRule( constraint.GetParentRule() );
268
269 reportViolation( drce, pos, layer );
270 }
271 }
272
273 return true;
274 } );
275}
276
277
279{
280 if( aItem->Type() == PCB_PAD_T )
281 {
282 PAD* pad = static_cast<PAD*>( aItem );
283
284 // TODO(JE) padstacks
285 if( pad->GetAttribute() == PAD_ATTRIB::NPTH
286 && ( pad->GetShape( PADSTACK::ALL_LAYERS ) == PAD_SHAPE::CIRCLE
287 || pad->GetShape( PADSTACK::ALL_LAYERS ) == PAD_SHAPE::OVAL )
288 && pad->GetSize( PADSTACK::ALL_LAYERS ).x <= pad->GetDrillSize().x
289 && pad->GetSize( PADSTACK::ALL_LAYERS ).y <= pad->GetDrillSize().y )
290 {
291 return true;
292 }
293 }
294
295 return false;
296}
297
298
299// Simple mask apertures aren't associated with copper items, so they only constitute a bridge
300// when they expose other copper items having at least two distinct nets. We use a map to record
301// the first net exposed by each mask aperture (on each copper layer).
302//
303// Note that this algorithm is also used for free pads.
304
306{
307 if( aItem->Type() == PCB_PAD_T && static_cast<PAD*>( aItem )->IsFreePad() )
308 return true;
309
310 static const LSET saved( { F_Mask, B_Mask } );
311
312 LSET maskLayers = aItem->GetLayerSet() & saved;
313 LSET copperLayers = ( aItem->GetLayerSet() & ~saved ) & LSET::AllCuMask();
314
315 return maskLayers.count() > 0 && copperLayers.count() == 0;
316}
317
318
320 PCB_LAYER_ID aTestLayer, int aTestNet,
321 BOARD_ITEM** aCollidingItem )
322{
323 if( aTestLayer == F_Mask && !aTestItem->IsOnLayer( F_Cu ) )
324 return false;
325
326 if( aTestLayer == B_Mask && !aTestItem->IsOnLayer( B_Cu ) )
327 return false;
328
329 PCB_LAYER_ID maskLayer = IsFrontLayer( aTestLayer ) ? F_Mask : B_Mask;
330
331 FOOTPRINT* fp = aMaskItem->GetParentFootprint();
332
333 // Mask apertures in footprints which allow soldermask bridges are ignored entirely.
334 if( fp && fp->AllowSolderMaskBridges() )
335 return false;
336
337 PTR_LAYER_CACHE_KEY key = { aMaskItem, maskLayer };
338
339 auto ii = m_maskApertureNetMap.find( key );
340
341 if( ii == m_maskApertureNetMap.end() )
342 {
343 m_maskApertureNetMap[ key ] = { aTestItem, aTestNet };
344
345 // First net; no bridge yet....
346 return false;
347 }
348
349 auto& [cacheKey, cacheEntry] = *ii;
350 auto& [alreadyEncounteredItem, encounteredItemNet] = cacheEntry;
351
352 if( encounteredItemNet == aTestNet && aTestNet >= 0 )
353 {
354 // Same net; still no bridge...
355 return false;
356 }
357
358 if( fp && aTestItem->GetParentFootprint() == fp )
359 {
360 std::map<wxString, int> padToNetTieGroupMap = fp->MapPadNumbersToNetTieGroups();
361 PAD* padA = nullptr;
362 PAD* padB = nullptr;
363
364 if( alreadyEncounteredItem->Type() == PCB_PAD_T )
365 padA = static_cast<PAD*>( alreadyEncounteredItem );
366
367 if( aTestItem->Type() == PCB_PAD_T )
368 padB = static_cast<PAD*>( aTestItem );
369
370 if( padA && padB && ( padA->SameLogicalPadAs( padB ) || padA->SharesNetTieGroup( padB ) ) )
371 {
372 return false;
373 }
374 else if( padA && aTestItem->Type() == PCB_SHAPE_T )
375 {
376 if( padToNetTieGroupMap.contains( padA->GetNumber() ) )
377 return false;
378 }
379 else if( padB && alreadyEncounteredItem->Type() == PCB_SHAPE_T )
380 {
381 if( padToNetTieGroupMap.contains( padB->GetNumber() ) )
382 return false;
383 }
384 }
385
386 *aCollidingItem = alreadyEncounteredItem;
387 return true;
388}
389
390
392{
393 if( FOOTPRINT* fp = aItem->GetParentFootprint() )
394 {
395 // If we're allowing bridges then we're allowing bridges. Nothing to check.
396 if( fp->AllowSolderMaskBridges() )
397 return false;
398
399 // Items belonging to a net-tie may share the mask aperture of pads in the same group.
400 if( aItem->Type() == PCB_PAD_T && fp->IsNetTie() )
401 {
402 PAD* pad = static_cast<PAD*>( aItem );
403 std::map<wxString, int> padNumberToGroupIdxMap = fp->MapPadNumbersToNetTieGroups();
404 int groupIdx = padNumberToGroupIdxMap[ pad->GetNumber() ];
405
406 if( groupIdx >= 0 )
407 {
408 if( aTestNet < 0 )
409 return false;
410
411 if( pad->GetNetCode() == aTestNet )
412 return false;
413
414 for( PAD* other : fp->GetNetTiePads( pad ) )
415 {
416 if( other->GetNetCode() == aTestNet )
417 return false;
418 }
419 }
420 }
421 }
422
423 return true;
424}
425
426
428 PCB_LAYER_ID aRefLayer, PCB_LAYER_ID aTargetLayer )
429{
430 PAD* pad = aItem->Type() == PCB_PAD_T ? static_cast<PAD*>( aItem ) : nullptr;
431 PCB_VIA* via = aItem->Type() == PCB_VIA_T ? static_cast<PCB_VIA*>( aItem ) : nullptr;
432 PCB_SHAPE* shape = aItem->Type() == PCB_SHAPE_T ? static_cast<PCB_SHAPE*>( aItem ) : nullptr;
433 int itemNet = -1;
434
435 DRC_CONSTRAINT constraint;
436 std::optional<bool> itemConstraintIgnored;
437
438 if( aItem->IsConnected() )
439 itemNet = static_cast<BOARD_CONNECTED_ITEM*>( aItem )->GetNetCode();
440
441 std::shared_ptr<SHAPE> itemShape = aItem->GetEffectiveShape( aRefLayer );
442
443 m_itemTree->QueryColliding( aItem, aRefLayer, aTargetLayer,
444 // Filter:
445 [&]( BOARD_ITEM* other ) -> bool
446 {
447 FOOTPRINT* itemFP = aItem->GetParentFootprint();
448 PAD* otherPad = other->Type() == PCB_PAD_T ? static_cast<PAD*>( other ) : nullptr;
449 int otherNet = -1;
450
451 if( other->IsConnected() )
452 otherNet = static_cast<BOARD_CONNECTED_ITEM*>( other )->GetNetCode();
453
454 if( otherNet > 0 && otherNet == itemNet )
455 return false;
456
457 if( isNullAperture( other ) )
458 return false;
459
460 if( itemFP && itemFP == other->GetParentFootprint() )
461 {
462 // Board-wide exclusion
463 if( BOARD* board = itemFP->GetBoard() )
464 {
465 if( board->GetDesignSettings().m_AllowSoldermaskBridgesInFPs )
466 return false;
467 }
468
469 // Footprint-specific exclusion
470 if( itemFP->AllowSolderMaskBridges() )
471 return false;
472 }
473
474 if( pad && otherPad && ( pad->SameLogicalPadAs( otherPad )
475 || pad->SharesNetTieGroup( otherPad ) ) )
476 {
477 return false;
478 }
479
480 if( itemFP && itemFP->IsNetTie() )
481 {
482 const std::set<int>& nets = itemFP->GetNetTieCache( aItem );
483
484 if( otherNet < 0 || nets.count( otherNet ) )
485 return false;
486 }
487
488 if( FOOTPRINT* otherFP = other->GetParentFootprint(); otherFP && otherFP->IsNetTie() )
489 {
490 const std::set<int>& nets = otherFP->GetNetTieCache( other );
491
492 if( itemNet < 0 || nets.count( itemNet ) )
493 return false;
494 }
495
496 BOARD_ITEM* a = aItem;
497 BOARD_ITEM* b = other;
498
499 // store canonical order so we don't collide in both directions (a:b and b:a)
500 if( static_cast<void*>( a ) > static_cast<void*>( b ) )
501 std::swap( a, b );
502
503 {
504 std::lock_guard<std::mutex> lock( m_checkedPairsMutex );
505 auto it = m_checkedPairs.find( { a, b } );
506
507 if( it != m_checkedPairs.end() && it->second.test( aTargetLayer ) )
508 {
509 return false;
510 }
511 else
512 {
513 m_checkedPairs[{ a, b }].set( aTargetLayer );
514 return true;
515 }
516 }
517 },
518 // Visitor:
519 [&]( BOARD_ITEM* other ) -> bool
520 {
521 PAD* otherPad = other->Type() == PCB_PAD_T ? static_cast<PAD*>( other ) : nullptr;
522 PCB_VIA* otherVia = other->Type() == PCB_VIA_T ? static_cast<PCB_VIA*>( other ) : nullptr;
523 PCB_SHAPE* otherShape = other->Type() == PCB_SHAPE_T ? static_cast<PCB_SHAPE*>( other ) : nullptr;
524 auto otherItemShape = other->GetEffectiveShape( aTargetLayer );
525 int otherNet = -1;
526
527 if( other->IsConnected() )
528 otherNet = static_cast<BOARD_CONNECTED_ITEM*>( other )->GetNetCode();
529
530 int actual;
531 VECTOR2I pos;
532 int clearance = 0;
533
534 if( aRefLayer == F_Mask || aRefLayer == B_Mask )
535 {
536 // Aperture-to-aperture must enforce web-min-width
538 }
539 else // ( aRefLayer == F_Cu || aRefLayer == B_Cu )
540 {
541 // Copper-to-aperture uses the solder-mask-to-copper-clearance
542 clearance = m_board->GetDesignSettings().m_SolderMaskToCopperClearance;
543 }
544
545 if( pad )
546 clearance += pad->GetSolderMaskExpansion( aRefLayer );
547 else if( via && !via->IsTented( aRefLayer ) )
548 clearance += via->GetSolderMaskExpansion();
549 else if( shape )
551
552 if( otherPad )
553 clearance += otherPad->GetSolderMaskExpansion( aTargetLayer );
554 else if( otherVia && !otherVia->IsTented( aTargetLayer ) )
555 clearance += otherVia->GetSolderMaskExpansion();
556 else if( otherShape )
557 clearance += otherShape->GetSolderMaskExpansion();
558
559 if( itemShape->Collide( otherItemShape.get(), clearance, &actual, &pos ) )
560 {
561 if( !itemConstraintIgnored.has_value() )
562 {
563 constraint = m_drcEngine->EvalRules( BRIDGED_MASK_CONSTRAINT, aItem, nullptr, aRefLayer );
564 itemConstraintIgnored = constraint.GetSeverity() == RPT_SEVERITY_IGNORE;
565 }
566
567 constraint = m_drcEngine->EvalRules( BRIDGED_MASK_CONSTRAINT, other, nullptr, aTargetLayer );
568 bool otherConstraintIgnored = constraint.GetSeverity() == RPT_SEVERITY_IGNORE;
569
570 // Mask apertures are ignored on their own; in other cases both participants must be ignored
571 if( ( isMaskAperture( aItem ) && itemConstraintIgnored )
572 || ( isMaskAperture( other ) && otherConstraintIgnored )
573 || ( itemConstraintIgnored && otherConstraintIgnored ) )
574 {
575 return !m_drcEngine->IsCancelled();
576 }
577
578 wxString msg;
579 BOARD_ITEM* colliding = nullptr;
580
581 if( aTargetLayer == F_Mask )
582 msg = _( "Front solder mask aperture bridges items with different nets" );
583 else
584 msg = _( "Rear solder mask aperture bridges items with different nets" );
585
586 // Simple mask apertures aren't associated with copper items, so they only
587 // constitute a bridge when they expose other copper items having at least
588 // two distinct nets.
589 if( isMaskAperture( aItem ) )
590 {
591 if( checkMaskAperture( aItem, other, aRefLayer, otherNet, &colliding ) )
592 {
593 std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_SOLDERMASK_BRIDGE );
594
595 drce->SetErrorMessage( msg );
596 drce->SetItems( aItem, colliding, other );
597 drce->SetViolatingRule( &m_bridgeRule );
598 reportViolation( drce, pos, aTargetLayer );
599 }
600 }
601 else if( isMaskAperture( other ) )
602 {
603 if( checkMaskAperture( other, aItem, aRefLayer, itemNet, &colliding ) )
604 {
605 std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_SOLDERMASK_BRIDGE );
606
607 drce->SetErrorMessage( msg );
608 drce->SetItems( other, colliding, aItem );
609 drce->SetViolatingRule( &m_bridgeRule );
610 reportViolation( drce, pos, aTargetLayer );
611 }
612 }
613 else if( checkItemMask( other, itemNet ) )
614 {
615 std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_SOLDERMASK_BRIDGE );
616
617 drce->SetErrorMessage( msg );
618 drce->SetItems( aItem, other );
619 drce->SetViolatingRule( &m_bridgeRule );
620 reportViolation( drce, pos, aTargetLayer );
621 }
622 }
623
624 return !m_drcEngine->IsCancelled();
625 },
627}
628
629
631 PCB_LAYER_ID aMaskLayer, PCB_LAYER_ID aTargetLayer )
632{
633 PAD* pad = aItem->Type() == PCB_PAD_T ? static_cast<PAD*>( aItem ) : nullptr;
634 PCB_VIA* via = aItem->Type() == PCB_VIA_T ? static_cast<PCB_VIA*>( aItem ) : nullptr;
635 PCB_SHAPE* shape = aItem->Type() == PCB_SHAPE_T ? static_cast<PCB_SHAPE*>( aItem ) : nullptr;
636
637 for( ZONE* zone : m_board->m_DRCCopperZones )
638 {
639 if( !zone->GetLayerSet().test( aTargetLayer ) )
640 continue;
641
642 int zoneNet = zone->GetNetCode();
643
644 if( aItem->IsConnected() )
645 {
646 BOARD_CONNECTED_ITEM* connectedItem = static_cast<BOARD_CONNECTED_ITEM*>( aItem );
647
648 if( zoneNet == connectedItem->GetNetCode() && zoneNet > 0 )
649 continue;
650 }
651
652 BOX2I inflatedBBox( aItemBBox );
653 int clearance = m_board->GetDesignSettings().m_SolderMaskToCopperClearance;
654
655 if( pad )
656 clearance += pad->GetSolderMaskExpansion( aTargetLayer );
657 else if( via && !via->IsTented( aTargetLayer ) )
658 clearance += via->GetSolderMaskExpansion();
659 else if( shape )
661
662 inflatedBBox.Inflate( clearance );
663
664 if( !inflatedBBox.Intersects( zone->GetBoundingBox() ) )
665 continue;
666
667 DRC_RTREE* zoneTree = m_board->m_CopperZoneRTreeCache[ zone ].get();
668 int actual;
669 VECTOR2I pos;
670
671 std::shared_ptr<SHAPE> itemShape = aItem->GetEffectiveShape( aMaskLayer );
672
673 if( zoneTree && zoneTree->QueryColliding( aItemBBox, itemShape.get(), aTargetLayer, clearance,
674 &actual, &pos ) )
675 {
676 wxString msg;
677 BOARD_ITEM* colliding = nullptr;
678
679 if( aMaskLayer == F_Mask )
680 msg = _( "Front solder mask aperture bridges items with different nets" );
681 else
682 msg = _( "Rear solder mask aperture bridges items with different nets" );
683
684 // Simple mask apertures aren't associated with copper items, so they only constitute
685 // a bridge when they expose other copper items having at least two distinct nets.
686 if( isMaskAperture( aItem ) && zoneNet >= 0 )
687 {
688 if( checkMaskAperture( aItem, zone, aTargetLayer, zoneNet, &colliding ) )
689 {
690 std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_SOLDERMASK_BRIDGE );
691
692 drce->SetErrorMessage( msg );
693 drce->SetItems( aItem, colliding, zone );
694 drce->SetViolatingRule( &m_bridgeRule );
695 reportViolation( drce, pos, aTargetLayer );
696 }
697 }
698 else
699 {
700 std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_SOLDERMASK_BRIDGE );
701
702 drce->SetErrorMessage( msg );
703 drce->SetItems( aItem, zone );
704 drce->SetViolatingRule( &m_bridgeRule );
705 reportViolation( drce, pos, aTargetLayer );
706 }
707 }
708
709 if( m_drcEngine->IsCancelled() )
710 return;
711 }
712}
713
714
716{
717 LSET copperAndMaskLayers( { F_Mask, B_Mask, F_Cu, B_Cu } );
718 std::atomic<int> count = 0;
719 std::vector<BOARD_ITEM*> test_items;
720
721 forEachGeometryItem( s_allBasicItemsButZones, copperAndMaskLayers,
722 [&]( BOARD_ITEM* item ) -> bool
723 {
724 test_items.push_back( item );
725 return true;
726 } );
727
729
730 auto returns = tp.submit_loop( 0, test_items.size(),
731 [&]( size_t i ) -> bool
732 {
733 BOARD_ITEM* item = test_items[ i ];
734
735 if( m_drcEngine->IsErrorLimitExceeded( DRCE_SOLDERMASK_BRIDGE ) )
736 return false;
737
738 BOX2I itemBBox = item->GetBoundingBox();
739
740 if( item->IsOnLayer( F_Mask ) && !isNullAperture( item ) )
741 {
742 // Test for aperture-to-aperture collisions
743 testItemAgainstItems( item, itemBBox, F_Mask, F_Mask );
744
745 // Test for aperture-to-zone collisions
746 testMaskItemAgainstZones( item, itemBBox, F_Mask, F_Cu );
747 }
748 else if( item->IsOnLayer( PADSTACK::ALL_LAYERS ) )
749 {
750 // Test for copper-item-to-aperture collisions
751 testItemAgainstItems( item, itemBBox, F_Cu, F_Mask );
752 }
753
754 if( item->IsOnLayer( B_Mask ) && !isNullAperture( item ) )
755 {
756 // Test for aperture-to-aperture collisions
757 testItemAgainstItems( item, itemBBox, B_Mask, B_Mask );
758
759 // Test for aperture-to-zone collisions
760 testMaskItemAgainstZones( item, itemBBox, B_Mask, B_Cu );
761 }
762 else if( item->IsOnLayer( B_Cu ) )
763 {
764 // Test for copper-item-to-aperture collisions
765 testItemAgainstItems( item, itemBBox, B_Cu, B_Mask );
766 }
767
768 ++count;
769
770 return true;
771 } );
772
773 for( auto& ret : returns )
774 {
775 if( !ret.valid() )
776 continue;
777
778 while( ret.wait_for( std::chrono::milliseconds( 100 ) ) == std::future_status::timeout )
779 reportProgress( count, test_items.size() );
780 }
781}
782
783
785{
786 if( m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_MASK_CLEARANCE )
787 && m_drcEngine->IsErrorLimitExceeded( DRCE_SOLDERMASK_BRIDGE ) )
788 {
789 REPORT_AUX( wxT( "Solder mask violations ignored. Tests not run." ) );
790 return true; // continue with other tests
791 }
792
793 m_board = m_drcEngine->GetBoard();
794 m_webWidth = m_board->GetDesignSettings().m_SolderMaskMinWidth;
795 m_maxError = m_board->GetDesignSettings().m_MaxError;
797
798 auto updateLargestClearance =
799 [&]( int aClearance )
800 {
801 m_largestClearance = std::max( m_largestClearance, aClearance );
802 };
803
804 for( FOOTPRINT* footprint : m_board->Footprints() )
805 {
806 for( PAD* pad : footprint->Pads() )
807 updateLargestClearance( pad->GetSolderMaskExpansion( PADSTACK::ALL_LAYERS ) );
808
809 for( BOARD_ITEM* item : footprint->GraphicalItems() )
810 {
811 if( item->Type() == PCB_SHAPE_T )
812 updateLargestClearance( static_cast<PCB_SHAPE*>( item )->GetSolderMaskExpansion() );
813 }
814 }
815
816 for( PCB_TRACK* track : m_board->Tracks() )
817 updateLargestClearance( track->GetSolderMaskExpansion() );
818
819 for( BOARD_ITEM* item : m_board->Drawings() )
820 {
821 if( item->Type() == PCB_SHAPE_T )
822 updateLargestClearance( static_cast<PCB_SHAPE*>( item )->GetSolderMaskExpansion() );
823 }
824
825 // Order is important here: m_webWidth must be added in before m_largestCourtyardClearance is
826 // maxed with the various SILK_CLEARANCE_CONSTRAINTS.
828
829 DRC_CONSTRAINT worstClearanceConstraint;
830
831 if( m_drcEngine->QueryWorstConstraint( SILK_CLEARANCE_CONSTRAINT, worstClearanceConstraint ) )
832 m_largestClearance = std::max( m_largestClearance, worstClearanceConstraint.m_Value.Min() );
833
834 if( !reportPhase( _( "Building solder mask..." ) ) )
835 return false; // DRC cancelled
836
837 m_checkedPairs.clear();
838 m_maskApertureNetMap.clear();
839
840 buildRTrees();
841
842 if( !reportPhase( _( "Checking solder mask to silk clearance..." ) ) )
843 return false; // DRC cancelled
844
846
847 if( !reportPhase( _( "Checking solder mask web integrity..." ) ) )
848 return false; // DRC cancelled
849
851
852 return !m_drcEngine->IsCancelled();
853}
854
855
856namespace detail
857{
859}
@ ERROR_OUTSIDE
BOX2< VECTOR2I > BOX2I
Definition box2.h:922
A base class derived from BOARD_ITEM for items that can be connected and have a net,...
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition board_item.h:79
virtual bool IsConnected() const
Returns information if the object is derived from BOARD_CONNECTED_ITEM.
Definition board_item.h:134
virtual void TransformShapeToPolygon(SHAPE_POLY_SET &aBuffer, PCB_LAYER_ID aLayer, int aClearance, int aError, ERROR_LOC aErrorLoc, bool ignoreLineWidth=false) const
Convert the item shape to a closed polygon.
virtual bool IsOnLayer(PCB_LAYER_ID aLayer) const
Test to see if this object is on the given layer.
Definition board_item.h:314
virtual std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
virtual const BOARD * GetBoard() const
Return the BOARD in which this BOARD_ITEM resides, or NULL if none.
FOOTPRINT * GetParentFootprint() const
virtual LSET GetLayerSet() const
Return a std::bitset of all layers on which the item physically resides.
Definition board_item.h:252
Information pertinent to a Pcbnew printed circuit board.
Definition board.h:317
constexpr BOX2< Vec > & Inflate(coord_type dx, coord_type dy)
Inflates the rectangle horizontally by dx and vertically by dy.
Definition box2.h:558
constexpr bool Intersects(const BOX2< Vec > &aRect) const
Definition box2.h:311
wxString GetName() const
Definition drc_rule.h:170
SEVERITY GetSeverity() const
Definition drc_rule.h:183
const MINOPTMAX< int > & GetValue() const
Definition drc_rule.h:162
MINOPTMAX< int > m_Value
Definition drc_rule.h:204
DRC_RULE * GetParentRule() const
Definition drc_rule.h:166
static std::shared_ptr< DRC_ITEM > Create(int aErrorCode)
Constructs a DRC_ITEM for the given error code.
Definition drc_item.cpp:381
Implement an R-tree for fast spatial and layer indexing of connectable items.
Definition drc_rtree.h:48
int QueryColliding(BOARD_ITEM *aRefItem, PCB_LAYER_ID aRefLayer, PCB_LAYER_ID aTargetLayer, std::function< bool(BOARD_ITEM *)> aFilter=nullptr, std::function< bool(BOARD_ITEM *)> aVisitor=nullptr, int aClearance=0) const
This is a fast test which essentially does bounding-box overlap given a worst-case clearance.
Definition drc_rtree.h:214
virtual const wxString GetName() const override
void testMaskItemAgainstZones(BOARD_ITEM *item, const BOX2I &itemBBox, PCB_LAYER_ID refLayer, PCB_LAYER_ID targetLayer)
virtual ~DRC_TEST_PROVIDER_SOLDER_MASK()=default
bool checkMaskAperture(BOARD_ITEM *aMaskItem, BOARD_ITEM *aTestItem, PCB_LAYER_ID aTestLayer, int aTestNet, BOARD_ITEM **aCollidingItem)
std::unique_ptr< DRC_RTREE > m_fullSolderMaskRTree
virtual bool Run() override
Run this provider against the given PCB with configured options (if any).
std::unordered_map< PTR_PTR_CACHE_KEY, LSET > m_checkedPairs
bool checkItemMask(BOARD_ITEM *aItem, int aTestNet)
std::unordered_map< PTR_LAYER_CACHE_KEY, std::pair< BOARD_ITEM *, int > > m_maskApertureNetMap
void testItemAgainstItems(BOARD_ITEM *aItem, const BOX2I &aItemBBox, PCB_LAYER_ID aRefLayer, PCB_LAYER_ID aTargetLayer)
static std::vector< KICAD_T > s_allBasicItemsButZones
virtual bool reportPhase(const wxString &aStageName)
int forEachGeometryItem(const std::vector< KICAD_T > &aTypes, const LSET &aLayers, const std::function< bool(BOARD_ITEM *)> &aFunc)
static std::vector< KICAD_T > s_allBasicItems
virtual void reportViolation(std::shared_ptr< DRC_ITEM > &item, const VECTOR2I &aMarkerPos, int aMarkerLayer, const std::vector< PCB_SHAPE > &aShapes={})
bool isInvisibleText(const BOARD_ITEM *aItem) const
wxString formatMsg(const wxString &aFormatString, const wxString &aSource, double aConstraint, double aActual, EDA_DATA_TYPE aDataType=EDA_DATA_TYPE::DISTANCE)
virtual bool reportProgress(size_t aCount, size_t aSize, size_t aDelta=1)
virtual const BOX2I GetBoundingBox() const
Return the orthogonal bounding box of this object for display purposes.
Definition eda_item.cpp:110
KICAD_T Type() const
Returns the type of object.
Definition eda_item.h:110
bool AllowSolderMaskBridges() const
Definition footprint.h:333
std::map< wxString, int > MapPadNumbersToNetTieGroups() const
const std::set< int > & GetNetTieCache(const BOARD_ITEM *aItem) const
Get the set of net codes that are allowed to connect to a footprint item.
Definition footprint.h:556
bool IsNetTie() const
Definition footprint.h:340
LSET is a set of PCB_LAYER_IDs.
Definition lset.h:37
static LSET AllCuMask()
return AllCuMask( MAX_CU_LAYERS );
Definition lset.cpp:591
T Min() const
Definition minoptmax.h:33
static constexpr PCB_LAYER_ID ALL_LAYERS
! Temporary layer identifier to identify code that is not padstack-aware
Definition padstack.h:145
Definition pad.h:54
const wxString & GetNumber() const
Definition pad.h:136
bool SameLogicalPadAs(const PAD *aOther) const
Before we had custom pad shapes it was common to have multiple overlapping pads to represent a more c...
Definition pad.h:159
int GetSolderMaskExpansion(PCB_LAYER_ID aLayer) const
Definition pad.cpp:1177
bool IsFreePad() const
Definition pad.cpp:284
bool SharesNetTieGroup(const PAD *aOther) const
Definition pad.cpp:261
int GetSolderMaskExpansion() const
bool IsTented(PCB_LAYER_ID aLayer) const override
Checks if the given object is tented (its copper shape is covered by solder mask) on a given side of ...
int GetSolderMaskExpansion() const
Represent a set of closed polygons.
void RemoveAllContours()
Remove all outlines & holes (clears) the polygon set.
void BooleanAdd(const SHAPE_POLY_SET &b)
Perform boolean polyset union.
void Simplify()
Simplify the polyset (merges overlapping polys, eliminates degeneracy/self-intersections)
void Deflate(int aAmount, CORNER_STRATEGY aCornerStrategy, int aMaxError)
Handle a list of polygons defining a copper zone.
Definition zone.h:74
const std::shared_ptr< SHAPE_POLY_SET > & GetFilledPolysList(PCB_LAYER_ID aLayer) const
Definition zone.h:600
void CacheTriangulation(PCB_LAYER_ID aLayer=UNDEFINED_LAYER)
Create a list of triangles that "fill" the solid areas used for instance to draw these solid areas on...
Definition zone.cpp:1301
const BOX2I GetBoundingBox() const override
Definition zone.cpp:621
void SetFillFlag(PCB_LAYER_ID aLayer, bool aFlag)
Definition zone.h:290
SHAPE_POLY_SET * GetFill(PCB_LAYER_ID aLayer)
Definition zone.h:606
void SetIsFilled(bool isFilled)
Definition zone.h:293
virtual LSET GetLayerSet() const override
Return a std::bitset of all layers on which the item physically resides.
Definition zone.h:136
The common library.
@ CHAMFER_ALL_CORNERS
All angles are chamfered.
@ DRCE_SILK_MASK_CLEARANCE
Definition drc_item.h:96
@ DRCE_SOLDERMASK_BRIDGE
Definition drc_item.h:93
@ BRIDGED_MASK_CONSTRAINT
Definition drc_rule.h:83
@ SILK_CLEARANCE_CONSTRAINT
Definition drc_rule.h:56
#define REPORT_AUX(s)
bool isMaskAperture(BOARD_ITEM *aItem)
bool isNullAperture(BOARD_ITEM *aItem)
#define _(s)
bool IsFrontLayer(PCB_LAYER_ID aLayerId)
Layer classification: check if it's a front layer.
Definition layer_ids.h:776
PCB_LAYER_ID
A quick note on layer IDs:
Definition layer_ids.h:60
@ B_Mask
Definition layer_ids.h:98
@ B_Cu
Definition layer_ids.h:65
@ F_Mask
Definition layer_ids.h:97
@ F_SilkS
Definition layer_ids.h:100
@ B_SilkS
Definition layer_ids.h:101
@ F_Cu
Definition layer_ids.h:64
static DRC_REGISTER_TEST_PROVIDER< DRC_TEST_PROVIDER_ANNULAR_WIDTH > dummy
@ NPTH
like PAD_PTH, but not plated mechanical use only, no connection allowed
Definition padstack.h:87
@ RPT_SEVERITY_IGNORE
int clearance
int actual
thread_pool & GetKiCadThreadPool()
Get a reference to the current thread pool.
static thread_pool * tp
BS::thread_pool< 0 > thread_pool
Definition thread_pool.h:31
@ PCB_SHAPE_T
class PCB_SHAPE, a segment not on copper layers
Definition typeinfo.h:88
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
Definition typeinfo.h:97
@ PCB_ZONE_T
class ZONE, a copper pour area
Definition typeinfo.h:107
@ PCB_TEXT_T
class PCB_TEXT, text on a layer
Definition typeinfo.h:92
@ PCB_FIELD_T
class PCB_FIELD, text associated with a footprint property
Definition typeinfo.h:90
@ PCB_PAD_T
class PAD, a pad in a footprint
Definition typeinfo.h:87
VECTOR2< int32_t > VECTOR2I
Definition vector2d.h:695