KiCad PCB EDA Suite
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drc_test_provider_solder_mask.cpp
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1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright The KiCad Developers.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, you may find one here:
18 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
19 * or you may search the http://www.gnu.org website for the version 2 license,
20 * or you may write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
22 */
23
24#include <common.h>
27#include <footprint.h>
28#include <pad.h>
29#include <pcb_track.h>
30#include <pcb_text.h>
31#include <zone.h>
32#include <geometry/seg.h>
33#include <drc/drc_engine.h>
34#include <drc/drc_item.h>
35#include <drc/drc_rule.h>
37#include <drc/drc_rtree.h>
38
39/*
40 Solder mask tests. Checks for silkscreen which is clipped by mask openings and for bridges
41 between mask apertures with different nets.
42 Errors generated:
43 - DRCE_SILK_MASK_CLEARANCE
44 - DRCE_SOLDERMASK_BRIDGE
45*/
46
48{
49public:
51 m_board( nullptr ),
52 m_webWidth( 0 ),
53 m_maxError( 0 ),
55 {
56 m_bridgeRule.m_Name = _( "board setup solder mask min width" );
57 }
58
59 virtual ~DRC_TEST_PROVIDER_SOLDER_MASK() = default;
60
61 virtual bool Run() override;
62
63 virtual const wxString GetName() const override { return wxT( "solder_mask_issues" ); };
64
65private:
66 void addItemToRTrees( BOARD_ITEM* aItem );
67 void buildRTrees();
68
70 void testMaskBridges();
71
72 void testItemAgainstItems( BOARD_ITEM* aItem, const BOX2I& aItemBBox,
73 PCB_LAYER_ID aRefLayer, PCB_LAYER_ID aTargetLayer );
74 void testMaskItemAgainstZones( BOARD_ITEM* item, const BOX2I& itemBBox,
75 PCB_LAYER_ID refLayer, PCB_LAYER_ID targetLayer );
76
77 bool checkMaskAperture( BOARD_ITEM* aMaskItem, BOARD_ITEM* aTestItem, PCB_LAYER_ID aTestLayer,
78 int aTestNet, BOARD_ITEM** aCollidingItem );
79
80 bool checkItemMask( BOARD_ITEM* aMaskItem, int aTestNet );
81
82private:
84
89
90 std::unique_ptr<DRC_RTREE> m_fullSolderMaskRTree;
91 std::unique_ptr<DRC_RTREE> m_itemTree;
92
93 std::unordered_map<PTR_PTR_CACHE_KEY, LSET> m_checkedPairs;
94
95 // Shapes used to define solder mask apertures don't have nets, so we assign them the
96 // first object+net that bridges their aperture (after which any other nets will generate
97 // violations).
98 std::unordered_map<PTR_LAYER_CACHE_KEY, std::pair<BOARD_ITEM*, int>> m_maskApertureNetMap;
99};
100
101
103{
104 ZONE* solderMask = m_board->m_SolderMaskBridges;
105
106 if( aItem->Type() == PCB_ZONE_T )
107 {
108 ZONE* zone = static_cast<ZONE*>( aItem );
109
110 for( PCB_LAYER_ID layer : { F_Mask, B_Mask } )
111 {
112 if( zone->IsOnLayer( layer ) )
113 {
114 solderMask->GetFill( layer )->BooleanAdd( *zone->GetFilledPolysList( layer ) );
115 }
116 }
117 }
118 else if( aItem->Type() == PCB_PAD_T )
119 {
120 for( PCB_LAYER_ID layer : { F_Mask, B_Mask } )
121 {
122 if( aItem->IsOnLayer( layer ) )
123 {
124 PAD* pad = static_cast<PAD*>( aItem );
125 int clearance = ( m_webWidth / 2 ) + pad->GetSolderMaskExpansion( layer );
126
127 aItem->TransformShapeToPolygon( *solderMask->GetFill( layer ), layer, clearance,
129
130 m_itemTree->Insert( aItem, layer, m_largestClearance );
131 }
132 }
133 }
134 else if( aItem->Type() == PCB_VIA_T )
135 {
136 for( PCB_LAYER_ID layer : { F_Mask, B_Mask } )
137 {
138 if( aItem->IsOnLayer( layer ) )
139 {
140 PCB_VIA* via = static_cast<PCB_VIA*>( aItem );
141 int clearance = ( m_webWidth / 2 ) + via->GetSolderMaskExpansion();
142
143 via->TransformShapeToPolygon( *solderMask->GetFill( layer ), layer, clearance,
145
146 m_itemTree->Insert( aItem, layer, m_largestClearance );
147 }
148 }
149 }
150 else if( aItem->Type() == PCB_FIELD_T || aItem->Type() == PCB_TEXT_T )
151 {
152 for( PCB_LAYER_ID layer : { F_Mask, B_Mask } )
153 {
154 if( aItem->IsOnLayer( layer ) )
155 {
156 const PCB_TEXT* text = static_cast<const PCB_TEXT*>( aItem );
157
158 text->TransformTextToPolySet( *solderMask->GetFill( layer ),
160
161 m_itemTree->Insert( aItem, layer, m_largestClearance );
162 }
163 }
164 }
165 else
166 {
167 for( PCB_LAYER_ID layer : { F_Mask, B_Mask } )
168 {
169 if( aItem->IsOnLayer( layer ) )
170 {
171 aItem->TransformShapeToPolygon( *solderMask->GetFill( layer ), layer,
173
174 m_itemTree->Insert( aItem, layer, m_largestClearance );
175 }
176 }
177 }
178}
179
180
182{
183 ZONE* solderMask = m_board->m_SolderMaskBridges;
184 LSET layers( { F_Mask, B_Mask, F_Cu, B_Cu } );
185
186 const size_t progressDelta = 500;
187 int count = 0;
188 int ii = 0;
189
190 solderMask->GetFill( F_Mask )->RemoveAllContours();
191 solderMask->GetFill( B_Mask )->RemoveAllContours();
192
193 m_fullSolderMaskRTree = std::make_unique<DRC_RTREE>();
194 m_itemTree = std::make_unique<DRC_RTREE>();
195
197 [&]( BOARD_ITEM* item ) -> bool
198 {
199 ++count;
200 return true;
201 } );
202
204 [&]( BOARD_ITEM* item ) -> bool
205 {
206 if( !reportProgress( ii++, count, progressDelta ) )
207 return false;
208
209 addItemToRTrees( item );
210 return true;
211 } );
212
213 solderMask->GetFill( F_Mask )->Simplify();
214 solderMask->GetFill( B_Mask )->Simplify();
215
216 if( m_webWidth > 0 )
217 {
218 solderMask->GetFill( F_Mask )->Deflate( m_webWidth / 2, CORNER_STRATEGY::CHAMFER_ALL_CORNERS, m_maxError );
219 solderMask->GetFill( B_Mask )->Deflate( m_webWidth / 2, CORNER_STRATEGY::CHAMFER_ALL_CORNERS, m_maxError );
220 }
221
222 solderMask->SetFillFlag( F_Mask, true );
223 solderMask->SetFillFlag( B_Mask, true );
224 solderMask->SetIsFilled( true );
225
226 solderMask->CacheTriangulation();
227
228 m_fullSolderMaskRTree->Insert( solderMask, F_Mask );
229 m_fullSolderMaskRTree->Insert( solderMask, B_Mask );
230
231 m_checkedPairs.clear();
232}
233
234
236{
237 LSET silkLayers( { F_SilkS, B_SilkS } );
238
239 // If we have no minimum web width then we delegate to the silk checker which does object-to-object
240 // testing (instead of object-to-solder-mask-zone-fill checking that we do here).
241 if( m_webWidth <= 0 )
242 return;
243
244 const size_t progressDelta = 250;
245 int count = 0;
246 int ii = 0;
247
249 [&]( BOARD_ITEM* item ) -> bool
250 {
251 ++count;
252 return true;
253 } );
254
256 [&]( BOARD_ITEM* item ) -> bool
257 {
259 return false;
260
261 if( !reportProgress( ii++, count, progressDelta ) )
262 return false;
263
264 if( isInvisibleText( item ) )
265 return true;
266
267 for( PCB_LAYER_ID layer : silkLayers.Seq() )
268 {
269 if( !item->IsOnLayer( layer ) )
270 continue;
271
272 PCB_LAYER_ID maskLayer = layer == F_SilkS ? F_Mask : B_Mask;
273 BOX2I itemBBox = item->GetBoundingBox();
274 DRC_CONSTRAINT constraint = m_drcEngine->EvalRules( SILK_CLEARANCE_CONSTRAINT,
275 item, nullptr, maskLayer );
276 int clearance = constraint.GetValue().Min();
277 int actual;
278 VECTOR2I pos;
279
280 if( constraint.GetSeverity() == RPT_SEVERITY_IGNORE || clearance < 0 )
281 return true;
282
283 std::shared_ptr<SHAPE> itemShape = item->GetEffectiveShape( layer );
284
285 if( m_fullSolderMaskRTree->QueryColliding( itemBBox, itemShape.get(), maskLayer,
286 clearance, &actual, &pos ) )
287 {
288 std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_SILK_MASK_CLEARANCE );
289
290 if( clearance > 0 )
291 {
292 wxString msg = formatMsg( _( "(%s clearance %s; actual %s)" ),
293 constraint.GetName(),
294 clearance,
295 actual );
296
297 drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
298 }
299
300 drce->SetItems( item );
301 drce->SetViolatingRule( constraint.GetParentRule() );
302
303 reportViolation( drce, pos, layer );
304 }
305 }
306
307 return true;
308 } );
309}
310
311
313{
314 if( aItem->Type() == PCB_PAD_T )
315 {
316 PAD* pad = static_cast<PAD*>( aItem );
317
318 // TODO(JE) padstacks
319 if( pad->GetAttribute() == PAD_ATTRIB::NPTH
320 && ( pad->GetShape( PADSTACK::ALL_LAYERS ) == PAD_SHAPE::CIRCLE
321 || pad->GetShape( PADSTACK::ALL_LAYERS ) == PAD_SHAPE::OVAL )
322 && pad->GetSize( PADSTACK::ALL_LAYERS ).x <= pad->GetDrillSize().x
323 && pad->GetSize( PADSTACK::ALL_LAYERS ).y <= pad->GetDrillSize().y )
324 {
325 return true;
326 }
327 }
328
329 return false;
330}
331
332
333// Simple mask apertures aren't associated with copper items, so they only constitute a bridge
334// when they expose other copper items having at least two distinct nets. We use a map to record
335// the first net exposed by each mask aperture (on each copper layer).
336//
337// Note that this algorithm is also used for free pads.
338
340{
341 if( aItem->Type() == PCB_PAD_T && static_cast<PAD*>( aItem )->IsFreePad() )
342 return true;
343
344 static const LSET saved( { F_Mask, B_Mask } );
345
346 LSET maskLayers = aItem->GetLayerSet() & saved;
347 LSET copperLayers = ( aItem->GetLayerSet() & ~saved ) & LSET::AllCuMask();
348
349 return maskLayers.count() > 0 && copperLayers.count() == 0;
350}
351
352
354 PCB_LAYER_ID aTestLayer, int aTestNet,
355 BOARD_ITEM** aCollidingItem )
356{
357 if( aTestLayer == F_Mask && !aTestItem->IsOnLayer( PADSTACK::ALL_LAYERS ) )
358 return false;
359
360 if( aTestLayer == B_Mask && !aTestItem->IsOnLayer( B_Cu ) )
361 return false;
362
363 PCB_LAYER_ID maskLayer = IsFrontLayer( aTestLayer ) ? F_Mask : B_Mask;
364
365 FOOTPRINT* fp = aMaskItem->GetParentFootprint();
366
367 // Mask apertures in footprints which allow soldermask bridges are ignored entirely.
368 if( fp && fp->AllowSolderMaskBridges() )
369 return false;
370
371 PTR_LAYER_CACHE_KEY key = { aMaskItem, maskLayer };
372
373 auto ii = m_maskApertureNetMap.find( key );
374
375 if( ii == m_maskApertureNetMap.end() )
376 {
377 m_maskApertureNetMap[ key ] = { aTestItem, aTestNet };
378
379 // First net; no bridge yet....
380 return false;
381 }
382
383 auto& [cacheKey, cacheEntry] = *ii;
384 auto& [alreadyEncounteredItem, encounteredItemNet] = cacheEntry;
385
386 if( encounteredItemNet == aTestNet && aTestNet >= 0 )
387 {
388 // Same net; still no bridge...
389 return false;
390 }
391
392 if( fp && aTestItem->GetParentFootprint() == fp )
393 {
394 std::map<wxString, int> padToNetTieGroupMap = fp->MapPadNumbersToNetTieGroups();
395 PAD* padA = nullptr;
396 PAD* padB = nullptr;
397
398 if( alreadyEncounteredItem->Type() == PCB_PAD_T )
399 padA = static_cast<PAD*>( alreadyEncounteredItem );
400
401 if( aTestItem->Type() == PCB_PAD_T )
402 padB = static_cast<PAD*>( aTestItem );
403
404 if( padA && padB && ( padA->SameLogicalPadAs( padB ) || padA->SharesNetTieGroup( padB ) ) )
405 {
406 return false;
407 }
408 else if( padA && aTestItem->Type() == PCB_SHAPE_T )
409 {
410 if( padToNetTieGroupMap.contains( padA->GetNumber() ) )
411 return false;
412 }
413 else if( padB && alreadyEncounteredItem->Type() == PCB_SHAPE_T )
414 {
415 if( padToNetTieGroupMap.contains( padB->GetNumber() ) )
416 return false;
417 }
418 }
419
420 *aCollidingItem = alreadyEncounteredItem;
421 return true;
422}
423
424
426{
427 if( FOOTPRINT* fp = aMaskItem->GetParentFootprint() )
428 {
429 // If we're allowing bridges then we're allowing bridges. Nothing to check.
430 if( fp->AllowSolderMaskBridges() )
431 return false;
432
433 // Graphic items are used to implement net-ties between pads of a group within a net-tie
434 // footprint. They must be allowed to intrude into their pad's mask aperture.
435 if( aTestNet < 0 && aMaskItem->Type() == PCB_PAD_T && fp->IsNetTie() )
436 {
437 std::map<wxString, int> padNumberToGroupIdxMap = fp->MapPadNumbersToNetTieGroups();
438
439 if( padNumberToGroupIdxMap[ static_cast<PAD*>( aMaskItem )->GetNumber() ] >= 0 )
440 return false;
441 }
442 }
443
444 return true;
445}
446
447
449 PCB_LAYER_ID aRefLayer,
450 PCB_LAYER_ID aTargetLayer )
451{
452 int itemNet = -1;
453
454 if( aItem->IsConnected() )
455 itemNet = static_cast<BOARD_CONNECTED_ITEM*>( aItem )->GetNetCode();
456
458 PAD* pad = aItem->Type() == PCB_PAD_T ? static_cast<PAD*>( aItem )
459 : nullptr;
460 PCB_VIA* via = aItem->Type() == PCB_VIA_T ? static_cast<PCB_VIA*>( aItem )
461 : nullptr;
462 std::shared_ptr<SHAPE> itemShape = aItem->GetEffectiveShape( aRefLayer );
463
464 m_itemTree->QueryColliding( aItem, aRefLayer, aTargetLayer,
465 // Filter:
466 [&]( BOARD_ITEM* other ) -> bool
467 {
468 FOOTPRINT* itemFP = aItem->GetParentFootprint();
469 PAD* otherPad = other->Type() == PCB_PAD_T ? static_cast<PAD*>( other )
470 : nullptr;
471 int otherNet = -1;
472
473 if( other->IsConnected() )
474 otherNet = static_cast<BOARD_CONNECTED_ITEM*>( other )->GetNetCode();
475
476 if( otherNet > 0 && otherNet == itemNet )
477 return false;
478
479 if( isNullAperture( other ) )
480 return false;
481
482 if( itemFP && itemFP == other->GetParentFootprint() )
483 {
484 // Board-wide exclusion
486 return false;
487
488 // Footprint-specific exclusion
489 if( itemFP->AllowSolderMaskBridges() )
490 return false;
491 }
492
493 if( pad && otherPad && ( pad->SameLogicalPadAs( otherPad )
494 || pad->SharesNetTieGroup( otherPad ) ) )
495 {
496 return false;
497 }
498
499 BOARD_ITEM* a = aItem;
500 BOARD_ITEM* b = other;
501
502 // store canonical order so we don't collide in both directions (a:b and b:a)
503 if( static_cast<void*>( a ) > static_cast<void*>( b ) )
504 std::swap( a, b );
505
506 auto it = m_checkedPairs.find( { a, b } );
507
508 if( it != m_checkedPairs.end() && it->second.test( aTargetLayer ) )
509 {
510 return false;
511 }
512 else
513 {
514 m_checkedPairs[ { a, b } ].set( aTargetLayer );
515 return true;
516 }
517 },
518 // Visitor:
519 [&]( BOARD_ITEM* other ) -> bool
520 {
521 PAD* otherPad = other->Type() == PCB_PAD_T ? static_cast<PAD*>( other )
522 : nullptr;
523 PCB_VIA* otherVia = other->Type() == PCB_VIA_T ? static_cast<PCB_VIA*>( other )
524 : nullptr;
525 auto otherShape = other->GetEffectiveShape( aTargetLayer );
526 int otherNet = -1;
527
528 if( other->IsConnected() )
529 otherNet = static_cast<BOARD_CONNECTED_ITEM*>( other )->GetNetCode();
530
531 int actual;
532 VECTOR2I pos;
533 int clearance = 0;
534
535 if( aRefLayer == F_Mask || aRefLayer == B_Mask )
536 {
537 // Aperture-to-aperture must enforce web-min-width
539 }
540 else // ( aRefLayer == F_Cu || aRefLayer == B_Cu )
541 {
542 // Copper-to-aperture uses the solder-mask-to-copper-clearance
544 }
545
546 if( pad )
547 clearance += pad->GetSolderMaskExpansion( PADSTACK::ALL_LAYERS );
548 else if( via && !via->IsTented( aRefLayer ) )
549 clearance += via->GetSolderMaskExpansion();
550
551 if( otherPad )
553 else if( otherVia && !otherVia->IsTented( aRefLayer ) )
554 clearance += otherVia->GetSolderMaskExpansion();
555
556 if( itemShape->Collide( otherShape.get(), clearance, &actual, &pos ) )
557 {
558 wxString msg;
559 BOARD_ITEM* colliding = nullptr;
560
561 if( aTargetLayer == F_Mask )
562 msg = _( "Front solder mask aperture bridges items with different nets" );
563 else
564 msg = _( "Rear solder mask aperture bridges items with different nets" );
565
566 // Simple mask apertures aren't associated with copper items, so they only
567 // constitute a bridge when they expose other copper items having at least
568 // two distinct nets.
569 if( isMaskAperture( aItem ) )
570 {
571 if( checkMaskAperture( aItem, other, aRefLayer, otherNet, &colliding ) )
572 {
574
575 drce->SetErrorMessage( msg );
576 drce->SetItems( aItem, colliding, other );
577 drce->SetViolatingRule( &m_bridgeRule );
578 reportViolation( drce, pos, aTargetLayer );
579 }
580 }
581 else if( isMaskAperture( other ) )
582 {
583 if( checkMaskAperture( other, aItem, aRefLayer, itemNet, &colliding ) )
584 {
586
587 drce->SetErrorMessage( msg );
588 drce->SetItems( other, colliding, aItem );
589 drce->SetViolatingRule( &m_bridgeRule );
590 reportViolation( drce, pos, aTargetLayer );
591 }
592 }
593 else if( checkItemMask( other, itemNet ) )
594 {
596
597 drce->SetErrorMessage( msg );
598 drce->SetItems( aItem, other );
599 drce->SetViolatingRule( &m_bridgeRule );
600 reportViolation( drce, pos, aTargetLayer );
601 }
602 }
603
604 return !m_drcEngine->IsCancelled();
605 },
607}
608
609
611 const BOX2I& aItemBBox,
612 PCB_LAYER_ID aMaskLayer,
613 PCB_LAYER_ID aTargetLayer )
614{
615 for( ZONE* zone : m_board->m_DRCCopperZones )
616 {
617 if( !zone->GetLayerSet().test( aTargetLayer ) )
618 continue;
619
620 int zoneNet = zone->GetNetCode();
621
622 if( aItem->IsConnected() )
623 {
624 BOARD_CONNECTED_ITEM* connectedItem = static_cast<BOARD_CONNECTED_ITEM*>( aItem );
625
626 if( zoneNet == connectedItem->GetNetCode() && zoneNet > 0 )
627 continue;
628 }
629
630 BOX2I inflatedBBox( aItemBBox );
632
633 if( aItem->Type() == PCB_PAD_T )
634 clearance += static_cast<PAD*>( aItem )->GetSolderMaskExpansion( PADSTACK::ALL_LAYERS );
635 else if( aItem->Type() == PCB_VIA_T )
636 clearance += static_cast<PCB_VIA*>( aItem )->GetSolderMaskExpansion();
637
638 inflatedBBox.Inflate( clearance );
639
640 if( !inflatedBBox.Intersects( zone->GetBoundingBox() ) )
641 continue;
642
643 DRC_RTREE* zoneTree = m_board->m_CopperZoneRTreeCache[ zone ].get();
644 int actual;
645 VECTOR2I pos;
646
647 std::shared_ptr<SHAPE> itemShape = aItem->GetEffectiveShape( aMaskLayer );
648
649 if( zoneTree && zoneTree->QueryColliding( aItemBBox, itemShape.get(), aTargetLayer,
650 clearance, &actual, &pos ) )
651 {
652 wxString msg;
653 BOARD_ITEM* colliding = nullptr;
654
655 if( aMaskLayer == F_Mask )
656 msg = _( "Front solder mask aperture bridges items with different nets" );
657 else
658 msg = _( "Rear solder mask aperture bridges items with different nets" );
659
660 // Simple mask apertures aren't associated with copper items, so they only constitute
661 // a bridge when they expose other copper items having at least two distinct nets.
662 if( isMaskAperture( aItem ) && zoneNet >= 0 )
663 {
664 if( checkMaskAperture( aItem, zone, aTargetLayer, zoneNet, &colliding ) )
665 {
667
668 drce->SetErrorMessage( msg );
669 drce->SetItems( aItem, colliding, zone );
670 drce->SetViolatingRule( &m_bridgeRule );
671 reportViolation( drce, pos, aTargetLayer );
672 }
673 }
674 else
675 {
677
678 drce->SetErrorMessage( msg );
679 drce->SetItems( aItem, zone );
680 drce->SetViolatingRule( &m_bridgeRule );
681 reportViolation( drce, pos, aTargetLayer );
682 }
683 }
684
685 if( m_drcEngine->IsCancelled() )
686 return;
687 }
688}
689
690
692{
693 LSET copperAndMaskLayers( { F_Mask, B_Mask, F_Cu, B_Cu } );
694
695 const size_t progressDelta = 250;
696 int count = 0;
697 int ii = 0;
698
699 forEachGeometryItem( s_allBasicItemsButZones, copperAndMaskLayers,
700 [&]( BOARD_ITEM* item ) -> bool
701 {
702 ++count;
703 return true;
704 } );
705
706 forEachGeometryItem( s_allBasicItemsButZones, copperAndMaskLayers,
707 [&]( BOARD_ITEM* item ) -> bool
708 {
710 return false;
711
712 if( !reportProgress( ii++, count, progressDelta ) )
713 return false;
714
715 BOX2I itemBBox = item->GetBoundingBox();
716
717 if( item->IsOnLayer( F_Mask ) && !isNullAperture( item ) )
718 {
719 // Test for aperture-to-aperture collisions
720 testItemAgainstItems( item, itemBBox, F_Mask, F_Mask );
721
722 // Test for aperture-to-zone collisions
723 testMaskItemAgainstZones( item, itemBBox, F_Mask, F_Cu );
724 }
725 else if( item->IsOnLayer( PADSTACK::ALL_LAYERS ) )
726 {
727 // Test for copper-item-to-aperture collisions
728 testItemAgainstItems( item, itemBBox, F_Cu, F_Mask );
729 }
730
731 if( item->IsOnLayer( B_Mask ) && !isNullAperture( item ) )
732 {
733 // Test for aperture-to-aperture collisions
734 testItemAgainstItems( item, itemBBox, B_Mask, B_Mask );
735
736 // Test for aperture-to-zone collisions
737 testMaskItemAgainstZones( item, itemBBox, B_Mask, B_Cu );
738 }
739 else if( item->IsOnLayer( B_Cu ) )
740 {
741 // Test for copper-item-to-aperture collisions
742 testItemAgainstItems( item, itemBBox, B_Cu, B_Mask );
743 }
744
745 return true;
746 } );
747}
748
749
751{
754 {
755 REPORT_AUX( wxT( "Solder mask violations ignored. Tests not run." ) );
756 return true; // continue with other tests
757 }
758
763
764 for( FOOTPRINT* footprint : m_board->Footprints() )
765 {
766 for( PAD* pad : footprint->Pads() )
767 m_largestClearance = std::max( m_largestClearance, pad->GetSolderMaskExpansion( PADSTACK::ALL_LAYERS ) );
768 }
769
770 // Order is important here: m_webWidth must be added in before m_largestCourtyardClearance is
771 // maxed with the various SILK_CLEARANCE_CONSTRAINTS.
773
774 DRC_CONSTRAINT worstClearanceConstraint;
775
776 if( m_drcEngine->QueryWorstConstraint( SILK_CLEARANCE_CONSTRAINT, worstClearanceConstraint ) )
777 m_largestClearance = std::max( m_largestClearance, worstClearanceConstraint.m_Value.Min() );
778
779 if( !reportPhase( _( "Building solder mask..." ) ) )
780 return false; // DRC cancelled
781
782 m_checkedPairs.clear();
783 m_maskApertureNetMap.clear();
784
785 buildRTrees();
786
787 if( !reportPhase( _( "Checking solder mask to silk clearance..." ) ) )
788 return false; // DRC cancelled
789
791
792 if( !reportPhase( _( "Checking solder mask web integrity..." ) ) )
793 return false; // DRC cancelled
794
796
797 return !m_drcEngine->IsCancelled();
798}
799
800
801namespace detail
802{
804}
@ ERROR_OUTSIDE
Definition: approximation.h:33
A base class derived from BOARD_ITEM for items that can be connected and have a net,...
Container for design settings for a BOARD object.
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition: board_item.h:79
virtual bool IsConnected() const
Returns information if the object is derived from BOARD_CONNECTED_ITEM.
Definition: board_item.h:134
virtual void TransformShapeToPolygon(SHAPE_POLY_SET &aBuffer, PCB_LAYER_ID aLayer, int aClearance, int aError, ERROR_LOC aErrorLoc, bool ignoreLineWidth=false) const
Convert the item shape to a closed polygon.
Definition: board_item.cpp:291
virtual bool IsOnLayer(PCB_LAYER_ID aLayer) const
Test to see if this object is on the given layer.
Definition: board_item.h:317
virtual std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
Definition: board_item.cpp:314
virtual const BOARD * GetBoard() const
Return the BOARD in which this BOARD_ITEM resides, or NULL if none.
Definition: board_item.cpp:79
FOOTPRINT * GetParentFootprint() const
Definition: board_item.cpp:97
virtual LSET GetLayerSet() const
Return a std::bitset of all layers on which the item physically resides.
Definition: board_item.h:252
Information pertinent to a Pcbnew printed circuit board.
Definition: board.h:314
ZONE * m_SolderMaskBridges
Definition: board.h:1351
std::vector< ZONE * > m_DRCCopperZones
Definition: board.h:1348
const FOOTPRINTS & Footprints() const
Definition: board.h:355
std::unordered_map< ZONE *, std::unique_ptr< DRC_RTREE > > m_CopperZoneRTreeCache
Definition: board.h:1341
BOARD_DESIGN_SETTINGS & GetDesignSettings() const
Definition: board.cpp:943
constexpr BOX2< Vec > & Inflate(coord_type dx, coord_type dy)
Inflates the rectangle horizontally by dx and vertically by dy.
Definition: box2.h:558
constexpr bool Intersects(const BOX2< Vec > &aRect) const
Definition: box2.h:311
MINOPTMAX< int > m_Value
Definition: drc_rule.h:202
BOARD * GetBoard() const
Definition: drc_engine.h:95
bool IsErrorLimitExceeded(int error_code)
bool IsCancelled() const
bool QueryWorstConstraint(DRC_CONSTRAINT_T aRuleId, DRC_CONSTRAINT &aConstraint)
static std::shared_ptr< DRC_ITEM > Create(int aErrorCode)
Constructs a DRC_ITEM for the given error code.
Definition: drc_item.cpp:393
Implement an R-tree for fast spatial and layer indexing of connectable items.
Definition: drc_rtree.h:48
int QueryColliding(BOARD_ITEM *aRefItem, PCB_LAYER_ID aRefLayer, PCB_LAYER_ID aTargetLayer, std::function< bool(BOARD_ITEM *)> aFilter=nullptr, std::function< bool(BOARD_ITEM *)> aVisitor=nullptr, int aClearance=0) const
This is a fast test which essentially does bounding-box overlap given a worst-case clearance.
Definition: drc_rtree.h:214
wxString m_Name
Definition: drc_rule.h:120
virtual const wxString GetName() const override
void testMaskItemAgainstZones(BOARD_ITEM *item, const BOX2I &itemBBox, PCB_LAYER_ID refLayer, PCB_LAYER_ID targetLayer)
virtual ~DRC_TEST_PROVIDER_SOLDER_MASK()=default
bool checkMaskAperture(BOARD_ITEM *aMaskItem, BOARD_ITEM *aTestItem, PCB_LAYER_ID aTestLayer, int aTestNet, BOARD_ITEM **aCollidingItem)
std::unique_ptr< DRC_RTREE > m_fullSolderMaskRTree
virtual bool Run() override
Run this provider against the given PCB with configured options (if any).
std::unordered_map< PTR_PTR_CACHE_KEY, LSET > m_checkedPairs
bool checkItemMask(BOARD_ITEM *aMaskItem, int aTestNet)
std::unordered_map< PTR_LAYER_CACHE_KEY, std::pair< BOARD_ITEM *, int > > m_maskApertureNetMap
void testItemAgainstItems(BOARD_ITEM *aItem, const BOX2I &aItemBBox, PCB_LAYER_ID aRefLayer, PCB_LAYER_ID aTargetLayer)
Represent a DRC "provider" which runs some DRC functions over a BOARD and spits out DRC_ITEM and posi...
static std::vector< KICAD_T > s_allBasicItemsButZones
virtual bool reportPhase(const wxString &aStageName)
virtual void reportViolation(std::shared_ptr< DRC_ITEM > &item, const VECTOR2I &aMarkerPos, int aMarkerLayer, DRC_CUSTOM_MARKER_HANDLER *aCustomHandler=nullptr)
int forEachGeometryItem(const std::vector< KICAD_T > &aTypes, const LSET &aLayers, const std::function< bool(BOARD_ITEM *)> &aFunc)
static std::vector< KICAD_T > s_allBasicItems
DRC_ENGINE * m_drcEngine
bool isInvisibleText(const BOARD_ITEM *aItem) const
virtual bool reportProgress(size_t aCount, size_t aSize, size_t aDelta=1)
virtual const BOX2I GetBoundingBox() const
Return the orthogonal bounding box of this object for display purposes.
Definition: eda_item.cpp:110
KICAD_T Type() const
Returns the type of object.
Definition: eda_item.h:109
bool AllowSolderMaskBridges() const
Definition: footprint.h:299
std::map< wxString, int > MapPadNumbersToNetTieGroups() const
Definition: footprint.cpp:3182
LSET is a set of PCB_LAYER_IDs.
Definition: lset.h:37
static LSET AllCuMask(int aCuLayerCount=MAX_CU_LAYERS)
Return a mask holding the requested number of Cu PCB_LAYER_IDs.
Definition: lset.cpp:583
T Min() const
Definition: minoptmax.h:33
static constexpr PCB_LAYER_ID ALL_LAYERS
! Temporary layer identifier to identify code that is not padstack-aware
Definition: padstack.h:144
Definition: pad.h:54
const wxString & GetNumber() const
Definition: pad.h:136
bool SameLogicalPadAs(const PAD *aOther) const
Before we had custom pad shapes it was common to have multiple overlapping pads to represent a more c...
Definition: pad.h:159
int GetSolderMaskExpansion(PCB_LAYER_ID aLayer) const
Definition: pad.cpp:1160
bool IsFreePad() const
Definition: pad.cpp:278
bool SharesNetTieGroup(const PAD *aOther) const
Definition: pad.cpp:255
int GetSolderMaskExpansion() const
Definition: pcb_track.cpp:1124
void RemoveAllContours()
Remove all outlines & holes (clears) the polygon set.
void BooleanAdd(const SHAPE_POLY_SET &b)
Perform boolean polyset union.
void Simplify()
Simplify the polyset (merges overlapping polys, eliminates degeneracy/self-intersections)
void Deflate(int aAmount, CORNER_STRATEGY aCornerStrategy, int aMaxError)
Handle a list of polygons defining a copper zone.
Definition: zone.h:74
const std::shared_ptr< SHAPE_POLY_SET > & GetFilledPolysList(PCB_LAYER_ID aLayer) const
Definition: zone.h:595
void CacheTriangulation(PCB_LAYER_ID aLayer=UNDEFINED_LAYER)
Create a list of triangles that "fill" the solid areas used for instance to draw these solid areas on...
Definition: zone.cpp:1256
const BOX2I GetBoundingBox() const override
Definition: zone.cpp:622
void SetFillFlag(PCB_LAYER_ID aLayer, bool aFlag)
Definition: zone.h:290
SHAPE_POLY_SET * GetFill(PCB_LAYER_ID aLayer)
Definition: zone.h:601
void SetIsFilled(bool isFilled)
Definition: zone.h:293
virtual bool IsOnLayer(PCB_LAYER_ID) const override
Test to see if this object is on the given layer.
Definition: zone.cpp:616
virtual LSET GetLayerSet() const override
Return a std::bitset of all layers on which the item physically resides.
Definition: zone.h:136
The common library.
@ DRCE_SILK_MASK_CLEARANCE
Definition: drc_item.h:96
@ DRCE_SOLDERMASK_BRIDGE
Definition: drc_item.h:93
@ SILK_CLEARANCE_CONSTRAINT
Definition: drc_rule.h:56
#define REPORT_AUX(s)
bool isMaskAperture(BOARD_ITEM *aItem)
bool isNullAperture(BOARD_ITEM *aItem)
#define _(s)
bool IsFrontLayer(PCB_LAYER_ID aLayerId)
Layer classification: check if it's a front layer.
Definition: layer_ids.h:765
PCB_LAYER_ID
A quick note on layer IDs:
Definition: layer_ids.h:60
@ B_Mask
Definition: layer_ids.h:98
@ B_Cu
Definition: layer_ids.h:65
@ F_Mask
Definition: layer_ids.h:97
@ F_SilkS
Definition: layer_ids.h:100
@ B_SilkS
Definition: layer_ids.h:101
@ F_Cu
Definition: layer_ids.h:64
static DRC_REGISTER_TEST_PROVIDER< DRC_TEST_PROVIDER_ANNULAR_WIDTH > dummy
@ NPTH
like PAD_PTH, but not plated mechanical use only, no connection allowed
int clearance
int actual
@ PCB_SHAPE_T
class PCB_SHAPE, a segment not on copper layers
Definition: typeinfo.h:88
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
Definition: typeinfo.h:97
@ PCB_ZONE_T
class ZONE, a copper pour area
Definition: typeinfo.h:107
@ PCB_TEXT_T
class PCB_TEXT, text on a layer
Definition: typeinfo.h:92
@ PCB_FIELD_T
class PCB_FIELD, text associated with a footprint property
Definition: typeinfo.h:90
@ PCB_PAD_T
class PAD, a pad in a footprint
Definition: typeinfo.h:87