57 m_bridgeRule.m_Name =
_(
"board setup solder mask min width" );
62 virtual bool Run()
override;
64 virtual const wxString
GetName()
const override {
return wxT(
"solder_mask_issues" ); };
115 ZONE* zone =
static_cast<ZONE*
>( aItem );
124 clearance +=
static_cast<PAD*
>( aItem )->GetSolderMaskExpansion( layer );
152 const size_t progressDelta = 500;
210 const size_t progressDelta = 250;
241 item,
nullptr, maskLayer );
258 wxString msg =
formatMsg(
_(
"(%s clearance %s; actual %s)" ),
263 drce->SetErrorMessage( drce->GetErrorText() + wxS(
" " ) + msg );
266 drce->SetItems( item );
315 return maskLayers.count() > 0 && copperLayers.count() == 0;
349 auto& [cacheKey, cacheEntry] = *ii;
350 auto& [alreadyEncounteredItem, encounteredItemNet] = cacheEntry;
352 if( encounteredItemNet == aTestNet && aTestNet >= 0 )
364 if( alreadyEncounteredItem->Type() ==
PCB_PAD_T )
365 padA =
static_cast<PAD*
>( alreadyEncounteredItem );
368 padB =
static_cast<PAD*
>( aTestItem );
376 if( padToNetTieGroupMap.contains( padA->
GetNumber() ) )
381 if( padToNetTieGroupMap.contains( padB->
GetNumber() ) )
386 *aCollidingItem = alreadyEncounteredItem;
396 if( fp->AllowSolderMaskBridges() )
403 std::map<wxString, int> padNumberToGroupIdxMap = fp->MapPadNumbersToNetTieGroups();
404 int groupIdx = padNumberToGroupIdxMap[
pad->GetNumber() ];
411 if(
pad->GetNetCode() == aTestNet )
414 for(
PAD* other : fp->GetNetTiePads(
pad ) )
416 if( other->GetNetCode() == aTestNet )
436 std::optional<bool> itemConstraintIgnored;
443 m_itemTree->QueryColliding( aItem, aRefLayer, aTargetLayer,
454 if( otherNet > 0 && otherNet == itemNet )
465 if( board->GetDesignSettings().m_AllowSoldermaskBridgesInFPs )
474 if(
pad && otherPad && (
pad->SameLogicalPadAs( otherPad )
475 ||
pad->SharesNetTieGroup( otherPad ) ) )
484 if( otherNet < 0 || nets.count( otherNet ) )
490 const std::set<int>& nets = otherFP->GetNetTieCache( other );
492 if( itemNet < 0 || nets.count( itemNet ) )
500 if(
static_cast<void*
>( a ) >
static_cast<void*
>( b ) )
507 if( it !=
m_checkedPairs.end() && it->second.test( aTargetLayer ) )
547 else if(
via && !
via->IsTented( aRefLayer ) )
554 else if( otherVia && !otherVia->
IsTented( aTargetLayer ) )
556 else if( otherShape )
559 if( itemShape->Collide( otherItemShape.get(),
clearance, &
actual, &pos ) )
561 if( !itemConstraintIgnored.has_value() )
573 || ( itemConstraintIgnored && otherConstraintIgnored ) )
581 if( aTargetLayer ==
F_Mask )
582 msg =
_(
"Front solder mask aperture bridges items with different nets" );
584 msg =
_(
"Rear solder mask aperture bridges items with different nets" );
595 drce->SetErrorMessage( msg );
596 drce->SetItems( aItem, colliding, other );
607 drce->SetErrorMessage( msg );
608 drce->SetItems( other, colliding, aItem );
617 drce->SetErrorMessage( msg );
618 drce->SetItems( aItem, other );
648 if( zoneNet == connectedItem->
GetNetCode() && zoneNet > 0 )
652 BOX2I inflatedBBox( aItemBBox );
656 clearance +=
pad->GetSolderMaskExpansion( aTargetLayer );
657 else if(
via && !
via->IsTented( aTargetLayer ) )
679 if( aMaskLayer ==
F_Mask )
680 msg =
_(
"Front solder mask aperture bridges items with different nets" );
682 msg =
_(
"Rear solder mask aperture bridges items with different nets" );
692 drce->SetErrorMessage( msg );
693 drce->SetItems( aItem, colliding, zone );
702 drce->SetErrorMessage( msg );
703 drce->SetItems( aItem, zone );
718 std::atomic<int> count = 0;
719 std::vector<BOARD_ITEM*> test_items;
724 test_items.push_back( item );
730 auto returns =
tp.submit_loop( 0, test_items.size(),
731 [&](
size_t i ) ->
bool
733 BOARD_ITEM* item = test_items[ i ];
735 if( m_drcEngine->IsErrorLimitExceeded( DRCE_SOLDERMASK_BRIDGE ) )
738 BOX2I itemBBox = item->GetBoundingBox();
740 if( item->IsOnLayer( F_Mask ) && !isNullAperture( item ) )
743 testItemAgainstItems( item, itemBBox, F_Mask, F_Mask );
746 testMaskItemAgainstZones( item, itemBBox, F_Mask, F_Cu );
751 testItemAgainstItems( item, itemBBox, F_Cu, F_Mask );
765 testItemAgainstItems( item, itemBBox, B_Cu, B_Mask );
773 for(
auto& ret : returns )
778 while( ret.wait_for( std::chrono::milliseconds( 100 ) ) == std::future_status::timeout )
779 reportProgress( count, test_items.size() );
789 REPORT_AUX( wxT(
"Solder mask violations ignored. Tests not run." ) );
798 auto updateLargestClearance =
799 [&](
int aClearance )
806 for(
PAD*
pad : footprint->Pads() )
809 for(
BOARD_ITEM* item : footprint->GraphicalItems() )
812 updateLargestClearance(
static_cast<PCB_SHAPE*
>( item )->GetSolderMaskExpansion() );
817 updateLargestClearance( track->GetSolderMaskExpansion() );
822 updateLargestClearance(
static_cast<PCB_SHAPE*
>( item )->GetSolderMaskExpansion() );
842 if( !
reportPhase(
_(
"Checking solder mask to silk clearance..." ) ) )
847 if( !
reportPhase(
_(
"Checking solder mask web integrity..." ) ) )
A base class derived from BOARD_ITEM for items that can be connected and have a net,...
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
virtual bool IsConnected() const
Returns information if the object is derived from BOARD_CONNECTED_ITEM.
virtual void TransformShapeToPolygon(SHAPE_POLY_SET &aBuffer, PCB_LAYER_ID aLayer, int aClearance, int aError, ERROR_LOC aErrorLoc, bool ignoreLineWidth=false) const
Convert the item shape to a closed polygon.
virtual bool IsOnLayer(PCB_LAYER_ID aLayer) const
Test to see if this object is on the given layer.
virtual std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
virtual const BOARD * GetBoard() const
Return the BOARD in which this BOARD_ITEM resides, or NULL if none.
FOOTPRINT * GetParentFootprint() const
virtual LSET GetLayerSet() const
Return a std::bitset of all layers on which the item physically resides.
Information pertinent to a Pcbnew printed circuit board.
constexpr BOX2< Vec > & Inflate(coord_type dx, coord_type dy)
Inflates the rectangle horizontally by dx and vertically by dy.
constexpr bool Intersects(const BOX2< Vec > &aRect) const
SEVERITY GetSeverity() const
const MINOPTMAX< int > & GetValue() const
DRC_RULE * GetParentRule() const
static std::shared_ptr< DRC_ITEM > Create(int aErrorCode)
Constructs a DRC_ITEM for the given error code.
Implement an R-tree for fast spatial and layer indexing of connectable items.
int QueryColliding(BOARD_ITEM *aRefItem, PCB_LAYER_ID aRefLayer, PCB_LAYER_ID aTargetLayer, std::function< bool(BOARD_ITEM *)> aFilter=nullptr, std::function< bool(BOARD_ITEM *)> aVisitor=nullptr, int aClearance=0) const
This is a fast test which essentially does bounding-box overlap given a worst-case clearance.
virtual const wxString GetName() const override
void testMaskItemAgainstZones(BOARD_ITEM *item, const BOX2I &itemBBox, PCB_LAYER_ID refLayer, PCB_LAYER_ID targetLayer)
virtual ~DRC_TEST_PROVIDER_SOLDER_MASK()=default
bool checkMaskAperture(BOARD_ITEM *aMaskItem, BOARD_ITEM *aTestItem, PCB_LAYER_ID aTestLayer, int aTestNet, BOARD_ITEM **aCollidingItem)
std::unique_ptr< DRC_RTREE > m_itemTree
void addItemToRTrees(BOARD_ITEM *aItem)
std::unique_ptr< DRC_RTREE > m_fullSolderMaskRTree
void testSilkToMaskClearance()
virtual bool Run() override
Run this provider against the given PCB with configured options (if any).
std::unordered_map< PTR_PTR_CACHE_KEY, LSET > m_checkedPairs
bool checkItemMask(BOARD_ITEM *aItem, int aTestNet)
std::mutex m_checkedPairsMutex
DRC_TEST_PROVIDER_SOLDER_MASK()
std::unordered_map< PTR_LAYER_CACHE_KEY, std::pair< BOARD_ITEM *, int > > m_maskApertureNetMap
void testItemAgainstItems(BOARD_ITEM *aItem, const BOX2I &aItemBBox, PCB_LAYER_ID aRefLayer, PCB_LAYER_ID aTargetLayer)
static std::vector< KICAD_T > s_allBasicItemsButZones
virtual bool reportPhase(const wxString &aStageName)
int forEachGeometryItem(const std::vector< KICAD_T > &aTypes, const LSET &aLayers, const std::function< bool(BOARD_ITEM *)> &aFunc)
static std::vector< KICAD_T > s_allBasicItems
virtual void reportViolation(std::shared_ptr< DRC_ITEM > &item, const VECTOR2I &aMarkerPos, int aMarkerLayer, const std::vector< PCB_SHAPE > &aShapes={})
bool isInvisibleText(const BOARD_ITEM *aItem) const
wxString formatMsg(const wxString &aFormatString, const wxString &aSource, double aConstraint, double aActual, EDA_DATA_TYPE aDataType=EDA_DATA_TYPE::DISTANCE)
virtual bool reportProgress(size_t aCount, size_t aSize, size_t aDelta=1)
virtual const BOX2I GetBoundingBox() const
Return the orthogonal bounding box of this object for display purposes.
KICAD_T Type() const
Returns the type of object.
LSET is a set of PCB_LAYER_IDs.
static LSET AllCuMask()
return AllCuMask( MAX_CU_LAYERS );
static constexpr PCB_LAYER_ID ALL_LAYERS
! Temporary layer identifier to identify code that is not padstack-aware
const wxString & GetNumber() const
bool SameLogicalPadAs(const PAD *aOther) const
Before we had custom pad shapes it was common to have multiple overlapping pads to represent a more c...
int GetSolderMaskExpansion(PCB_LAYER_ID aLayer) const
bool SharesNetTieGroup(const PAD *aOther) const
int GetSolderMaskExpansion() const
bool IsTented(PCB_LAYER_ID aLayer) const override
Checks if the given object is tented (its copper shape is covered by solder mask) on a given side of ...
int GetSolderMaskExpansion() const
Represent a set of closed polygons.
void RemoveAllContours()
Remove all outlines & holes (clears) the polygon set.
void BooleanAdd(const SHAPE_POLY_SET &b)
Perform boolean polyset union.
void Simplify()
Simplify the polyset (merges overlapping polys, eliminates degeneracy/self-intersections)
void Deflate(int aAmount, CORNER_STRATEGY aCornerStrategy, int aMaxError)
Handle a list of polygons defining a copper zone.
const std::shared_ptr< SHAPE_POLY_SET > & GetFilledPolysList(PCB_LAYER_ID aLayer) const
void CacheTriangulation(PCB_LAYER_ID aLayer=UNDEFINED_LAYER)
Create a list of triangles that "fill" the solid areas used for instance to draw these solid areas on...
const BOX2I GetBoundingBox() const override
void SetFillFlag(PCB_LAYER_ID aLayer, bool aFlag)
SHAPE_POLY_SET * GetFill(PCB_LAYER_ID aLayer)
void SetIsFilled(bool isFilled)
virtual LSET GetLayerSet() const override
Return a std::bitset of all layers on which the item physically resides.
@ CHAMFER_ALL_CORNERS
All angles are chamfered.
@ DRCE_SILK_MASK_CLEARANCE
@ BRIDGED_MASK_CONSTRAINT
@ SILK_CLEARANCE_CONSTRAINT
bool isMaskAperture(BOARD_ITEM *aItem)
bool isNullAperture(BOARD_ITEM *aItem)
bool IsFrontLayer(PCB_LAYER_ID aLayerId)
Layer classification: check if it's a front layer.
PCB_LAYER_ID
A quick note on layer IDs:
static DRC_REGISTER_TEST_PROVIDER< DRC_TEST_PROVIDER_ANNULAR_WIDTH > dummy
@ NPTH
like PAD_PTH, but not plated mechanical use only, no connection allowed
thread_pool & GetKiCadThreadPool()
Get a reference to the current thread pool.
BS::thread_pool< 0 > thread_pool
@ PCB_SHAPE_T
class PCB_SHAPE, a segment not on copper layers
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
@ PCB_ZONE_T
class ZONE, a copper pour area
@ PCB_TEXT_T
class PCB_TEXT, text on a layer
@ PCB_FIELD_T
class PCB_FIELD, text associated with a footprint property
@ PCB_PAD_T
class PAD, a pad in a footprint
VECTOR2< int32_t > VECTOR2I