KiCad PCB EDA Suite
drc_test_provider_solder_mask.cpp
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1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright (C) 2004-2022 KiCad Developers.
5 *
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21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
22 */
23
24#include <common.h>
27#include <footprint.h>
28#include <pad.h>
29#include <pcb_track.h>
30#include <zone.h>
31#include <geometry/seg.h>
32#include <drc/drc_engine.h>
33#include <drc/drc_item.h>
34#include <drc/drc_rule.h>
36#include <drc/drc_rtree.h>
37
38/*
39 Solder mask tests. Checks for silkscreen which is clipped by mask openings and for bridges
40 between mask apertures with different nets.
41 Errors generated:
42 - DRCE_SILK_CLEARANCE
43 - DRCE_SOLDERMASK_BRIDGE
44*/
45
47{
48public:
50 m_board( nullptr ),
51 m_webWidth( 0 ),
52 m_maxError( 0 ),
54 {
55 m_bridgeRule.m_Name = _( "board setup solder mask min width" );
56 }
57
59 {
60 }
61
62 virtual bool Run() override;
63
64 virtual const wxString GetName() const override
65 {
66 return wxT( "solder_mask_issues" );
67 };
68
69 virtual const wxString GetDescription() const override
70 {
71 return wxT( "Tests for silkscreen being clipped by solder mask and copper being exposed "
72 "by mask apertures of other nets" );
73 }
74
75private:
76 void addItemToRTrees( BOARD_ITEM* aItem );
77 void buildRTrees();
78
80 void testMaskBridges();
81
82 void testItemAgainstItems( BOARD_ITEM* aItem, const BOX2I& aItemBBox,
83 PCB_LAYER_ID aRefLayer, PCB_LAYER_ID aTargetLayer );
84 void testMaskItemAgainstZones( BOARD_ITEM* item, const BOX2I& itemBBox,
85 PCB_LAYER_ID refLayer, PCB_LAYER_ID targetLayer );
86
87 bool checkMaskAperture( BOARD_ITEM* aMaskItem, BOARD_ITEM* aTestItem, PCB_LAYER_ID aTestLayer,
88 int aTestNet, BOARD_ITEM** aCollidingItem );
89
90 bool checkItemMask( BOARD_ITEM* aMaskItem, int aTestNet );
91
92private:
94
99
100 std::unique_ptr<DRC_RTREE> m_fullSolderMaskRTree;
101 std::unique_ptr<DRC_RTREE> m_itemTree;
102
103 std::unordered_map<PTR_PTR_CACHE_KEY, LSET> m_checkedPairs;
104
105 // Shapes used to define solder mask apertures don't have nets, so we assign them the
106 // first object+net that bridges their aperture (after which any other nets will generate
107 // violations).
108 std::unordered_map<PTR_LAYER_CACHE_KEY, std::pair<BOARD_ITEM*, int>> m_maskApertureNetMap;
109};
110
111
113{
114 ZONE* solderMask = m_board->m_SolderMask;
115
116 if( aItem->Type() == PCB_ZONE_T || aItem->Type() == PCB_FP_ZONE_T )
117 {
118 ZONE* zone = static_cast<ZONE*>( aItem );
119
120 for( PCB_LAYER_ID layer : { F_Mask, B_Mask } )
121 {
122 if( zone->IsOnLayer( layer ) )
123 {
124 solderMask->GetFill( layer )->BooleanAdd( *zone->GetFilledPolysList( layer ),
126 }
127 }
128 }
129 else if( aItem->Type() == PCB_PAD_T )
130 {
131 for( PCB_LAYER_ID layer : { F_Mask, B_Mask } )
132 {
133 if( aItem->IsOnLayer( layer ) )
134 {
135 PAD* pad = static_cast<PAD*>( aItem );
136 int clearance = ( m_webWidth / 2 ) + pad->GetSolderMaskExpansion();
137
138 aItem->TransformShapeToPolygon( *solderMask->GetFill( layer ), layer, clearance,
140
141 m_itemTree->Insert( aItem, layer, m_largestClearance );
142 }
143 }
144 }
145 else if( aItem->Type() == PCB_VIA_T )
146 {
147 for( PCB_LAYER_ID layer : { F_Mask, B_Mask } )
148 {
149 if( aItem->IsOnLayer( layer ) )
150 {
151 PCB_VIA* via = static_cast<PCB_VIA*>( aItem );
152 int clearance = ( m_webWidth / 2 ) + via->GetSolderMaskExpansion();
153
154 via->TransformShapeToPolygon( *solderMask->GetFill( layer ), layer, clearance,
156
157 m_itemTree->Insert( aItem, layer, m_largestClearance );
158 }
159 }
160 }
161 else
162 {
163 for( PCB_LAYER_ID layer : { F_Mask, B_Mask } )
164 {
165 if( aItem->IsOnLayer( layer ) )
166 {
167 aItem->TransformShapeToPolygon( *solderMask->GetFill( layer ), layer,
169
170 m_itemTree->Insert( aItem, layer, m_largestClearance );
171 }
172 }
173 }
174}
175
176
178{
179 ZONE* solderMask = m_board->m_SolderMask;
180 LSET layers = { 4, F_Mask, B_Mask, F_Cu, B_Cu };
181
182 const size_t progressDelta = 500;
183 int count = 0;
184 int ii = 0;
185
186 solderMask->GetFill( F_Mask )->RemoveAllContours();
187 solderMask->GetFill( B_Mask )->RemoveAllContours();
188
189 m_fullSolderMaskRTree = std::make_unique<DRC_RTREE>();
190 m_itemTree = std::make_unique<DRC_RTREE>();
191
193 [&]( BOARD_ITEM* item ) -> bool
194 {
195 ++count;
196 return true;
197 } );
198
200 [&]( BOARD_ITEM* item ) -> bool
201 {
202 if( !reportProgress( ii++, count, progressDelta ) )
203 return false;
204
205 addItemToRTrees( item );
206 return true;
207 } );
208
211
213
214 solderMask->GetFill( F_Mask )->Deflate( m_webWidth / 2, numSegs );
215 solderMask->GetFill( B_Mask )->Deflate( m_webWidth / 2, numSegs );
216
217 solderMask->SetFillFlag( F_Mask, true );
218 solderMask->SetFillFlag( B_Mask, true );
219 solderMask->SetIsFilled( true );
220
221 solderMask->CacheTriangulation();
222
223 m_fullSolderMaskRTree->Insert( solderMask, F_Mask );
224 m_fullSolderMaskRTree->Insert( solderMask, B_Mask );
225
226 m_checkedPairs.clear();
227}
228
229
231{
232 LSET silkLayers = { 2, F_SilkS, B_SilkS };
233
234 const size_t progressDelta = 250;
235 int count = 0;
236 int ii = 0;
237
239 [&]( BOARD_ITEM* item ) -> bool
240 {
241 ++count;
242 return true;
243 } );
244
246 [&]( BOARD_ITEM* item ) -> bool
247 {
249 return false;
250
251 if( !reportProgress( ii++, count, progressDelta ) )
252 return false;
253
254 if( isInvisibleText( item ) )
255 return true;
256
257 for( PCB_LAYER_ID layer : silkLayers.Seq() )
258 {
259 if( !item->IsOnLayer( layer ) )
260 continue;
261
262 BOX2I itemBBox = item->GetBoundingBox();
263 DRC_CONSTRAINT constraint = m_drcEngine->EvalRules( SILK_CLEARANCE_CONSTRAINT,
264 item, nullptr, layer );
265 int clearance = constraint.GetValue().Min();
266 int actual;
267 VECTOR2I pos;
268
269 if( constraint.GetSeverity() == RPT_SEVERITY_IGNORE || clearance <= 0 )
270 return true;
271
272 std::shared_ptr<SHAPE> itemShape = item->GetEffectiveShape( layer );
273
274 if( m_fullSolderMaskRTree->QueryColliding( itemBBox, itemShape.get(), layer,
275 clearance, &actual, &pos ) )
276 {
277 auto drce = DRC_ITEM::Create( DRCE_SILK_CLEARANCE );
278 wxString msg = formatMsg( _( "(%s clearance %s; actual %s)" ),
279 constraint.GetName(),
280 clearance,
281 actual );
282
283 drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
284 drce->SetItems( item );
285 drce->SetViolatingRule( constraint.GetParentRule() );
286
287 reportViolation( drce, pos, layer );
288 }
289 }
290
291 return true;
292 } );
293}
294
295
297{
298 if( aItem->Type() == PCB_PAD_T )
299 {
300 PAD* pad = static_cast<PAD*>( aItem );
301
302 if( pad->GetAttribute() == PAD_ATTRIB::NPTH
303 && ( pad->GetShape() == PAD_SHAPE::CIRCLE || pad->GetShape() == PAD_SHAPE::OVAL )
304 && pad->GetSize().x <= pad->GetDrillSize().x
305 && pad->GetSize().y <= pad->GetDrillSize().y )
306 {
307 return true;
308 }
309 }
310
311 return false;
312}
313
314
315// Simple mask apertures aren't associated with copper items, so they only constitute a bridge
316// when they expose other copper items having at least two distinct nets. We use a map to record
317// the first net exposed by each mask aperture (on each copper layer).
318//
319// Note that this algorithm is also used for free pads.
320
322{
323 if( aItem->Type() == PCB_PAD_T && static_cast<PAD*>( aItem )->IsFreePad() )
324 return true;
325
326 static const LSET saved( 2, F_Mask, B_Mask );
327
328 LSET maskLayers = aItem->GetLayerSet() & saved;
329 LSET otherLayers = aItem->GetLayerSet() & ~saved;
330
331 return maskLayers.count() > 0 && otherLayers.count() == 0;
332}
333
334
336 PCB_LAYER_ID aTestLayer, int aTestNet,
337 BOARD_ITEM** aCollidingItem )
338{
339 if( !IsCopperLayer( aTestLayer ) )
340 return false;
341
342 FOOTPRINT* fp = static_cast<FOOTPRINT*>( aMaskItem->GetParentFootprint() );
343
344 if( fp && ( fp->GetAttributes() & FP_ALLOW_SOLDERMASK_BRIDGES ) > 0 )
345 {
346 // Mask apertures in footprints which allow soldermask bridges are ignored entirely.
347 return false;
348 }
349
350 PTR_LAYER_CACHE_KEY key = { aMaskItem, aTestLayer };
351
352 auto ii = m_maskApertureNetMap.find( key );
353
354 if( ii == m_maskApertureNetMap.end() )
355 {
356 m_maskApertureNetMap[ key ] = { aTestItem, aTestNet };
357
358 // First net; no bridge yet....
359 return false;
360 }
361
362 if( ii->second.second == aTestNet && aTestNet > 0 )
363 {
364 // Same net; still no bridge...
365 return false;
366 }
367
368 *aCollidingItem = ii->second.first;
369 return true;
370}
371
372
374{
375 FOOTPRINT* fp = static_cast<FOOTPRINT*>( aMaskItem->GetParentFootprint() );
376
377 wxCHECK( fp, false );
378
379 if( ( fp->GetAttributes() & FP_ALLOW_SOLDERMASK_BRIDGES ) > 0 )
380 {
381 // If we're allowing bridges then we're allowing bridges. Nothing to check.
382 return false;
383 }
384
385 // Graphic items are used to implement net-ties between pads of a group within a net-tie
386 // footprint. They must be allowed to intrude into their pad's mask aperture.
387 if( aTestNet < 0 && aMaskItem->Type() == PCB_PAD_T && fp->IsNetTie() )
388 {
389 std::map<wxString, int> padNumberToGroupIdxMap = fp->MapPadNumbersToNetTieGroups();
390
391 if( padNumberToGroupIdxMap[ static_cast<PAD*>( aMaskItem )->GetNumber() ] >= 0 )
392 return false;
393 }
394
395 return true;
396}
397
398
400 PCB_LAYER_ID aRefLayer,
401 PCB_LAYER_ID aTargetLayer )
402{
403 int itemNet = -1;
404
405 if( aItem->IsConnected() )
406 itemNet = static_cast<BOARD_CONNECTED_ITEM*>( aItem )->GetNetCode();
407
409 PAD* pad = dynamic_cast<PAD*>( aItem );
410 PCB_VIA* via = dynamic_cast<PCB_VIA*>( aItem );
411 std::shared_ptr<SHAPE> itemShape = aItem->GetEffectiveShape( aRefLayer );
412
413 m_itemTree->QueryColliding( aItem, aRefLayer, aTargetLayer,
414 // Filter:
415 [&]( BOARD_ITEM* other ) -> bool
416 {
417 FOOTPRINT* itemFP = static_cast<FOOTPRINT*>( aItem->GetParentFootprint() );
418 PAD* otherPad = dynamic_cast<PAD*>( other );
419 int otherNet = -1;
420
421 if( other->IsConnected() )
422 otherNet = static_cast<BOARD_CONNECTED_ITEM*>( other )->GetNetCode();
423
424 if( otherNet > 0 && otherNet == itemNet )
425 return false;
426
427 if( isNullAperture( other ) )
428 return false;
429
430 if( itemFP && itemFP == other->GetParentFootprint() )
431 {
432 // Board-wide exclusion
434 return false;
435
436 // Footprint-specific exclusion
437 if( ( itemFP->GetAttributes() & FP_ALLOW_SOLDERMASK_BRIDGES ) > 0 )
438 return false;
439 }
440
441 if( pad && otherPad && pad->SameLogicalPadAs( otherPad ) )
442 {
443 return false;
444 }
445
446 BOARD_ITEM* a = aItem;
447 BOARD_ITEM* b = other;
448
449 // store canonical order so we don't collide in both directions (a:b and b:a)
450 if( static_cast<void*>( a ) > static_cast<void*>( b ) )
451 std::swap( a, b );
452
453 auto it = m_checkedPairs.find( { a, b } );
454
455 if( it != m_checkedPairs.end() && it->second.test( aTargetLayer ) )
456 {
457 return false;
458 }
459 else
460 {
461 m_checkedPairs[ { a, b } ].set( aTargetLayer );
462 return true;
463 }
464 },
465 // Visitor:
466 [&]( BOARD_ITEM* other ) -> bool
467 {
468 PAD* otherPad = dynamic_cast<PAD*>( other );
469 PCB_VIA* otherVia = dynamic_cast<PCB_VIA*>( other );
470 auto otherShape = other->GetEffectiveShape( aTargetLayer );
471 int otherNet = -1;
472
473 if( other->IsConnected() )
474 otherNet = static_cast<BOARD_CONNECTED_ITEM*>( other )->GetNetCode();
475
476 int actual;
477 VECTOR2I pos;
478 int clearance = 0;
479
480 if( aRefLayer == F_Mask || aRefLayer == B_Mask )
481 {
482 // Aperture-to-aperture must enforce web-min-width
483 clearance = m_webWidth;
484 }
485 else // ( aRefLayer == F_Cu || aRefLayer == B_Cu )
486 {
487 // Copper-to-aperture uses the solder-mask-to-copper-clearance
489 }
490
491 if( pad )
492 clearance += pad->GetSolderMaskExpansion();
493 else if( via )
494 clearance += via->GetSolderMaskExpansion();
495
496 if( otherPad )
497 clearance += otherPad->GetSolderMaskExpansion();
498 else if( otherVia )
499 clearance += otherVia->GetSolderMaskExpansion();
500
501 if( itemShape->Collide( otherShape.get(), clearance, &actual, &pos ) )
502 {
503 wxString msg;
504 BOARD_ITEM* colliding = nullptr;
505
506 if( aTargetLayer == F_Mask )
507 msg = _( "Front solder mask aperture bridges items with different nets" );
508 else
509 msg = _( "Rear solder mask aperture bridges items with different nets" );
510
511 // Simple mask apertures aren't associated with copper items, so they only
512 // constitute a bridge when they expose other copper items having at least
513 // two distinct nets.
514 if( isMaskAperture( aItem ) )
515 {
516 if( checkMaskAperture( aItem, other, aRefLayer, otherNet, &colliding ) )
517 {
519
520 drce->SetErrorMessage( msg );
521 drce->SetItems( aItem, colliding, other );
522 drce->SetViolatingRule( &m_bridgeRule );
523 reportViolation( drce, pos, aTargetLayer );
524 }
525 }
526 else if( isMaskAperture( other ) )
527 {
528 if( checkMaskAperture( other, aItem, aRefLayer, itemNet, &colliding ) )
529 {
531
532 drce->SetErrorMessage( msg );
533 drce->SetItems( other, colliding, aItem );
534 drce->SetViolatingRule( &m_bridgeRule );
535 reportViolation( drce, pos, aTargetLayer );
536 }
537 }
538 else if( checkItemMask( other, itemNet ) )
539 {
541
542 drce->SetErrorMessage( msg );
543 drce->SetItems( aItem, other );
544 drce->SetViolatingRule( &m_bridgeRule );
545 reportViolation( drce, pos, aTargetLayer );
546 }
547 }
548
549 return !m_drcEngine->IsCancelled();
550 },
552}
553
554
556 const BOX2I& aItemBBox,
557 PCB_LAYER_ID aMaskLayer,
558 PCB_LAYER_ID aTargetLayer )
559{
560 for( ZONE* zone : m_board->m_DRCCopperZones )
561 {
562 if( !zone->GetLayerSet().test( aTargetLayer ) )
563 continue;
564
565 int zoneNet = zone->GetNetCode();
566
567 if( aItem->IsConnected() )
568 {
569 BOARD_CONNECTED_ITEM* connectedItem = static_cast<BOARD_CONNECTED_ITEM*>( aItem );
570
571 if( zoneNet == connectedItem->GetNetCode() && zoneNet > 0 )
572 continue;
573 }
574
575 BOX2I inflatedBBox( aItemBBox );
577
578 if( aItem->Type() == PCB_PAD_T )
579 clearance += static_cast<PAD*>( aItem )->GetSolderMaskExpansion();
580 else if( aItem->Type() == PCB_VIA_T )
581 clearance += static_cast<PCB_VIA*>( aItem )->GetSolderMaskExpansion();
582
583 inflatedBBox.Inflate( clearance );
584
585 if( !inflatedBBox.Intersects( zone->GetBoundingBox() ) )
586 continue;
587
588 DRC_RTREE* zoneTree = m_board->m_CopperZoneRTreeCache[ zone ].get();
589 int actual;
590 VECTOR2I pos;
591
592 std::shared_ptr<SHAPE> itemShape = aItem->GetEffectiveShape( aMaskLayer );
593
594 if( zoneTree && zoneTree->QueryColliding( aItemBBox, itemShape.get(), aTargetLayer,
595 clearance, &actual, &pos ) )
596 {
597 wxString msg;
598 BOARD_ITEM* colliding = nullptr;
599
600 if( aMaskLayer == F_Mask )
601 msg = _( "Front solder mask aperture bridges items with different nets" );
602 else
603 msg = _( "Rear solder mask aperture bridges items with different nets" );
604
605 // Simple mask apertures aren't associated with copper items, so they only constitute
606 // a bridge when they expose other copper items having at least two distinct nets.
607 if( isMaskAperture( aItem ) && zoneNet >= 0 )
608 {
609 if( checkMaskAperture( aItem, zone, aTargetLayer, zoneNet, &colliding ) )
610 {
612
613 drce->SetErrorMessage( msg );
614 drce->SetItems( aItem, colliding, zone );
615 drce->SetViolatingRule( &m_bridgeRule );
616 reportViolation( drce, pos, aTargetLayer );
617 }
618 }
619 else
620 {
622
623 drce->SetErrorMessage( msg );
624 drce->SetItems( aItem, zone );
625 drce->SetViolatingRule( &m_bridgeRule );
626 reportViolation( drce, pos, aTargetLayer );
627 }
628 }
629
630 if( m_drcEngine->IsCancelled() )
631 return;
632 }
633}
634
635
637{
638 LSET copperAndMaskLayers = { 4, F_Mask, B_Mask, F_Cu, B_Cu };
639
640 const size_t progressDelta = 250;
641 int count = 0;
642 int ii = 0;
643
644 forEachGeometryItem( s_allBasicItemsButZones, copperAndMaskLayers,
645 [&]( BOARD_ITEM* item ) -> bool
646 {
647 ++count;
648 return true;
649 } );
650
651 forEachGeometryItem( s_allBasicItemsButZones, copperAndMaskLayers,
652 [&]( BOARD_ITEM* item ) -> bool
653 {
655 return false;
656
657 if( !reportProgress( ii++, count, progressDelta ) )
658 return false;
659
660 BOX2I itemBBox = item->GetBoundingBox();
661
662 if( item->IsOnLayer( F_Mask ) && !isNullAperture( item ) )
663 {
664 // Test for aperture-to-aperture collisions
665 testItemAgainstItems( item, itemBBox, F_Mask, F_Mask );
666
667 // Test for aperture-to-zone collisions
668 testMaskItemAgainstZones( item, itemBBox, F_Mask, F_Cu );
669 }
670 else if( item->IsOnLayer( F_Cu ) )
671 {
672 // Test for copper-item-to-aperture collisions
673 testItemAgainstItems( item, itemBBox, F_Cu, F_Mask );
674 }
675
676 if( item->IsOnLayer( B_Mask ) && !isNullAperture( item ) )
677 {
678 // Test for aperture-to-aperture collisions
679 testItemAgainstItems( item, itemBBox, B_Mask, B_Mask );
680
681 // Test for aperture-to-zone collisions
682 testMaskItemAgainstZones( item, itemBBox, B_Mask, B_Cu );
683 }
684 else if( item->IsOnLayer( B_Cu ) )
685 {
686 // Test for copper-item-to-aperture collisions
687 testItemAgainstItems( item, itemBBox, B_Cu, B_Mask );
688 }
689
690 return true;
691 } );
692}
693
694
696{
699 {
700 reportAux( wxT( "Solder mask violations ignored. Tests not run." ) );
701 return true; // continue with other tests
702 }
703
708
709 for( FOOTPRINT* footprint : m_board->Footprints() )
710 {
711 for( PAD* pad : footprint->Pads() )
712 m_largestClearance = std::max( m_largestClearance, pad->GetSolderMaskExpansion() );
713 }
714
715 // Order is important here: m_webWidth must be added in before m_largestCourtyardClearance is
716 // maxed with the various SILK_CLEARANCE_CONSTRAINTS.
718
719 DRC_CONSTRAINT worstClearanceConstraint;
720
721 if( m_drcEngine->QueryWorstConstraint( SILK_CLEARANCE_CONSTRAINT, worstClearanceConstraint ) )
722 m_largestClearance = std::max( m_largestClearance, worstClearanceConstraint.m_Value.Min() );
723
724 reportAux( wxT( "Worst clearance : %d nm" ), m_largestClearance );
725
726 if( !reportPhase( _( "Building solder mask..." ) ) )
727 return false; // DRC cancelled
728
729 m_checkedPairs.clear();
730 m_maskApertureNetMap.clear();
731
732 buildRTrees();
733
734 if( !reportPhase( _( "Checking solder mask to silk clearance..." ) ) )
735 return false; // DRC cancelled
736
738
739 if( !reportPhase( _( "Checking solder mask web integrity..." ) ) )
740 return false; // DRC cancelled
741
743
745
746 return !m_drcEngine->IsCancelled();
747}
748
749
750namespace detail
751{
753}
A base class derived from BOARD_ITEM for items that can be connected and have a net,...
Container for design settings for a BOARD object.
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition: board_item.h:58
virtual bool IsConnected() const
Returns information if the object is derived from BOARD_CONNECTED_ITEM.
Definition: board_item.h:115
virtual void TransformShapeToPolygon(SHAPE_POLY_SET &aBuffer, PCB_LAYER_ID aLayer, int aClearance, int aError, ERROR_LOC aErrorLoc, bool ignoreLineWidth=false) const
Convert the item shape to a closed polygon.
Definition: board_item.cpp:196
virtual bool IsOnLayer(PCB_LAYER_ID aLayer) const
Test to see if this object is on the given layer.
Definition: board_item.h:245
virtual std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
Definition: board_item.cpp:219
virtual const BOARD * GetBoard() const
Return the BOARD in which this BOARD_ITEM resides, or NULL if none.
Definition: board_item.cpp:43
virtual LSET GetLayerSet() const
Return a std::bitset of all layers on which the item physically resides.
Definition: board_item.h:185
BOARD_ITEM_CONTAINER * GetParentFootprint() const
Definition: board_item.cpp:239
Information pertinent to a Pcbnew printed circuit board.
Definition: board.h:265
std::vector< ZONE * > m_DRCCopperZones
Definition: board.h:1151
FOOTPRINTS & Footprints()
Definition: board.h:307
ZONE * m_SolderMask
Definition: board.h:1154
std::unordered_map< ZONE *, std::unique_ptr< DRC_RTREE > > m_CopperZoneRTreeCache
Definition: board.h:1145
BOARD_DESIGN_SETTINGS & GetDesignSettings() const
Definition: board.cpp:643
bool Intersects(const BOX2< Vec > &aRect) const
Definition: box2.h:269
BOX2< Vec > & Inflate(coord_type dx, coord_type dy)
Inflates the rectangle horizontally by dx and vertically by dy.
Definition: box2.h:506
MINOPTMAX< int > m_Value
Definition: drc_rule.h:170
BOARD * GetBoard() const
Definition: drc_engine.h:89
bool IsErrorLimitExceeded(int error_code)
bool IsCancelled() const
bool QueryWorstConstraint(DRC_CONSTRAINT_T aRuleId, DRC_CONSTRAINT &aConstraint)
static std::shared_ptr< DRC_ITEM > Create(int aErrorCode)
Constructs a DRC_ITEM for the given error code.
Definition: drc_item.cpp:325
Implement an R-tree for fast spatial and layer indexing of connectable items.
Definition: drc_rtree.h:48
int QueryColliding(BOARD_ITEM *aRefItem, PCB_LAYER_ID aRefLayer, PCB_LAYER_ID aTargetLayer, std::function< bool(BOARD_ITEM *)> aFilter=nullptr, std::function< bool(BOARD_ITEM *)> aVisitor=nullptr, int aClearance=0) const
This is a fast test which essentially does bounding-box overlap given a worst-case clearance.
Definition: drc_rtree.h:211
wxString m_Name
Definition: drc_rule.h:110
virtual const wxString GetName() const override
void testMaskItemAgainstZones(BOARD_ITEM *item, const BOX2I &itemBBox, PCB_LAYER_ID refLayer, PCB_LAYER_ID targetLayer)
bool checkMaskAperture(BOARD_ITEM *aMaskItem, BOARD_ITEM *aTestItem, PCB_LAYER_ID aTestLayer, int aTestNet, BOARD_ITEM **aCollidingItem)
std::unique_ptr< DRC_RTREE > m_fullSolderMaskRTree
virtual bool Run() override
Run this provider against the given PCB with configured options (if any).
virtual const wxString GetDescription() const override
std::unordered_map< PTR_PTR_CACHE_KEY, LSET > m_checkedPairs
bool checkItemMask(BOARD_ITEM *aMaskItem, int aTestNet)
std::unordered_map< PTR_LAYER_CACHE_KEY, std::pair< BOARD_ITEM *, int > > m_maskApertureNetMap
void testItemAgainstItems(BOARD_ITEM *aItem, const BOX2I &aItemBBox, PCB_LAYER_ID aRefLayer, PCB_LAYER_ID aTargetLayer)
Represent a DRC "provider" which runs some DRC functions over a BOARD and spits out #DRC_ITEMs and po...
static std::vector< KICAD_T > s_allBasicItemsButZones
virtual bool reportPhase(const wxString &aStageName)
int forEachGeometryItem(const std::vector< KICAD_T > &aTypes, LSET aLayers, const std::function< bool(BOARD_ITEM *)> &aFunc)
virtual bool reportProgress(int aCount, int aSize, int aDelta)
virtual void reportViolation(std::shared_ptr< DRC_ITEM > &item, const VECTOR2I &aMarkerPos, int aMarkerLayer)
virtual void reportAux(wxString fmt,...)
static std::vector< KICAD_T > s_allBasicItems
DRC_ENGINE * m_drcEngine
bool isInvisibleText(const BOARD_ITEM *aItem) const
virtual void reportRuleStatistics()
virtual const BOX2I GetBoundingBox() const
Return the orthogonal bounding box of this object for display purposes.
Definition: eda_item.cpp:74
KICAD_T Type() const
Returns the type of object.
Definition: eda_item.h:97
std::map< wxString, int > MapPadNumbersToNetTieGroups() const
Definition: footprint.cpp:2272
int GetAttributes() const
Definition: footprint.h:250
bool IsNetTie() const
Definition: footprint.h:257
LSET is a set of PCB_LAYER_IDs.
Definition: layer_ids.h:530
LSEQ Seq(const PCB_LAYER_ID *aWishListSequence, unsigned aCount) const
Return an LSEQ from the union of this LSET and a desired sequence.
Definition: lset.cpp:411
T Min() const
Definition: minoptmax.h:33
Definition: pad.h:59
int GetSolderMaskExpansion() const
Definition: pad.cpp:821
bool IsFreePad() const
Definition: pad.cpp:172
int GetSolderMaskExpansion() const
Definition: pcb_track.cpp:445
void Deflate(int aAmount, int aCircleSegmentsCount, CORNER_STRATEGY aCornerStrategy=ROUND_ALL_CORNERS)
void BooleanAdd(const SHAPE_POLY_SET &b, POLYGON_MODE aFastMode)
Perform boolean polyset difference For aFastMode meaning, see function booleanOp.
void Simplify(POLYGON_MODE aFastMode)
Handle a list of polygons defining a copper zone.
Definition: zone.h:57
const std::shared_ptr< SHAPE_POLY_SET > & GetFilledPolysList(PCB_LAYER_ID aLayer) const
Definition: zone.h:602
void CacheTriangulation(PCB_LAYER_ID aLayer=UNDEFINED_LAYER)
Create a list of triangles that "fill" the solid areas used for instance to draw these solid areas on...
Definition: zone.cpp:1002
const BOX2I GetBoundingBox() const override
Definition: zone.cpp:320
void SetFillFlag(PCB_LAYER_ID aLayer, bool aFlag)
Definition: zone.h:240
SHAPE_POLY_SET * GetFill(PCB_LAYER_ID aLayer)
Definition: zone.h:608
void SetIsFilled(bool isFilled)
Definition: zone.h:243
virtual bool IsOnLayer(PCB_LAYER_ID) const override
Test to see if this object is on the given layer.
Definition: zone.cpp:314
virtual LSET GetLayerSet() const override
Return a std::bitset of all layers on which the item physically resides.
Definition: zone.h:122
The common library.
@ DRCE_SOLDERMASK_BRIDGE
Definition: drc_item.h:85
@ DRCE_SILK_CLEARANCE
Definition: drc_item.h:88
@ SILK_CLEARANCE_CONSTRAINT
Definition: drc_rule.h:52
bool isMaskAperture(BOARD_ITEM *aItem)
bool isNullAperture(BOARD_ITEM *aItem)
#define _(s)
static constexpr EDA_ANGLE & FULL_CIRCLE
Definition: eda_angle.h:410
@ FP_ALLOW_SOLDERMASK_BRIDGES
Definition: footprint.h:74
@ ERROR_OUTSIDE
int GetArcToSegmentCount(int aRadius, int aErrorMax, const EDA_ANGLE &aArcAngle)
bool IsCopperLayer(int aLayerId)
Tests whether a layer is a copper layer.
Definition: layer_ids.h:825
PCB_LAYER_ID
A quick note on layer IDs:
Definition: layer_ids.h:59
@ B_Mask
Definition: layer_ids.h:106
@ B_Cu
Definition: layer_ids.h:95
@ F_Mask
Definition: layer_ids.h:107
@ F_SilkS
Definition: layer_ids.h:104
@ B_SilkS
Definition: layer_ids.h:103
@ F_Cu
Definition: layer_ids.h:64
static DRC_REGISTER_TEST_PROVIDER< DRC_TEST_PROVIDER_ANNULAR_WIDTH > dummy
@ NPTH
like PAD_PTH, but not plated
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
Definition: typeinfo.h:102
@ PCB_ZONE_T
class ZONE, a copper pour area
Definition: typeinfo.h:112
@ PCB_FP_ZONE_T
class ZONE, managed by a footprint
Definition: typeinfo.h:100
@ PCB_PAD_T
class PAD, a pad in a footprint
Definition: typeinfo.h:87