KiCad PCB EDA Suite
Loading...
Searching...
No Matches
pcb_track.cpp
Go to the documentation of this file.
1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright (C) 2012 Jean-Pierre Charras, jp.charras at wanadoo.fr
5 * Copyright (C) 2012 SoftPLC Corporation, Dick Hollenbeck <[email protected]>
6 * Copyright (C) 2012 Wayne Stambaugh <[email protected]>
7 * Copyright (C) 1992-2024 KiCad Developers, see AUTHORS.txt for contributors.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, you may find one here:
21 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
22 * or you may search the http://www.gnu.org website for the version 2 license,
23 * or you may write to the Free Software Foundation, Inc.,
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
25 */
26#include <pcb_base_frame.h>
27#include <core/mirror.h>
29#include <board.h>
32#include <pcb_track.h>
33#include <base_units.h>
34#include <string_utils.h>
35#include <view/view.h>
38#include <geometry/seg.h>
41#include <geometry/shape_arc.h>
42#include <drc/drc_engine.h>
43#include <pcb_painter.h>
44#include <trigo.h>
45
46#include <google/protobuf/any.pb.h>
47#include <api/api_enums.h>
48#include <api/api_utils.h>
49#include <api/api_pcb_utils.h>
50#include <api/board/board_types.pb.h>
51
54
56 BOARD_CONNECTED_ITEM( aParent, idtype )
57{
58 m_Width = pcbIUScale.mmToIU( 0.2 ); // Gives a reasonable default width
59 m_CachedScale = -1.0; // Set invalid to force update
60 m_CachedLOD = 0.0; // Set to always display
61}
62
63
65{
66 return new PCB_TRACK( *this );
67}
68
69
70PCB_ARC::PCB_ARC( BOARD_ITEM* aParent, const SHAPE_ARC* aArc ) :
71 PCB_TRACK( aParent, PCB_ARC_T )
72{
73 m_Start = aArc->GetP0();
74 m_End = aArc->GetP1();
75 m_Mid = aArc->GetArcMid();
76}
77
78
80{
81 return new PCB_ARC( *this );
82}
83
84
86 PCB_TRACK( aParent, PCB_VIA_T )
87{
88 SetViaType( VIATYPE::THROUGH );
91
94
96
97 m_isFree = false;
98}
99
100
101PCB_VIA::PCB_VIA( const PCB_VIA& aOther ) :
102 PCB_TRACK( aOther.GetParent(), PCB_VIA_T )
103{
104 PCB_VIA::operator=( aOther );
105
106 const_cast<KIID&>( m_Uuid ) = aOther.m_Uuid;
108}
109
110
112{
114
115 m_Width = aOther.m_Width;
116 m_Start = aOther.m_Start;
117 m_End = aOther.m_End;
118 m_CachedLOD = aOther.m_CachedLOD;
120
122 m_viaType = aOther.m_viaType;
123 m_drill = aOther.m_drill;
126 m_isFree = aOther.m_isFree;
127
128 return *this;
129}
130
131
133{
134 return new PCB_VIA( *this );
135}
136
137
138wxString PCB_VIA::GetItemDescription( UNITS_PROVIDER* aUnitsProvider ) const
139{
140 wxString formatStr;
141
142 switch( GetViaType() )
143 {
144 case VIATYPE::BLIND_BURIED: formatStr = _( "Blind/Buried Via %s on %s" ); break;
145 case VIATYPE::MICROVIA: formatStr = _( "Micro Via %s on %s" ); break;
146 default: formatStr = _( "Via %s on %s" ); break;
147 }
148
149 return wxString::Format( formatStr, GetNetnameMsg(), layerMaskDescribe() );
150}
151
152
154{
155 return BITMAPS::via;
156}
157
158
159bool PCB_TRACK::operator==( const BOARD_ITEM& aOther ) const
160{
161 if( aOther.Type() != Type() )
162 return false;
163
164 const PCB_TRACK& other = static_cast<const PCB_TRACK&>( aOther );
165
166 return *this == other;
167}
168
169
170bool PCB_TRACK::operator==( const PCB_TRACK& aOther ) const
171{
172 return m_Start == aOther.m_Start
173 && m_End == aOther.m_End
174 && m_layer == aOther.m_layer
175 && m_Width == aOther.m_Width;
176}
177
178
179double PCB_TRACK::Similarity( const BOARD_ITEM& aOther ) const
180{
181 if( aOther.Type() != Type() )
182 return 0.0;
183
184 const PCB_TRACK& other = static_cast<const PCB_TRACK&>( aOther );
185
186 double similarity = 1.0;
187
188 if( m_layer != other.m_layer )
189 similarity *= 0.9;
190
191 if( m_Width != other.m_Width )
192 similarity *= 0.9;
193
194 if( m_Start != other.m_Start )
195 similarity *= 0.9;
196
197 if( m_End != other.m_End )
198 similarity *= 0.9;
199
200 return similarity;
201}
202
203
204bool PCB_ARC::operator==( const BOARD_ITEM& aOther ) const
205{
206 if( aOther.Type() != Type() )
207 return false;
208
209 const PCB_ARC& other = static_cast<const PCB_ARC&>( aOther );
210
211 return m_Start == other.m_Start && m_End == other.m_End && m_Mid == other.m_Mid &&
212 m_layer == other.m_layer && m_Width == other.m_Width;
213}
214
215
216double PCB_ARC::Similarity( const BOARD_ITEM& aOther ) const
217{
218 if( aOther.Type() != Type() )
219 return 0.0;
220
221 const PCB_ARC& other = static_cast<const PCB_ARC&>( aOther );
222
223 double similarity = 1.0;
224
225 if( m_layer != other.m_layer )
226 similarity *= 0.9;
227
228 if( m_Width != other.m_Width )
229 similarity *= 0.9;
230
231 if( m_Start != other.m_Start )
232 similarity *= 0.9;
233
234 if( m_End != other.m_End )
235 similarity *= 0.9;
236
237 if( m_Mid != other.m_Mid )
238 similarity *= 0.9;
239
240 return similarity;
241}
242
243
244bool PCB_VIA::operator==( const BOARD_ITEM& aOther ) const
245{
246 if( aOther.Type() != Type() )
247 return false;
248
249 const PCB_VIA& other = static_cast<const PCB_VIA&>( aOther );
250
251 return m_Start == other.m_Start && m_End == other.m_End && m_layer == other.m_layer &&
252 m_bottomLayer == other.m_bottomLayer && m_Width == other.m_Width &&
253 m_viaType == other.m_viaType && m_drill == other.m_drill &&
257}
258
259
260double PCB_VIA::Similarity( const BOARD_ITEM& aOther ) const
261{
262 if( aOther.Type() != Type() )
263 return 0.0;
264
265 const PCB_VIA& other = static_cast<const PCB_VIA&>( aOther );
266
267 double similarity = 1.0;
268
269 if( m_layer != other.m_layer )
270 similarity *= 0.9;
271
272 if( m_Width != other.m_Width )
273 similarity *= 0.9;
274
275 if( m_Start != other.m_Start )
276 similarity *= 0.9;
277
278 if( m_End != other.m_End )
279 similarity *= 0.9;
280
281 if( m_bottomLayer != other.m_bottomLayer )
282 similarity *= 0.9;
283
284 if( m_viaType != other.m_viaType )
285 similarity *= 0.9;
286
287 if( m_drill != other.m_drill )
288 similarity *= 0.9;
289
291 similarity *= 0.9;
292
294 similarity *= 0.9;
295
297 similarity *= 0.9;
298
299 return similarity;
300}
301
302
303void PCB_TRACK::Serialize( google::protobuf::Any &aContainer ) const
304{
305 kiapi::board::types::Track track;
306
307 track.mutable_id()->set_value( m_Uuid.AsStdString() );
308 track.mutable_start()->set_x_nm( GetStart().x );
309 track.mutable_start()->set_y_nm( GetStart().y );
310 track.mutable_end()->set_x_nm( GetEnd().x );
311 track.mutable_end()->set_y_nm( GetEnd().y );
312 track.mutable_width()->set_value_nm( GetWidth() );
313 track.set_layer( ToProtoEnum<PCB_LAYER_ID, kiapi::board::types::BoardLayer>( GetLayer() ) );
314 track.set_locked( IsLocked() ? kiapi::common::types::LockedState::LS_LOCKED
315 : kiapi::common::types::LockedState::LS_UNLOCKED );
316 track.mutable_net()->mutable_code()->set_value( GetNetCode() );
317 track.mutable_net()->set_name( GetNetname() );
318
319 aContainer.PackFrom( track );
320}
321
322
323bool PCB_TRACK::Deserialize( const google::protobuf::Any &aContainer )
324{
325 kiapi::board::types::Track track;
326
327 if( !aContainer.UnpackTo( &track ) )
328 return false;
329
330 const_cast<KIID&>( m_Uuid ) = KIID( track.id().value() );
331 SetStart( VECTOR2I( track.start().x_nm(), track.start().y_nm() ) );
332 SetEnd( VECTOR2I( track.end().x_nm(), track.end().y_nm() ) );
333 SetWidth( track.width().value_nm() );
334 SetLayer( FromProtoEnum<PCB_LAYER_ID, kiapi::board::types::BoardLayer>( track.layer() ) );
335 SetNetCode( track.net().code().value() );
336 SetLocked( track.locked() == kiapi::common::types::LockedState::LS_LOCKED );
337
338 return true;
339}
340
341
342void PCB_ARC::Serialize( google::protobuf::Any &aContainer ) const
343{
344 kiapi::board::types::Arc arc;
345
346 arc.mutable_id()->set_value( m_Uuid.AsStdString() );
347 arc.mutable_start()->set_x_nm( GetStart().x );
348 arc.mutable_start()->set_y_nm( GetStart().y );
349 arc.mutable_mid()->set_x_nm( GetMid().x );
350 arc.mutable_mid()->set_y_nm( GetMid().y );
351 arc.mutable_end()->set_x_nm( GetEnd().x );
352 arc.mutable_end()->set_y_nm( GetEnd().y );
353 arc.mutable_width()->set_value_nm( GetWidth() );
354 arc.set_layer( ToProtoEnum<PCB_LAYER_ID, kiapi::board::types::BoardLayer>( GetLayer() ) );
355 arc.set_locked( IsLocked() ? kiapi::common::types::LockedState::LS_LOCKED
356 : kiapi::common::types::LockedState::LS_UNLOCKED );
357 arc.mutable_net()->mutable_code()->set_value( GetNetCode() );
358 arc.mutable_net()->set_name( GetNetname() );
359
360 aContainer.PackFrom( arc );
361}
362
363
364bool PCB_ARC::Deserialize( const google::protobuf::Any &aContainer )
365{
366 kiapi::board::types::Arc arc;
367
368 if( !aContainer.UnpackTo( &arc ) )
369 return false;
370
371 const_cast<KIID&>( m_Uuid ) = KIID( arc.id().value() );
372 SetStart( VECTOR2I( arc.start().x_nm(), arc.start().y_nm() ) );
373 SetMid( VECTOR2I( arc.mid().x_nm(), arc.mid().y_nm() ) );
374 SetEnd( VECTOR2I( arc.end().x_nm(), arc.end().y_nm() ) );
375 SetWidth( arc.width().value_nm() );
376 SetLayer( FromProtoEnum<PCB_LAYER_ID, kiapi::board::types::BoardLayer>( arc.layer() ) );
377 SetNetCode( arc.net().code().value() );
378 SetLocked( arc.locked() == kiapi::common::types::LockedState::LS_LOCKED );
379
380 return true;
381}
382
383
384void PCB_VIA::Serialize( google::protobuf::Any &aContainer ) const
385{
386 kiapi::board::types::Via via;
387
388 via.mutable_id()->set_value( m_Uuid.AsStdString() );
389 via.mutable_position()->set_x_nm( GetPosition().x );
390 via.mutable_position()->set_y_nm( GetPosition().y );
391
392 kiapi::board::types::PadStack* padstack = via.mutable_pad_stack();
393 padstack->set_type( GetViaType() == VIATYPE::BLIND_BURIED
394 ? kiapi::board::types::PadStackType::PST_BLIND_BURIED
395 : kiapi::board::types::PadStackType::PST_THROUGH );
396 padstack->set_start_layer(
397 ToProtoEnum<PCB_LAYER_ID, kiapi::board::types::BoardLayer>( m_layer ) );
398 padstack->set_end_layer(
399 ToProtoEnum<PCB_LAYER_ID, kiapi::board::types::BoardLayer>( m_bottomLayer ) );
400 kiapi::common::PackVector2( *padstack->mutable_drill_diameter(),
401 { GetDrillValue(), GetDrillValue() } );
402
403 kiapi::board::types::PadStackLayer* stackLayer = padstack->add_layers();
404 kiapi::board::PackLayerSet( *stackLayer->mutable_layers(), GetLayerSet() );
405 kiapi::common::PackVector2( *stackLayer->mutable_size(),
406 { GetWidth(), GetWidth() } );
407
408 kiapi::board::types::UnconnectedLayerRemoval ulr;
409
411 {
413 ulr = kiapi::board::types::UnconnectedLayerRemoval::ULR_REMOVE_EXCEPT_START_AND_END;
414 else
415 ulr = kiapi::board::types::UnconnectedLayerRemoval::ULR_REMOVE;
416 }
417 else
418 {
419 ulr = kiapi::board::types::UnconnectedLayerRemoval::ULR_KEEP;
420 }
421
422 // TODO: Microvia status is ignored here. Do we still need it?
423
424 padstack->set_unconnected_layer_removal( ulr );
425
426 via.set_locked( IsLocked() ? kiapi::common::types::LockedState::LS_LOCKED
427 : kiapi::common::types::LockedState::LS_UNLOCKED );
428 via.mutable_net()->mutable_code()->set_value( GetNetCode() );
429 via.mutable_net()->set_name( GetNetname() );
430
431 aContainer.PackFrom( via );
432}
433
434
435bool PCB_VIA::Deserialize( const google::protobuf::Any &aContainer )
436{
437 kiapi::board::types::Via via;
438
439 if( !aContainer.UnpackTo( &via ) )
440 return false;
441
442 const_cast<KIID&>( m_Uuid ) = KIID( via.id().value() );
443 SetStart( VECTOR2I( via.position().x_nm(), via.position().y_nm() ) );
444 SetEnd( GetStart() );
445 SetDrill( via.pad_stack().drill_diameter().x_nm() );
446
447 const kiapi::board::types::PadStack& padstack = via.pad_stack();
448
449 // We don't yet support complex padstacks for vias
450 if( padstack.layers_size() == 1 )
451 {
452 const kiapi::board::types::PadStackLayer& layer = padstack.layers( 0 );
453 SetWidth( layer.size().x_nm() );
454 }
455
456 switch( padstack.type() )
457 {
458 case kiapi::board::types::PadStackType::PST_BLIND_BURIED:
459 SetViaType( VIATYPE::BLIND_BURIED );
460 break;
461
462 default:
463 SetViaType( VIATYPE::THROUGH );
464 break;
465 }
466
467 if( GetViaType() != VIATYPE::THROUGH )
468 {
469 m_layer = FromProtoEnum<PCB_LAYER_ID, kiapi::board::types::BoardLayer>(
470 padstack.start_layer() );
471
472 m_bottomLayer = FromProtoEnum<PCB_LAYER_ID, kiapi::board::types::BoardLayer>(
473 padstack.end_layer() );
474 }
475 else
476 {
477 m_layer = F_Cu;
479 }
480
481 switch( padstack.unconnected_layer_removal() )
482 {
483 case kiapi::board::types::UnconnectedLayerRemoval::ULR_REMOVE:
485 m_keepStartEndLayer = false;
486 break;
487
488 case kiapi::board::types::UnconnectedLayerRemoval::ULR_REMOVE_EXCEPT_START_AND_END:
490 m_keepStartEndLayer = true;
491 break;
492
493 default:
494 case kiapi::board::types::UnconnectedLayerRemoval::ULR_KEEP:
496 m_keepStartEndLayer = false;
497 break;
498 }
499
500 SetNetCode( via.net().code().value() );
501 SetLocked( via.locked() == kiapi::common::types::LockedState::LS_LOCKED );
502
503 return true;
504}
505
506
508{
509 SEG a( m_Start, m_End );
510 SEG b( aTrack.GetStart(), aTrack.GetEnd() );
511 return a.ApproxCollinear( b );
512}
513
514
516{
517 DRC_CONSTRAINT constraint;
518
519 if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine )
520 {
522
523 constraint = bds.m_DRCEngine->EvalRules( TRACK_WIDTH_CONSTRAINT, this, nullptr, m_layer );
524 }
525
526 if( aSource )
527 *aSource = constraint.GetName();
528
529 return constraint.Value();
530}
531
532
534{
535 DRC_CONSTRAINT constraint;
536
537 if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine )
538 {
540
541 constraint = bds.m_DRCEngine->EvalRules( VIA_DIAMETER_CONSTRAINT, this, nullptr, m_layer );
542 }
543
544 if( aSource )
545 *aSource = constraint.GetName();
546
547 return constraint.Value();
548}
549
550
552{
553 DRC_CONSTRAINT constraint;
554
555 if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine )
556 {
558
559 constraint = bds.m_DRCEngine->EvalRules( HOLE_SIZE_CONSTRAINT, this, nullptr, m_layer );
560 }
561
562 if( aSource )
563 *aSource = constraint.GetName();
564
565 return constraint.Value();
566}
567
568
569int PCB_VIA::GetMinAnnulus( PCB_LAYER_ID aLayer, wxString* aSource ) const
570{
571 if( !FlashLayer( aLayer ) )
572 {
573 if( aSource )
574 *aSource = _( "removed annular ring" );
575
576 return 0;
577 }
578
579 DRC_CONSTRAINT constraint;
580
581 if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine )
582 {
584
585 constraint = bds.m_DRCEngine->EvalRules( ANNULAR_WIDTH_CONSTRAINT, this, nullptr, aLayer );
586 }
587
588 if( constraint.Value().HasMin() )
589 {
590 if( aSource )
591 *aSource = constraint.GetName();
592
593 return constraint.Value().Min();
594 }
595
596 return 0;
597}
598
599
601{
602 if( m_drill > 0 ) // Use the specific value.
603 return m_drill;
604
605 // Use the default value from the Netclass
606 NETCLASS* netclass = GetEffectiveNetClass();
607
608 if( GetViaType() == VIATYPE::MICROVIA )
609 return netclass->GetuViaDrill();
610
611 return netclass->GetViaDrill();
612}
613
614
615EDA_ITEM_FLAGS PCB_TRACK::IsPointOnEnds( const VECTOR2I& point, int min_dist ) const
616{
617 EDA_ITEM_FLAGS result = 0;
618
619 if( min_dist < 0 )
620 min_dist = m_Width / 2;
621
622 if( min_dist == 0 )
623 {
624 if( m_Start == point )
625 result |= STARTPOINT;
626
627 if( m_End == point )
628 result |= ENDPOINT;
629 }
630 else
631 {
632 double dist = GetLineLength( m_Start, point );
633
634 if( min_dist >= KiROUND( dist ) )
635 result |= STARTPOINT;
636
637 dist = GetLineLength( m_End, point );
638
639 if( min_dist >= KiROUND( dist ) )
640 result |= ENDPOINT;
641 }
642
643 return result;
644}
645
646
648{
649 // end of track is round, this is its radius, rounded up
650 int radius = ( m_Width + 1 ) / 2;
651 int ymax, xmax, ymin, xmin;
652
653 if( Type() == PCB_VIA_T )
654 {
655 ymax = m_Start.y;
656 xmax = m_Start.x;
657
658 ymin = m_Start.y;
659 xmin = m_Start.x;
660 }
661 else if( Type() == PCB_ARC_T )
662 {
663 std::shared_ptr<SHAPE> arc = GetEffectiveShape();
664 BOX2I bbox = arc->BBox();
665
666 xmin = bbox.GetLeft();
667 xmax = bbox.GetRight();
668 ymin = bbox.GetTop();
669 ymax = bbox.GetBottom();
670 }
671 else
672 {
673 ymax = std::max( m_Start.y, m_End.y );
674 xmax = std::max( m_Start.x, m_End.x );
675
676 ymin = std::min( m_Start.y, m_End.y );
677 xmin = std::min( m_Start.x, m_End.x );
678 }
679
680 ymax += radius;
681 xmax += radius;
682
683 ymin -= radius;
684 xmin -= radius;
685
686 // return a rectangle which is [pos,dim) in nature. therefore the +1
687 return BOX2ISafe( VECTOR2I( xmin, ymin ),
688 VECTOR2L( (int64_t) xmax - xmin + 1, (int64_t) ymax - ymin + 1 ) );
689}
690
691
693{
694 return GetLineLength( m_Start, m_End );
695}
696
697
698void PCB_TRACK::Rotate( const VECTOR2I& aRotCentre, const EDA_ANGLE& aAngle )
699{
700 RotatePoint( m_Start, aRotCentre, aAngle );
701 RotatePoint( m_End, aRotCentre, aAngle );
702}
703
704
705void PCB_ARC::Rotate( const VECTOR2I& aRotCentre, const EDA_ANGLE& aAngle )
706{
707 RotatePoint( m_Start, aRotCentre, aAngle );
708 RotatePoint( m_End, aRotCentre, aAngle );
709 RotatePoint( m_Mid, aRotCentre, aAngle );
710}
711
712
713void PCB_TRACK::Mirror( const VECTOR2I& aCentre, bool aMirrorAroundXAxis )
714{
715 if( aMirrorAroundXAxis )
716 {
717 MIRROR( m_Start.y, aCentre.y );
718 MIRROR( m_End.y, aCentre.y );
719 }
720 else
721 {
722 MIRROR( m_Start.x, aCentre.x );
723 MIRROR( m_End.x, aCentre.x );
724 }
725}
726
727
728void PCB_ARC::Mirror( const VECTOR2I& aCentre, bool aMirrorAroundXAxis )
729{
730 if( aMirrorAroundXAxis )
731 {
732 MIRROR( m_Start.y, aCentre.y );
733 MIRROR( m_End.y, aCentre.y );
734 MIRROR( m_Mid.y, aCentre.y );
735 }
736 else
737 {
738 MIRROR( m_Start.x, aCentre.x );
739 MIRROR( m_End.x, aCentre.x );
740 MIRROR( m_Mid.x, aCentre.x );
741 }
742}
743
744
745void PCB_TRACK::Flip( const VECTOR2I& aCentre, bool aFlipLeftRight )
746{
747 if( aFlipLeftRight )
748 {
749 m_Start.x = aCentre.x - ( m_Start.x - aCentre.x );
750 m_End.x = aCentre.x - ( m_End.x - aCentre.x );
751 }
752 else
753 {
754 m_Start.y = aCentre.y - ( m_Start.y - aCentre.y );
755 m_End.y = aCentre.y - ( m_End.y - aCentre.y );
756 }
757
758 int copperLayerCount = GetBoard()->GetCopperLayerCount();
759 SetLayer( FlipLayer( GetLayer(), copperLayerCount ) );
760}
761
762
763void PCB_ARC::Flip( const VECTOR2I& aCentre, bool aFlipLeftRight )
764{
765 if( aFlipLeftRight )
766 {
767 m_Start.x = aCentre.x - ( m_Start.x - aCentre.x );
768 m_End.x = aCentre.x - ( m_End.x - aCentre.x );
769 m_Mid.x = aCentre.x - ( m_Mid.x - aCentre.x );
770 }
771 else
772 {
773 m_Start.y = aCentre.y - ( m_Start.y - aCentre.y );
774 m_End.y = aCentre.y - ( m_End.y - aCentre.y );
775 m_Mid.y = aCentre.y - ( m_Mid.y - aCentre.y );
776 }
777
778 int copperLayerCount = GetBoard()->GetCopperLayerCount();
779 SetLayer( FlipLayer( GetLayer(), copperLayerCount ) );
780}
781
782
783bool PCB_ARC::IsCCW() const
784{
785 VECTOR2I start_end = m_End - m_Start;
786 VECTOR2I start_mid = m_Mid - m_Start;
787
788 return start_end.Cross( start_mid ) < 0;
789}
790
791
792void PCB_VIA::Flip( const VECTOR2I& aCentre, bool aFlipLeftRight )
793{
794 if( aFlipLeftRight )
795 {
796 m_Start.x = aCentre.x - ( m_Start.x - aCentre.x );
797 m_End.x = aCentre.x - ( m_End.x - aCentre.x );
798 }
799 else
800 {
801 m_Start.y = aCentre.y - ( m_Start.y - aCentre.y );
802 m_End.y = aCentre.y - ( m_End.y - aCentre.y );
803 }
804
805 if( GetViaType() != VIATYPE::THROUGH )
806 {
807 int copperLayerCount = GetBoard()->GetCopperLayerCount();
808 PCB_LAYER_ID top_layer;
809 PCB_LAYER_ID bottom_layer;
810 LayerPair( &top_layer, &bottom_layer );
811 top_layer = FlipLayer( top_layer, copperLayerCount );
812 bottom_layer = FlipLayer( bottom_layer, copperLayerCount );
813 SetLayerPair( top_layer, bottom_layer );
814 }
815}
816
817
818INSPECT_RESULT PCB_TRACK::Visit( INSPECTOR inspector, void* testData,
819 const std::vector<KICAD_T>& aScanTypes )
820{
821 for( KICAD_T scanType : aScanTypes )
822 {
823 if( scanType == Type() )
824 {
825 if( INSPECT_RESULT::QUIT == inspector( this, testData ) )
826 return INSPECT_RESULT::QUIT;
827 }
828 }
829
830 return INSPECT_RESULT::CONTINUE;
831}
832
833
834std::shared_ptr<SHAPE_SEGMENT> PCB_VIA::GetEffectiveHoleShape() const
835{
836 return std::make_shared<SHAPE_SEGMENT>( SEG( m_Start, m_Start ), m_drill );
837}
838
839
841{
842 if( const BOARD* board = GetBoard() )
843 return board->GetTentVias();
844 else
845 return true;
846}
847
848
850{
851 if( const BOARD* board = GetBoard() )
852 return board->GetDesignSettings().m_SolderMaskExpansion;
853 else
854 return 0;
855}
856
857
859{
860#if 0
861 // Nice and simple, but raises its ugly head in performance profiles....
862 return GetLayerSet().test( aLayer );
863#endif
864
865 if( aLayer >= m_layer && aLayer <= m_bottomLayer )
866 return true;
867
868 if( !IsTented() )
869 {
870 if( aLayer == F_Mask )
871 return IsOnLayer( F_Cu );
872 else if( aLayer == B_Mask )
873 return IsOnLayer( B_Cu );
874 }
875
876 return false;
877}
878
879
881{
882 LSET layermask;
883
885 return layermask;
886
887 if( GetViaType() == VIATYPE::THROUGH )
888 layermask = LSET::AllCuMask();
889 else
890 wxASSERT( m_layer <= m_bottomLayer );
891
892 // PCB_LAYER_IDs are numbered from front to back, this is top to bottom.
893 for( int id = m_layer; id <= m_bottomLayer; ++id )
894 layermask.set( id );
895
896 if( !IsTented() )
897 {
898 if( layermask.test( F_Cu ) )
899 layermask.set( F_Mask );
900
901 if( layermask.test( B_Cu ) )
902 layermask.set( B_Mask );
903 }
904
905 return layermask;
906}
907
908
909void PCB_VIA::SetLayerSet( LSET aLayerSet )
910{
911 bool first = true;
912
913 for( PCB_LAYER_ID layer : aLayerSet.Seq() )
914 {
915 // m_layer and m_bottomLayer are copper layers, so consider only copper layers in aLayerSet
916 if( !IsCopperLayer( layer ) )
917 continue;
918
919 if( first )
920 {
921 m_layer = layer;
922 first = false;
923 }
924
925 m_bottomLayer = layer;
926 }
927}
928
929
930void PCB_VIA::SetLayerPair( PCB_LAYER_ID aTopLayer, PCB_LAYER_ID aBottomLayer )
931{
932
933 m_layer = aTopLayer;
934 m_bottomLayer = aBottomLayer;
936}
937
938
940{
941 m_layer = aLayer;
942}
943
944
946{
947 m_bottomLayer = aLayer;
948}
949
950
951void PCB_VIA::LayerPair( PCB_LAYER_ID* top_layer, PCB_LAYER_ID* bottom_layer ) const
952{
953 PCB_LAYER_ID t_layer = F_Cu;
954 PCB_LAYER_ID b_layer = B_Cu;
955
956 if( GetViaType() != VIATYPE::THROUGH )
957 {
958 b_layer = m_bottomLayer;
959 t_layer = m_layer;
960
961 if( b_layer < t_layer )
962 std::swap( b_layer, t_layer );
963 }
964
965 if( top_layer )
966 *top_layer = t_layer;
967
968 if( bottom_layer )
969 *bottom_layer = b_layer;
970}
971
972
974{
975 return m_layer;
976}
977
978
980{
981 return m_bottomLayer;
982}
983
984
986{
987 if( GetViaType() == VIATYPE::THROUGH )
988 {
989 m_layer = F_Cu;
991 }
992
993 if( m_bottomLayer < m_layer )
994 std::swap( m_bottomLayer, m_layer );
995}
996
997
998bool PCB_VIA::FlashLayer( LSET aLayers ) const
999{
1000 for( PCB_LAYER_ID layer : aLayers.Seq() )
1001 {
1002 if( FlashLayer( layer ) )
1003 return true;
1004 }
1005
1006 return false;
1007}
1008
1009
1010bool PCB_VIA::FlashLayer( int aLayer ) const
1011{
1012 // Return the "normal" shape if the caller doesn't specify a particular layer
1013 if( aLayer == UNDEFINED_LAYER )
1014 return true;
1015
1016 const BOARD* board = GetBoard();
1017
1018 if( !board )
1019 return true;
1020
1021 if( !IsOnLayer( static_cast<PCB_LAYER_ID>( aLayer ) ) )
1022 return false;
1023
1024 if( !m_removeUnconnectedLayer || !IsCopperLayer( aLayer ) )
1025 return true;
1026
1027 if( m_keepStartEndLayer && ( aLayer == m_layer || aLayer == m_bottomLayer ) )
1028 return true;
1029
1030 // Must be static to keep from raising its ugly head in performance profiles
1031 static std::initializer_list<KICAD_T> connectedTypes = { PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T,
1032 PCB_PAD_T };
1033
1034 if( m_zoneLayerOverrides[ aLayer ] == ZLO_FORCE_FLASHED )
1035 return true;
1036 else
1037 return board->GetConnectivity()->IsConnectedOnLayer( this, aLayer, connectedTypes );
1038}
1039
1040
1042 PCB_LAYER_ID* aBottommost ) const
1043{
1044 *aTopmost = UNDEFINED_LAYER;
1045 *aBottommost = UNDEFINED_LAYER;
1046
1047 static std::initializer_list<KICAD_T> connectedTypes = { PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T,
1048 PCB_PAD_T };
1049
1050 for( int layer = TopLayer(); layer <= BottomLayer(); ++layer )
1051 {
1052 bool connected = false;
1053
1054 if( m_zoneLayerOverrides[ layer ] == ZLO_FORCE_FLASHED )
1055 connected = true;
1056 else if( GetBoard()->GetConnectivity()->IsConnectedOnLayer( this, layer, connectedTypes ) )
1057 connected = true;
1058
1059 if( connected )
1060 {
1061 if( *aTopmost == UNDEFINED_LAYER )
1062 *aTopmost = ToLAYER_ID( layer );
1063
1064 *aBottommost = ToLAYER_ID( layer );
1065 }
1066 }
1067
1068}
1069
1070
1071void PCB_TRACK::ViewGetLayers( int aLayers[], int& aCount ) const
1072{
1073 // Show the track and its netname on different layers
1074 aLayers[0] = GetLayer();
1075 aLayers[1] = GetNetnameLayer( aLayers[0] );
1076 aCount = 2;
1077
1078 if( IsLocked() )
1079 aLayers[ aCount++ ] = LAYER_LOCKED_ITEM_SHADOW;
1080}
1081
1082
1083double PCB_TRACK::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
1084{
1085 constexpr double HIDE = std::numeric_limits<double>::max();
1086
1087 PCB_PAINTER* painter = static_cast<PCB_PAINTER*>( aView->GetPainter() );
1088 PCB_RENDER_SETTINGS* renderSettings = painter->GetSettings();
1089
1090 if( !aView->IsLayerVisible( LAYER_TRACKS ) )
1091 return HIDE;
1092
1093 if( IsNetnameLayer( aLayer ) )
1094 {
1096 return HIDE;
1097
1098 // Hide netnames on dimmed tracks
1099 if( renderSettings->GetHighContrast() )
1100 {
1101 if( m_layer != renderSettings->GetPrimaryHighContrastLayer() )
1102 return HIDE;
1103 }
1104
1105 // Pick the approximate size of the netname (square chars)
1106 wxString netName = GetUnescapedShortNetname();
1107 size_t num_chars = netName.size();
1108
1109 if( GetLength() < num_chars * GetWidth() )
1110 return HIDE;
1111
1112 // When drawing netnames, clip the track to the viewport
1113 VECTOR2I start( GetStart() );
1114 VECTOR2I end( GetEnd() );
1115 BOX2D viewport = aView->GetViewport();
1116 BOX2I clipBox = BOX2ISafe( viewport );
1117
1118 ClipLine( &clipBox, start.x, start.y, end.x, end.y );
1119
1120 VECTOR2I line = ( end - start );
1121
1122 if( line.EuclideanNorm() == 0 )
1123 return HIDE;
1124
1125 // Netnames will be shown only if zoom is appropriate
1126 return ( double ) pcbIUScale.mmToIU( 4 ) / ( m_Width + 1 );
1127 }
1128
1129 if( aLayer == LAYER_LOCKED_ITEM_SHADOW )
1130 {
1131 // Hide shadow if the main layer is not shown
1132 if( !aView->IsLayerVisible( m_layer ) )
1133 return HIDE;
1134
1135 // Hide shadow on dimmed tracks
1136 if( renderSettings->GetHighContrast() )
1137 {
1138 if( m_layer != renderSettings->GetPrimaryHighContrastLayer() )
1139 return HIDE;
1140 }
1141 }
1142
1143 // Other layers are shown without any conditions
1144 return 0.0;
1145}
1146
1147
1149{
1150 BOX2I bbox = GetBoundingBox();
1151
1152 if( const BOARD* board = GetBoard() )
1153 bbox.Inflate( 2 * board->GetDesignSettings().GetBiggestClearanceValue() );
1154 else
1155 bbox.Inflate( GetWidth() ); // Add a bit extra for safety
1156
1157 return bbox;
1158}
1159
1160
1161void PCB_VIA::ViewGetLayers( int aLayers[], int& aCount ) const
1162{
1163 aLayers[0] = LAYER_VIA_HOLES;
1164 aLayers[1] = LAYER_VIA_HOLEWALLS;
1165 aLayers[2] = LAYER_VIA_NETNAMES;
1166
1167 // Just show it on common via & via holes layers
1168 switch( GetViaType() )
1169 {
1170 case VIATYPE::THROUGH: aLayers[3] = LAYER_VIA_THROUGH; break;
1171 case VIATYPE::BLIND_BURIED: aLayers[3] = LAYER_VIA_BBLIND; break;
1172 case VIATYPE::MICROVIA: aLayers[3] = LAYER_VIA_MICROVIA; break;
1173 default: aLayers[3] = LAYER_GP_OVERLAY; break;
1174 }
1175
1176 aCount = 4;
1177
1178 if( IsLocked() )
1179 aLayers[ aCount++ ] = LAYER_LOCKED_ITEM_SHADOW;
1180
1181 // Vias can also be on a solder mask layer. They are on these layers or not,
1182 // depending on the plot and solder mask options
1183 if( IsOnLayer( F_Mask ) )
1184 aLayers[ aCount++ ] = F_Mask;
1185
1186 if( IsOnLayer( B_Mask ) )
1187 aLayers[ aCount++ ] = B_Mask;
1188}
1189
1190
1191double PCB_VIA::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
1192{
1193 constexpr double HIDE = (double)std::numeric_limits<double>::max();
1194
1195 PCB_PAINTER* painter = static_cast<PCB_PAINTER*>( aView->GetPainter() );
1196 PCB_RENDER_SETTINGS* renderSettings = painter->GetSettings();
1197 LSET visible = LSET::AllLayersMask();
1198
1199 // Meta control for hiding all vias
1200 if( !aView->IsLayerVisible( LAYER_VIAS ) )
1201 return HIDE;
1202
1203 // Handle board visibility
1204 if( const BOARD* board = GetBoard() )
1205 visible = board->GetVisibleLayers() & board->GetEnabledLayers();
1206
1207 // In high contrast mode don't show vias that don't cross the high-contrast layer
1208 if( renderSettings->GetHighContrast() )
1209 {
1210 PCB_LAYER_ID highContrastLayer = renderSettings->GetPrimaryHighContrastLayer();
1211
1212 if( LSET::FrontTechMask().Contains( highContrastLayer ) )
1213 highContrastLayer = F_Cu;
1214 else if( LSET::BackTechMask().Contains( highContrastLayer ) )
1215 highContrastLayer = B_Cu;
1216
1217 if( !GetLayerSet().Contains( highContrastLayer ) )
1218 return HIDE;
1219 }
1220
1221 if( IsHoleLayer( aLayer ) )
1222 {
1223 if( m_viaType == VIATYPE::BLIND_BURIED || m_viaType == VIATYPE::MICROVIA )
1224 {
1225 // Show a blind or micro via's hole if it crosses a visible layer
1226 if( !( visible & GetLayerSet() ).any() )
1227 return HIDE;
1228 }
1229 else
1230 {
1231 // Show a through via's hole if any physical layer is shown
1232 if( !( visible & LSET::PhysicalLayersMask() ).any() )
1233 return HIDE;
1234 }
1235 }
1236 else if( IsNetnameLayer( aLayer ) )
1237 {
1238 if( renderSettings->GetHighContrast() )
1239 {
1240 // Hide netnames unless via is flashed to a high-contrast layer
1241 if( !FlashLayer( renderSettings->GetPrimaryHighContrastLayer() ) )
1242 return HIDE;
1243 }
1244 else
1245 {
1246 // Hide netnames unless pad is flashed to a visible layer
1247 if( !FlashLayer( visible ) )
1248 return HIDE;
1249 }
1250
1251 // Netnames will be shown only if zoom is appropriate
1252 return m_Width == 0 ? HIDE : ( (double)pcbIUScale.mmToIU( 10 ) / m_Width );
1253 }
1254
1255 // Passed all tests; show.
1256 return 0.0;
1257}
1258
1259
1261{
1262 switch( Type() )
1263 {
1264 case PCB_ARC_T: return _( "Track (arc)" );
1265 case PCB_VIA_T: return _( "Via" );
1266 case PCB_TRACE_T:
1267 default: return _( "Track" );
1268 }
1269}
1270
1271
1272void PCB_TRACK::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>& aList )
1273{
1274 wxString msg;
1275 BOARD* board = GetBoard();
1276
1277 aList.emplace_back( _( "Type" ), GetFriendlyName() );
1278
1279 GetMsgPanelInfoBase_Common( aFrame, aList );
1280
1281 aList.emplace_back( _( "Layer" ), layerMaskDescribe() );
1282
1283 aList.emplace_back( _( "Width" ), aFrame->MessageTextFromValue( m_Width ) );
1284
1285 if( Type() == PCB_ARC_T )
1286 {
1287 double radius = static_cast<PCB_ARC*>( this )->GetRadius();
1288 aList.emplace_back( _( "Radius" ), aFrame->MessageTextFromValue( radius ) );
1289 }
1290
1291 aList.emplace_back( _( "Segment Length" ), aFrame->MessageTextFromValue( GetLength() ) );
1292
1293 // Display full track length (in Pcbnew)
1294 if( board && GetNetCode() > 0 )
1295 {
1296 int count;
1297 double trackLen;
1298 double lenPadToDie;
1299
1300 std::tie( count, trackLen, lenPadToDie ) = board->GetTrackLength( *this );
1301
1302 aList.emplace_back( _( "Routed Length" ), aFrame->MessageTextFromValue( trackLen ) );
1303
1304 if( lenPadToDie != 0 )
1305 {
1306 msg = aFrame->MessageTextFromValue( lenPadToDie );
1307 aList.emplace_back( _( "Pad To Die Length" ), msg );
1308
1309 msg = aFrame->MessageTextFromValue( trackLen + lenPadToDie );
1310 aList.emplace_back( _( "Full Length" ), msg );
1311 }
1312 }
1313
1314 wxString source;
1315 int clearance = GetOwnClearance( GetLayer(), &source );
1316
1317 aList.emplace_back( wxString::Format( _( "Min Clearance: %s" ),
1318 aFrame->MessageTextFromValue( clearance ) ),
1319 wxString::Format( _( "(from %s)" ), source ) );
1320
1321 MINOPTMAX<int> constraintValue = GetWidthConstraint( &source );
1322 msg = aFrame->MessageTextFromMinOptMax( constraintValue );
1323
1324 if( !msg.IsEmpty() )
1325 {
1326 aList.emplace_back( wxString::Format( _( "Width Constraints: %s" ), msg ),
1327 wxString::Format( _( "(from %s)" ), source ) );
1328 }
1329}
1330
1331
1332void PCB_VIA::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>& aList )
1333{
1334 wxString msg;
1335
1336 switch( GetViaType() )
1337 {
1338 case VIATYPE::MICROVIA: msg = _( "Micro Via" ); break;
1339 case VIATYPE::BLIND_BURIED: msg = _( "Blind/Buried Via" ); break;
1340 case VIATYPE::THROUGH: msg = _( "Through Via" ); break;
1341 default: msg = _( "Via" ); break;
1342 }
1343
1344 aList.emplace_back( _( "Type" ), msg );
1345
1346 GetMsgPanelInfoBase_Common( aFrame, aList );
1347
1348 aList.emplace_back( _( "Layer" ), layerMaskDescribe() );
1349 aList.emplace_back( _( "Diameter" ), aFrame->MessageTextFromValue( m_Width ) );
1350 aList.emplace_back( _( "Hole" ), aFrame->MessageTextFromValue( GetDrillValue() ) );
1351
1352 wxString source;
1353 int clearance = GetOwnClearance( GetLayer(), &source );
1354
1355 aList.emplace_back( wxString::Format( _( "Min Clearance: %s" ),
1356 aFrame->MessageTextFromValue( clearance ) ),
1357 wxString::Format( _( "(from %s)" ), source ) );
1358
1359 int minAnnulus = GetMinAnnulus( GetLayer(), &source );
1360
1361 aList.emplace_back( wxString::Format( _( "Min Annular Width: %s" ),
1362 aFrame->MessageTextFromValue( minAnnulus ) ),
1363 wxString::Format( _( "(from %s)" ), source ) );
1364}
1365
1366
1368 std::vector<MSG_PANEL_ITEM>& aList ) const
1369{
1370 aList.emplace_back( _( "Net" ), UnescapeString( GetNetname() ) );
1371
1372 aList.emplace_back( _( "Resolved Netclass" ),
1373 UnescapeString( GetEffectiveNetClass()->GetName() ) );
1374
1375#if 0 // Enable for debugging
1376 if( GetBoard() )
1377 aList.emplace_back( _( "NetCode" ), wxString::Format( wxT( "%d" ), GetNetCode() ) );
1378
1379 aList.emplace_back( wxT( "Flags" ), wxString::Format( wxT( "0x%08X" ), m_flags ) );
1380
1381 aList.emplace_back( wxT( "Start pos" ), wxString::Format( wxT( "%d %d" ),
1382 m_Start.x,
1383 m_Start.y ) );
1384 aList.emplace_back( wxT( "End pos" ), wxString::Format( wxT( "%d %d" ),
1385 m_End.x,
1386 m_End.y ) );
1387#endif
1388
1389 if( aFrame->GetName() == PCB_EDIT_FRAME_NAME && IsLocked() )
1390 aList.emplace_back( _( "Status" ), _( "Locked" ) );
1391}
1392
1393
1395{
1396 const BOARD* board = GetBoard();
1397 PCB_LAYER_ID top_layer;
1398 PCB_LAYER_ID bottom_layer;
1399
1400 LayerPair( &top_layer, &bottom_layer );
1401
1402 return board->GetLayerName( top_layer ) + wxT( " - " ) + board->GetLayerName( bottom_layer );
1403}
1404
1405
1406bool PCB_TRACK::HitTest( const VECTOR2I& aPosition, int aAccuracy ) const
1407{
1408 return TestSegmentHit( aPosition, m_Start, m_End, aAccuracy + ( m_Width / 2 ) );
1409}
1410
1411
1412bool PCB_ARC::HitTest( const VECTOR2I& aPosition, int aAccuracy ) const
1413{
1414 int max_dist = aAccuracy + ( m_Width / 2 );
1415
1416 // Short-circuit common cases where the arc is connected to a track or via at an endpoint
1417 if( EuclideanNorm( GetStart() - aPosition ) <= max_dist ||
1418 EuclideanNorm( GetEnd() - aPosition ) <= max_dist )
1419 {
1420 return true;
1421 }
1422
1423 VECTOR2I center = GetPosition();
1424 VECTOR2I relpos = aPosition - center;
1425 double dist = EuclideanNorm( relpos );
1426 double radius = GetRadius();
1427
1428 if( std::abs( dist - radius ) > max_dist )
1429 return false;
1430
1431 EDA_ANGLE arc_angle = GetAngle();
1432 EDA_ANGLE arc_angle_start = GetArcAngleStart(); // Always 0.0 ... 360 deg
1433 EDA_ANGLE arc_hittest( relpos );
1434
1435 // Calculate relative angle between the starting point of the arc, and the test point
1436 arc_hittest -= arc_angle_start;
1437
1438 // Normalise arc_hittest between 0 ... 360 deg
1439 arc_hittest.Normalize();
1440
1441 if( arc_angle < ANGLE_0 )
1442 return arc_hittest >= ANGLE_360 + arc_angle;
1443
1444 return arc_hittest <= arc_angle;
1445}
1446
1447
1448bool PCB_VIA::HitTest( const VECTOR2I& aPosition, int aAccuracy ) const
1449{
1450 int max_dist = aAccuracy + ( m_Width / 2 );
1451
1452 // rel_pos is aPosition relative to m_Start (or the center of the via)
1453 VECTOR2I rel_pos = aPosition - m_Start;
1454 double dist = (double) rel_pos.x * rel_pos.x + (double) rel_pos.y * rel_pos.y;
1455 return dist <= (double) max_dist * max_dist;
1456}
1457
1458
1459bool PCB_TRACK::HitTest( const BOX2I& aRect, bool aContained, int aAccuracy ) const
1460{
1461 BOX2I arect = aRect;
1462 arect.Inflate( aAccuracy );
1463
1464 if( aContained )
1465 return arect.Contains( GetStart() ) && arect.Contains( GetEnd() );
1466 else
1467 return arect.Intersects( GetStart(), GetEnd() );
1468}
1469
1470
1471bool PCB_ARC::HitTest( const BOX2I& aRect, bool aContained, int aAccuracy ) const
1472{
1473 BOX2I arect = aRect;
1474 arect.Inflate( aAccuracy );
1475
1476 BOX2I box( GetStart() );
1477 box.Merge( GetMid() );
1478 box.Merge( GetEnd() );
1479
1480 box.Inflate( GetWidth() / 2 );
1481
1482 if( aContained )
1483 return arect.Contains( box );
1484 else
1485 return arect.Intersects( box );
1486}
1487
1488
1489bool PCB_VIA::HitTest( const BOX2I& aRect, bool aContained, int aAccuracy ) const
1490{
1491 BOX2I arect = aRect;
1492 arect.Inflate( aAccuracy );
1493
1494 BOX2I box( GetStart() );
1495 box.Inflate( GetWidth() / 2 );
1496
1497 if( aContained )
1498 return arect.Contains( box );
1499 else
1500 return arect.IntersectsCircle( GetStart(), GetWidth() / 2 );
1501}
1502
1503
1504wxString PCB_TRACK::GetItemDescription( UNITS_PROVIDER* aUnitsProvider ) const
1505{
1506 return wxString::Format( Type() == PCB_ARC_T ? _("Track (arc) %s on %s, length %s" )
1507 : _("Track %s on %s, length %s" ),
1508 GetNetnameMsg(),
1509 GetLayerName(),
1510 aUnitsProvider->MessageTextFromValue( GetLength() ) );
1511}
1512
1513
1515{
1516 return BITMAPS::add_tracks;
1517}
1518
1520{
1521 assert( aImage->Type() == PCB_TRACE_T );
1522
1523 std::swap( *((PCB_TRACK*) this), *((PCB_TRACK*) aImage) );
1524}
1525
1527{
1528 assert( aImage->Type() == PCB_ARC_T );
1529
1530 std::swap( *this, *static_cast<PCB_ARC*>( aImage ) );
1531}
1532
1534{
1535 assert( aImage->Type() == PCB_VIA_T );
1536
1537 std::swap( *((PCB_VIA*) this), *((PCB_VIA*) aImage) );
1538}
1539
1540
1542{
1544 return center;
1545}
1546
1547
1549{
1550 auto center = CalcArcCenter( m_Start, m_Mid , m_End );
1551 return GetLineLength( center, m_Start );
1552}
1553
1554
1556{
1557 VECTOR2I center = GetPosition();
1558 EDA_ANGLE angle1 = EDA_ANGLE( m_Mid - center ) - EDA_ANGLE( m_Start - center );
1559 EDA_ANGLE angle2 = EDA_ANGLE( m_End - center ) - EDA_ANGLE( m_Mid - center );
1560
1561 return angle1.Normalize180() + angle2.Normalize180();
1562}
1563
1564
1566{
1567 VECTOR2I pos( GetPosition() );
1568 VECTOR2D dir( (double) m_Start.x - pos.x, (double) m_Start.y - pos.y );
1569
1570 EDA_ANGLE angleStart( dir );
1571 return angleStart.Normalize();
1572}
1573
1574
1575// Note: used in python tests. Ignore CLion's claim that it's unused....
1577{
1578 VECTOR2I pos( GetPosition() );
1579 VECTOR2D dir( (double) m_End.x - pos.x, (double) m_End.y - pos.y );
1580
1581 EDA_ANGLE angleEnd( dir );
1582 return angleEnd.Normalize();
1583}
1584
1585bool PCB_ARC::IsDegenerated( int aThreshold ) const
1586{
1587 // Too small arcs cannot be really handled: arc center (and arc radius)
1588 // cannot be safely computed if the distance between mid and end points
1589 // is too small (a few internal units)
1590
1591 // len of both segments must be < aThreshold to be a very small degenerated arc
1592 return ( GetMid() - GetStart() ).EuclideanNorm() < aThreshold
1593 && ( GetMid() - GetEnd() ).EuclideanNorm() < aThreshold;
1594}
1595
1596
1598{
1599 if( a->GetNetCode() != b->GetNetCode() )
1600 return a->GetNetCode() < b->GetNetCode();
1601
1602 if( a->GetLayer() != b->GetLayer() )
1603 return a->GetLayer() < b->GetLayer();
1604
1605 if( a->Type() != b->Type() )
1606 return a->Type() < b->Type();
1607
1608 if( a->m_Uuid != b->m_Uuid )
1609 return a->m_Uuid < b->m_Uuid;
1610
1611 return a < b;
1612}
1613
1614
1615std::shared_ptr<SHAPE> PCB_TRACK::GetEffectiveShape( PCB_LAYER_ID aLayer, FLASHING aFlash ) const
1616{
1617 return std::make_shared<SHAPE_SEGMENT>( m_Start, m_End, m_Width );
1618}
1619
1620
1621std::shared_ptr<SHAPE> PCB_VIA::GetEffectiveShape( PCB_LAYER_ID aLayer, FLASHING aFlash ) const
1622{
1623 if( aFlash == FLASHING::ALWAYS_FLASHED
1624 || ( aFlash == FLASHING::DEFAULT && FlashLayer( aLayer ) ) )
1625 {
1626 return std::make_shared<SHAPE_CIRCLE>( m_Start, m_Width / 2 );
1627 }
1628 else
1629 {
1630 return std::make_shared<SHAPE_CIRCLE>( m_Start, GetDrillValue() / 2 );
1631 }
1632}
1633
1634
1635std::shared_ptr<SHAPE> PCB_ARC::GetEffectiveShape( PCB_LAYER_ID aLayer, FLASHING aFlash ) const
1636{
1637 return std::make_shared<SHAPE_ARC>( GetStart(), GetMid(), GetEnd(), GetWidth() );
1638}
1639
1640
1642 int aClearance, int aError, ERROR_LOC aErrorLoc,
1643 bool ignoreLineWidth ) const
1644{
1645 wxASSERT_MSG( !ignoreLineWidth, wxT( "IgnoreLineWidth has no meaning for tracks." ) );
1646
1647
1648 switch( Type() )
1649 {
1650 case PCB_VIA_T:
1651 {
1652 int radius = ( m_Width / 2 ) + aClearance;
1653 TransformCircleToPolygon( aBuffer, m_Start, radius, aError, aErrorLoc );
1654 break;
1655 }
1656
1657 case PCB_ARC_T:
1658 {
1659 const PCB_ARC* arc = static_cast<const PCB_ARC*>( this );
1660 int width = m_Width + ( 2 * aClearance );
1661
1662 TransformArcToPolygon( aBuffer, arc->GetStart(), arc->GetMid(), arc->GetEnd(), width,
1663 aError, aErrorLoc );
1664 break;
1665 }
1666
1667 default:
1668 {
1669 int width = m_Width + ( 2 * aClearance );
1670
1671 TransformOvalToPolygon( aBuffer, m_Start, m_End, width, aError, aErrorLoc );
1672 break;
1673 }
1674 }
1675}
1676
1677
1678static struct TRACK_VIA_DESC
1679{
1681 {
1683 .Undefined( VIATYPE::NOT_DEFINED )
1684 .Map( VIATYPE::THROUGH, _HKI( "Through" ) )
1685 .Map( VIATYPE::BLIND_BURIED, _HKI( "Blind/buried" ) )
1686 .Map( VIATYPE::MICROVIA, _HKI( "Micro" ) );
1687
1689
1690 if( layerEnum.Choices().GetCount() == 0 )
1691 {
1692 layerEnum.Undefined( UNDEFINED_LAYER );
1693
1694 for( LSEQ seq = LSET::AllLayersMask().Seq(); seq; ++seq )
1695 layerEnum.Map( *seq, LSET::Name( *seq ) );
1696 }
1697
1699
1700 // Track
1703
1704 propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "Width" ),
1705 &PCB_TRACK::SetWidth, &PCB_TRACK::GetWidth, PROPERTY_DISPLAY::PT_SIZE ) );
1706 propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Position X" ),
1708 &PCB_TRACK::SetX, &PCB_TRACK::GetX, PROPERTY_DISPLAY::PT_COORD,
1710 propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Position Y" ),
1712 &PCB_TRACK::SetY, &PCB_TRACK::GetY, PROPERTY_DISPLAY::PT_COORD,
1714 propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "End X" ),
1715 &PCB_TRACK::SetEndX, &PCB_TRACK::GetEndX, PROPERTY_DISPLAY::PT_COORD,
1717 propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "End Y" ),
1718 &PCB_TRACK::SetEndY, &PCB_TRACK::GetEndY, PROPERTY_DISPLAY::PT_COORD,
1720
1721 // Arc
1724
1725 // Via
1728
1729 // TODO test drill, use getdrillvalue?
1730 const wxString groupVia = _HKI( "Via Properties" );
1731
1732 propMgr.Mask( TYPE_HASH( PCB_VIA ), TYPE_HASH( BOARD_CONNECTED_ITEM ), _HKI( "Layer" ) );
1733
1734 propMgr.ReplaceProperty( TYPE_HASH( PCB_TRACK ), _HKI( "Width" ),
1735 new PROPERTY<PCB_VIA, int, PCB_TRACK>( _HKI( "Diameter" ),
1736 &PCB_VIA::SetWidth, &PCB_VIA::GetWidth, PROPERTY_DISPLAY::PT_SIZE ) );
1737 propMgr.AddProperty( new PROPERTY<PCB_VIA, int>( _HKI( "Hole" ),
1738 &PCB_VIA::SetDrill, &PCB_VIA::GetDrillValue, PROPERTY_DISPLAY::PT_SIZE ), groupVia );
1739 propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Layer" ),
1741 &PCB_VIA::SetLayer, &PCB_VIA::GetLayer ), groupVia );
1742 propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, PCB_LAYER_ID>( _HKI( "Layer Bottom" ),
1744 propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, VIATYPE>( _HKI( "Via Type" ),
1746 }
1748
constexpr EDA_IU_SCALE pcbIUScale
Definition: base_units.h:108
BITMAPS
A list of all bitmap identifiers.
Definition: bitmaps_list.h:33
@ ZLO_NONE
Definition: board_item.h:65
@ ZLO_FORCE_FLASHED
Definition: board_item.h:66
BOX2I BOX2ISafe(const BOX2D &aInput)
Definition: box2.h:893
A base class derived from BOARD_ITEM for items that can be connected and have a net,...
wxString GetNetnameMsg() const
virtual NETCLASS * GetEffectiveNetClass() const
Return the NETCLASS for this item.
bool SetNetCode(int aNetCode, bool aNoAssert)
Set net using a net code.
virtual int GetOwnClearance(PCB_LAYER_ID aLayer, wxString *aSource=nullptr) const
Return an item's "own" clearance in internal units.
wxString GetUnescapedShortNetname() const
Container for design settings for a BOARD object.
std::shared_ptr< DRC_ENGINE > m_DRCEngine
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition: board_item.h:77
virtual PCB_LAYER_ID GetLayer() const
Return the primary layer this item is on.
Definition: board_item.h:226
int GetY() const
Definition: board_item.h:101
virtual void SetLocked(bool aLocked)
Definition: board_item.h:300
PCB_LAYER_ID m_layer
Definition: board_item.h:388
int GetX() const
Definition: board_item.h:95
void SetX(int aX)
Definition: board_item.h:117
void SetY(int aY)
Definition: board_item.h:123
virtual void SetLayer(PCB_LAYER_ID aLayer)
Set the layer this item is on.
Definition: board_item.h:260
virtual const BOARD * GetBoard() const
Return the BOARD in which this BOARD_ITEM resides, or NULL if none.
Definition: board_item.cpp:46
virtual bool IsLocked() const
Definition: board_item.cpp:74
virtual wxString layerMaskDescribe() const
Return a string (to be shown to the user) describing a layer mask.
Definition: board_item.cpp:115
wxString GetLayerName() const
Return the name of the PCB layer on which the item resides.
Definition: board_item.cpp:103
Information pertinent to a Pcbnew printed circuit board.
Definition: board.h:281
int GetCopperLayerCount() const
Definition: board.cpp:656
const wxString GetLayerName(PCB_LAYER_ID aLayer) const
Return the name of a aLayer.
Definition: board.cpp:567
std::tuple< int, double, double > GetTrackLength(const PCB_TRACK &aTrack) const
Return data on the length and number of track segments connected to a given track.
Definition: board.cpp:2177
BOARD_DESIGN_SETTINGS & GetDesignSettings() const
Definition: board.cpp:797
std::shared_ptr< CONNECTIVITY_DATA > GetConnectivity() const
Return a list of missing connections between components/tracks.
Definition: board.h:459
bool Intersects(const BOX2< Vec > &aRect) const
Definition: box2.h:294
coord_type GetTop() const
Definition: box2.h:219
bool IntersectsCircle(const Vec &aCenter, const int aRadius) const
Definition: box2.h:487
bool Contains(const Vec &aPoint) const
Definition: box2.h:158
BOX2< Vec > & Inflate(coord_type dx, coord_type dy)
Inflates the rectangle horizontally by dx and vertically by dy.
Definition: box2.h:541
coord_type GetRight() const
Definition: box2.h:207
coord_type GetLeft() const
Definition: box2.h:218
coord_type GetBottom() const
Definition: box2.h:212
BOX2< Vec > & Merge(const BOX2< Vec > &aRect)
Modify the position and size of the rectangle in order to contain aRect.
Definition: box2.h:623
wxString GetName() const
Definition: drc_rule.h:149
MINOPTMAX< int > & Value()
Definition: drc_rule.h:142
EDA_ANGLE Normalize()
Definition: eda_angle.h:255
EDA_ANGLE Normalize180()
Definition: eda_angle.h:294
The base class for create windows for drawing purpose.
A base class for most all the KiCad significant classes used in schematics and boards.
Definition: eda_item.h:88
EDA_ITEM & operator=(const EDA_ITEM &aItem)
Assign the members of aItem to another object.
Definition: eda_item.cpp:258
const KIID m_Uuid
Definition: eda_item.h:485
KICAD_T Type() const
Returns the type of object.
Definition: eda_item.h:100
EDA_ITEM_FLAGS m_flags
Definition: eda_item.h:490
ENUM_MAP & Map(T aValue, const wxString &aName)
Definition: property.h:669
static ENUM_MAP< T > & Instance()
Definition: property.h:663
ENUM_MAP & Undefined(T aValue)
Definition: property.h:676
wxPGChoices & Choices()
Definition: property.h:712
Contains methods for drawing PCB-specific items.
Definition: pcb_painter.h:164
virtual PCB_RENDER_SETTINGS * GetSettings() override
Return a pointer to current settings that are going to be used when drawing items.
Definition: pcb_painter.h:169
PCB specific render settings.
Definition: pcb_painter.h:77
PCB_LAYER_ID GetPrimaryHighContrastLayer() const
Return the board layer which is in high-contrast mode.
bool GetHighContrast() const
Hold a (potentially large) number of VIEW_ITEMs and renders them on a graphics device provided by the...
Definition: view.h:68
BOX2D GetViewport() const
Return the current viewport visible area rectangle.
Definition: view.cpp:512
bool IsLayerVisible(int aLayer) const
Return information about visibility of a particular layer.
Definition: view.h:412
PAINTER * GetPainter() const
Return the painter object used by the view for drawing #VIEW_ITEMS.
Definition: view.h:215
Definition: kiid.h:49
std::string AsStdString() const
Definition: kiid.cpp:263
LSEQ is a sequence (and therefore also a set) of PCB_LAYER_IDs.
Definition: layer_ids.h:520
LSET is a set of PCB_LAYER_IDs.
Definition: layer_ids.h:574
static LSET AllLayersMask()
Definition: lset.cpp:898
LSEQ Seq(const PCB_LAYER_ID *aWishListSequence, unsigned aCount) const
Return an LSEQ from the union of this LSET and a desired sequence.
Definition: lset.cpp:418
static LSET AllCuMask(int aCuLayerCount=MAX_CU_LAYERS)
Return a mask holding the requested number of Cu PCB_LAYER_IDs.
Definition: lset.cpp:863
static LSET PhysicalLayersMask()
Return a mask holding all layers which are physically realized.
Definition: lset.cpp:960
static const wxChar * Name(PCB_LAYER_ID aLayerId)
Return the fixed name association with aLayerId.
Definition: lset.cpp:89
static LSET FrontTechMask()
Return a mask holding all technical layers (no CU layer) on front side.
Definition: lset.cpp:917
static LSET BackTechMask()
Return a mask holding all technical layers (no CU layer) on back side.
Definition: lset.cpp:905
T Min() const
Definition: minoptmax.h:33
bool HasMin() const
Definition: minoptmax.h:37
A collection of nets and the parameters used to route or test these nets.
Definition: netclass.h:44
int GetViaDrill() const
Definition: netclass.h:81
int GetuViaDrill() const
Definition: netclass.h:89
static const int UNCONNECTED
Constant that holds the "unconnected net" number (typically 0) all items "connected" to this net are ...
Definition: netinfo.h:375
bool operator==(const BOARD_ITEM &aOther) const override
Definition: pcb_track.cpp:204
virtual VECTOR2I GetPosition() const override
Definition: pcb_track.cpp:1541
bool IsDegenerated(int aThreshold=5) const
Definition: pcb_track.cpp:1585
virtual void swapData(BOARD_ITEM *aImage) override
Definition: pcb_track.cpp:1526
bool IsCCW() const
Definition: pcb_track.cpp:783
void Serialize(google::protobuf::Any &aContainer) const override
Serializes this object to the given Any message.
Definition: pcb_track.cpp:342
EDA_ITEM * Clone() const override
Create a duplicate of this item with linked list members set to NULL.
Definition: pcb_track.cpp:79
EDA_ANGLE GetArcAngleStart() const
Definition: pcb_track.cpp:1565
virtual bool HitTest(const VECTOR2I &aPosition, int aAccuracy=0) const override
Test if aPosition is inside or on the boundary of this item.
Definition: pcb_track.cpp:1412
EDA_ANGLE GetArcAngleEnd() const
Definition: pcb_track.cpp:1576
bool Deserialize(const google::protobuf::Any &aContainer) override
Deserializes the given protobuf message into this object.
Definition: pcb_track.cpp:364
void SetMid(const VECTOR2I &aMid)
Definition: pcb_track.h:314
double GetRadius() const
Definition: pcb_track.cpp:1548
EDA_ANGLE GetAngle() const
Definition: pcb_track.cpp:1555
const VECTOR2I & GetMid() const
Definition: pcb_track.h:315
PCB_ARC(BOARD_ITEM *aParent)
Definition: pcb_track.h:290
void Flip(const VECTOR2I &aCentre, bool aFlipLeftRight) override
Flip this object, i.e.
Definition: pcb_track.cpp:763
double Similarity(const BOARD_ITEM &aOther) const override
Return a measure of how likely the other object is to represent the same object.
Definition: pcb_track.cpp:216
VECTOR2I m_Mid
Arc mid point, halfway between start and end.
Definition: pcb_track.h:375
void Rotate(const VECTOR2I &aRotCentre, const EDA_ANGLE &aAngle) override
Rotate this object.
Definition: pcb_track.cpp:705
std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const override
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
Definition: pcb_track.cpp:1635
void Mirror(const VECTOR2I &aCentre, bool aMirrorAroundXAxis) override
Definition: pcb_track.cpp:728
double m_CachedScale
Last zoom scale used to draw this track's net.
Definition: pcb_track.h:283
double m_CachedLOD
Last LOD used to draw this track's net.
Definition: pcb_track.h:282
void Rotate(const VECTOR2I &aRotCentre, const EDA_ANGLE &aAngle) override
Rotate this object.
Definition: pcb_track.cpp:698
virtual void ViewGetLayers(int aLayers[], int &aCount) const override
Return the all the layers within the VIEW the object is painted on.
Definition: pcb_track.cpp:1071
void Serialize(google::protobuf::Any &aContainer) const override
Serializes this object to the given Any message.
Definition: pcb_track.cpp:303
void SetEndY(int aY)
Definition: pcb_track.h:116
void SetWidth(int aWidth)
Definition: pcb_track.h:106
double ViewGetLOD(int aLayer, KIGFX::VIEW *aView) const override
Return the level of detail (LOD) of the item.
Definition: pcb_track.cpp:1083
virtual double GetLength() const
Get the length of the track using the hypotenuse calculation.
Definition: pcb_track.cpp:692
int GetWidth() const
Definition: pcb_track.h:107
virtual void swapData(BOARD_ITEM *aImage) override
Definition: pcb_track.cpp:1519
void SetEnd(const VECTOR2I &aEnd)
Definition: pcb_track.h:109
void SetStart(const VECTOR2I &aStart)
Definition: pcb_track.h:112
wxString GetItemDescription(UNITS_PROVIDER *aUnitsProvider) const override
Return a user-visible description string of this item.
Definition: pcb_track.cpp:1504
const BOX2I ViewBBox() const override
Return the bounding box of the item covering all its layers.
Definition: pcb_track.cpp:1148
int GetEndX() const
Definition: pcb_track.h:118
bool Deserialize(const google::protobuf::Any &aContainer) override
Deserializes the given protobuf message into this object.
Definition: pcb_track.cpp:323
INSPECT_RESULT Visit(INSPECTOR inspector, void *testData, const std::vector< KICAD_T > &aScanTypes) override
May be re-implemented for each derived class in order to handle all the types given by its member dat...
Definition: pcb_track.cpp:818
bool ApproxCollinear(const PCB_TRACK &aTrack)
Definition: pcb_track.cpp:507
VECTOR2I m_End
Line end point.
Definition: pcb_track.h:280
void GetMsgPanelInfo(EDA_DRAW_FRAME *aFrame, std::vector< MSG_PANEL_ITEM > &aList) override
Populate aList of MSG_PANEL_ITEM objects with it's internal state for display purposes.
Definition: pcb_track.cpp:1272
virtual EDA_ITEM * Clone() const override
Create a duplicate of this item with linked list members set to NULL.
Definition: pcb_track.cpp:64
const BOX2I GetBoundingBox() const override
Return the orthogonal bounding box of this object for display purposes.
Definition: pcb_track.cpp:647
void TransformShapeToPolygon(SHAPE_POLY_SET &aBuffer, PCB_LAYER_ID aLayer, int aClearance, int aError, ERROR_LOC aErrorLoc, bool ignoreLineWidth=false) const override
Convert the track shape to a closed polygon.
Definition: pcb_track.cpp:1641
const VECTOR2I & GetStart() const
Definition: pcb_track.h:113
virtual bool operator==(const BOARD_ITEM &aOther) const override
Definition: pcb_track.cpp:159
VECTOR2I m_Start
Line start point.
Definition: pcb_track.h:279
int GetEndY() const
Definition: pcb_track.h:119
wxString GetFriendlyName() const override
Definition: pcb_track.cpp:1260
BITMAPS GetMenuImage() const override
Return a pointer to an image to be used in menus.
Definition: pcb_track.cpp:1514
void Flip(const VECTOR2I &aCentre, bool aFlipLeftRight) override
Flip this object, i.e.
Definition: pcb_track.cpp:745
bool HitTest(const VECTOR2I &aPosition, int aAccuracy=0) const override
Test if aPosition is inside or on the boundary of this item.
Definition: pcb_track.cpp:1406
virtual double Similarity(const BOARD_ITEM &aOther) const override
Return a measure of how likely the other object is to represent the same object.
Definition: pcb_track.cpp:179
std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const override
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
Definition: pcb_track.cpp:1615
const VECTOR2I & GetEnd() const
Definition: pcb_track.h:110
PCB_TRACK(BOARD_ITEM *aParent, KICAD_T idtype=PCB_TRACE_T)
Definition: pcb_track.cpp:55
int m_Width
Thickness of track, or via diameter.
Definition: pcb_track.h:278
virtual MINOPTMAX< int > GetWidthConstraint(wxString *aSource=nullptr) const
Definition: pcb_track.cpp:515
void SetEndX(int aX)
Definition: pcb_track.h:115
virtual void Mirror(const VECTOR2I &aCentre, bool aMirrorAroundXAxis)
Definition: pcb_track.cpp:713
EDA_ITEM_FLAGS IsPointOnEnds(const VECTOR2I &point, int min_dist=0) const
Return STARTPOINT if point if near (dist = min_dist) start point, ENDPOINT if point if near (dist = m...
Definition: pcb_track.cpp:615
void GetMsgPanelInfoBase_Common(EDA_DRAW_FRAME *aFrame, std::vector< MSG_PANEL_ITEM > &aList) const
Definition: pcb_track.cpp:1367
bool IsTented() const override
Definition: pcb_track.cpp:840
PCB_LAYER_ID BottomLayer() const
Definition: pcb_track.cpp:979
BITMAPS GetMenuImage() const override
Return a pointer to an image to be used in menus.
Definition: pcb_track.cpp:153
VECTOR2I GetPosition() const override
Definition: pcb_track.h:465
std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const override
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
Definition: pcb_track.cpp:1621
bool Deserialize(const google::protobuf::Any &aContainer) override
Deserializes the given protobuf message into this object.
Definition: pcb_track.cpp:435
bool FlashLayer(int aLayer) const
Check to see whether the via should have a pad on the specific layer.
Definition: pcb_track.cpp:1010
void SetDrillDefault()
Set the drill value for vias to the default value UNDEFINED_DRILL_DIAMETER.
Definition: pcb_track.h:569
PCB_LAYER_ID m_bottomLayer
The bottom layer of the via (the top layer is in m_layer)
Definition: pcb_track.h:615
bool m_isFree
"Free" vias don't get their nets auto-updated
Definition: pcb_track.h:623
bool HitTest(const VECTOR2I &aPosition, int aAccuracy=0) const override
Test if aPosition is inside or on the boundary of this item.
Definition: pcb_track.cpp:1448
virtual void SetLayerSet(LSET aLayers) override
Note SetLayerSet() initialize the first and last copper layers connected by the via.
Definition: pcb_track.cpp:909
void SetBottomLayer(PCB_LAYER_ID aLayer)
Definition: pcb_track.cpp:945
std::array< ZONE_LAYER_OVERRIDE, MAX_CU_LAYERS > m_zoneLayerOverrides
Definition: pcb_track.h:626
int GetSolderMaskExpansion() const
Definition: pcb_track.cpp:849
void SetDrill(int aDrill)
Set the drill value for vias.
Definition: pcb_track.h:550
MINOPTMAX< int > GetDrillConstraint(wxString *aSource=nullptr) const
Definition: pcb_track.cpp:551
bool operator==(const BOARD_ITEM &aOther) const override
Definition: pcb_track.cpp:244
void GetMsgPanelInfo(EDA_DRAW_FRAME *aFrame, std::vector< MSG_PANEL_ITEM > &aList) override
Populate aList of MSG_PANEL_ITEM objects with it's internal state for display purposes.
Definition: pcb_track.cpp:1332
EDA_ITEM * Clone() const override
Create a duplicate of this item with linked list members set to NULL.
Definition: pcb_track.cpp:132
int m_drill
for vias: via drill (- 1 for default value)
Definition: pcb_track.h:619
double ViewGetLOD(int aLayer, KIGFX::VIEW *aView) const override
Return the level of detail (LOD) of the item.
Definition: pcb_track.cpp:1191
void SetTopLayer(PCB_LAYER_ID aLayer)
Definition: pcb_track.cpp:939
std::shared_ptr< SHAPE_SEGMENT > GetEffectiveHoleShape() const override
Definition: pcb_track.cpp:834
void SetLayerPair(PCB_LAYER_ID aTopLayer, PCB_LAYER_ID aBottomLayer)
For a via m_layer contains the top layer, the other layer is in m_bottomLayer/.
Definition: pcb_track.cpp:930
double Similarity(const BOARD_ITEM &aOther) const override
Return a measure of how likely the other object is to represent the same object.
Definition: pcb_track.cpp:260
bool m_removeUnconnectedLayer
Remove annular rings on unconnected layers.
Definition: pcb_track.h:621
void GetOutermostConnectedLayers(PCB_LAYER_ID *aTopmost, PCB_LAYER_ID *aBottommost) const
Return the top-most and bottom-most connected layers.
Definition: pcb_track.cpp:1041
void ViewGetLayers(int aLayers[], int &aCount) const override
Return the all the layers within the VIEW the object is painted on.
Definition: pcb_track.cpp:1161
void SanitizeLayers()
Check so that the layers are correct depending on the type of via, and so that the top actually is on...
Definition: pcb_track.cpp:985
PCB_VIA & operator=(const PCB_VIA &aOther)
Definition: pcb_track.cpp:111
void swapData(BOARD_ITEM *aImage) override
Definition: pcb_track.cpp:1533
void Serialize(google::protobuf::Any &aContainer) const override
Serializes this object to the given Any message.
Definition: pcb_track.cpp:384
PCB_VIA(BOARD_ITEM *aParent)
Definition: pcb_track.cpp:85
wxString layerMaskDescribe() const override
Return a string (to be shown to the user) describing a layer mask.
Definition: pcb_track.cpp:1394
void SetViaType(VIATYPE aViaType)
Definition: pcb_track.h:411
int GetMinAnnulus(PCB_LAYER_ID aLayer, wxString *aSource) const
Definition: pcb_track.cpp:569
bool IsOnLayer(PCB_LAYER_ID aLayer) const override
Test to see if this object is on the given layer.
Definition: pcb_track.cpp:858
PCB_LAYER_ID TopLayer() const
Definition: pcb_track.cpp:973
wxString GetItemDescription(UNITS_PROVIDER *aUnitsProvider) const override
Return a user-visible description string of this item.
Definition: pcb_track.cpp:138
VIATYPE m_viaType
through, blind/buried or micro
Definition: pcb_track.h:617
bool m_keepStartEndLayer
Keep the start and end annular rings.
Definition: pcb_track.h:622
int GetDrillValue() const
Calculate the drill value for vias (m_drill if > 0, or default drill value for the board).
Definition: pcb_track.cpp:600
VIATYPE GetViaType() const
Definition: pcb_track.h:410
MINOPTMAX< int > GetWidthConstraint(wxString *aSource=nullptr) const override
Definition: pcb_track.cpp:533
virtual LSET GetLayerSet() const override
Return a std::bitset of all layers on which the item physically resides.
Definition: pcb_track.cpp:880
void LayerPair(PCB_LAYER_ID *top_layer, PCB_LAYER_ID *bottom_layer) const
Return the 2 layers used by the via (the via actually uses all layers between these 2 layers)
Definition: pcb_track.cpp:951
void Flip(const VECTOR2I &aCentre, bool aFlipLeftRight) override
Flip this object, i.e.
Definition: pcb_track.cpp:792
Provide class metadata.Helper macro to map type hashes to names.
Definition: property_mgr.h:85
void InheritsAfter(TYPE_ID aDerived, TYPE_ID aBase)
Declare an inheritance relationship between types.
void Mask(TYPE_ID aDerived, TYPE_ID aBase, const wxString &aName)
Sets a base class property as masked in a derived class.
static PROPERTY_MANAGER & Instance()
Definition: property_mgr.h:87
PROPERTY_BASE & AddProperty(PROPERTY_BASE *aProperty, const wxString &aGroup=wxEmptyString)
Register a property.
PROPERTY_BASE & ReplaceProperty(size_t aBase, const wxString &aName, PROPERTY_BASE *aNew, const wxString &aGroup=wxEmptyString)
Replace an existing property for a specific type.
Definition: seg.h:42
bool ApproxCollinear(const SEG &aSeg, int aDistanceThreshold=1) const
Definition: seg.cpp:390
const VECTOR2I & GetArcMid() const
Definition: shape_arc.h:115
const VECTOR2I & GetP1() const
Definition: shape_arc.h:114
const VECTOR2I & GetP0() const
Definition: shape_arc.h:113
Represent a set of closed polygons.
wxString MessageTextFromMinOptMax(const MINOPTMAX< int > &aValue) const
wxString MessageTextFromValue(double aValue, bool aAddUnitLabel=true, EDA_DATA_TYPE aType=EDA_DATA_TYPE::DISTANCE) const
A lower-precision version of StringFromValue().
T EuclideanNorm() const
Compute the Euclidean norm of the vector, which is defined as sqrt(x ** 2 + y ** 2).
Definition: vector2d.h:265
extended_type Cross(const VECTOR2< T > &aVector) const
Compute cross product of self with aVector.
Definition: vector2d.h:457
void TransformCircleToPolygon(SHAPE_LINE_CHAIN &aBuffer, const VECTOR2I &aCenter, int aRadius, int aError, ERROR_LOC aErrorLoc, int aMinSegCount=0)
Convert a circle to a polygon, using multiple straight lines.
void TransformArcToPolygon(SHAPE_POLY_SET &aBuffer, const VECTOR2I &aStart, const VECTOR2I &aMid, const VECTOR2I &aEnd, int aWidth, int aError, ERROR_LOC aErrorLoc)
Convert arc to multiple straight segments.
void TransformOvalToPolygon(SHAPE_POLY_SET &aBuffer, const VECTOR2I &aStart, const VECTOR2I &aEnd, int aWidth, int aError, ERROR_LOC aErrorLoc, int aMinSegCount=0)
Convert a oblong shape to a polygon, using multiple segments.
#define _HKI(x)
@ ANNULAR_WIDTH_CONSTRAINT
Definition: drc_rule.h:57
@ VIA_DIAMETER_CONSTRAINT
Definition: drc_rule.h:63
@ TRACK_WIDTH_CONSTRAINT
Definition: drc_rule.h:56
@ HOLE_SIZE_CONSTRAINT
Definition: drc_rule.h:51
#define _(s)
static constexpr EDA_ANGLE ANGLE_0
Definition: eda_angle.h:435
static constexpr EDA_ANGLE ANGLE_360
Definition: eda_angle.h:441
#define PCB_EDIT_FRAME_NAME
INSPECT_RESULT
Definition: eda_item.h:43
const INSPECTOR_FUNC & INSPECTOR
Definition: eda_item.h:81
#define ENDPOINT
ends. (Used to support dragging.)
std::uint32_t EDA_ITEM_FLAGS
#define STARTPOINT
When a line is selected, these flags indicate which.
static std::vector< KICAD_T > connectedTypes
ERROR_LOC
When approximating an arc or circle, should the error be placed on the outside or inside of the curve...
bool ClipLine(const BOX2I *aClipBox, int &x1, int &y1, int &x2, int &y2)
Test if any part of a line falls within the bounds of a rectangle.
@ LAYER_VIA_NETNAMES
Definition: layer_ids.h:170
constexpr PCB_LAYER_ID PCBNEW_LAYER_ID_START
Definition: layer_ids.h:140
FLASHING
Enum used during connectivity building to ensure we do not query connectivity while building the data...
Definition: layer_ids.h:149
int GetNetnameLayer(int aLayer)
Returns a netname layer corresponding to the given layer.
Definition: layer_ids.h:1021
bool IsCopperLayer(int aLayerId)
Tests whether a layer is a copper layer.
Definition: layer_ids.h:880
@ LAYER_LOCKED_ITEM_SHADOW
shadow layer for locked items
Definition: layer_ids.h:243
@ LAYER_VIA_HOLEWALLS
Definition: layer_ids.h:238
@ LAYER_GP_OVERLAY
general purpose overlay
Definition: layer_ids.h:222
@ LAYER_TRACKS
Definition: layer_ids.h:216
@ LAYER_VIA_HOLES
to draw via holes (pad holes do not use this layer)
Definition: layer_ids.h:219
@ LAYER_VIA_MICROVIA
to draw micro vias
Definition: layer_ids.h:198
@ LAYER_VIA_THROUGH
to draw usual through hole vias
Definition: layer_ids.h:200
@ LAYER_VIAS
Meta control for all vias opacity/visibility.
Definition: layer_ids.h:197
@ LAYER_VIA_BBLIND
to draw blind/buried vias
Definition: layer_ids.h:199
bool IsNetnameLayer(int aLayer)
Test whether a layer is a netname layer.
Definition: layer_ids.h:1044
bool IsHoleLayer(int aLayer)
Definition: layer_ids.h:919
PCB_LAYER_ID
A quick note on layer IDs:
Definition: layer_ids.h:60
@ B_Mask
Definition: layer_ids.h:106
@ B_Cu
Definition: layer_ids.h:95
@ F_Mask
Definition: layer_ids.h:107
@ UNDEFINED_LAYER
Definition: layer_ids.h:61
@ F_Cu
Definition: layer_ids.h:64
PCB_LAYER_ID ToLAYER_ID(int aLayer)
Definition: lset.cpp:1022
PCB_LAYER_ID FlipLayer(PCB_LAYER_ID aLayerId, int aCopperLayersCount)
Definition: lset.cpp:634
void MIRROR(T &aPoint, const T &aMirrorRef)
Updates aPoint with the mirror of aPoint relative to the aMirrorRef.
Definition: mirror.h:40
void PackLayerSet(google::protobuf::RepeatedField< int > &aOutput, const LSET &aLayerSet)
void PackVector2(kiapi::common::types::Vector2 &aOutput, const VECTOR2I aInput)
Definition: api_utils.cpp:69
EDA_ANGLE abs(const EDA_ANGLE &aAngle)
Definition: eda_angle.h:424
static struct TRACK_VIA_DESC _TRACK_VIA_DESC
VIATYPE
Definition: pcb_track.h:64
#define TYPE_HASH(x)
Definition: property.h:71
#define ENUM_TO_WXANY(type)
Macro to define read-only fields (no setter method available)
Definition: property.h:765
#define REGISTER_TYPE(x)
Definition: property_mgr.h:366
wxString UnescapeString(const wxString &aSource)
constexpr int mmToIU(double mm) const
Definition: base_units.h:88
bool operator()(const PCB_TRACK *aFirst, const PCB_TRACK *aSecond) const
Definition: pcb_track.cpp:1597
bool TestSegmentHit(const VECTOR2I &aRefPoint, const VECTOR2I &aStart, const VECTOR2I &aEnd, int aDist)
Test if aRefPoint is with aDistance on the line defined by aStart and aEnd.
Definition: trigo.cpp:174
void RotatePoint(int *pX, int *pY, const EDA_ANGLE &aAngle)
Calculate the new point of coord coord pX, pY, for a rotation center 0, 0.
Definition: trigo.cpp:228
const VECTOR2I CalcArcCenter(const VECTOR2I &aStart, const VECTOR2I &aMid, const VECTOR2I &aEnd)
Determine the center of an arc or circle given three points on its circumference.
Definition: trigo.cpp:520
double GetLineLength(const VECTOR2I &aPointA, const VECTOR2I &aPointB)
Return the length of a line segment defined by aPointA and aPointB.
Definition: trigo.h:194
double EuclideanNorm(const VECTOR2I &vector)
Definition: trigo.h:128
KICAD_T
The set of class identification values stored in EDA_ITEM::m_structType.
Definition: typeinfo.h:78
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
Definition: typeinfo.h:97
@ PCB_PAD_T
class PAD, a pad in a footprint
Definition: typeinfo.h:87
@ PCB_ARC_T
class PCB_ARC, an arc track segment on a copper layer
Definition: typeinfo.h:98
@ PCB_TRACE_T
class PCB_TRACK, a track segment (segment on a copper layer)
Definition: typeinfo.h:96
constexpr ret_type KiROUND(fp_type v)
Round a floating point number to an integer using "round halfway cases away from zero".
Definition: util.h:118
VECTOR2< long long int > VECTOR2L
Definition: vector2d.h:589
VECTOR2< int > VECTOR2I
Definition: vector2d.h:588