pcb_track.cpp

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/*
 * This program source code file is part of KiCad, a free EDA CAD application.
 *
 * Copyright (C) 2012 Jean-Pierre Charras, jp.charras at wanadoo.fr
 * Copyright (C) 2012 SoftPLC Corporation, Dick Hollenbeck <[email protected]>
 * Copyright (C) 2012 Wayne Stambaugh <[email protected]>
 * Copyright The KiCad Developers, see AUTHORS.txt for contributors.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <https://www.gnu.org/licenses/>.
 */
 
#include "pcb_track.h"
 
#include <pcb_base_frame.h>
#include <core/mirror.h>
#include <connectivity/connectivity_data.h>
#include <board.h>
#include <board_design_settings.h>
#include <convert_basic_shapes_to_polygon.h>
#include <base_units.h>
#include <layer_range.h>
#include <length_delay_calculation/length_delay_calculation.h>
#include <lset.h>
#include <cstdlib>
#include <map>
#include <set>
#include <string_utils.h>
#include <view/view.h>
#include <settings/color_settings.h>
#include <settings/settings_manager.h>
#include <geometry/geometry_utils.h>
#include <geometry/seg.h>
#include <geometry/shape_segment.h>
#include <geometry/shape_circle.h>
#include <geometry/shape_arc.h>
#include <drc/drc_engine.h>
#include <pcb_painter.h>
#include <trigo.h>
#include <properties/property_validators.h>
#include <properties/property.h>
#include <properties/property_mgr.h>
 
#include <google/protobuf/any.pb.h>
#include <api/api_enums.h>
#include <api/api_utils.h>
#include <api/api_pcb_utils.h>
#include <api/board/board_types.pb.h>
 
using KIGFX::PCB_PAINTER;
using KIGFX::PCB_RENDER_SETTINGS;
 
PCB_TRACK::PCB_TRACK( BOARD_ITEM* aParent, KICAD_T idtype ) :
    BOARD_CONNECTED_ITEM( aParent, idtype )
{
    m_width = pcbIUScale.mmToIU( 0.2 );     // Gives a reasonable default width
    m_hasSolderMask = false;
}
 
 
EDA_ITEM* PCB_TRACK::Clone() const
{
    return new PCB_TRACK( *this );
}
 
 
void PCB_TRACK::CopyFrom( const BOARD_ITEM* aOther )
{
    wxCHECK( aOther && aOther->Type() == PCB_TRACE_T, /* void */ );
    *this = *static_cast<const PCB_TRACK*>( aOther );
}
 
 
PCB_ARC::PCB_ARC( BOARD_ITEM* aParent, const SHAPE_ARC* aArc ) :
    PCB_TRACK( aParent, PCB_ARC_T )
{
    m_Start = aArc->GetP0();
    m_End = aArc->GetP1();
    m_Mid = aArc->GetArcMid();
}
 
 
EDA_ITEM* PCB_ARC::Clone() const
{
    return new PCB_ARC( *this );
}
 
 
void PCB_ARC::CopyFrom( const BOARD_ITEM* aOther )
{
    wxCHECK( aOther && aOther->Type() == PCB_ARC_T, /* void */ );
    *this = *static_cast<const PCB_ARC*>( aOther );
}
 
 
PCB_VIA::PCB_VIA( BOARD_ITEM* aParent ) :
        PCB_TRACK( aParent, PCB_VIA_T ),
        m_padStack( this )
{
    SetViaType( VIATYPE::THROUGH );
    Padstack().Drill().start = F_Cu;
    Padstack().Drill().end = B_Cu;
    SetDrillDefault();
 
    m_padStack.SetUnconnectedLayerMode( UNCONNECTED_LAYER_MODE::KEEP_ALL );
 
    // Padstack layerset is not used for vias right now
    m_padStack.LayerSet().reset();
 
    // For now, vias are always circles
    m_padStack.SetShape( PAD_SHAPE::CIRCLE, PADSTACK::ALL_LAYERS );
 
    ClearZoneLayerOverrides();
 
    m_isFree = false;
}
 
 
PCB_VIA::PCB_VIA( const PCB_VIA& aOther ) :
        PCB_TRACK( aOther.GetParent(), PCB_VIA_T ),
        m_padStack( this )
{
    PCB_VIA::operator=( aOther );
 
    SetUuidDirect( aOther.m_Uuid );
 
    for( size_t ii = 0; ii < m_zoneLayerOverrides.size(); ++ii )
    {
        m_zoneLayerOverrides[ii].store( aOther.m_zoneLayerOverrides[ii].load( std::memory_order_relaxed ),
                                        std::memory_order_relaxed );
    }
}
 
 
PCB_VIA& PCB_VIA::operator=( const PCB_VIA &aOther )
{
    BOARD_CONNECTED_ITEM::operator=( aOther );
 
    m_Start = aOther.m_Start;
    m_End = aOther.m_End;
 
    m_viaType = aOther.m_viaType;
    m_padStack = aOther.m_padStack;
    m_isFree = aOther.m_isFree;
 
    return *this;
}
 
 
void PCB_VIA::CopyFrom( const BOARD_ITEM* aOther )
{
    wxCHECK( aOther && aOther->Type() == PCB_VIA_T, /* void */ );
    *this = *static_cast<const PCB_VIA*>( aOther );
}
 
 
EDA_ITEM* PCB_VIA::Clone() const
{
    return new PCB_VIA( *this );
}
 
 
wxString PCB_VIA::GetItemDescription( UNITS_PROVIDER* aUnitsProvider, bool aFull ) const
{
    wxString formatStr;
 
    switch( GetViaType() )
    {
    case VIATYPE::BLIND:    formatStr = _( "Blind via %s on %s" );  break;
    case VIATYPE::BURIED:   formatStr = _( "Buried via %s on %s" ); break;
    case VIATYPE::MICROVIA: formatStr = _( "Micro via %s on %s" );  break;
    default:                formatStr = _( "Via %s on %s" );        break;
    }
 
    return wxString::Format( formatStr, GetNetnameMsg(), LayerMaskDescribe() );
}
 
 
BITMAPS PCB_VIA::GetMenuImage() const
{
    return BITMAPS::via;
}
 
 
bool PCB_TRACK::operator==( const BOARD_ITEM& aBoardItem ) const
{
    if( aBoardItem.Type() != Type() )
        return false;
 
    const PCB_TRACK& other = static_cast<const PCB_TRACK&>( aBoardItem );
 
    return *this == other;
}
 
 
bool PCB_TRACK::operator==( const PCB_TRACK& aOther ) const
{
    return m_Start == aOther.m_Start
            && m_End == aOther.m_End
            && m_layer == aOther.m_layer
            && m_width == aOther.m_width
            && m_hasSolderMask == aOther.m_hasSolderMask
            && m_solderMaskMargin == aOther.m_solderMaskMargin;
}
 
 
double PCB_TRACK::Similarity( const BOARD_ITEM& aOther ) const
{
    if( aOther.Type() != Type() )
        return 0.0;
 
    const PCB_TRACK& other = static_cast<const PCB_TRACK&>( aOther );
 
    double similarity = 1.0;
 
    if( m_layer != other.m_layer )
        similarity *= 0.9;
 
    if( m_width != other.m_width )
        similarity *= 0.9;
 
    if( m_Start != other.m_Start )
        similarity *= 0.9;
 
    if( m_End != other.m_End )
        similarity *= 0.9;
 
    if( m_hasSolderMask != other.m_hasSolderMask )
        similarity *= 0.9;
 
    if( m_solderMaskMargin != other.m_solderMaskMargin )
        similarity *= 0.9;
 
    return similarity;
}
 
 
bool PCB_ARC::operator==( const BOARD_ITEM& aBoardItem ) const
{
    if( aBoardItem.Type() != Type() )
        return false;
 
    const PCB_ARC& other = static_cast<const PCB_ARC&>( aBoardItem );
 
    return *this == other;
}
 
 
bool PCB_ARC::operator==( const PCB_TRACK& aOther ) const
{
    if( aOther.Type() != Type() )
        return false;
 
    const PCB_ARC& other = static_cast<const PCB_ARC&>( aOther );
 
    return *this == other;
}
 
 
bool PCB_ARC::operator==( const PCB_ARC& aOther ) const
{
    return m_Start == aOther.m_Start
            && m_End == aOther.m_End
            && m_Mid == aOther.m_Mid
            && m_layer == aOther.m_layer
            && GetWidth() == aOther.GetWidth()
            && m_hasSolderMask == aOther.m_hasSolderMask
            && m_solderMaskMargin == aOther.m_solderMaskMargin;
}
 
 
double PCB_ARC::Similarity( const BOARD_ITEM& aOther ) const
{
    if( aOther.Type() != Type() )
        return 0.0;
 
    const PCB_ARC& other = static_cast<const PCB_ARC&>( aOther );
 
    double similarity = 1.0;
 
    if( m_layer != other.m_layer )
        similarity *= 0.9;
 
    if( GetWidth() != other.GetWidth() )
        similarity *= 0.9;
 
    if( m_Start != other.m_Start )
        similarity *= 0.9;
 
    if( m_End != other.m_End )
        similarity *= 0.9;
 
    if( m_Mid != other.m_Mid )
        similarity *= 0.9;
 
    if( m_hasSolderMask != other.m_hasSolderMask )
        similarity *= 0.9;
 
    if( m_solderMaskMargin != other.m_solderMaskMargin )
        similarity *= 0.9;
 
    return similarity;
}
 
 
bool PCB_VIA::operator==( const BOARD_ITEM& aBoardItem ) const
{
    if( aBoardItem.Type() != Type() )
        return false;
 
    const PCB_VIA& other = static_cast<const PCB_VIA&>( aBoardItem );
 
    return *this == other;
}
 
 
bool PCB_VIA::operator==( const PCB_TRACK& aOther ) const
{
    if( aOther.Type() != Type() )
        return false;
 
    const PCB_VIA& other = static_cast<const PCB_VIA&>( aOther );
 
    return *this == other;
}
 
 
bool PCB_VIA::operator==( const PCB_VIA& aOther ) const
{
    return m_Start == aOther.m_Start
            && m_End == aOther.m_End
            && m_layer == aOther.m_layer
            && m_padStack == aOther.m_padStack
            && m_viaType == aOther.m_viaType
            && sameZoneLayerOverrides( aOther );
}
 
 
bool PCB_VIA::sameZoneLayerOverrides( const PCB_VIA& aOther ) const
{
    for( size_t ii = 0; ii < m_zoneLayerOverrides.size(); ++ii )
    {
        if( m_zoneLayerOverrides[ii].load( std::memory_order_relaxed )
                != aOther.m_zoneLayerOverrides[ii].load( std::memory_order_relaxed ) )
        {
            return false;
        }
    }
 
    return true;
}
 
 
double PCB_VIA::Similarity( const BOARD_ITEM& aOther ) const
{
    if( aOther.Type() != Type() )
        return 0.0;
 
    const PCB_VIA& other = static_cast<const PCB_VIA&>( aOther );
 
    double similarity = 1.0;
 
    if( m_layer != other.m_layer )
        similarity *= 0.9;
 
    if( m_Start != other.m_Start )
        similarity *= 0.9;
 
    if( m_End != other.m_End )
        similarity *= 0.9;
 
    if( m_padStack != other.m_padStack )
        similarity *= 0.9;
 
    if( m_viaType != other.m_viaType )
        similarity *= 0.9;
 
    if( !sameZoneLayerOverrides( other ) )
        similarity *= 0.9;
 
    return similarity;
}
 
 
void PCB_VIA::SetWidth( int aWidth )
{
    m_padStack.SetSize( { aWidth, aWidth }, PADSTACK::ALL_LAYERS );
    wxFAIL_MSG( wxT( "Warning: PCB_VIA::SetWidth() called without a layer argument" ) );
}
 
 
int PCB_VIA::GetWidth() const
{
    // This is present because of the parent class.  It should never be actually called on a via.
    wxCHECK_MSG( false, m_padStack.Size( PADSTACK::ALL_LAYERS ).x,
                 wxT( "Warning: PCB_VIA::GetWidth() called without a layer argument" ) );
}
 
 
void PCB_VIA::SetWidth( PCB_LAYER_ID aLayer, int aWidth )
{
    m_padStack.SetSize( { aWidth, aWidth }, aLayer );
}
 
 
int PCB_VIA::GetWidth( PCB_LAYER_ID aLayer ) const
{
    return m_padStack.Size( aLayer ).x;
}
 
 
void PCB_TRACK::Serialize( google::protobuf::Any &aContainer ) const
{
    kiapi::board::types::Track track;
 
    track.mutable_id()->set_value( m_Uuid.AsStdString() );
    track.mutable_start()->set_x_nm( GetStart().x );
    track.mutable_start()->set_y_nm( GetStart().y );
    track.mutable_end()->set_x_nm( GetEnd().x );
    track.mutable_end()->set_y_nm( GetEnd().y );
    track.mutable_width()->set_value_nm( GetWidth() );
    track.set_layer( ToProtoEnum<PCB_LAYER_ID, kiapi::board::types::BoardLayer>( GetLayer() ) );
    track.set_locked( IsLocked() ? kiapi::common::types::LockedState::LS_LOCKED
                                 : kiapi::common::types::LockedState::LS_UNLOCKED );
    PackNet( track.mutable_net() );
 
    if( const BOARD* board = GetBoard() )
        track.mutable_parent()->set_value( board->m_Uuid.AsStdString() );
 
    if( HasSolderMask() )
    {
        kiapi::board::types::SolderMaskOverrides* sm = track.mutable_solder_mask();
        sm->set_expose_copper( true );
 
        if( GetLocalSolderMaskMargin().has_value() )
            sm->mutable_solder_mask_margin()->set_value_nm( GetLocalSolderMaskMargin().value() );
    }
 
    kiapi::common::PackCustomProperties( track.mutable_custom_properties(), *this );
    aContainer.PackFrom( track );
}
 
 
bool PCB_TRACK::Deserialize( const google::protobuf::Any &aContainer )
{
    kiapi::board::types::Track track;
 
    if( !aContainer.UnpackTo( &track ) )
        return false;
 
    SetUuidDirect( KIID( track.id().value() ) );
    SetStart( VECTOR2I( track.start().x_nm(), track.start().y_nm() ) );
    SetEnd( VECTOR2I( track.end().x_nm(), track.end().y_nm() ) );
    SetWidth( track.width().value_nm() );
    SetLayer( FromProtoEnum<PCB_LAYER_ID, kiapi::board::types::BoardLayer>( track.layer() ) );
    UnpackNet( track.net() );
    SetLocked( track.locked() == kiapi::common::types::LockedState::LS_LOCKED );
    kiapi::common::UnpackCustomProperties( track.custom_properties(), *this );
 
    if( track.has_solder_mask() )
    {
        SetHasSolderMask( track.solder_mask().expose_copper() );
 
        if( track.solder_mask().has_solder_mask_margin() )
            SetLocalSolderMaskMargin( track.solder_mask().solder_mask_margin().value_nm() );
        else
            SetLocalSolderMaskMargin( {} );
    }
    else
    {
        SetHasSolderMask( false );
        SetLocalSolderMaskMargin( {} );
    }
 
    return true;
}
 
 
void PCB_ARC::Serialize( google::protobuf::Any &aContainer ) const
{
    kiapi::board::types::Arc arc;
 
    arc.mutable_id()->set_value( m_Uuid.AsStdString() );
    arc.mutable_start()->set_x_nm( GetStart().x );
    arc.mutable_start()->set_y_nm( GetStart().y );
    arc.mutable_mid()->set_x_nm( GetMid().x );
    arc.mutable_mid()->set_y_nm( GetMid().y );
    arc.mutable_end()->set_x_nm( GetEnd().x );
    arc.mutable_end()->set_y_nm( GetEnd().y );
    arc.mutable_width()->set_value_nm( GetWidth() );
    arc.set_layer( ToProtoEnum<PCB_LAYER_ID, kiapi::board::types::BoardLayer>( GetLayer() ) );
    arc.set_locked( IsLocked() ? kiapi::common::types::LockedState::LS_LOCKED
                               : kiapi::common::types::LockedState::LS_UNLOCKED );
    PackNet( arc.mutable_net() );
 
    if( const BOARD* board = GetBoard() )
        arc.mutable_parent()->set_value( board->m_Uuid.AsStdString() );
 
    if( HasSolderMask() )
    {
        kiapi::board::types::SolderMaskOverrides* sm = arc.mutable_solder_mask();
        sm->set_expose_copper( true );
 
        if( GetLocalSolderMaskMargin().has_value() )
            sm->mutable_solder_mask_margin()->set_value_nm( GetLocalSolderMaskMargin().value() );
    }
 
    kiapi::common::PackCustomProperties( arc.mutable_custom_properties(), *this );
    aContainer.PackFrom( arc );
}
 
 
bool PCB_ARC::Deserialize( const google::protobuf::Any &aContainer )
{
    kiapi::board::types::Arc arc;
 
    if( !aContainer.UnpackTo( &arc ) )
        return false;
 
    SetUuidDirect( KIID( arc.id().value() ) );
    SetStart( VECTOR2I( arc.start().x_nm(), arc.start().y_nm() ) );
    SetMid( VECTOR2I( arc.mid().x_nm(), arc.mid().y_nm() ) );
    SetEnd( VECTOR2I( arc.end().x_nm(), arc.end().y_nm() ) );
    SetWidth( arc.width().value_nm() );
    SetLayer( FromProtoEnum<PCB_LAYER_ID, kiapi::board::types::BoardLayer>( arc.layer() ) );
    UnpackNet( arc.net() );
    SetLocked( arc.locked() == kiapi::common::types::LockedState::LS_LOCKED );
    kiapi::common::UnpackCustomProperties( arc.custom_properties(), *this );
 
    if( arc.has_solder_mask() )
    {
        SetHasSolderMask( arc.solder_mask().expose_copper() );
 
        if( arc.solder_mask().has_solder_mask_margin() )
            SetLocalSolderMaskMargin( arc.solder_mask().solder_mask_margin().value_nm() );
        else
            SetLocalSolderMaskMargin( {} );
    }
    else
    {
        SetHasSolderMask( false );
        SetLocalSolderMaskMargin( {} );
    }
 
    return true;
}
 
 
void PCB_VIA::Serialize( google::protobuf::Any &aContainer ) const
{
    kiapi::board::types::Via via;
    Serialize( via );
    aContainer.PackFrom( via );
}
 
 
void PCB_VIA::Serialize( kiapi::board::types::Via& aVia ) const
{
    aVia.mutable_id()->set_value( m_Uuid.AsStdString() );
    aVia.mutable_position()->set_x_nm( GetPosition().x );
    aVia.mutable_position()->set_y_nm( GetPosition().y );
 
    PADSTACK padstack = Padstack();
 
    padstack.Serialize( *aVia.mutable_pad_stack() );
 
    // PADSTACK::m_layerSet is not used by vias
    aVia.mutable_pad_stack()->clear_layers();
    kiapi::board::PackLayerSet( *aVia.mutable_pad_stack()->mutable_layers(), GetLayerSet() );
 
    aVia.set_type( ToProtoEnum<VIATYPE, kiapi::board::types::ViaType>( GetViaType() ) );
    aVia.set_locked( IsLocked() ? kiapi::common::types::LockedState::LS_LOCKED
                               : kiapi::common::types::LockedState::LS_UNLOCKED );
    PackNet( aVia.mutable_net() );
 
    if( const BOARD* board = GetBoard() )
        aVia.mutable_parent()->set_value( board->m_Uuid.AsStdString() );
 
    kiapi::board::PackTeardropSettings( *aVia.mutable_teardrop(), GetTeardropParams() );
 
    aVia.set_is_free( GetIsFree() );
 
    {
        // Pack drops ZLO_NONE, so walking every copper layer emits only the overridden ones
        std::map<PCB_LAYER_ID, ZONE_LAYER_OVERRIDE> overrides;
 
        for( PCB_LAYER_ID layer : LAYER_RANGE( F_Cu, B_Cu, MAX_CU_LAYERS ) )
            overrides[layer] = GetZoneLayerOverride( layer );
 
        kiapi::board::PackZoneLayerOverrides( aVia.mutable_zone_layer_overrides(), overrides );
    }
 
    kiapi::common::PackCustomProperties( aVia.mutable_custom_properties(), *this );
}
 
 
bool PCB_VIA::Deserialize( const google::protobuf::Any &aContainer )
{
    kiapi::board::types::Via via;
 
    if( !aContainer.UnpackTo( &via ) )
        return false;
 
    return Deserialize( via );
}
 
 
bool PCB_VIA::Deserialize( const kiapi::board::types::Via& aVia )
{
    SetUuidDirect( KIID( aVia.id().value() ) );
    SetStart( VECTOR2I( aVia.position().x_nm(), aVia.position().y_nm() ) );
    SetEnd( GetStart() );
 
    google::protobuf::Any padStackWrapper;
    padStackWrapper.PackFrom( aVia.pad_stack() );
 
    if( !m_padStack.Deserialize( padStackWrapper ) )
        return false;
 
    // PADSTACK::m_layerSet is not used by vias
    m_padStack.LayerSet().reset();
 
    SetViaType( FromProtoEnum<VIATYPE>( aVia.type() ) );
    UnpackNet( aVia.net() );
    SetLocked( aVia.locked() == kiapi::common::types::LockedState::LS_LOCKED );
    kiapi::common::UnpackCustomProperties( aVia.custom_properties(), *this );
 
    if( aVia.has_teardrop() )
        kiapi::board::UnpackTeardropSettings( GetTeardropParams(), aVia.teardrop() );
    else
        SetTeardropsEnabled( false );
 
    SetIsFree( aVia.is_free() );
 
    ClearZoneLayerOverrides();
 
    {
        std::map<PCB_LAYER_ID, ZONE_LAYER_OVERRIDE> overrides;
        kiapi::board::UnpackZoneLayerOverrides( overrides, aVia.zone_layer_overrides() );
 
        for( const auto& [layer, value] : overrides )
            SetZoneLayerOverride( layer, value );
    }
 
    return true;
}
 
 
bool PCB_TRACK::ApproxCollinear( const PCB_TRACK& aTrack )
{
    SEG a( m_Start, m_End );
    SEG b( aTrack.GetStart(), aTrack.GetEnd() );
    return a.ApproxCollinear( b );
}
 
 
MINOPTMAX<int> PCB_TRACK::GetWidthConstraint( wxString* aSource ) const
{
    DRC_CONSTRAINT constraint;
 
    if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine )
    {
        BOARD_DESIGN_SETTINGS& bds = GetBoard()->GetDesignSettings();
 
        constraint = bds.m_DRCEngine->EvalRules( TRACK_WIDTH_CONSTRAINT, this, nullptr, m_layer );
    }
 
    if( aSource )
        *aSource = constraint.GetName();
 
    return constraint.Value();
}
 
 
MINOPTMAX<int> PCB_VIA::GetWidthConstraint( wxString* aSource ) const
{
    DRC_CONSTRAINT constraint;
 
    if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine )
    {
        BOARD_DESIGN_SETTINGS& bds = GetBoard()->GetDesignSettings();
 
        constraint = bds.m_DRCEngine->EvalRules( VIA_DIAMETER_CONSTRAINT, this, nullptr, m_layer );
    }
 
    if( aSource )
        *aSource = constraint.GetName();
 
    return constraint.Value();
}
 
 
MINOPTMAX<int> PCB_VIA::GetDrillConstraint( wxString* aSource ) const
{
    DRC_CONSTRAINT constraint;
 
    if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine )
    {
        BOARD_DESIGN_SETTINGS& bds = GetBoard()->GetDesignSettings();
 
        // Holes are not layer-specific, as in the hole size test
        constraint = bds.m_DRCEngine->EvalRules( HOLE_SIZE_CONSTRAINT, this, nullptr, UNDEFINED_LAYER );
    }
 
    if( aSource )
        *aSource = constraint.GetName();
 
    return constraint.Value();
}
 
 
void PCB_VIA::SetSizeFromRules( int aDiameter, int aDrill )
{
    // Area rules test the via's shape, so evaluate them at the preferred size
    SetPadstackMode( PADSTACK::MODE::NORMAL );
    SetWidth( PADSTACK::ALL_LAYERS, aDiameter );
    SetDrill( aDrill );
 
    // Callers size vias that may still move, so keep them out of the pointer-keyed rule caches
    bool wasTransient = HasFlag( ROUTER_TRANSIENT );
    SetFlags( ROUTER_TRANSIENT );
 
    int diameter = GetWidthConstraint().PinnedOpt( aDiameter );
    int drill = GetDrillConstraint().PinnedOpt( aDrill );
 
    if( !wasTransient )
        ClearFlags( ROUTER_TRANSIENT );
 
    SetWidth( PADSTACK::ALL_LAYERS, diameter );
    SetDrill( drill );
}
 
 
int PCB_VIA::GetMinAnnulus( PCB_LAYER_ID aLayer, wxString* aSource ) const
{
    if( !FlashLayer( aLayer ) )
    {
        if( aSource )
            *aSource = _( "removed annular ring" );
 
        return 0;
    }
 
    DRC_CONSTRAINT constraint;
 
    if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine )
    {
        BOARD_DESIGN_SETTINGS& bds = GetBoard()->GetDesignSettings();
 
        constraint = bds.m_DRCEngine->EvalRules( ANNULAR_WIDTH_CONSTRAINT, this, nullptr, aLayer );
    }
 
    if( constraint.Value().HasMin() )
    {
        if( aSource )
            *aSource = constraint.GetName();
 
        return constraint.Value().Min();
    }
 
    return 0;
}
 
 
void PCB_VIA::SetPrimaryDrillSize( const VECTOR2I& aSize )
{
    m_padStack.Drill().size = aSize;
}
 
 
void PCB_VIA::SetPrimaryDrillShape( PAD_DRILL_SHAPE aShape )
{
    m_padStack.Drill().shape = aShape;
}
 
 
void PCB_VIA::SetPrimaryDrillStartLayer( PCB_LAYER_ID aLayer )
{
    m_padStack.Drill().start = aLayer;
}
 
 
void PCB_VIA::SetPrimaryDrillEndLayer( PCB_LAYER_ID aLayer )
{
    m_padStack.Drill().end = aLayer;
}
 
 
void PCB_VIA::SetFrontPostMachining( const std::optional<PAD_DRILL_POST_MACHINING_MODE>& aMode )
{
    m_padStack.FrontPostMachining().mode = aMode;
}
 
 
void PCB_VIA::SetBackPostMachining( const std::optional<PAD_DRILL_POST_MACHINING_MODE>& aMode )
{
    m_padStack.BackPostMachining().mode = aMode;
}
 
 
void PCB_VIA::SetPrimaryDrillFilled( const std::optional<bool>& aFilled )
{
    m_padStack.Drill().is_filled = aFilled;
}
 
 
void PCB_VIA::SetPrimaryDrillFilledFlag( bool aFilled )
{
    m_padStack.Drill().is_filled = aFilled;
}
 
 
void PCB_VIA::SetPrimaryDrillCapped( const std::optional<bool>& aCapped )
{
    m_padStack.Drill().is_capped = aCapped;
}
 
 
void PCB_VIA::SetPrimaryDrillCappedFlag( bool aCapped )
{
    m_padStack.Drill().is_capped = aCapped;
}
 
 
// Two microvias belong to one structure when the upper one lands on the lower one. Exact
// concentricity is only the extreme case of that, so the test is hole overlap.
std::vector<std::vector<PCB_VIA*>> PCB_VIA::CollectMicroviaColumns( BOARD* aBoard )
{
    std::map<int, int> ordinals;
    int                n = 0;
 
    for( PCB_LAYER_ID layer : LAYER_RANGE( F_Cu, B_Cu, aBoard->GetCopperLayerCount() ) )
        ordinals[layer] = n++;
 
    std::vector<PCB_VIA*> microvias;
 
    for( PCB_TRACK* track : aBoard->Tracks() )
    {
        if( track->Type() != PCB_VIA_T )
            continue;
 
        PCB_VIA* via = static_cast<PCB_VIA*>( track );
 
        if( via->GetViaType() != VIATYPE::MICROVIA )
            continue;
 
        // A via on a single layer lands on nothing.
        if( via->TopLayer() == via->BottomLayer() )
            continue;
 
        if( ordinals.count( via->TopLayer() ) && ordinals.count( via->BottomLayer() ) )
            microvias.push_back( via );
    }
 
    auto upper = [&]( PCB_VIA* aVia )
    {
        return std::min( ordinals[aVia->TopLayer()], ordinals[aVia->BottomLayer()] );
    };
 
    auto lower = [&]( PCB_VIA* aVia )
    {
        return std::max( ordinals[aVia->TopLayer()], ordinals[aVia->BottomLayer()] );
    };
 
    // Touching holes have no wall between them, so they count as one column too.
    auto overlaps = []( PCB_VIA* aFirst, PCB_VIA* aSecond )
    {
        double reach = ( aFirst->GetDrillValue() + aSecond->GetDrillValue() ) / 2.0;
 
        return ( aFirst->GetPosition() - aSecond->GetPosition() ).EuclideanNorm() <= reach;
    };
 
    // Overlap needs the centres closer than the largest hole, so bucket the vias by landing
    // layer and position and only the neighbouring buckets have to be looked at.
    int cellSize = 1;
 
    for( PCB_VIA* via : microvias )
        cellSize = std::max( cellSize, via->GetDrillValue() );
 
    auto cellOf = [&]( int aCoord )
    {
        return (int) std::floor( (double) aCoord / cellSize );
    };
 
    std::map<std::tuple<int, int, int>, std::vector<PCB_VIA*>> byCell;
 
    for( PCB_VIA* via : microvias )
    {
        VECTOR2I pos = via->GetPosition();
        byCell[{ upper( via ), cellOf( pos.x ), cellOf( pos.y ) }].push_back( via );
    }
 
    // The via a given one lands on, if any.
    auto below = [&]( PCB_VIA* aVia ) -> PCB_VIA*
    {
        VECTOR2I pos = aVia->GetPosition();
 
        for( int dx = -1; dx <= 1; ++dx )
        {
            for( int dy = -1; dy <= 1; ++dy )
            {
                auto it = byCell.find( { lower( aVia ), cellOf( pos.x ) + dx, cellOf( pos.y ) + dy } );
 
                if( it == byCell.end() )
                    continue;
 
                for( PCB_VIA* other : it->second )
                {
                    if( other != aVia && overlaps( aVia, other ) )
                        return other;
                }
            }
        }
 
        return nullptr;
    };
 
    std::set<PCB_VIA*> carried;
 
    for( PCB_VIA* via : microvias )
    {
        if( PCB_VIA* under = below( via ) )
            carried.insert( under );
    }
 
    std::vector<std::vector<PCB_VIA*>> columns;
    std::set<PCB_VIA*>                 taken;
 
    for( PCB_VIA* via : microvias )
    {
        // Walk down from the top of each structure so every one is built once.
        if( carried.count( via ) )
            continue;
 
        std::vector<PCB_VIA*> column;
        bool                  landsOnAnother = false;
 
        for( PCB_VIA* step = via; step; step = below( step ) )
        {
            if( !taken.insert( step ).second )
            {
                landsOnAnother = true;
                break;
            }
 
            column.push_back( step );
 
            if( column.size() > ordinals.size() )
                break;
        }
 
        if( column.size() > 1 || landsOnAnother )
            columns.push_back( std::move( column ) );
    }
 
    return columns;
}
 
 
int PCB_VIA::GetDrillValue() const
{
    if( m_padStack.Drill().size.x > 0 ) // Use the specific value.
        return m_padStack.Drill().size.x;
 
    // Use the default value from the Netclass
    NETCLASS* netclass = GetEffectiveNetClass();
 
    if( GetViaType() == VIATYPE::MICROVIA )
        return netclass->GetuViaDrill();
 
    return netclass->GetViaDrill();
}
 
 
void PCB_VIA::SetSecondaryDrillSize( const VECTOR2I& aSize )
{
    m_padStack.SecondaryDrill().size = aSize;
}
 
 
void PCB_VIA::ClearSecondaryDrillSize()
{
    m_padStack.SecondaryDrill().size = { 0, 0 };
}
 
 
void PCB_VIA::SetSecondaryDrillSize( const std::optional<int>& aDrill )
{
    if( aDrill.has_value() && *aDrill > 0 )
        SetSecondaryDrillSize( { *aDrill, *aDrill } );
    else
        ClearSecondaryDrillSize();
}
 
 
std::optional<int> PCB_VIA::GetSecondaryDrillSize() const
{
    if( m_padStack.SecondaryDrill().size.x > 0 )
        return m_padStack.SecondaryDrill().size.x;
 
    return std::nullopt;
}
 
 
void PCB_VIA::SetSecondaryDrillStartLayer( PCB_LAYER_ID aLayer )
{
    m_padStack.SecondaryDrill().start = aLayer;
}
 
 
void PCB_VIA::SetSecondaryDrillEndLayer( PCB_LAYER_ID aLayer )
{
    m_padStack.SecondaryDrill().end = aLayer;
}
 
 
void PCB_VIA::SetSecondaryDrillShape( PAD_DRILL_SHAPE aShape )
{
    m_padStack.SecondaryDrill().shape = aShape;
}
 
 
void PCB_VIA::SetTertiaryDrillSize( const VECTOR2I& aSize )
{
    m_padStack.TertiaryDrill().size = aSize;
}
 
 
void PCB_VIA::ClearTertiaryDrillSize()
{
    m_padStack.TertiaryDrill().size = { 0, 0 };
}
 
 
void PCB_VIA::SetTertiaryDrillSize( const std::optional<int>& aDrill )
{
    if( aDrill.has_value() && *aDrill > 0 )
        SetTertiaryDrillSize( { *aDrill, *aDrill } );
    else
        ClearTertiaryDrillSize();
}
 
 
std::optional<int> PCB_VIA::GetTertiaryDrillSize() const
{
    if( m_padStack.TertiaryDrill().size.x > 0 )
        return m_padStack.TertiaryDrill().size.x;
 
    return std::nullopt;
}
 
 
void PCB_VIA::SetTertiaryDrillStartLayer( PCB_LAYER_ID aLayer )
{
    m_padStack.TertiaryDrill().start = aLayer;
}
 
 
void PCB_VIA::SetTertiaryDrillEndLayer( PCB_LAYER_ID aLayer )
{
    m_padStack.TertiaryDrill().end = aLayer;
}
 
 
void PCB_VIA::SetTertiaryDrillShape( PAD_DRILL_SHAPE aShape )
{
    m_padStack.TertiaryDrill().shape = aShape;
}
 
 
bool PCB_VIA::IsBackdrilledOrPostMachined( PCB_LAYER_ID aLayer ) const
{
    if( !IsCopperLayer( aLayer ) )
        return false;
 
    const BOARD* board = GetBoard();
 
    if( !board )
        return false;
 
    // Check secondary drill (backdrill from top)
    const PADSTACK::DRILL_PROPS& secondaryDrill = m_padStack.SecondaryDrill();
 
    if( secondaryDrill.size.x > 0
            && secondaryDrill.start != UNDEFINED_LAYER
            && secondaryDrill.end != UNDEFINED_LAYER )
    {
        // Contains honours copper Z-order; the range iterator instead walks PCB_LAYER_ID enum
        // order, which for a bottom-anchored span spans the wrong (top inner) layers.
        if( LAYER_RANGE::Contains( secondaryDrill.start, secondaryDrill.end, aLayer ) )
            return true;
    }
 
    // Check tertiary drill (backdrill from bottom)
    const PADSTACK::DRILL_PROPS& tertiaryDrill = m_padStack.TertiaryDrill();
 
    if( tertiaryDrill.size.x > 0
            && tertiaryDrill.start != UNDEFINED_LAYER
            && tertiaryDrill.end != UNDEFINED_LAYER )
    {
        if( LAYER_RANGE::Contains( tertiaryDrill.start, tertiaryDrill.end, aLayer ) )
            return true;
    }
 
    // Check if the layer is affected by post-machining
    if( GetPostMachiningKnockout( aLayer ) > 0 )
        return true;
 
    return false;
}
 
 
int PCB_VIA::GetPostMachiningKnockout( PCB_LAYER_ID aLayer ) const
{
    if( !IsCopperLayer( aLayer ) )
        return 0;
 
    const BOARD* board = GetBoard();
 
    if( !board )
        return 0;
 
    const BOARD_STACKUP& stackup = board->GetDesignSettings().GetStackupDescriptor();
 
    // Check front post-machining (counterbore/countersink from top)
    const PADSTACK::POST_MACHINING_PROPS& frontPM = m_padStack.FrontPostMachining();
 
    if( frontPM.mode.has_value()
            && *frontPM.mode != PAD_DRILL_POST_MACHINING_MODE::NOT_POST_MACHINED
            && *frontPM.mode != PAD_DRILL_POST_MACHINING_MODE::UNKNOWN
            && frontPM.size > 0 )
    {
        int pmDepth = frontPM.depth;
 
        // For countersink without explicit depth, calculate from diameter and angle
        if( pmDepth <= 0
                && *frontPM.mode == PAD_DRILL_POST_MACHINING_MODE::COUNTERSINK
                && frontPM.angle > 0 )
        {
            double halfAngleRad = ( frontPM.angle / 10.0 ) * M_PI / 180.0 / 2.0;
            pmDepth = static_cast<int>( ( frontPM.size / 2.0 ) / tan( halfAngleRad ) );
        }
 
        if( pmDepth > 0 )
        {
            // Calculate distance from F_Cu to aLayer
            int layerDist = stackup.GetLayerDistance( F_Cu, aLayer );
 
            if( layerDist < pmDepth )
            {
                // For countersink, diameter decreases with depth
                if( *frontPM.mode == PAD_DRILL_POST_MACHINING_MODE::COUNTERSINK && frontPM.angle > 0 )
                {
                    double halfAngleRad = ( frontPM.angle / 10.0 ) * M_PI / 180.0 / 2.0;
                    int diameterAtLayer = frontPM.size - static_cast<int>( 2.0 * layerDist * tan( halfAngleRad ) );
                    return std::max( 0, diameterAtLayer );
                }
                else
                {
                    // Counterbore - constant diameter
                    return frontPM.size;
                }
            }
        }
    }
 
    // Check back post-machining (counterbore/countersink from bottom)
    const PADSTACK::POST_MACHINING_PROPS& backPM = m_padStack.BackPostMachining();
 
    if( backPM.mode.has_value()
            && *backPM.mode != PAD_DRILL_POST_MACHINING_MODE::NOT_POST_MACHINED
            && *backPM.mode != PAD_DRILL_POST_MACHINING_MODE::UNKNOWN
            && backPM.size > 0 )
    {
        int pmDepth = backPM.depth;
 
        // For countersink without explicit depth, calculate from diameter and angle
        if( pmDepth <= 0
                && *backPM.mode == PAD_DRILL_POST_MACHINING_MODE::COUNTERSINK
                && backPM.angle > 0 )
        {
            double halfAngleRad = ( backPM.angle / 10.0 ) * M_PI / 180.0 / 2.0;
            pmDepth = static_cast<int>( ( backPM.size / 2.0 ) / tan( halfAngleRad ) );
        }
 
        if( pmDepth > 0 )
        {
            // Calculate distance from B_Cu to aLayer
            int layerDist = stackup.GetLayerDistance( B_Cu, aLayer );
 
            if( layerDist < pmDepth )
            {
                // For countersink, diameter decreases with depth
                if( *backPM.mode == PAD_DRILL_POST_MACHINING_MODE::COUNTERSINK && backPM.angle > 0 )
                {
                    double halfAngleRad = ( backPM.angle / 10.0 ) * M_PI / 180.0 / 2.0;
                    int diameterAtLayer = backPM.size - static_cast<int>( 2.0 * layerDist * tan( halfAngleRad ) );
                    return std::max( 0, diameterAtLayer );
                }
                else
                {
                    // Counterbore - constant diameter
                    return backPM.size;
                }
            }
        }
    }
 
    return 0;
}
 
 
EDA_ITEM_FLAGS PCB_TRACK::IsPointOnEnds( const VECTOR2I& point, int min_dist ) const
{
    EDA_ITEM_FLAGS result = 0;
 
    if( min_dist < 0 )
        min_dist = m_width / 2;
 
    if( min_dist == 0 )
    {
        if( m_Start == point  )
            result |= STARTPOINT;
 
        if( m_End == point )
            result |= ENDPOINT;
    }
    else
    {
        double dist = m_Start.Distance( point );
 
        if( min_dist >= dist )
            result |= STARTPOINT;
 
        dist = m_End.Distance( point );
 
        if( min_dist >= dist )
            result |= ENDPOINT;
    }
 
    return result;
}
 
 
const BOX2I PCB_TRACK::GetBoundingBox() const
{
    // end of track is round, this is its radius, rounded up
    int radius = ( m_width + 1 ) / 2;
    int ymax, xmax, ymin, xmin;
 
    if( Type() == PCB_ARC_T )
    {
        std::shared_ptr<SHAPE> arc = GetEffectiveShape();
        BOX2I bbox = arc->BBox();
 
        xmin = bbox.GetLeft();
        xmax = bbox.GetRight();
        ymin = bbox.GetTop();
        ymax = bbox.GetBottom();
    }
    else
    {
        ymax = std::max( m_Start.y, m_End.y );
        xmax = std::max( m_Start.x, m_End.x );
 
        ymin = std::min( m_Start.y, m_End.y );
        xmin = std::min( m_Start.x, m_End.x );
    }
 
    ymax += radius;
    xmax += radius;
 
    ymin -= radius;
    xmin -= radius;
 
    // return a rectangle which is [pos,dim) in nature.  therefore the +1
    return BOX2ISafe( VECTOR2I( xmin, ymin ),
                      VECTOR2L( (int64_t) xmax - xmin + 1, (int64_t) ymax - ymin + 1 ) );
}
 
 
const BOX2I PCB_VIA::GetBoundingBox() const
{
    int diameter = 0;
 
    Padstack().ForEachUniqueLayer(
            [&]( PCB_LAYER_ID aLayer )
            {
                if( IsGhostLayer( aLayer ) )
                    return;
 
                diameter = std::max( diameter, GetWidth( aLayer ) );
            } );
 
    diameter = std::max( diameter, Padstack().GetMaxHoleSize() );
 
    // via is round, this is its radius, rounded up
    int radius = ( diameter + 1 ) / 2;
 
    int ymax = m_Start.y + radius;
    int xmax = m_Start.x + radius;
 
    int ymin = m_Start.y - radius;
    int xmin = m_Start.x - radius;
 
    // return a rectangle which is [pos,dim) in nature.  therefore the +1
    return BOX2ISafe( VECTOR2I( xmin, ymin ),
                      VECTOR2L( (int64_t) xmax - xmin + 1, (int64_t) ymax - ymin + 1 ) );
}
 
 
const BOX2I PCB_VIA::GetBoundingBox( PCB_LAYER_ID aLayer ) const
{
    int diameter = GetWidth( aLayer );
 
    if( IsBackdrilledOrPostMachined( aLayer ) )
        diameter = std::max( diameter, Padstack().GetMaxHoleSize() );
 
    // via is round, this is its radius, rounded up
    int radius = ( diameter + 1 ) / 2;
 
    int ymax = m_Start.y + radius;
    int xmax = m_Start.x + radius;
 
    int ymin = m_Start.y - radius;
    int xmin = m_Start.x - radius;
 
    // return a rectangle which is [pos,dim) in nature.  therefore the +1
    return BOX2ISafe( VECTOR2I( xmin, ymin ),
                      VECTOR2L( (int64_t) xmax - xmin + 1, (int64_t) ymax - ymin + 1 ) );
}
 
 
double PCB_TRACK::GetLength() const
{
    return m_Start.Distance( m_End );
}
 
 
double PCB_TRACK::GetDelay() const
{
    const BOARD* board = GetBoard();
 
    if( !board )
        return 0.0;
 
    const LENGTH_DELAY_CALCULATION*            calc = board->GetLengthCalculation();
    std::vector<LENGTH_DELAY_CALCULATION_ITEM> items{ calc->GetLengthCalculationItem( this ) };
    constexpr PATH_OPTIMISATIONS               opts = { .OptimiseVias = false,
                                                        .MergeTracks = false,
                                                        .OptimiseTracesInPads = false,
                                                        .InferViaInPad = false
                                                      };
 
    return (double) calc->CalculateDelay( items, opts );
}
 
 
void PCB_TRACK::Rotate( const VECTOR2I& aRotCentre, const EDA_ANGLE& aAngle )
{
    RotatePoint( m_Start, aRotCentre, aAngle );
    RotatePoint( m_End, aRotCentre, aAngle );
}
 
 
void PCB_ARC::Rotate( const VECTOR2I& aRotCentre, const EDA_ANGLE& aAngle )
{
    RotatePoint( m_Start, aRotCentre, aAngle );
    RotatePoint( m_End, aRotCentre, aAngle );
    RotatePoint( m_Mid, aRotCentre, aAngle );
}
 
 
void PCB_TRACK::Mirror( const VECTOR2I& aCentre, FLIP_DIRECTION aFlipDirection )
{
    MIRROR( m_Start, aCentre, aFlipDirection );
    MIRROR( m_End, aCentre, aFlipDirection );
}
 
 
void PCB_ARC::Mirror( const VECTOR2I& aCentre, FLIP_DIRECTION aFlipDirection )
{
    MIRROR( m_Start, aCentre, aFlipDirection );
    MIRROR( m_End, aCentre, aFlipDirection );
    MIRROR( m_Mid, aCentre, aFlipDirection );
}
 
 
void PCB_TRACK::Flip( const VECTOR2I& aCentre, FLIP_DIRECTION aFlipDirection )
{
    if( aFlipDirection == FLIP_DIRECTION::LEFT_RIGHT )
    {
        m_Start.x = aCentre.x - ( m_Start.x - aCentre.x );
        m_End.x   = aCentre.x - ( m_End.x - aCentre.x );
    }
    else
    {
        m_Start.y = aCentre.y - ( m_Start.y - aCentre.y );
        m_End.y   = aCentre.y - ( m_End.y - aCentre.y );
    }
 
    SetLayer( GetBoard()->FlipLayer( GetLayer() ) );
}
 
 
void PCB_ARC::Flip( const VECTOR2I& aCentre, FLIP_DIRECTION aFlipDirection )
{
    if( aFlipDirection == FLIP_DIRECTION::LEFT_RIGHT )
    {
        m_Start.x = aCentre.x - ( m_Start.x - aCentre.x );
        m_End.x   = aCentre.x - ( m_End.x - aCentre.x );
        m_Mid.x = aCentre.x - ( m_Mid.x - aCentre.x );
    }
    else
    {
        m_Start.y = aCentre.y - ( m_Start.y - aCentre.y );
        m_End.y   = aCentre.y - ( m_End.y - aCentre.y );
        m_Mid.y = aCentre.y - ( m_Mid.y - aCentre.y );
    }
 
    SetLayer( GetBoard()->FlipLayer( GetLayer() ) );
}
 
 
bool PCB_ARC::IsCCW() const
{
    VECTOR2L start = m_Start;
    VECTOR2L start_end = m_End - start;
    VECTOR2L start_mid = m_Mid - start;
 
    return start_end.Cross( start_mid ) < 0;
}
 
 
void PCB_VIA::Flip( const VECTOR2I& aCentre, FLIP_DIRECTION aFlipDirection )
{
    if( aFlipDirection == FLIP_DIRECTION::LEFT_RIGHT )
    {
        m_Start.x = aCentre.x - ( m_Start.x - aCentre.x );
        m_End.x   = aCentre.x - ( m_End.x - aCentre.x );
    }
    else
    {
        m_Start.y = aCentre.y - ( m_Start.y - aCentre.y );
        m_End.y   = aCentre.y - ( m_End.y - aCentre.y );
    }
 
    if( GetViaType() != VIATYPE::THROUGH )
    {
        PCB_LAYER_ID top_layer;
        PCB_LAYER_ID bottom_layer;
        LayerPair( &top_layer, &bottom_layer );
        top_layer    = GetBoard()->FlipLayer( top_layer );
        bottom_layer = GetBoard()->FlipLayer( bottom_layer );
        SetLayerPair( top_layer, bottom_layer );
    }
}
 
 
INSPECT_RESULT PCB_TRACK::Visit( INSPECTOR inspector, void* testData, const std::vector<KICAD_T>& aScanTypes )
{
    for( KICAD_T scanType : aScanTypes )
    {
        if( scanType == Type() )
        {
            if( INSPECT_RESULT::QUIT == inspector( this, testData ) )
                return INSPECT_RESULT::QUIT;
        }
    }
 
    return INSPECT_RESULT::CONTINUE;
}
 
 
std::shared_ptr<SHAPE_SEGMENT> PCB_VIA::GetEffectiveHoleShape( PCB_LAYER_ID aLayer, DRC_CONSTRAINT_T aUsage ) const
{
    // An unset padstack drill falls back to the netclass value
    int holeSize = GetDrillValue();
 
    // See if we want to include a larger backdrill or post-machining hole
    if( aUsage == HOLE_TO_HOLE_CONSTRAINT
            || ( aUsage == HOLE_CLEARANCE_CONSTRAINT && IsBackdrilledOrPostMachined( aLayer ) )
            || ( aUsage == ANNULAR_WIDTH_CONSTRAINT && IsBackdrilledOrPostMachined( aLayer ) )
            || ( aUsage == PHYSICAL_CLEARANCE_CONSTRAINT && IsBackdrilledOrPostMachined( aLayer ) )
            || ( aUsage == SILK_CLEARANCE_CONSTRAINT && IsBackdrilledOrPostMachined( aLayer ) ) )
    {
        holeSize = std::max( holeSize, Padstack().GetMaxHoleSize() );
    }
 
    return std::make_shared<SHAPE_SEGMENT>( SEG( m_Start, m_Start ), holeSize );
}
 
// clang-format off: the suggestion is slightly less readable
void PCB_VIA::SetFrontTentingMode( TENTING_MODE aMode )
{
    switch( aMode )
    {
    case TENTING_MODE::FROM_BOARD: m_padStack.FrontOuterLayers().has_solder_mask.reset();  break;
    case TENTING_MODE::TENTED:     m_padStack.FrontOuterLayers().has_solder_mask = true;   break;
    case TENTING_MODE::NOT_TENTED: m_padStack.FrontOuterLayers().has_solder_mask = false;  break;
    }
}
 
 
TENTING_MODE PCB_VIA::GetFrontTentingMode() const
{
    if( m_padStack.FrontOuterLayers().has_solder_mask.has_value() )
    {
        return *m_padStack.FrontOuterLayers().has_solder_mask ? TENTING_MODE::TENTED
                                                              : TENTING_MODE::NOT_TENTED;
    }
 
    return TENTING_MODE::FROM_BOARD;
}
 
 
void PCB_VIA::SetBackTentingMode( TENTING_MODE aMode )
{
    switch( aMode )
    {
    case TENTING_MODE::FROM_BOARD: m_padStack.BackOuterLayers().has_solder_mask.reset();  break;
    case TENTING_MODE::TENTED:     m_padStack.BackOuterLayers().has_solder_mask = true;   break;
    case TENTING_MODE::NOT_TENTED: m_padStack.BackOuterLayers().has_solder_mask = false;  break;
    }
}
 
 
TENTING_MODE PCB_VIA::GetBackTentingMode() const
{
    if( m_padStack.BackOuterLayers().has_solder_mask.has_value() )
    {
        return *m_padStack.BackOuterLayers().has_solder_mask ? TENTING_MODE::TENTED
                                                             : TENTING_MODE::NOT_TENTED;
    }
 
    return TENTING_MODE::FROM_BOARD;
}
 
 
void PCB_VIA::SetFrontCoveringMode( COVERING_MODE aMode )
{
    switch( aMode )
    {
    case COVERING_MODE::FROM_BOARD:  m_padStack.FrontOuterLayers().has_covering.reset();  break;
    case COVERING_MODE::COVERED:     m_padStack.FrontOuterLayers().has_covering = true;   break;
    case COVERING_MODE::NOT_COVERED: m_padStack.FrontOuterLayers().has_covering = false;  break;
    }
}
 
 
COVERING_MODE PCB_VIA::GetFrontCoveringMode() const
{
    if( m_padStack.FrontOuterLayers().has_covering.has_value() )
    {
        return *m_padStack.FrontOuterLayers().has_covering ? COVERING_MODE::COVERED
                                                           : COVERING_MODE::NOT_COVERED;
    }
 
    return COVERING_MODE::FROM_BOARD;
}
 
 
void PCB_VIA::SetBackCoveringMode( COVERING_MODE aMode )
{
    switch( aMode )
    {
    case COVERING_MODE::FROM_BOARD:  m_padStack.BackOuterLayers().has_covering.reset();  break;
    case COVERING_MODE::COVERED:     m_padStack.BackOuterLayers().has_covering = true;   break;
    case COVERING_MODE::NOT_COVERED: m_padStack.BackOuterLayers().has_covering = false;  break;
    }
}
 
 
COVERING_MODE PCB_VIA::GetBackCoveringMode() const
{
    if( m_padStack.BackOuterLayers().has_covering.has_value() )
    {
        return *m_padStack.BackOuterLayers().has_covering ? COVERING_MODE::COVERED
                                                          : COVERING_MODE::NOT_COVERED;
    }
 
    return COVERING_MODE::FROM_BOARD;
}
 
 
void PCB_VIA::SetFrontPluggingMode( PLUGGING_MODE aMode )
{
    switch( aMode )
    {
    case PLUGGING_MODE::FROM_BOARD:  m_padStack.FrontOuterLayers().has_plugging.reset();  break;
    case PLUGGING_MODE::PLUGGED:     m_padStack.FrontOuterLayers().has_plugging = true;   break;
    case PLUGGING_MODE::NOT_PLUGGED: m_padStack.FrontOuterLayers().has_plugging = false;  break;
    }
}
 
 
PLUGGING_MODE PCB_VIA::GetFrontPluggingMode() const
{
    if( m_padStack.FrontOuterLayers().has_plugging.has_value() )
    {
        return *m_padStack.FrontOuterLayers().has_plugging ? PLUGGING_MODE::PLUGGED
                                                           : PLUGGING_MODE::NOT_PLUGGED;
    }
 
    return PLUGGING_MODE::FROM_BOARD;
}
 
 
void PCB_VIA::SetBackPluggingMode( PLUGGING_MODE aMode )
{
    switch( aMode )
    {
    case PLUGGING_MODE::FROM_BOARD:  m_padStack.BackOuterLayers().has_plugging.reset();  break;
    case PLUGGING_MODE::PLUGGED:     m_padStack.BackOuterLayers().has_plugging = true;   break;
    case PLUGGING_MODE::NOT_PLUGGED: m_padStack.BackOuterLayers().has_plugging = false;  break;
    }
}
 
 
PLUGGING_MODE PCB_VIA::GetBackPluggingMode() const
{
    if( m_padStack.BackOuterLayers().has_plugging.has_value() )
    {
        return *m_padStack.BackOuterLayers().has_plugging ? PLUGGING_MODE::PLUGGED
                                                          : PLUGGING_MODE::NOT_PLUGGED;
    }
 
    return PLUGGING_MODE::FROM_BOARD;
}
 
 
void PCB_VIA::SetCappingMode( CAPPING_MODE aMode )
{
    switch( aMode )
    {
    case CAPPING_MODE::FROM_BOARD: m_padStack.Drill().is_capped.reset();  break;
    case CAPPING_MODE::CAPPED:     m_padStack.Drill().is_capped = true;   break;
    case CAPPING_MODE::NOT_CAPPED: m_padStack.Drill().is_capped = false;  break;
    }
}
 
 
CAPPING_MODE PCB_VIA::GetCappingMode() const
{
    if( m_padStack.Drill().is_capped.has_value() )
    {
        return *m_padStack.Drill().is_capped ? CAPPING_MODE::CAPPED
                                             : CAPPING_MODE::NOT_CAPPED;
    }
 
    return CAPPING_MODE::FROM_BOARD;
}
 
 
void PCB_VIA::SetFillingMode( FILLING_MODE aMode )
{
    switch( aMode )
    {
    case FILLING_MODE::FROM_BOARD: m_padStack.Drill().is_filled.reset();  break;
    case FILLING_MODE::FILLED:     m_padStack.Drill().is_filled = true;   break;
    case FILLING_MODE::NOT_FILLED: m_padStack.Drill().is_filled = false;  break;
    }
}
 
 
FILLING_MODE PCB_VIA::GetFillingMode() const
{
    if( m_padStack.Drill().is_filled.has_value() )
    {
        return *m_padStack.Drill().is_filled ? FILLING_MODE::FILLED
                                             : FILLING_MODE::NOT_FILLED;
    }
 
    return FILLING_MODE::FROM_BOARD;
}
 
 
bool PCB_VIA::IsTented( PCB_LAYER_ID aLayer ) const
{
    wxCHECK_MSG( IsFrontLayer( aLayer ) || IsBackLayer( aLayer ), true, "Invalid layer passed to IsTented" );
 
    bool front = IsFrontLayer( aLayer );
 
    if( front && m_padStack.FrontOuterLayers().has_solder_mask.has_value() )
        return *m_padStack.FrontOuterLayers().has_solder_mask;
 
    if( !front && m_padStack.BackOuterLayers().has_solder_mask.has_value() )
        return *m_padStack.BackOuterLayers().has_solder_mask;
 
    if( const BOARD* board = GetBoard() )
    {
        return front ? board->GetDesignSettings().m_TentViasFront
                     : board->GetDesignSettings().m_TentViasBack;
    }
 
    return true;
}
 
 
int PCB_VIA::GetSolderMaskExpansion() const
{
    if( const BOARD* board = GetBoard() )
        return board->GetDesignSettings().m_SolderMaskExpansion;
    else
        return 0;
}
 
 
int PCB_TRACK::GetSolderMaskExpansion() const
{
    int margin = 0;
 
    if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine
        && GetBoard()->GetDesignSettings().m_DRCEngine->HasRulesForConstraintType( SOLDER_MASK_EXPANSION_CONSTRAINT ) )
    {
        DRC_CONSTRAINT              constraint;
        std::shared_ptr<DRC_ENGINE> drcEngine = GetBoard()->GetDesignSettings().m_DRCEngine;
 
        constraint = drcEngine->EvalRules( SOLDER_MASK_EXPANSION_CONSTRAINT, this, nullptr, m_layer );
 
        if( constraint.m_Value.HasOpt() )
            margin = constraint.m_Value.Opt();
    }
    else if( m_solderMaskMargin.has_value() )
    {
        margin = m_solderMaskMargin.value();
    }
    else if( const BOARD* board = GetBoard() )
    {
        margin = board->GetDesignSettings().m_SolderMaskExpansion;
    }
 
    // Ensure the resulting mask opening has a non-negative size
    if( margin < 0 )
        margin = std::max( margin, -m_width / 2 );
 
    return margin;
}
 
 
bool PCB_TRACK::IsOnLayer( PCB_LAYER_ID aLayer ) const
{
    if( aLayer == m_layer )
    {
        return true;
    }
 
    if( m_hasSolderMask && (   ( aLayer == F_Mask && m_layer == F_Cu )
                            || ( aLayer == B_Mask && m_layer == B_Cu ) ) )
    {
        return true;
    }
 
    return false;
}
 
 
bool PCB_VIA::IsOnLayer( PCB_LAYER_ID aLayer ) const
{
    if( IsCopperLayer( aLayer ) &&
        LAYER_RANGE::Contains( Padstack().Drill().start, Padstack().Drill().end, aLayer ) )
    {
        return true;
    }
 
    // Test for via on mask layers: a via on on a mask layer if not tented and if
    // it is on the corresponding external copper layer
    if( aLayer == F_Mask )
        return Padstack().Drill().start == F_Cu && !IsTented( F_Mask );
    else if( aLayer == B_Mask )
        return Padstack().Drill().end == B_Cu && !IsTented( B_Mask );
 
    return false;
}
 
 
bool PCB_VIA::IsOnCopperLayer() const
{
    return true;
}
 
 
bool PCB_VIA::HasValidLayerPair( int aCopperLayerCount ) const
{
    // return true if top and bottom layers are valid, depending on the copper layer count
    // aCopperLayerCount is expected >= 2
 
    int layer_id = aCopperLayerCount*2;
 
    if( Padstack().Drill().start > B_Cu )
    {
        if( Padstack().Drill().start > layer_id )
            return false;
    }
    if( Padstack().Drill().end > B_Cu )
    {
        if( Padstack().Drill().end > layer_id )
            return false;
    }
 
    return true;
}
 
 
PCB_LAYER_ID PCB_VIA::GetLayer() const
{
    return Padstack().Drill().start;
}
 
 
void PCB_VIA::SetLayer( PCB_LAYER_ID aLayer )
{
     Padstack().Drill().start = aLayer;
}
 
 
void PCB_TRACK::SetLayerSet( const LSET& aLayerSet )
{
    aLayerSet.RunOnLayers(
            [&]( PCB_LAYER_ID layer )
            {
                if( IsCopperLayer( layer ) )
                    SetLayer( layer );
                else if( IsSolderMaskLayer( layer ) )
                    SetHasSolderMask( true );
            } );
}
 
 
LSET PCB_TRACK::GetLayerSet() const
{
    LSET layermask( { m_layer } );
 
    if( m_hasSolderMask )
    {
        if( layermask.test( F_Cu ) )
            layermask.set( F_Mask );
        else if( layermask.test( B_Cu ) )
            layermask.set( B_Mask );
    }
 
    return layermask;
}
 
 
LSET PCB_VIA::GetLayerSet() const
{
    LSET layermask;
 
    if( Padstack().Drill().start < PCBNEW_LAYER_ID_START )
        return layermask;
 
    if( GetViaType() == VIATYPE::THROUGH )
    {
        layermask = LSET::AllCuMask( BoardCopperLayerCount() );
    }
    else
    {
        LAYER_RANGE range( Padstack().Drill().start, Padstack().Drill().end, BoardCopperLayerCount() );
 
        int cnt = BoardCopperLayerCount();
        // PCB_LAYER_IDs are numbered from front to back, this is top to bottom.
        for( PCB_LAYER_ID id : range )
        {
            layermask.set( id );
 
            if( --cnt <= 0 )
                break;
        }
    }
 
    if( !IsTented( F_Mask ) && layermask.test( F_Cu ) )
        layermask.set( F_Mask );
 
    if( !IsTented( B_Mask ) && layermask.test( B_Cu ) )
        layermask.set( B_Mask );
 
    return layermask;
}
 
 
void PCB_VIA::SetLayerSet( const LSET& aLayerSet )
{
    // Vias do not use a LSET, just a top and bottom layer pair
    // So we need to set these 2 layers according to the allowed layers in aLayerSet
 
    // For via through, only F_Cu and B_Cu are allowed. aLayerSet is ignored
    if( GetViaType() == VIATYPE::THROUGH )
    {
        Padstack().Drill().start = F_Cu;
        Padstack().Drill().end = B_Cu;
        return;
    }
 
    // For blind buried vias, find the top and bottom layers
    bool top_found = false;
    bool bottom_found = false;
 
    aLayerSet.RunOnLayers(
            [&]( PCB_LAYER_ID layer )
            {
                // tpo layer and bottom Layer are copper layers, so consider only copper layers
                if( IsCopperLayer( layer ) )
                {
                    // The top layer is the first layer found in list and
                    // cannot the B_Cu
                    if( !top_found && layer != B_Cu )
                    {
                        Padstack().Drill().start = layer;
                        top_found = true;
                    }
 
                    // The bottom layer is the last layer found in list or B_Cu
                    if( !bottom_found )
                        Padstack().Drill().end = layer;
 
                    if( layer == B_Cu )
                        bottom_found = true;
                }
            } );
}
 
 
void PCB_VIA::SetLayerPair( PCB_LAYER_ID aTopLayer, PCB_LAYER_ID aBottomLayer )
{
    Padstack().Drill().start = aTopLayer;
    Padstack().Drill().end = aBottomLayer;
    SanitizeLayers();
 
    if( !( GetFlags() & ROUTER_TRANSIENT ) )
    {
        if( BOARD* board = GetBoard() )
            board->InvalidateClearanceCache( m_Uuid );
    }
}
 
 
void PCB_VIA::SetTopLayer( PCB_LAYER_ID aLayer )
{
    // refuse invalid via
    if( aLayer == Padstack().Drill().end )
        return;
 
    Padstack().Drill().start = aLayer;
    SanitizeLayers();
 
    if( !( GetFlags() & ROUTER_TRANSIENT ) )
    {
        if( BOARD* board = GetBoard() )
            board->InvalidateClearanceCache( m_Uuid );
    }
}
 
 
void PCB_VIA::SetBottomLayer( PCB_LAYER_ID aLayer )
{
    // refuse invalid via
    if( aLayer == Padstack().Drill().start )
        return;
 
    Padstack().Drill().end = aLayer;
    SanitizeLayers();
 
    if( !( GetFlags() & ROUTER_TRANSIENT ) )
    {
        if( BOARD* board = GetBoard() )
            board->InvalidateClearanceCache( m_Uuid );
    }
}
 
 
void PCB_VIA::LayerPair( PCB_LAYER_ID* top_layer, PCB_LAYER_ID* bottom_layer ) const
{
    PCB_LAYER_ID t_layer = F_Cu;
    PCB_LAYER_ID b_layer = B_Cu;
 
    if( GetViaType() != VIATYPE::THROUGH )
    {
        b_layer = Padstack().Drill().end;
        t_layer = Padstack().Drill().start;
 
        if( !IsCopperLayerLowerThan( b_layer, t_layer ) )
            std::swap( b_layer, t_layer );
    }
 
    if( top_layer )
        *top_layer = t_layer;
 
    if( bottom_layer )
        *bottom_layer = b_layer;
}
 
 
PCB_LAYER_ID PCB_VIA::TopLayer() const
{
    return Padstack().Drill().start;
}
 
 
PCB_LAYER_ID PCB_VIA::BottomLayer() const
{
    return Padstack().Drill().end;
}
 
 
void PCB_VIA::SanitizeLayers()
{
    if( GetViaType() == VIATYPE::THROUGH )
    {
        Padstack().Drill().start = F_Cu;
        Padstack().Drill().end = B_Cu;
    }
 
    if( !IsCopperLayerLowerThan( Padstack().Drill().end, Padstack().Drill().start) )
        std::swap( Padstack().Drill().end, Padstack().Drill().start );
 
    int copperCount = BoardCopperLayerCount();
 
    auto sanitizeBackdrill =
            [copperCount]( PADSTACK::DRILL_PROPS& aDrill )
            {
                if( aDrill.start != UNDEFINED_LAYER && !IsCopperLayer( aDrill.start ) )
                    aDrill.start = UNDEFINED_LAYER;
 
                if( aDrill.end != UNDEFINED_LAYER && !IsCopperLayer( aDrill.end ) )
                    aDrill.end = UNDEFINED_LAYER;
 
                if( copperCount > 0 )
                {
                    LSET cuMask = LSET::AllCuMask( copperCount );
 
                    if( aDrill.start != UNDEFINED_LAYER && !cuMask.Contains( aDrill.start ) )
                        aDrill.start = UNDEFINED_LAYER;
 
                    if( aDrill.end != UNDEFINED_LAYER && !cuMask.Contains( aDrill.end ) )
                        aDrill.end = UNDEFINED_LAYER;
                }
 
                // A backdrill side with no must-cut layer does not exist.
                if( aDrill.end == UNDEFINED_LAYER )
                    aDrill.size = { 0, 0 };
            };
 
    sanitizeBackdrill( Padstack().SecondaryDrill() );
    sanitizeBackdrill( Padstack().TertiaryDrill() );
}
 
 
std::optional<PCB_VIA::VIA_PARAMETER_ERROR>
PCB_VIA::ValidateViaParameters( std::optional<int> aDiameter,
                                std::optional<int> aPrimaryDrill,
                                std::optional<PCB_LAYER_ID> aPrimaryStartLayer,
                                std::optional<PCB_LAYER_ID> aPrimaryEndLayer,
                                std::optional<int> aSecondaryDrill,
                                std::optional<PCB_LAYER_ID> aSecondaryStartLayer,
                                std::optional<PCB_LAYER_ID> aSecondaryEndLayer,
                                std::optional<int> aTertiaryDrill,
                                std::optional<PCB_LAYER_ID> aTertiaryStartLayer,
                                std::optional<PCB_LAYER_ID> aTertiaryEndLayer,
                                int aCopperLayerCount )
{
    VIA_PARAMETER_ERROR error;
 
    if( aDiameter.has_value() && aDiameter.value() < GEOMETRY_MIN_SIZE )
    {
        error.m_Message = _( "Via diameter is too small." );
        error.m_Field = VIA_PARAMETER_ERROR::FIELD::DIAMETER;
        return error;
    }
 
    if( aPrimaryDrill.has_value() && aPrimaryDrill.value() < GEOMETRY_MIN_SIZE )
    {
        error.m_Message = _( "Via drill is too small." );
        error.m_Field = VIA_PARAMETER_ERROR::FIELD::DRILL;
        return error;
    }
 
    if( aDiameter.has_value() && !aPrimaryDrill.has_value() )
    {
        error.m_Message = _( "No via hole size defined." );
        error.m_Field = VIA_PARAMETER_ERROR::FIELD::DRILL;
        return error;
    }
 
    if( aPrimaryDrill.has_value() && !aDiameter.has_value() )
    {
        error.m_Message = _( "No via diameter defined." );
        error.m_Field = VIA_PARAMETER_ERROR::FIELD::DIAMETER;
        return error;
    }
 
    if( aDiameter.has_value() && aPrimaryDrill.has_value()
            && aDiameter.value() <= aPrimaryDrill.value() )
    {
        error.m_Message = _( "Via hole size must be smaller than via diameter" );
        error.m_Field = VIA_PARAMETER_ERROR::FIELD::DRILL;
        return error;
    }
 
    std::optional<LSET> copperMask;
 
    auto validateLayer = [&]( std::optional<PCB_LAYER_ID> aLayer,
                              VIA_PARAMETER_ERROR::FIELD aField ) -> bool
    {
        if( !aLayer.has_value() )
            return true;
 
        PCB_LAYER_ID layer = aLayer.value();
 
        if( layer == UNDEFINED_LAYER )
            return true;
 
        if( !IsCopperLayer( layer ) )
        {
            error.m_Message = _( "Via layer must be a copper layer." );
            error.m_Field = aField;
            return false;
        }
 
        if( aCopperLayerCount > 0 )
        {
            if( !copperMask.has_value() )
                copperMask = LSET::AllCuMask( aCopperLayerCount );
 
            if( !copperMask->Contains( layer ) )
            {
                error.m_Message = _( "Via layer is outside the board stack." );
                error.m_Field = aField;
                return false;
            }
        }
 
        return true;
    };
 
    if( !validateLayer( aPrimaryStartLayer, VIA_PARAMETER_ERROR::FIELD::START_LAYER ) )
        return error;
 
    if( !validateLayer( aPrimaryEndLayer, VIA_PARAMETER_ERROR::FIELD::END_LAYER ) )
        return error;
 
    if( aPrimaryStartLayer.has_value() && aPrimaryEndLayer.has_value()
            && aPrimaryStartLayer.value() == aPrimaryEndLayer.value() )
    {
        error.m_Message = _( "Via start layer and end layer cannot be the same" );
        error.m_Field = VIA_PARAMETER_ERROR::FIELD::START_LAYER;
        return error;
    }
 
    if( aSecondaryDrill.has_value() )
    {
        if( aSecondaryDrill.value() < aPrimaryDrill.value_or( GEOMETRY_MIN_SIZE ) )
        {
            error.m_Message = _( "Backdrill diameter is too small." );
            error.m_Field = VIA_PARAMETER_ERROR::FIELD::SECONDARY_DRILL;
            return error;
        }
 
        if( !validateLayer( aSecondaryStartLayer, VIA_PARAMETER_ERROR::FIELD::SECONDARY_START_LAYER ) )
            return error;
 
        if( !validateLayer( aSecondaryEndLayer, VIA_PARAMETER_ERROR::FIELD::SECONDARY_END_LAYER ) )
            return error;
    }
 
    if( aTertiaryDrill.has_value() )
    {
        if( aTertiaryDrill.value() < aPrimaryDrill.value_or( GEOMETRY_MIN_SIZE ) )
        {
            error.m_Message = _( "Tertiary backdrill diameter is too small." );
            error.m_Field = VIA_PARAMETER_ERROR::FIELD::TERTIARY_DRILL;
            return error;
        }
 
        if( !validateLayer( aTertiaryStartLayer, VIA_PARAMETER_ERROR::FIELD::TERTIARY_START_LAYER ) )
            return error;
 
        if( !validateLayer( aTertiaryEndLayer, VIA_PARAMETER_ERROR::FIELD::TERTIARY_END_LAYER ) )
            return error;
    }
 
    return std::nullopt;
}
 
 
bool PCB_VIA::IsMicroVia() const
{
    return m_viaType == VIATYPE::MICROVIA;
}
 
 
bool PCB_VIA::IsBlindVia() const
{
    // We don't actually have an GUI or file tokens to differentiate these, so we have to look at
    // the layers.
    if( m_viaType == VIATYPE::BLIND || m_viaType == VIATYPE::BURIED )
    {
        bool startOuter = Padstack().Drill().start == F_Cu || Padstack().Drill().start == B_Cu;
        bool endOuter = Padstack().Drill().end == F_Cu || Padstack().Drill().end == B_Cu;
 
        return startOuter ^ endOuter;
    }
 
    return false;
}
 
 
bool PCB_VIA::IsBuriedVia() const
{
    // We don't actually have an GUI or file tokens to differentiate these, so we have to look at
    // the layers.
    if( m_viaType == VIATYPE::BLIND || m_viaType == VIATYPE::BURIED )
    {
        return Padstack().Drill().start != F_Cu && Padstack().Drill().start != B_Cu
                && Padstack().Drill().end != F_Cu && Padstack().Drill().end != B_Cu;
    }
 
    return false;
}
 
 
bool PCB_VIA::IsGhostLayer( PCB_LAYER_ID aLayer ) const
{
    if( ( m_viaType == VIATYPE::MICROVIA || m_viaType == VIATYPE::BLIND || m_viaType == VIATYPE::BURIED )
            && m_padStack.Mode() == PADSTACK::MODE::FRONT_INNER_BACK )
    {
        switch( aLayer )
        {
        case F_Cu:
            if( Padstack().Drill().start != F_Cu )
                return true;
 
            break;
 
        case B_Cu:
            if( Padstack().Drill().end !=  B_Cu )
                return true;
 
            break;
 
        case PADSTACK::INNER_LAYERS:
            if( GetBoard() && GetBoard()->GetCopperLayerCount() == 2 )
                return true;
 
            break;
 
        default:
            wxFAIL_MSG( wxT( "Unsupported layer for FRONT_INNER_BACK" ) );
        }
    }
 
    return false;
}
 
 
bool PCB_VIA::FlashLayer( const LSET& aLayers ) const
{
    for( PCB_LAYER_ID layer : aLayers )
    {
        if( FlashLayer( layer ) )
            return true;
    }
 
    return false;
}
 
 
bool PCB_VIA::FlashLayer( int aLayer ) const
{
    // Return the "normal" shape if the caller doesn't specify a particular layer
    if( aLayer == UNDEFINED_LAYER )
        return true;
 
    const BOARD* board = GetBoard();
    PCB_LAYER_ID layer = static_cast<PCB_LAYER_ID>( aLayer );
 
    if( !board )
        return true;
 
    if( !IsOnLayer( layer ) )
        return false;
 
    if( !IsCopperLayer( layer ) )
        return true;
 
    switch( Padstack().UnconnectedLayerMode() )
    {
    case UNCONNECTED_LAYER_MODE::KEEP_ALL:
        return true;
 
    case UNCONNECTED_LAYER_MODE::REMOVE_EXCEPT_START_AND_END:
        if( layer == Padstack().Drill().start || layer == Padstack().Drill().end )
            return true;
 
        // Check for removal below
        break;
 
    case UNCONNECTED_LAYER_MODE::REMOVE_ALL:
        // Check for removal below
        break;
 
    case UNCONNECTED_LAYER_MODE::START_END_ONLY:
        return layer == Padstack().Drill().start || layer == Padstack().Drill().end;
    }
 
    if( GetZoneLayerOverride( layer ) == ZLO_FORCE_FLASHED )
    {
        return true;
    }
    else
    {
        // Must be static to keep from raising its ugly head in performance profiles
        static std::initializer_list<KICAD_T> nonZoneTypes = { PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T,
                                                               PCB_PAD_T };
 
        return board->GetConnectivity()->IsConnectedOnLayer( this, layer, nonZoneTypes );
    }
}
 
 
// IsCopperLayer() accepts any even id below PCB_LAYER_ID_COUNT, but only F_Cu..In30_Cu carry a
// distinct ordinal.  Anything above aliases B_Cu or indexes past the override array
static bool hasLayerOrdinal( PCB_LAYER_ID aLayer )
{
    return IsCopperLayer( aLayer ) && aLayer <= In30_Cu;
}
 
 
void PCB_VIA::ClearZoneLayerOverrides()
{
    for( std::atomic<ZONE_LAYER_OVERRIDE>& entry : m_zoneLayerOverrides )
        entry.store( ZLO_NONE, std::memory_order_relaxed );
}
 
 
ZONE_LAYER_OVERRIDE PCB_VIA::GetZoneLayerOverride( PCB_LAYER_ID aLayer ) const
{
    if( !hasLayerOrdinal( aLayer ) )
        return ZLO_NONE;
 
    return m_zoneLayerOverrides[CopperLayerToOrdinal( aLayer )].load( std::memory_order_relaxed );
}
 
 
void PCB_VIA::SetZoneLayerOverride( PCB_LAYER_ID aLayer, ZONE_LAYER_OVERRIDE aOverride )
{
    if( !hasLayerOrdinal( aLayer ) )
        return;
 
    m_zoneLayerOverrides[CopperLayerToOrdinal( aLayer )].store( aOverride, std::memory_order_relaxed );
}
 
 
void PCB_VIA::GetOutermostConnectedLayers( PCB_LAYER_ID* aTopmost,
                                           PCB_LAYER_ID* aBottommost ) const
{
    *aTopmost = UNDEFINED_LAYER;
    *aBottommost = UNDEFINED_LAYER;
 
    static std::initializer_list<KICAD_T> nonZoneTypes = { PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T,
                                                           PCB_PAD_T };
 
    for( int layer = TopLayer(); layer <= BottomLayer(); ++layer )
    {
        bool connected = false;
 
        if( GetZoneLayerOverride( static_cast<PCB_LAYER_ID>( layer ) ) == ZLO_FORCE_FLASHED )
        {
            connected = true;
        }
        else if( GetBoard()->GetConnectivity()->IsConnectedOnLayer( this, layer, nonZoneTypes ) )
        {
            connected = true;
        }
 
        if( connected )
        {
            if( *aTopmost == UNDEFINED_LAYER )
                *aTopmost = ToLAYER_ID( layer );
 
            *aBottommost = ToLAYER_ID( layer );
        }
    }
 
}
 
 
std::vector<int> PCB_TRACK::ViewGetLayers() const
{
    // Show the track and its netname on different layers
    const PCB_LAYER_ID layer = GetLayer();
    std::vector<int>   layers{
        layer,
        GetNetnameLayer( layer ),
        LAYER_CLEARANCE_START + layer,
    };
 
    layers.reserve( 6 );
 
    if( m_hasSolderMask )
    {
        if( m_layer == F_Cu )
            layers.push_back( F_Mask );
        else if( m_layer == B_Cu )
            layers.push_back( B_Mask );
    }
 
    if( IsLocked() )
        layers.push_back( LAYER_LOCKED_ITEM_SHADOW );
 
    return layers;
}
 
 
double PCB_TRACK::ViewGetLOD( int aLayer, const KIGFX::VIEW* aView ) const
{
    PCB_PAINTER*         painter = static_cast<PCB_PAINTER*>( aView->GetPainter() );
    PCB_RENDER_SETTINGS* renderSettings = painter->GetSettings();
 
    if( !aView->IsLayerVisibleCached( LAYER_TRACKS ) )
        return LOD_HIDE;
 
    if( IsNetnameLayer( aLayer ) )
    {
        if( GetNetCode() <= NETINFO_LIST::UNCONNECTED )
            return LOD_HIDE;
 
        // Hide netnames on dimmed tracks
        if( renderSettings->GetHighContrast() )
        {
            if( m_layer != renderSettings->GetPrimaryHighContrastLayer() )
                return LOD_HIDE;
        }
 
        VECTOR2I start( GetStart() );
        VECTOR2I end( GetEnd() );
 
        // Calc the approximate size of the netname (assume square chars)
        SEG::ecoord nameSize = GetDisplayNetname().size() * GetWidth();
 
        if( VECTOR2I( end - start ).SquaredEuclideanNorm() < nameSize * nameSize )
            return LOD_HIDE;
 
        BOX2I clipBox = BOX2ISafe( aView->GetViewport() );
 
        ClipLine( &clipBox, start.x, start.y, end.x, end.y );
 
        if( VECTOR2I( end - start ).SquaredEuclideanNorm() == 0 )
            return LOD_HIDE;
 
        // Netnames will be shown only if zoom is appropriate
        return lodScaleForThreshold( aView, m_width, pcbIUScale.mmToIU( 4.0 ) );
    }
 
    if( aLayer == LAYER_LOCKED_ITEM_SHADOW )
    {
        // Hide shadow if the main layer is not shown
        if( !aView->IsLayerVisibleCached( m_layer ) )
            return LOD_HIDE;
 
        // Hide shadow on dimmed tracks
        if( renderSettings->GetHighContrast() )
        {
            if( m_layer != renderSettings->GetPrimaryHighContrastLayer() )
                return LOD_HIDE;
        }
    }
 
    // Other layers are shown without any conditions
    return LOD_SHOW;
}
 
 
const BOX2I PCB_TRACK::ViewBBox() const
{
    BOX2I bbox = GetBoundingBox();
 
    if( const BOARD* board = GetBoard() )
    {
        bbox.Inflate( 2 * board->GetDesignSettings().GetBiggestClearanceValue() );
 
        // Only a via drills, so a plain segment would just be given an oversized box
        if( HasHole() )
            bbox = board->ExpandBoundingBoxForDrillSymbols( bbox );
    }
    else
    {
        bbox.Inflate( GetWidth() );     // Add a bit extra for safety
    }
 
    return bbox;
}
 
 
std::vector<int> PCB_VIA::ViewGetLayers() const
{
    LAYER_RANGE layers( Padstack().Drill().start, Padstack().Drill().end, MAX_CU_LAYERS );
    std::vector<int> ret_layers{ LAYER_VIA_HOLES, LAYER_VIA_HOLEWALLS, LAYER_VIA_NETNAMES };
    ret_layers.reserve( MAX_CU_LAYERS + 6 );
 
    // A drill map on a layer asks the holes to draw their symbols there, so the symbols stay
    // in the view index and one hole edit repaints one hole
    if( const BOARD* drillBoard = GetBoard() )
    {
        for( PCB_LAYER_ID mapLayer : drillBoard->DrillSymbolLayers().Seq() )
            ret_layers.push_back( DRILL_SYMBOL_LAYER_FOR( mapLayer ) );
    }
 
    // TODO(JE) Rendering order issue
#if 0
    // Blind/buried vias (and microvias) use a different net name layer
    PCB_LAYER_ID layerTop, layerBottom;
    LayerPair( &layerTop, &layerBottom );
 
    bool isBlindBuried =
            m_viaType == VIATYPE::BLIND
            || m_viaType == VIATYPE::BURIED
            || ( m_viaType == VIATYPE::MICROVIA && ( layerTop != F_Cu || layerBottom != B_Cu ) );
#endif
    LSET cuMask = LSET::AllCuMask();
 
    if( const BOARD* board = GetBoard() )
        cuMask &= board->GetEnabledLayers();
 
    for( PCB_LAYER_ID layer : layers )
    {
        if( !cuMask.Contains( layer ) )
            continue;
 
        ret_layers.push_back( LAYER_VIA_COPPER_START + layer );
        ret_layers.push_back( LAYER_CLEARANCE_START + layer );
    }
 
    if( IsLocked() )
        ret_layers.push_back( LAYER_LOCKED_ITEM_SHADOW );
 
    // Vias can also be on a solder mask layer. They are on these layers or not,
    // depending on the plot and solder mask options
    if( IsOnLayer( F_Mask ) )
        ret_layers.push_back( F_Mask );
 
    if( IsOnLayer( B_Mask ) )
        ret_layers.push_back( B_Mask );
 
    return ret_layers;
}
 
 
double PCB_VIA::ViewGetLOD( int aLayer, const KIGFX::VIEW* aView ) const
{
    PCB_PAINTER*         painter = static_cast<PCB_PAINTER*>( aView->GetPainter() );
    PCB_RENDER_SETTINGS* renderSettings = painter->GetSettings();
    const BOARD*         board = GetBoard();
 
    // Reviewing a drill drawing with vias hidden is normal, so the symbols answer to the
    // map's own layer rather than to the vias meta control
    if( IsDrillSymbolLayer( aLayer ) )
    {
        return aView->IsLayerVisibleCached( aLayer - LAYER_DRILL_SYMBOL_START ) ? LOD_SHOW
                                                                                : LOD_HIDE;
    }
 
    // Meta control for hiding all vias
    if( !aView->IsLayerVisibleCached( LAYER_VIAS ) )
        return LOD_HIDE;
 
    // In high contrast mode don't show vias that don't cross the high-contrast layer
    if( renderSettings->GetHighContrast() )
    {
        PCB_LAYER_ID highContrastLayer = renderSettings->GetPrimaryHighContrastLayer();
 
        if( LSET::FrontTechMask().Contains( highContrastLayer ) )
            highContrastLayer = F_Cu;
        else if( LSET::BackTechMask().Contains( highContrastLayer ) )
            highContrastLayer = B_Cu;
 
        if( IsCopperLayer( highContrastLayer ) && GetViaType() != VIATYPE::THROUGH )
        {
            if( IsCopperLayerLowerThan( Padstack().Drill().start, highContrastLayer  )
                || IsCopperLayerLowerThan( highContrastLayer, Padstack().Drill().end ) )
            {
                return LOD_HIDE;
            }
        }
    }
 
    if( IsHoleLayer( aLayer ) )
    {
        LSET visible;
 
        if( board )
        {
            visible = board->GetVisibleLayers();
            visible &= board->GetEnabledLayers();
        }
        else
        {
            visible = LSET::AllLayersMask();
        }
 
        if( m_viaType == VIATYPE::THROUGH )
        {
            // Show a through via's hole if any physical layer is shown
            visible &= LSET::PhysicalLayersMask();
 
            if( !visible.any() )
                return LOD_HIDE;
        }
        else
        {
            // Show a blind or micro via's hole if it crosses a visible layer
            visible &= GetLayerSet();
 
            if( !visible.any() )
                return LOD_HIDE;
        }
 
        // The hole won't be visible anyway at this scale
        return lodScaleForThreshold( aView, GetDrillValue(), pcbIUScale.mmToIU( 0.25 ) );
    }
    else if( IsNetnameLayer( aLayer ) )
    {
        if( renderSettings->GetHighContrast() )
        {
            // Hide netnames unless via is flashed to a high-contrast layer
            if( !FlashLayer( renderSettings->GetPrimaryHighContrastLayer() ) )
                return LOD_HIDE;
        }
        else
        {
            LSET visible;
 
            if( board )
            {
                visible = board->GetVisibleLayers();
                visible &= board->GetEnabledLayers();
            }
            else
            {
                visible = LSET::AllLayersMask();
            }
 
            // Hide netnames unless pad is flashed to a visible layer
            if( !FlashLayer( visible ) )
                return LOD_HIDE;
        }
 
        int width = GetWidth( ToLAYER_ID( aLayer ) );
 
        // Netnames will be shown only if zoom is appropriate
        return lodScaleForThreshold( aView, width, pcbIUScale.mmToIU( 10 ) );
    }
 
    if( !IsCopperLayer( aLayer ) )
    {
        int width = GetWidth( ToLAYER_ID( aLayer ) );
 
        return lodScaleForThreshold( aView, width, pcbIUScale.mmToIU( 0.6 ) );
    }
 
    return LOD_SHOW;
}
 
 
wxString PCB_TRACK::GetFriendlyName() const
{
    switch( Type() )
    {
    case PCB_ARC_T:     return _( "Track (arc)" );
    case PCB_VIA_T:     return _( "Via" );
    case PCB_TRACE_T:
    default:            return _( "Track" );
    }
}
 
 
void PCB_TRACK::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>& aList )
{
    wxString  msg;
    BOARD*    board = GetBoard();
 
    aList.emplace_back( _( "Type" ), GetFriendlyName() );
 
    GetMsgPanelInfoBase_Common( aFrame, aList );
 
    aList.emplace_back( _( "Layer" ), LayerMaskDescribe() );
 
    aList.emplace_back( _( "Width" ), aFrame->MessageTextFromValue( m_width ) );
 
    if( Type() == PCB_ARC_T )
    {
        double radius = static_cast<PCB_ARC*>( this )->GetRadius();
        aList.emplace_back( _( "Radius" ), aFrame->MessageTextFromValue( radius ) );
 
        aList.emplace_back( _( "Angle" ), wxString::Format( "%.2fdeg",
                            static_cast<PCB_ARC*>(this)->GetAngle().AsDegrees() ) );
    }
 
    double segmentLength = GetLength();
    double segmentDelay = GetDelay();
 
    if( segmentDelay == 0.0 )
    {
        aList.emplace_back( _( "Segment Length" ), aFrame->MessageTextFromValue( segmentLength ) );
    }
    else
    {
        aList.emplace_back( _( "Segment Delay" ),
                            aFrame->MessageTextFromValue( segmentDelay, true, EDA_DATA_TYPE::TIME ) );
    }
 
    // Display full track length (in Pcbnew)
    if( board && GetNetCode() > 0 )
    {
        int    count = 0;
        double trackLen = 0.0;
        double lenPadToDie = 0.0;
        double trackDelay = 0.0;
        double delayPadToDie = 0.0;
 
        std::tie( count, trackLen, lenPadToDie, trackDelay, delayPadToDie ) = board->GetTrackLength( *this );
 
        if( trackDelay == 0.0 )
        {
            aList.emplace_back( _( "Routed Length" ), aFrame->MessageTextFromValue( trackLen ) );
 
            if( lenPadToDie != 0 )
            {
                msg = aFrame->MessageTextFromValue( lenPadToDie );
                aList.emplace_back( _( "Pad To Die Length" ), msg );
 
                msg = aFrame->MessageTextFromValue( trackLen + lenPadToDie );
                aList.emplace_back( _( "Full Length" ), msg );
            }
        }
        else
        {
            aList.emplace_back( _( "Routed Delay" ),
                                aFrame->MessageTextFromValue( trackDelay, true, EDA_DATA_TYPE::TIME ) );
 
            if( delayPadToDie != 0.0 )
            {
                msg = aFrame->MessageTextFromValue( delayPadToDie, true, EDA_DATA_TYPE::TIME );
                aList.emplace_back( _( "Pad To Die Delay" ), msg );
 
                msg = aFrame->MessageTextFromValue( trackDelay + delayPadToDie, true, EDA_DATA_TYPE::TIME );
                aList.emplace_back( _( "Full Delay" ), msg );
            }
        }
    }
 
    SHAPE_POLY_SET copper;
    TransformShapeToPolySet( copper, GetLayer(), 0, ARC_LOW_DEF, ERROR_INSIDE );
    aList.emplace_back( _( "Copper Area" ),
                        aFrame->MessageTextFromValue( copper.Area(), true, EDA_DATA_TYPE::AREA ) );
 
    wxString source;
    int clearance = GetOwnClearance( GetLayer(), &source );
 
    aList.emplace_back( wxString::Format( _( "Min Clearance: %s" ),
                                          aFrame->MessageTextFromValue( clearance ) ),
                        wxString::Format( _( "(from %s)" ), source ) );
 
    MINOPTMAX<int> constraintValue = GetWidthConstraint( &source );
    msg = aFrame->MessageTextFromMinOptMax( constraintValue );
 
    if( !msg.IsEmpty() )
    {
        aList.emplace_back( wxString::Format( _( "Width Constraints: %s" ), msg ),
                            wxString::Format( _( "(from %s)" ), source ) );
    }
}
 
 
void PCB_VIA::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>& aList )
{
    wxString  msg;
 
    switch( GetViaType() )
    {
    case VIATYPE::MICROVIA:     msg = _( "Micro Via" );    break;
    case VIATYPE::BLIND:        msg = _( "Blind Via" );    break;
    case VIATYPE::BURIED:       msg = _( "Buried Via" );   break;
    case VIATYPE::THROUGH:      msg = _( "Through Via" );  break;
    default:                    msg = _( "Via" );          break;
    }
 
    aList.emplace_back( _( "Type" ), msg );
 
    GetMsgPanelInfoBase_Common( aFrame, aList );
 
    aList.emplace_back( _( "Layer" ), LayerMaskDescribe() );
 
    std::set<int> widths;
    m_padStack.ForEachUniqueLayer(
            [&]( PCB_LAYER_ID aLayer )
            {
                if( IsGhostLayer( aLayer ) )
                    return;
 
                widths.insert( GetWidth( aLayer ) );
            } );
 
    if( widths.size() == 1 )
        aList.emplace_back( _( "Diameter" ), aFrame->MessageTextFromValue( *widths.begin() ) );
    else
        aList.emplace_back( _( "Diameter" ), _( "(mixed)" ) );
 
    aList.emplace_back( _( "Hole" ), aFrame->MessageTextFromValue( GetDrillValue() ) );
 
    wxString  source;
    int clearance = GetOwnClearance( GetLayer(), &source );
 
    aList.emplace_back( wxString::Format( _( "Min Clearance: %s" ), aFrame->MessageTextFromValue( clearance ) ),
                        wxString::Format( _( "(from %s)" ), source ) );
 
    int minAnnulus = GetMinAnnulus( GetLayer(), &source );
 
    aList.emplace_back( wxString::Format( _( "Min Annular Width: %s" ), aFrame->MessageTextFromValue( minAnnulus ) ),
                        wxString::Format( _( "(from %s)" ), source ) );
}
 
 
void PCB_TRACK::GetMsgPanelInfoBase_Common( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>& aList ) const
{
    aList.emplace_back( _( "Net" ), UnescapeString( GetNetname() ) );
 
    if( NETINFO_ITEM* netInfo = GetNet() )
    {
        const wxString& chainName = netInfo->GetNetChain();
 
        if( !chainName.IsEmpty() )
            aList.emplace_back( _( "Net Chain" ), UnescapeString( chainName ) );
    }
 
    aList.emplace_back( _( "Resolved Netclass" ),
                        UnescapeString( GetEffectiveNetClass()->GetHumanReadableName() ) );
 
#if 0   // Enable for debugging
    if( GetBoard() )
        aList.emplace_back( _( "NetCode" ), fmt::format( "{}", GetNetCode() ) );
 
    aList.emplace_back( wxT( "Flags" ), fmt::format( "#08X", m_flags ) );
 
    aList.emplace_back( wxT( "Start pos" ), fmt::format( "{} {}", m_Start.x, m_Start.y ) );
    aList.emplace_back( wxT( "End pos" ), fmt::format( "{} {}", m_End.x, m_End.y ) );
#endif
 
    if( aFrame->GetName() == PCB_EDIT_FRAME_NAME && IsLocked() )
        aList.emplace_back( _( "Status" ), _( "Locked" ) );
}
 
 
wxString PCB_VIA::LayerMaskDescribe() const
{
    const BOARD* board = GetBoard();
    PCB_LAYER_ID top_layer;
    PCB_LAYER_ID bottom_layer;
 
    LayerPair( &top_layer, &bottom_layer );
 
    return board->GetLayerName( top_layer ) + wxT( " - " ) + board->GetLayerName( bottom_layer );
}
 
 
double PCB_TRACK::GetCoverageArea( int aTextMargin ) const
{
    // Width squared, so a long track does not outrank a short one it happens to cross
    const double width = GetWidth();
    return width * width;
}
 
 
bool PCB_TRACK::HitTest( const VECTOR2I& aPosition, int aAccuracy ) const
{
    return TestSegmentHit( aPosition, m_Start, m_End, aAccuracy + ( m_width / 2 ) );
}
 
 
bool PCB_ARC::HitTest( const VECTOR2I& aPosition, int aAccuracy ) const
{
    double max_dist = aAccuracy + ( GetWidth() / 2.0 );
 
    // Short-circuit common cases where the arc is connected to a track or via at an endpoint
    if( GetStart().Distance( aPosition ) <= max_dist || GetEnd().Distance( aPosition ) <= max_dist )
    {
        return true;
    }
 
    VECTOR2L center = GetPosition();
    VECTOR2L relpos = aPosition - center;
    int64_t dist = relpos.EuclideanNorm();
    double radius = GetRadius();
 
    if( std::abs( dist - radius ) > max_dist )
        return false;
 
    EDA_ANGLE arc_angle = GetAngle();
    EDA_ANGLE arc_angle_start = GetArcAngleStart();    // Always 0.0 ... 360 deg
    EDA_ANGLE arc_hittest( relpos );
 
    // Calculate relative angle between the starting point of the arc, and the test point
    arc_hittest -= arc_angle_start;
 
    // Normalise arc_hittest between 0 ... 360 deg
    arc_hittest.Normalize();
 
    if( arc_angle < ANGLE_0 )
        return arc_hittest >= ANGLE_360 + arc_angle;
 
    return arc_hittest <= arc_angle;
}
 
 
double PCB_VIA::GetCoverageArea( int aTextMargin ) const
{
    // A via covers its pad, so the width rule it inherits from tracks does not apply
    return BOARD_ITEM::GetCoverageArea( aTextMargin );
}
 
 
bool PCB_VIA::HitTest( const VECTOR2I& aPosition, int aAccuracy ) const
{
    bool hit = false;
 
    Padstack().ForEachUniqueLayer(
            [&]( PCB_LAYER_ID aLayer )
            {
                if( hit )
                    return;
 
                if( IsGhostLayer( aLayer ) )
                    return;
 
                int max_dist = aAccuracy + ( GetWidth( aLayer ) / 2 );
 
                // rel_pos is aPosition relative to m_Start (or the center of the via)
                VECTOR2D rel_pos = aPosition - m_Start;
                double dist = rel_pos.x * rel_pos.x + rel_pos.y * rel_pos.y;
 
                if( dist <= static_cast<double>( max_dist ) * max_dist )
                    hit = true;
            } );
 
    return hit;
}
 
 
bool PCB_TRACK::HitTest( const BOX2I& aRect, bool aContained, int aAccuracy ) const
{
    BOX2I arect = aRect;
    arect.Inflate( aAccuracy );
 
    if( aContained )
        return arect.Contains( GetStart() ) && arect.Contains( GetEnd() );
    else
        return arect.Intersects( GetStart(), GetEnd() );
}
 
 
bool PCB_ARC::HitTest( const BOX2I& aRect, bool aContained, int aAccuracy ) const
{
    BOX2I arect = aRect;
    arect.Inflate( aAccuracy );
 
    BOX2I box( GetStart() );
    box.Merge( GetMid() );
    box.Merge( GetEnd() );
 
    box.Inflate( GetWidth() / 2 );
 
    if( aContained )
        return arect.Contains( box );
    else
        return arect.Intersects( box );
}
 
 
bool PCB_VIA::HitTest( const BOX2I& aRect, bool aContained, int aAccuracy ) const
{
    BOX2I arect = aRect;
    arect.Inflate( aAccuracy );
 
    bool hit = false;
 
    Padstack().ForEachUniqueLayer(
            [&]( PCB_LAYER_ID aLayer )
            {
                if( hit )
                    return;
 
                if( IsGhostLayer( aLayer ) )
                    return;
 
                BOX2I box( GetStart() );
                box.Inflate( GetWidth( aLayer ) / 2 );
 
                if( aContained )
                    hit = arect.Contains( box );
                else
                    hit = arect.IntersectsCircle( GetStart(), GetWidth( aLayer ) / 2 );
            } );
 
    return hit;
}
 
 
bool PCB_TRACK::HitTest( const SHAPE_LINE_CHAIN& aPoly, bool aContained ) const
{
    return KIGEOM::ShapeHitTest( aPoly, *GetEffectiveShape(), aContained );
}
 
 
wxString PCB_TRACK::GetItemDescription( UNITS_PROVIDER* aUnitsProvider, bool aFull ) const
{
    return wxString::Format( Type() == PCB_ARC_T ? _("Track (arc) %s on %s, length %s" )
                                                 : _("Track %s on %s, length %s" ),
                             GetNetnameMsg(),
                             GetLayerName(),
                             aUnitsProvider->MessageTextFromValue( GetLength() ) );
}
 
 
BITMAPS PCB_TRACK::GetMenuImage() const
{
    return BITMAPS::add_tracks;
}
 
 
void PCB_TRACK::swapData( BOARD_ITEM* aImage )
{
    wxASSERT( aImage->Type() == PCB_TRACE_T );
 
    std::swap( *((PCB_TRACK*) this), *((PCB_TRACK*) aImage) );
}
 
 
void PCB_ARC::swapData( BOARD_ITEM* aImage )
{
    wxASSERT( aImage->Type() == PCB_ARC_T );
 
    std::swap( *this, *static_cast<PCB_ARC*>( aImage ) );
}
 
 
void PCB_VIA::swapData( BOARD_ITEM* aImage )
{
    wxASSERT( aImage->Type() == PCB_VIA_T );
 
    std::swap( *((PCB_VIA*) this), *((PCB_VIA*) aImage) );
}
 
 
VECTOR2I PCB_ARC::GetPosition() const
{
    VECTOR2I center = CalcArcCenter( m_Start, m_Mid, m_End );
    return center;
}
 
 
double PCB_ARC::GetRadius() const
{
    auto center = CalcArcCenter( m_Start, m_Mid , m_End );
    return std::min( center.Distance( m_Start ), (double) INT_MAX / 2.0 );
}
 
 
EDA_ANGLE PCB_ARC::GetAngle() const
{
    VECTOR2D  center = GetPosition();
    EDA_ANGLE angle1 = EDA_ANGLE( m_Mid - center ) - EDA_ANGLE( m_Start - center );
    EDA_ANGLE angle2 = EDA_ANGLE( m_End - center ) - EDA_ANGLE( m_Mid - center );
 
    return angle1.Normalize180() + angle2.Normalize180();
}
 
 
EDA_ANGLE PCB_ARC::GetArcAngleStart() const
{
    VECTOR2D  pos( GetPosition() );
    EDA_ANGLE angleStart( m_Start - pos );
 
    return angleStart.Normalize();
}
 
 
// Note: used in python tests.  Ignore CLion's claim that it's unused....
EDA_ANGLE PCB_ARC::GetArcAngleEnd() const
{
    VECTOR2D  pos( GetPosition() );
    EDA_ANGLE angleEnd( m_End - pos );
 
    return angleEnd.Normalize();
}
 
bool PCB_ARC::IsDegenerated( int aThreshold ) const
{
    // We have lots of code that will blow up if the radius overflows an int.
    if( GetRadius() >= (double)INT_MAX/2.0 )
        return true;
 
    // Too small arcs cannot be really handled: arc center (and arc radius)
    // cannot be safely computed if the distance between mid and end points
    // is too small (a few internal units)
 
    // len of both segments must be < aThreshold to be a very small degenerated arc
    return ( GetMid() - GetStart() ).EuclideanNorm() < aThreshold
            && ( GetMid() - GetEnd() ).EuclideanNorm() < aThreshold;
}
 
 
bool PCB_TRACK::cmp_tracks::operator() ( const PCB_TRACK* a, const PCB_TRACK* b ) const
{
    if( a->GetNetCode() != b->GetNetCode() )
        return a->GetNetCode() < b->GetNetCode();
 
    if( a->GetLayer() != b->GetLayer() )
        return a->GetLayer() < b->GetLayer();
 
    if( a->Type() != b->Type() )
        return a->Type() < b->Type();
 
    if( a->m_Uuid != b->m_Uuid )
        return a->m_Uuid < b->m_Uuid;
 
    return a < b;
}
 
 
std::shared_ptr<SHAPE> PCB_TRACK::GetEffectiveShape( PCB_LAYER_ID aLayer, FLASHING, DRC_CONSTRAINT_T ) const
{
    int width = m_width;
 
    if( IsSolderMaskLayer( aLayer ) )
        width += 2 * GetSolderMaskExpansion();
 
    return std::make_shared<SHAPE_SEGMENT>( m_Start, m_End, width );
}
 
 
std::shared_ptr<SHAPE> PCB_VIA::GetEffectiveShape( PCB_LAYER_ID aLayer, FLASHING aFlash,
                                                   DRC_CONSTRAINT_T aUsage ) const
{
    int diameter = 0;
 
    if( aFlash == FLASHING::ALWAYS_FLASHED || ( aFlash == FLASHING::DEFAULT && FlashLayer( aLayer ) ) )
    {
        if( aLayer == UNDEFINED_LAYER )
        {
            Padstack().ForEachUniqueLayer(
                    [&]( PCB_LAYER_ID layer )
                    {
                        if( IsGhostLayer( layer ) )
                            return;
 
                        diameter = std::max( diameter, GetWidth( layer ) );
                    } );
        }
        else
        {
            PCB_LAYER_ID cuLayer = m_padStack.EffectiveLayerFor( aLayer );
            diameter = GetWidth( cuLayer );
        }
    }
    else
    {
        diameter = GetDrillValue();
    }
 
    // In some cases we want to add in any backdrill or post-machining
    if( ( aUsage == PHYSICAL_CLEARANCE_CONSTRAINT && IsBackdrilledOrPostMachined( aLayer ) )
            || ( aUsage == SILK_CLEARANCE_CONSTRAINT && IsBackdrilledOrPostMachined( aLayer ) ) )
    {
        diameter = std::max( diameter, Padstack().GetMaxHoleSize() );
    }
 
    return std::make_shared<SHAPE_CIRCLE>( m_Start, diameter / 2 );
}
 
 
std::shared_ptr<SHAPE> PCB_ARC::GetEffectiveShape( PCB_LAYER_ID aLayer, FLASHING, DRC_CONSTRAINT_T ) const
{
    int width = GetWidth();
 
    if( IsSolderMaskLayer( aLayer ) )
        width += 2 * GetSolderMaskExpansion();
 
    SHAPE_ARC arc( GetStart(), GetMid(), GetEnd(), width );
 
    if( arc.IsEffectiveLine() )
        return std::make_shared<SHAPE_SEGMENT>( GetStart(), GetEnd(), width );
 
    return std::make_shared<SHAPE_ARC>( arc );
}
 
 
void PCB_TRACK::TransformShapeToPolygon( SHAPE_POLY_SET& aBuffer, PCB_LAYER_ID aLayer, int aClearance,
                                         int aError, ERROR_LOC aErrorLoc, bool ignoreLineWidth ) const
{
    wxASSERT_MSG( !ignoreLineWidth, wxT( "IgnoreLineWidth has no meaning for tracks." ) );
 
    switch( Type() )
    {
    case PCB_VIA_T:
    {
        int radius = ( static_cast<const PCB_VIA*>( this )->GetWidth( aLayer ) / 2 ) + aClearance;
        TransformCircleToPolygon( aBuffer, m_Start, radius, aError, aErrorLoc );
        break;
    }
 
    case PCB_ARC_T:
    {
        const PCB_ARC* arc = static_cast<const PCB_ARC*>( this );
        int            width = m_width + ( 2 * aClearance );
 
        if( IsSolderMaskLayer( aLayer ) )
            width += 2 * GetSolderMaskExpansion();
 
        TransformArcToPolygon( aBuffer, arc->GetStart(), arc->GetMid(), arc->GetEnd(), width, aError, aErrorLoc );
        break;
    }
 
    default:
    {
        int width = m_width + ( 2 * aClearance );
 
        if( IsSolderMaskLayer( aLayer ) )
            width += 2 * GetSolderMaskExpansion();
 
        TransformOvalToPolygon( aBuffer, m_Start, m_End, width, aError, aErrorLoc );
 
        break;
    }
    }
}
 
 
static struct TRACK_VIA_DESC
{
    TRACK_VIA_DESC()
    {
        // clang-format off: the suggestion is less readable
        ENUM_MAP<VIATYPE>::Instance()
                .Undefined( VIATYPE::NOT_DEFINED )
                .Map( VIATYPE::THROUGH,      _HKI( "Through" ) )
                .Map( VIATYPE::BLIND,        _HKI( "Blind" ) )
                .Map( VIATYPE::BURIED,       _HKI( "Buried" ) )
                .Map( VIATYPE::MICROVIA,     _HKI( "Micro" ) );
 
        ENUM_MAP<TENTING_MODE>::Instance()
                .Undefined( TENTING_MODE::FROM_BOARD )
                .Map( TENTING_MODE::FROM_BOARD, _HKI( "From board stackup" ) )
                .Map( TENTING_MODE::TENTED,     _HKI( "Tented" ) )
                .Map( TENTING_MODE::NOT_TENTED, _HKI( "Not tented" ) );
 
        ENUM_MAP<COVERING_MODE>::Instance()
                .Undefined( COVERING_MODE::FROM_BOARD )
                .Map( COVERING_MODE::FROM_BOARD, _HKI( "From board stackup" ) )
                .Map( COVERING_MODE::COVERED,     _HKI( "Covered" ) )
                .Map( COVERING_MODE::NOT_COVERED, _HKI( "Not covered" ) );
 
        ENUM_MAP<PLUGGING_MODE>::Instance()
                .Undefined( PLUGGING_MODE::FROM_BOARD )
                .Map( PLUGGING_MODE::FROM_BOARD, _HKI( "From board stackup" ) )
                .Map( PLUGGING_MODE::PLUGGED,     _HKI( "Plugged" ) )
                .Map( PLUGGING_MODE::NOT_PLUGGED, _HKI( "Not plugged" ) );
 
        ENUM_MAP<CAPPING_MODE>::Instance()
                .Undefined( CAPPING_MODE::FROM_BOARD )
                .Map( CAPPING_MODE::FROM_BOARD, _HKI( "From board stackup" ) )
                .Map( CAPPING_MODE::CAPPED,     _HKI( "Capped" ) )
                .Map( CAPPING_MODE::NOT_CAPPED, _HKI( "Not capped" ) );
 
        ENUM_MAP<FILLING_MODE>::Instance()
                .Undefined( FILLING_MODE::FROM_BOARD )
                .Map( FILLING_MODE::FROM_BOARD, _HKI( "From board stackup" ) )
                .Map( FILLING_MODE::FILLED,     _HKI( "Filled" ) )
                .Map( FILLING_MODE::NOT_FILLED, _HKI( "Not filled" ) );
 
        // clang-format on: the suggestion is less readable
 
        // Pad and via registration can run in either order across translation units.
        ENUM_MAP<PAD_DRILL_POST_MACHINING_MODE>& pmMap = ENUM_MAP<PAD_DRILL_POST_MACHINING_MODE>::Instance();
 
        if( pmMap.Choices().GetCount() == 0 )
        {
            pmMap.Undefined( PAD_DRILL_POST_MACHINING_MODE::UNKNOWN )
                .Map( PAD_DRILL_POST_MACHINING_MODE::NOT_POST_MACHINED, _HKI( "Not post-machined" ) )
                .Map( PAD_DRILL_POST_MACHINING_MODE::COUNTERBORE,       _HKI( "Counterbore" ) )
                .Map( PAD_DRILL_POST_MACHINING_MODE::COUNTERSINK,       _HKI( "Countersink" ) );
        }
 
        ENUM_MAP<BACKDRILL_MODE>& bdMap = ENUM_MAP<BACKDRILL_MODE>::Instance();
 
        if( bdMap.Choices().GetCount() == 0 )
        {
            bdMap.Undefined( BACKDRILL_MODE::NO_BACKDRILL )
                .Map( BACKDRILL_MODE::NO_BACKDRILL,     _HKI( "No backdrill" ) )
                .Map( BACKDRILL_MODE::BACKDRILL_BOTTOM, _HKI( "Backdrill bottom" ) )
                .Map( BACKDRILL_MODE::BACKDRILL_TOP,    _HKI( "Backdrill top" ) )
                .Map( BACKDRILL_MODE::BACKDRILL_BOTH,   _HKI( "Backdrill both" ) );
        }
 
        ENUM_MAP<PCB_LAYER_ID>& layerEnum = ENUM_MAP<PCB_LAYER_ID>::Instance();
 
        if( layerEnum.Choices().GetCount() == 0 )
        {
            layerEnum.Undefined( UNDEFINED_LAYER );
 
            for( PCB_LAYER_ID layer : LSET::AllLayersMask() )
                layerEnum.Map( layer, LSET::Name( layer ) );
        }
 
        auto viaDiameterPropertyValidator =
                []( const wxAny&& aValue, EDA_ITEM* aItem ) -> VALIDATOR_RESULT
                {
                    if( !aItem || aItem->Type() != PCB_VIA_T )
                        return std::nullopt;
 
                    if( !aValue.CheckType<int>() )
                        return std::nullopt;
 
                    PCB_VIA* via = static_cast<PCB_VIA*>( aItem );
 
                    std::optional<int> diameter = aValue.As<int>();
                    std::optional<int> drill = via->GetDrillValue();
 
                    std::optional<PCB_LAYER_ID> startLayer;
 
                    if( via->Padstack().Drill().start != UNDEFINED_LAYER )
                        startLayer = via->Padstack().Drill().start;
 
                    std::optional<PCB_LAYER_ID> endLayer;
 
                    if( via->Padstack().Drill().end != UNDEFINED_LAYER )
                        endLayer = via->Padstack().Drill().end;
 
                    int copperLayerCount = via->BoardCopperLayerCount();
 
                    if( std::optional<PCB_VIA::VIA_PARAMETER_ERROR> error =
                                PCB_VIA::ValidateViaParameters( diameter, drill, startLayer, endLayer,
                                                                std::nullopt, std::nullopt, std::nullopt, // secondary drill
                                                                std::nullopt, std::nullopt, std::nullopt, // tertiary drill
                                                                copperLayerCount ) )
                    {
                        return std::make_unique<VALIDATION_ERROR_MSG>( error->m_Message );
                    }
 
                    return std::nullopt;
                };
 
        auto viaDrillPropertyValidator =
                []( const wxAny&& aValue, EDA_ITEM* aItem ) -> VALIDATOR_RESULT
                {
                    if( !aItem || aItem->Type() != PCB_VIA_T )
                        return std::nullopt;
 
                    if( !aValue.CheckType<int>() )
                        return std::nullopt;
 
                    PCB_VIA* via = static_cast<PCB_VIA*>( aItem );
 
                    std::optional<int> diameter = via->GetFrontWidth();
                    std::optional<int> drill = aValue.As<int>();
 
                    std::optional<PCB_LAYER_ID> startLayer;
 
                    if( via->Padstack().Drill().start != UNDEFINED_LAYER )
                        startLayer = via->Padstack().Drill().start;
 
                    std::optional<PCB_LAYER_ID> endLayer;
 
                    if( via->Padstack().Drill().end != UNDEFINED_LAYER )
                        endLayer = via->Padstack().Drill().end;
 
                    std::optional<int> secondaryDrill = via->GetSecondaryDrillSize();
 
                    std::optional<PCB_LAYER_ID> secondaryStart;
 
                    if( via->GetSecondaryDrillStartLayer() != UNDEFINED_LAYER )
                        secondaryStart = via->GetSecondaryDrillStartLayer();
 
                    std::optional<PCB_LAYER_ID> secondaryEnd;
 
                    if( via->GetSecondaryDrillEndLayer() != UNDEFINED_LAYER )
                        secondaryEnd = via->GetSecondaryDrillEndLayer();
 
                    std::optional<int> tertiaryDrill = via->GetTertiaryDrillSize();
 
                    std::optional<PCB_LAYER_ID> tertiaryStart;
 
                    if( via->GetTertiaryDrillStartLayer() != UNDEFINED_LAYER )
                        tertiaryStart = via->GetTertiaryDrillStartLayer();
 
                    std::optional<PCB_LAYER_ID> tertiaryEnd;
 
                    if( via->GetTertiaryDrillEndLayer() != UNDEFINED_LAYER )
                        tertiaryEnd = via->GetTertiaryDrillEndLayer();
 
                    int copperLayerCount = via->BoardCopperLayerCount();
 
                    if( std::optional<PCB_VIA::VIA_PARAMETER_ERROR> error =
                                PCB_VIA::ValidateViaParameters( diameter, drill, startLayer, endLayer,
                                                                secondaryDrill, secondaryStart, secondaryEnd,
                                                                tertiaryDrill, tertiaryStart, tertiaryEnd,
                                                                copperLayerCount ) )
                    {
                        return std::make_unique<VALIDATION_ERROR_MSG>( error->m_Message );
                    }
 
                    return std::nullopt;
                };
 
        auto viaStartLayerPropertyValidator =
                []( const wxAny&& aValue, EDA_ITEM* aItem ) -> VALIDATOR_RESULT
                {
                    if( !aItem || aItem->Type() != PCB_VIA_T )
                        return std::nullopt;
 
                    PCB_LAYER_ID layer;
 
                    if( aValue.CheckType<PCB_LAYER_ID>() )
                        layer = aValue.As<PCB_LAYER_ID>();
                    else if( aValue.CheckType<int>() )
                        layer = static_cast<PCB_LAYER_ID>( aValue.As<int>() );
                    else
                        return std::nullopt;
 
                    PCB_VIA* via = static_cast<PCB_VIA*>( aItem );
 
                    std::optional<int> diameter = via->GetFrontWidth();
                    std::optional<int> drill = via->GetDrillValue();
 
                    std::optional<PCB_LAYER_ID> endLayer;
 
                    if( via->BottomLayer() != UNDEFINED_LAYER )
                        endLayer = via->BottomLayer();
 
                    std::optional<int> secondaryDrill = via->GetSecondaryDrillSize();
 
                    std::optional<PCB_LAYER_ID> secondaryStart;
 
                    if( via->GetSecondaryDrillStartLayer() != UNDEFINED_LAYER )
                        secondaryStart = via->GetSecondaryDrillStartLayer();
 
                    std::optional<PCB_LAYER_ID> secondaryEnd;
 
                    if( via->GetSecondaryDrillEndLayer() != UNDEFINED_LAYER )
                        secondaryEnd = via->GetSecondaryDrillEndLayer();
 
                    int copperLayerCount = via->BoardCopperLayerCount();
 
                    if( std::optional<PCB_VIA::VIA_PARAMETER_ERROR> error =
                                PCB_VIA::ValidateViaParameters( diameter, drill, layer, endLayer,
                                                                secondaryDrill, secondaryStart, secondaryEnd,
                                                                std::nullopt, std::nullopt, std::nullopt, // tertiary drill
                                                                copperLayerCount ) )
                    {
                        return std::make_unique<VALIDATION_ERROR_MSG>( error->m_Message );
                    }
 
                    return std::nullopt;
                };
 
        auto viaEndLayerPropertyValidator =
                []( const wxAny&& aValue, EDA_ITEM* aItem ) -> VALIDATOR_RESULT
                {
                    if( !aItem || aItem->Type() != PCB_VIA_T )
                        return std::nullopt;
 
                    PCB_LAYER_ID layer;
 
                    if( aValue.CheckType<PCB_LAYER_ID>() )
                        layer = aValue.As<PCB_LAYER_ID>();
                    else if( aValue.CheckType<int>() )
                        layer = static_cast<PCB_LAYER_ID>( aValue.As<int>() );
                    else
                        return std::nullopt;
 
                    PCB_VIA* via = static_cast<PCB_VIA*>( aItem );
 
                    std::optional<int> diameter = via->GetFrontWidth();
                    std::optional<int> drill = via->GetDrillValue();
 
                    std::optional<PCB_LAYER_ID> startLayer;
 
                    if( via->TopLayer() != UNDEFINED_LAYER )
                        startLayer = via->TopLayer();
 
                    std::optional<int> secondaryDrill = via->GetSecondaryDrillSize();
 
                    std::optional<PCB_LAYER_ID> secondaryStart;
 
                    if( via->GetSecondaryDrillStartLayer() != UNDEFINED_LAYER )
                        secondaryStart = via->GetSecondaryDrillStartLayer();
 
                    std::optional<PCB_LAYER_ID> secondaryEnd;
 
                    if( via->GetSecondaryDrillEndLayer() != UNDEFINED_LAYER )
                        secondaryEnd = via->GetSecondaryDrillEndLayer();
 
                    int copperLayerCount = via->BoardCopperLayerCount();
 
                    if( std::optional<PCB_VIA::VIA_PARAMETER_ERROR> error =
                                PCB_VIA::ValidateViaParameters( diameter, drill, startLayer, layer,
                                                                secondaryDrill, secondaryStart, secondaryEnd,
                                                                std::nullopt, std::nullopt, std::nullopt, // tertiary drill
                                                                copperLayerCount ) )
                    {
                        return std::make_unique<VALIDATION_ERROR_MSG>( error->m_Message );
                    }
 
                    return std::nullopt;
                };
 
        PROPERTY_MANAGER& propMgr = PROPERTY_MANAGER::Instance();
 
        // Track
        REGISTER_TYPE( PCB_TRACK );
        propMgr.InheritsAfter( TYPE_HASH( PCB_TRACK ), TYPE_HASH( BOARD_CONNECTED_ITEM ) );
 
        propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "Width" ),
                    &PCB_TRACK::SetWidth, &PCB_TRACK::GetWidth, PROPERTY_DISPLAY::PT_SIZE ) ).SetIsCopyable();
        propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Position X" ),
                    new PROPERTY<PCB_TRACK, int>( _HKI( "Start X" ),
                                &PCB_TRACK::SetStartX, &PCB_TRACK::GetStartX, PROPERTY_DISPLAY::PT_COORD,
                                ORIGIN_TRANSFORMS::ABS_X_COORD) );
        propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Position Y" ),
                    new PROPERTY<PCB_TRACK, int>( _HKI( "Start Y" ),
                                &PCB_TRACK::SetStartY, &PCB_TRACK::GetStartY, PROPERTY_DISPLAY::PT_COORD,
                                ORIGIN_TRANSFORMS::ABS_Y_COORD ) );
        propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "End X" ),
                    &PCB_TRACK::SetEndX, &PCB_TRACK::GetEndX, PROPERTY_DISPLAY::PT_COORD,
                    ORIGIN_TRANSFORMS::ABS_X_COORD) );
        propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "End Y" ),
                    &PCB_TRACK::SetEndY, &PCB_TRACK::GetEndY, PROPERTY_DISPLAY::PT_COORD,
                    ORIGIN_TRANSFORMS::ABS_Y_COORD) );
 
        const wxString groupTechLayers = _HKI( "Technical Layers" );
 
        auto isExternalLayerTrack =
            []( INSPECTABLE* aItem )
            {
                if( PCB_TRACK* track = dynamic_cast<PCB_TRACK*>( aItem ) )
                    return IsExternalCopperLayer( track->GetLayer() );
 
                return false;
            };
 
        propMgr.AddProperty( new PROPERTY<PCB_TRACK, bool>( _HKI( "Soldermask" ),
                    &PCB_TRACK::SetHasSolderMask, &PCB_TRACK::HasSolderMask ), groupTechLayers )
                .SetAvailableFunc( isExternalLayerTrack ).SetIsCopyable();
        propMgr.AddProperty( new PROPERTY<PCB_TRACK, std::optional<int>>( _HKI( "Soldermask Margin Override" ),
                    &PCB_TRACK::SetLocalSolderMaskMargin, &PCB_TRACK::GetLocalSolderMaskMargin,
                    PROPERTY_DISPLAY::PT_SIZE ),
                    groupTechLayers )
                .SetAvailableFunc( isExternalLayerTrack ).SetIsCopyable();
 
        // Arc
        REGISTER_TYPE( PCB_ARC );
        propMgr.InheritsAfter( TYPE_HASH( PCB_ARC ), TYPE_HASH( PCB_TRACK ) );
 
        // Via
        REGISTER_TYPE( PCB_VIA );
        propMgr.InheritsAfter( TYPE_HASH( PCB_VIA ), TYPE_HASH( BOARD_CONNECTED_ITEM ) );
 
        const wxString groupVia = _HKI( "Via Properties" );
        const wxString groupBackdrill = _HKI( "Backdrill" );
        const wxString groupPostMachining = _HKI( "Post-machining" );
 
        propMgr.Mask( TYPE_HASH( PCB_VIA ), TYPE_HASH( BOARD_CONNECTED_ITEM ), _HKI( "Layer" ) );
 
        propMgr.AddProperty( new PROPERTY<PCB_VIA, bool>( _HKI( "Automatically Update Net" ),
                    &PCB_VIA::SetIsNotFree, &PCB_VIA::GetIsNotFree ) );
 
        // clang-format off: the suggestion is less readable
        propMgr.AddProperty( new PROPERTY<PCB_VIA, int>( _HKI( "Diameter" ),
                    &PCB_VIA::SetFrontWidth, &PCB_VIA::GetFrontWidth, PROPERTY_DISPLAY::PT_SIZE ),
                    groupVia )
                .SetValidator( viaDiameterPropertyValidator ).SetIsCopyable();
        propMgr.AddProperty( new PROPERTY<PCB_VIA, int>( _HKI( "Hole" ),
                    &PCB_VIA::SetDrill, &PCB_VIA::GetDrillValue, PROPERTY_DISPLAY::PT_SIZE ),
                    groupVia )
                .SetValidator( viaDrillPropertyValidator ).SetIsCopyable();
        propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, PCB_LAYER_ID>( _HKI( "Layer Top" ),
                    &PCB_VIA::SetTopLayer, &PCB_VIA::GetLayer ),
                    groupVia )
                .SetValidator( viaStartLayerPropertyValidator );
        propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, PCB_LAYER_ID>( _HKI( "Layer Bottom" ),
                    &PCB_VIA::SetBottomLayer, &PCB_VIA::BottomLayer ),
                    groupVia )
                .SetValidator( viaEndLayerPropertyValidator );
        propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, VIATYPE>( _HKI( "Via Type" ),
                    &PCB_VIA::SetViaType, &PCB_VIA::GetViaType ),
                    groupVia );
        propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, TENTING_MODE>( _HKI( "Front Tenting" ),
                    &PCB_VIA::SetFrontTentingMode, &PCB_VIA::GetFrontTentingMode ),
                    groupVia ).SetIsCopyable();
        propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, TENTING_MODE>( _HKI( "Back Tenting" ),
                    &PCB_VIA::SetBackTentingMode, &PCB_VIA::GetBackTentingMode ),
                    groupVia ).SetIsCopyable();
        propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, COVERING_MODE>( _HKI( "Front Covering" ),
                    &PCB_VIA::SetFrontCoveringMode, &PCB_VIA::GetFrontCoveringMode ),
                    groupVia ).SetIsCopyable();
        propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, COVERING_MODE>( _HKI( "Back Covering" ),
                    &PCB_VIA::SetBackCoveringMode, &PCB_VIA::GetBackCoveringMode ),
                    groupVia ).SetIsCopyable();
        propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, PLUGGING_MODE>( _HKI( "Front Plugging" ),
                    &PCB_VIA::SetFrontPluggingMode, &PCB_VIA::GetFrontPluggingMode ),
                    groupVia ).SetIsCopyable();
        propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, PLUGGING_MODE>( _HKI( "Back Plugging" ),
                    &PCB_VIA::SetBackPluggingMode, &PCB_VIA::GetBackPluggingMode ),
                    groupVia ).SetIsCopyable();
        propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, CAPPING_MODE>( _HKI( "Capping" ),
                    &PCB_VIA::SetCappingMode, &PCB_VIA::GetCappingMode ),
                    groupVia ).SetIsCopyable();
        propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, FILLING_MODE>( _HKI( "Filling" ),
                    &PCB_VIA::SetFillingMode, &PCB_VIA::GetFillingMode ),
                    groupVia ).SetIsCopyable();
 
        propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, BACKDRILL_MODE>( _HKI( "Backdrill Mode" ),
                    &PCB_VIA::SetBackdrillMode, &PCB_VIA::GetBackdrillMode ),
                    groupBackdrill )
                .SetAvailableFunc( []( INSPECTABLE* aItem )
                                   {
                                       if( PCB_VIA* via = dynamic_cast<PCB_VIA*>( aItem ) )
                                       {
                                           if( via->GetViaType() == VIATYPE::THROUGH )
                                               return true;
 
                                           if( via->Padstack().GetBackdrillMode() != BACKDRILL_MODE::NO_BACKDRILL )
                                               return true;
                                       }
 
                                       return false;
                                   } );
 
        propMgr.AddProperty( new PROPERTY<PCB_VIA, std::optional<int>>( _HKI( "Bottom Backdrill Size" ),
                    &PCB_VIA::SetBottomBackdrillSize, &PCB_VIA::GetBottomBackdrillSize, PROPERTY_DISPLAY::PT_SIZE ),
                    groupBackdrill )
                .SetAvailableFunc( []( INSPECTABLE* aItem ) -> bool
                                   {
                                       if( PCB_VIA* via = dynamic_cast<PCB_VIA*>( aItem ) )
                                       {
                                           BACKDRILL_MODE mode = via->GetBackdrillMode();
                                           return mode == BACKDRILL_MODE::BACKDRILL_BOTTOM
                                                   || mode == BACKDRILL_MODE::BACKDRILL_BOTH;
                                       }
 
                                       return false;
                                   } );
 
        propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, PCB_LAYER_ID>( _HKI( "Bottom Backdrill Must-Cut" ),
                    &PCB_VIA::SetBottomBackdrillLayer, &PCB_VIA::GetBottomBackdrillLayer ), groupBackdrill )
                .SetAvailableFunc( []( INSPECTABLE* aItem ) -> bool
                                   {
                                       if( PCB_VIA* via = dynamic_cast<PCB_VIA*>( aItem ) )
                                       {
                                           BACKDRILL_MODE mode = via->GetBackdrillMode();
                                           return mode == BACKDRILL_MODE::BACKDRILL_BOTTOM
                                                   || mode == BACKDRILL_MODE::BACKDRILL_BOTH;
                                       }
 
                                       return false;
                                   } );
 
        propMgr.AddProperty( new PROPERTY<PCB_VIA, std::optional<int>>( _HKI( "Top Backdrill Size" ),
                    &PCB_VIA::SetTopBackdrillSize, &PCB_VIA::GetTopBackdrillSize, PROPERTY_DISPLAY::PT_SIZE ),
                    groupBackdrill )
                .SetAvailableFunc( []( INSPECTABLE* aItem ) -> bool
                                   {
                                       if( PCB_VIA* via = dynamic_cast<PCB_VIA*>( aItem ) )
                                       {
                                           BACKDRILL_MODE mode = via->GetBackdrillMode();
                                           return mode == BACKDRILL_MODE::BACKDRILL_TOP
                                                   || mode == BACKDRILL_MODE::BACKDRILL_BOTH;
                                       }
 
                                       return false;
                                   } );
 
        propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, PCB_LAYER_ID>( _HKI( "Top Backdrill Must-Cut" ),
                    &PCB_VIA::SetTopBackdrillLayer, &PCB_VIA::GetTopBackdrillLayer ), groupBackdrill )
                .SetAvailableFunc( []( INSPECTABLE* aItem ) -> bool
                                   {
                                       if( PCB_VIA* via = dynamic_cast<PCB_VIA*>( aItem ) )
                                       {
                                           BACKDRILL_MODE mode = via->GetBackdrillMode();
                                           return mode == BACKDRILL_MODE::BACKDRILL_TOP
                                                   || mode == BACKDRILL_MODE::BACKDRILL_BOTH;
                                       }
 
                                       return false;
                                   } );
 
        propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, PAD_DRILL_POST_MACHINING_MODE>( _HKI( "Front Post-machining" ),
                    &PCB_VIA::SetFrontPostMachiningMode, &PCB_VIA::GetFrontPostMachiningMode ),
                    groupPostMachining );
 
        propMgr.AddProperty( new PROPERTY<PCB_VIA, int>( _HKI( "Front Post-machining Size" ),
                    &PCB_VIA::SetFrontPostMachiningSize, &PCB_VIA::GetFrontPostMachiningSize,
                    PROPERTY_DISPLAY::PT_SIZE ),
                    groupPostMachining )
                .SetAvailableFunc(
                        []( INSPECTABLE* aItem )
                        {
                            if( PCB_VIA* via = dynamic_cast<PCB_VIA*>( aItem ) )
                            {
                                std::optional<PAD_DRILL_POST_MACHINING_MODE> mode = via->GetFrontPostMachining();
 
                                if( mode.has_value() )
                                {
                                     return mode.value() == PAD_DRILL_POST_MACHINING_MODE::COUNTERBORE
                                            || mode.value() == PAD_DRILL_POST_MACHINING_MODE::COUNTERSINK;
                                }
                            }
 
                            return false;
                        } );
 
        propMgr.AddProperty( new PROPERTY<PCB_VIA, int>( _HKI( "Front Post-machining Depth" ),
                    &PCB_VIA::SetFrontPostMachiningDepth, &PCB_VIA::GetFrontPostMachiningDepth,
                    PROPERTY_DISPLAY::PT_SIZE ),
                    groupPostMachining )
                .SetAvailableFunc(
                        []( INSPECTABLE* aItem )
                        {
                            if( PCB_VIA* via = dynamic_cast<PCB_VIA*>( aItem ) )
                            {
                                std::optional<PAD_DRILL_POST_MACHINING_MODE> mode = via->GetFrontPostMachining();
 
                                if( mode.has_value() )
                                    return mode.value() == PAD_DRILL_POST_MACHINING_MODE::COUNTERBORE;
                            }
 
                            return false;
                        } );
 
        propMgr.AddProperty( new PROPERTY<PCB_VIA, int>( _HKI( "Front Post-machining Angle" ),
                    &PCB_VIA::SetFrontPostMachiningAngle, &PCB_VIA::GetFrontPostMachiningAngle,
                    PROPERTY_DISPLAY::PT_DECIDEGREE ),
                    groupPostMachining )
                .SetAvailableFunc(
                        []( INSPECTABLE* aItem )
                        {
                            if( PCB_VIA* via = dynamic_cast<PCB_VIA*>( aItem ) )
                            {
                                std::optional<PAD_DRILL_POST_MACHINING_MODE> mode = via->GetFrontPostMachining();
 
                                if( mode.has_value() )
                                    return mode == PAD_DRILL_POST_MACHINING_MODE::COUNTERSINK;
                            }
 
                            return false;
                        } );
 
        propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, PAD_DRILL_POST_MACHINING_MODE>( _HKI( "Back Post-machining" ),
                    &PCB_VIA::SetBackPostMachiningMode, &PCB_VIA::GetBackPostMachiningMode ), groupPostMachining );
 
        propMgr.AddProperty( new PROPERTY<PCB_VIA, int>( _HKI( "Back Post-machining Size" ),
                    &PCB_VIA::SetBackPostMachiningSize, &PCB_VIA::GetBackPostMachiningSize, PROPERTY_DISPLAY::PT_SIZE ),
                    groupPostMachining )
                .SetAvailableFunc(
                        []( INSPECTABLE* aItem )
                        {
                            if( PCB_VIA* via = dynamic_cast<PCB_VIA*>( aItem ) )
                            {
                                std::optional<PAD_DRILL_POST_MACHINING_MODE> mode = via->GetBackPostMachining();
 
                                if( mode.has_value() )
                                {
                                    return mode.value() == PAD_DRILL_POST_MACHINING_MODE::COUNTERBORE
                                            || mode.value() == PAD_DRILL_POST_MACHINING_MODE::COUNTERSINK;
                                }
                            }
 
                            return false;
                        } );
 
        propMgr.AddProperty( new PROPERTY<PCB_VIA, int>( _HKI( "Back Post-machining Depth" ),
                    &PCB_VIA::SetBackPostMachiningDepth, &PCB_VIA::GetBackPostMachiningDepth, PROPERTY_DISPLAY::PT_SIZE ),
                    groupPostMachining )
                .SetAvailableFunc(
                        []( INSPECTABLE* aItem )
                        {
                            if( PCB_VIA* via = dynamic_cast<PCB_VIA*>( aItem ) )
                            {
                                std::optional<PAD_DRILL_POST_MACHINING_MODE> mode = via->GetBackPostMachining();
 
                                if( mode.has_value() )
                                    return mode.value() == PAD_DRILL_POST_MACHINING_MODE::COUNTERBORE;
                            }
 
                            return false;
                        } );
 
        propMgr.AddProperty( new PROPERTY<PCB_VIA, int>( _HKI( "Back Post-machining Angle" ),
                    &PCB_VIA::SetBackPostMachiningAngle, &PCB_VIA::GetBackPostMachiningAngle, PROPERTY_DISPLAY::PT_DECIDEGREE ),
                    groupPostMachining )
                .SetAvailableFunc(
                        []( INSPECTABLE* aItem )
                        {
                            if( PCB_VIA* via = dynamic_cast<PCB_VIA*>( aItem ) )
                            {
                                std::optional<PAD_DRILL_POST_MACHINING_MODE> mode = via->GetBackPostMachining();
 
                                if( mode.has_value() )
                                    return mode.value() == PAD_DRILL_POST_MACHINING_MODE::COUNTERSINK;
                            }
 
                            return false;
                        } );
        // clang-format on: the suggestion is less readable
    }
} _TRACK_VIA_DESC;
 
ENUM_TO_WXANY( VIATYPE );
ENUM_TO_WXANY( TENTING_MODE );
ENUM_TO_WXANY( COVERING_MODE );
ENUM_TO_WXANY( PLUGGING_MODE );
ENUM_TO_WXANY( CAPPING_MODE );
ENUM_TO_WXANY( FILLING_MODE );