KiCad PCB EDA Suite
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pcb_track.cpp
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1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright (C) 2012 Jean-Pierre Charras, jp.charras at wanadoo.fr
5 * Copyright (C) 2012 SoftPLC Corporation, Dick Hollenbeck <[email protected]>
6 * Copyright (C) 2012 Wayne Stambaugh <[email protected]>
7 * Copyright (C) 1992-2023 KiCad Developers, see AUTHORS.txt for contributors.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, you may find one here:
21 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
22 * or you may search the http://www.gnu.org website for the version 2 license,
23 * or you may write to the Free Software Foundation, Inc.,
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
25 */
26
27#include <pcb_base_frame.h>
28#include <core/mirror.h>
30#include <board.h>
33#include <pcb_track.h>
34#include <base_units.h>
35#include <string_utils.h>
36#include <view/view.h>
39#include <geometry/seg.h>
42#include <geometry/shape_arc.h>
43#include <drc/drc_engine.h>
44#include <pcb_painter.h>
45#include <trigo.h>
46
49
51 BOARD_CONNECTED_ITEM( aParent, idtype )
52{
53 m_Width = pcbIUScale.mmToIU( 0.2 ); // Gives a reasonable default width
54 m_CachedScale = -1.0; // Set invalid to force update
55 m_CachedLOD = 0.0; // Set to always display
56}
57
58
60{
61 return new PCB_TRACK( *this );
62}
63
64
65PCB_ARC::PCB_ARC( BOARD_ITEM* aParent, const SHAPE_ARC* aArc ) :
66 PCB_TRACK( aParent, PCB_ARC_T )
67{
68 m_Start = aArc->GetP0();
69 m_End = aArc->GetP1();
70 m_Mid = aArc->GetArcMid();
71}
72
73
75{
76 return new PCB_ARC( *this );
77}
78
79
81 PCB_TRACK( aParent, PCB_VIA_T )
82{
83 SetViaType( VIATYPE::THROUGH );
86
89
91
92 m_isFree = false;
93}
94
95
96PCB_VIA::PCB_VIA( const PCB_VIA& aOther ) :
97 PCB_TRACK( aOther.GetParent(), PCB_VIA_T )
98{
99 PCB_VIA::operator=( aOther );
100
101 const_cast<KIID&>( m_Uuid ) = aOther.m_Uuid;
103}
104
105
107{
109
110 m_Width = aOther.m_Width;
111 m_Start = aOther.m_Start;
112 m_End = aOther.m_End;
113 m_CachedLOD = aOther.m_CachedLOD;
115
117 m_viaType = aOther.m_viaType;
118 m_drill = aOther.m_drill;
121 m_isFree = aOther.m_isFree;
122
123 return *this;
124}
125
126
128{
129 return new PCB_VIA( *this );
130}
131
132
133wxString PCB_VIA::GetItemDescription( UNITS_PROVIDER* aUnitsProvider ) const
134{
135 wxString formatStr;
136
137 switch( GetViaType() )
138 {
139 case VIATYPE::BLIND_BURIED: formatStr = _( "Blind/Buried Via %s on %s" ); break;
140 case VIATYPE::MICROVIA: formatStr = _( "Micro Via %s on %s" ); break;
141 default: formatStr = _( "Via %s on %s" ); break;
142 }
143
144 return wxString::Format( formatStr, GetNetnameMsg(), layerMaskDescribe() );
145}
146
147
149{
150 return BITMAPS::via;
151}
152
153
154bool PCB_TRACK::operator==( const BOARD_ITEM& aOther ) const
155{
156 if( aOther.Type() != Type() )
157 return false;
158
159 const PCB_TRACK& other = static_cast<const PCB_TRACK&>( aOther );
160
161 return m_Start == other.m_Start && m_End == other.m_End && m_layer == other.m_layer &&
162 m_Width == other.m_Width;
163}
164
165
166double PCB_TRACK::Similarity( const BOARD_ITEM& aOther ) const
167{
168 if( aOther.Type() != Type() )
169 return 0.0;
170
171 const PCB_TRACK& other = static_cast<const PCB_TRACK&>( aOther );
172
173 double similarity = 1.0;
174
175 if( m_layer != other.m_layer )
176 similarity *= 0.9;
177
178 if( m_Width != other.m_Width )
179 similarity *= 0.9;
180
181 if( m_Start != other.m_Start )
182 similarity *= 0.9;
183
184 if( m_End != other.m_End )
185 similarity *= 0.9;
186
187 return similarity;
188}
189
190
191bool PCB_ARC::operator==( const BOARD_ITEM& aOther ) const
192{
193 if( aOther.Type() != Type() )
194 return false;
195
196 const PCB_ARC& other = static_cast<const PCB_ARC&>( aOther );
197
198 return m_Start == other.m_Start && m_End == other.m_End && m_Mid == other.m_Mid &&
199 m_layer == other.m_layer && m_Width == other.m_Width;
200}
201
202
203double PCB_ARC::Similarity( const BOARD_ITEM& aOther ) const
204{
205 if( aOther.Type() != Type() )
206 return 0.0;
207
208 const PCB_ARC& other = static_cast<const PCB_ARC&>( aOther );
209
210 double similarity = 1.0;
211
212 if( m_layer != other.m_layer )
213 similarity *= 0.9;
214
215 if( m_Width != other.m_Width )
216 similarity *= 0.9;
217
218 if( m_Start != other.m_Start )
219 similarity *= 0.9;
220
221 if( m_End != other.m_End )
222 similarity *= 0.9;
223
224 if( m_Mid != other.m_Mid )
225 similarity *= 0.9;
226
227 return similarity;
228}
229
230
231bool PCB_VIA::operator==( const BOARD_ITEM& aOther ) const
232{
233 if( aOther.Type() != Type() )
234 return false;
235
236 const PCB_VIA& other = static_cast<const PCB_VIA&>( aOther );
237
238 return m_Start == other.m_Start && m_End == other.m_End && m_layer == other.m_layer &&
239 m_bottomLayer == other.m_bottomLayer && m_Width == other.m_Width &&
240 m_viaType == other.m_viaType && m_drill == other.m_drill &&
244}
245
246
247double PCB_VIA::Similarity( const BOARD_ITEM& aOther ) const
248{
249 if( aOther.Type() != Type() )
250 return 0.0;
251
252 const PCB_VIA& other = static_cast<const PCB_VIA&>( aOther );
253
254 double similarity = 1.0;
255
256 if( m_layer != other.m_layer )
257 similarity *= 0.9;
258
259 if( m_Width != other.m_Width )
260 similarity *= 0.9;
261
262 if( m_Start != other.m_Start )
263 similarity *= 0.9;
264
265 if( m_End != other.m_End )
266 similarity *= 0.9;
267
268 if( m_bottomLayer != other.m_bottomLayer )
269 similarity *= 0.9;
270
271 if( m_viaType != other.m_viaType )
272 similarity *= 0.9;
273
274 if( m_drill != other.m_drill )
275 similarity *= 0.9;
276
278 similarity *= 0.9;
279
281 similarity *= 0.9;
282
284 similarity *= 0.9;
285
286 return similarity;
287}
288
289
291{
292 SEG a( m_Start, m_End );
293 SEG b( aTrack.GetStart(), aTrack.GetEnd() );
294 return a.ApproxCollinear( b );
295}
296
297
298int PCB_TRACK::GetLocalClearance( wxString* aSource ) const
299{
300 // Not currently implemented
301 return 0;
302}
303
304
306{
307 DRC_CONSTRAINT constraint;
308
309 if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine )
310 {
312
313 constraint = bds.m_DRCEngine->EvalRules( TRACK_WIDTH_CONSTRAINT, this, nullptr, m_layer );
314 }
315
316 if( aSource )
317 *aSource = constraint.GetName();
318
319 return constraint.Value();
320}
321
322
324{
325 DRC_CONSTRAINT constraint;
326
327 if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine )
328 {
330
331 constraint = bds.m_DRCEngine->EvalRules( VIA_DIAMETER_CONSTRAINT, this, nullptr, m_layer );
332 }
333
334 if( aSource )
335 *aSource = constraint.GetName();
336
337 return constraint.Value();
338}
339
340
342{
343 DRC_CONSTRAINT constraint;
344
345 if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine )
346 {
348
349 constraint = bds.m_DRCEngine->EvalRules( HOLE_SIZE_CONSTRAINT, this, nullptr, m_layer );
350 }
351
352 if( aSource )
353 *aSource = constraint.GetName();
354
355 return constraint.Value();
356}
357
358
359int PCB_VIA::GetMinAnnulus( PCB_LAYER_ID aLayer, wxString* aSource ) const
360{
361 if( !FlashLayer( aLayer ) )
362 {
363 if( aSource )
364 *aSource = _( "removed annular ring" );
365
366 return 0;
367 }
368
369 DRC_CONSTRAINT constraint;
370
371 if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine )
372 {
374
375 constraint = bds.m_DRCEngine->EvalRules( ANNULAR_WIDTH_CONSTRAINT, this, nullptr, aLayer );
376 }
377
378 if( constraint.Value().HasMin() )
379 {
380 if( aSource )
381 *aSource = constraint.GetName();
382
383 return constraint.Value().Min();
384 }
385
386 return 0;
387}
388
389
391{
392 if( m_drill > 0 ) // Use the specific value.
393 return m_drill;
394
395 // Use the default value from the Netclass
396 NETCLASS* netclass = GetEffectiveNetClass();
397
398 if( GetViaType() == VIATYPE::MICROVIA )
399 return netclass->GetuViaDrill();
400
401 return netclass->GetViaDrill();
402}
403
404
405EDA_ITEM_FLAGS PCB_TRACK::IsPointOnEnds( const VECTOR2I& point, int min_dist ) const
406{
407 EDA_ITEM_FLAGS result = 0;
408
409 if( min_dist < 0 )
410 min_dist = m_Width / 2;
411
412 if( min_dist == 0 )
413 {
414 if( m_Start == point )
415 result |= STARTPOINT;
416
417 if( m_End == point )
418 result |= ENDPOINT;
419 }
420 else
421 {
422 double dist = GetLineLength( m_Start, point );
423
424 if( min_dist >= KiROUND( dist ) )
425 result |= STARTPOINT;
426
427 dist = GetLineLength( m_End, point );
428
429 if( min_dist >= KiROUND( dist ) )
430 result |= ENDPOINT;
431 }
432
433 return result;
434}
435
436
438{
439 // end of track is round, this is its radius, rounded up
440 int radius = ( m_Width + 1 ) / 2;
441 int ymax, xmax, ymin, xmin;
442
443 if( Type() == PCB_VIA_T )
444 {
445 ymax = m_Start.y;
446 xmax = m_Start.x;
447
448 ymin = m_Start.y;
449 xmin = m_Start.x;
450 }
451 else if( Type() == PCB_ARC_T )
452 {
453 std::shared_ptr<SHAPE> arc = GetEffectiveShape();
454 BOX2I bbox = arc->BBox();
455
456 xmin = bbox.GetLeft();
457 xmax = bbox.GetRight();
458 ymin = bbox.GetTop();
459 ymax = bbox.GetBottom();
460 }
461 else
462 {
463 ymax = std::max( m_Start.y, m_End.y );
464 xmax = std::max( m_Start.x, m_End.x );
465
466 ymin = std::min( m_Start.y, m_End.y );
467 xmin = std::min( m_Start.x, m_End.x );
468 }
469
470 ymax += radius;
471 xmax += radius;
472
473 ymin -= radius;
474 xmin -= radius;
475
476 // return a rectangle which is [pos,dim) in nature. therefore the +1
477 BOX2I ret( VECTOR2I( xmin, ymin ), VECTOR2I( xmax - xmin + 1, ymax - ymin + 1 ) );
478
479 return ret;
480}
481
482
484{
485 return GetLineLength( m_Start, m_End );
486}
487
488
489void PCB_TRACK::Rotate( const VECTOR2I& aRotCentre, const EDA_ANGLE& aAngle )
490{
491 RotatePoint( m_Start, aRotCentre, aAngle );
492 RotatePoint( m_End, aRotCentre, aAngle );
493}
494
495
496void PCB_ARC::Rotate( const VECTOR2I& aRotCentre, const EDA_ANGLE& aAngle )
497{
498 RotatePoint( m_Start, aRotCentre, aAngle );
499 RotatePoint( m_End, aRotCentre, aAngle );
500 RotatePoint( m_Mid, aRotCentre, aAngle );
501}
502
503
504void PCB_TRACK::Mirror( const VECTOR2I& aCentre, bool aMirrorAroundXAxis )
505{
506 if( aMirrorAroundXAxis )
507 {
508 MIRROR( m_Start.y, aCentre.y );
509 MIRROR( m_End.y, aCentre.y );
510 }
511 else
512 {
513 MIRROR( m_Start.x, aCentre.x );
514 MIRROR( m_End.x, aCentre.x );
515 }
516}
517
518
519void PCB_ARC::Mirror( const VECTOR2I& aCentre, bool aMirrorAroundXAxis )
520{
521 if( aMirrorAroundXAxis )
522 {
523 MIRROR( m_Start.y, aCentre.y );
524 MIRROR( m_End.y, aCentre.y );
525 MIRROR( m_Mid.y, aCentre.y );
526 }
527 else
528 {
529 MIRROR( m_Start.x, aCentre.x );
530 MIRROR( m_End.x, aCentre.x );
531 MIRROR( m_Mid.x, aCentre.x );
532 }
533}
534
535
536void PCB_TRACK::Flip( const VECTOR2I& aCentre, bool aFlipLeftRight )
537{
538 if( aFlipLeftRight )
539 {
540 m_Start.x = aCentre.x - ( m_Start.x - aCentre.x );
541 m_End.x = aCentre.x - ( m_End.x - aCentre.x );
542 }
543 else
544 {
545 m_Start.y = aCentre.y - ( m_Start.y - aCentre.y );
546 m_End.y = aCentre.y - ( m_End.y - aCentre.y );
547 }
548
549 int copperLayerCount = GetBoard()->GetCopperLayerCount();
550 SetLayer( FlipLayer( GetLayer(), copperLayerCount ) );
551}
552
553
554void PCB_ARC::Flip( const VECTOR2I& aCentre, bool aFlipLeftRight )
555{
556 if( aFlipLeftRight )
557 {
558 m_Start.x = aCentre.x - ( m_Start.x - aCentre.x );
559 m_End.x = aCentre.x - ( m_End.x - aCentre.x );
560 m_Mid.x = aCentre.x - ( m_Mid.x - aCentre.x );
561 }
562 else
563 {
564 m_Start.y = aCentre.y - ( m_Start.y - aCentre.y );
565 m_End.y = aCentre.y - ( m_End.y - aCentre.y );
566 m_Mid.y = aCentre.y - ( m_Mid.y - aCentre.y );
567 }
568
569 int copperLayerCount = GetBoard()->GetCopperLayerCount();
570 SetLayer( FlipLayer( GetLayer(), copperLayerCount ) );
571}
572
573
574bool PCB_ARC::IsCCW() const
575{
576 VECTOR2I start_end = m_End - m_Start;
577 VECTOR2I start_mid = m_Mid - m_Start;
578
579 return start_end.Cross( start_mid ) < 0;
580}
581
582
583void PCB_VIA::Flip( const VECTOR2I& aCentre, bool aFlipLeftRight )
584{
585 if( aFlipLeftRight )
586 {
587 m_Start.x = aCentre.x - ( m_Start.x - aCentre.x );
588 m_End.x = aCentre.x - ( m_End.x - aCentre.x );
589 }
590 else
591 {
592 m_Start.y = aCentre.y - ( m_Start.y - aCentre.y );
593 m_End.y = aCentre.y - ( m_End.y - aCentre.y );
594 }
595
596 if( GetViaType() != VIATYPE::THROUGH )
597 {
598 int copperLayerCount = GetBoard()->GetCopperLayerCount();
599 PCB_LAYER_ID top_layer;
600 PCB_LAYER_ID bottom_layer;
601 LayerPair( &top_layer, &bottom_layer );
602 top_layer = FlipLayer( top_layer, copperLayerCount );
603 bottom_layer = FlipLayer( bottom_layer, copperLayerCount );
604 SetLayerPair( top_layer, bottom_layer );
605 }
606}
607
608
609INSPECT_RESULT PCB_TRACK::Visit( INSPECTOR inspector, void* testData,
610 const std::vector<KICAD_T>& aScanTypes )
611{
612 for( KICAD_T scanType : aScanTypes )
613 {
614 if( scanType == Type() )
615 {
616 if( INSPECT_RESULT::QUIT == inspector( this, testData ) )
617 return INSPECT_RESULT::QUIT;
618 }
619 }
620
621 return INSPECT_RESULT::CONTINUE;
622}
623
624
625std::shared_ptr<SHAPE_SEGMENT> PCB_VIA::GetEffectiveHoleShape() const
626{
627 return std::make_shared<SHAPE_SEGMENT>( SEG( m_Start, m_Start ), m_drill );
628}
629
630
632{
633 if( const BOARD* board = GetBoard() )
634 return board->GetTentVias();
635 else
636 return true;
637}
638
639
641{
642 if( const BOARD* board = GetBoard() )
643 return board->GetDesignSettings().m_SolderMaskExpansion;
644 else
645 return 0;
646}
647
648
650{
651#if 0
652 // Nice and simple, but raises its ugly head in performance profiles....
653 return GetLayerSet().test( aLayer );
654#endif
655
656 if( aLayer >= m_layer && aLayer <= m_bottomLayer )
657 return true;
658
659 if( !IsTented() )
660 {
661 if( aLayer == F_Mask )
662 return IsOnLayer( F_Cu );
663 else if( aLayer == B_Mask )
664 return IsOnLayer( B_Cu );
665 }
666
667 return false;
668}
669
670
672{
673 LSET layermask;
674
676 return layermask;
677
678 if( GetViaType() == VIATYPE::THROUGH )
679 layermask = LSET::AllCuMask();
680 else
681 wxASSERT( m_layer <= m_bottomLayer );
682
683 // PCB_LAYER_IDs are numbered from front to back, this is top to bottom.
684 for( int id = m_layer; id <= m_bottomLayer; ++id )
685 layermask.set( id );
686
687 if( !IsTented() )
688 {
689 if( layermask.test( F_Cu ) )
690 layermask.set( F_Mask );
691
692 if( layermask.test( B_Cu ) )
693 layermask.set( B_Mask );
694 }
695
696 return layermask;
697}
698
699
700void PCB_VIA::SetLayerSet( LSET aLayerSet )
701{
702 bool first = true;
703
704 for( PCB_LAYER_ID layer : aLayerSet.Seq() )
705 {
706 // m_layer and m_bottomLayer are copper layers, so consider only copper layers in aLayerSet
707 if( !IsCopperLayer( layer ) )
708 continue;
709
710 if( first )
711 {
712 m_layer = layer;
713 first = false;
714 }
715
716 m_bottomLayer = layer;
717 }
718}
719
720
721void PCB_VIA::SetLayerPair( PCB_LAYER_ID aTopLayer, PCB_LAYER_ID aBottomLayer )
722{
723
724 m_layer = aTopLayer;
725 m_bottomLayer = aBottomLayer;
727}
728
729
731{
732 m_layer = aLayer;
733}
734
735
737{
738 m_bottomLayer = aLayer;
739}
740
741
742void PCB_VIA::LayerPair( PCB_LAYER_ID* top_layer, PCB_LAYER_ID* bottom_layer ) const
743{
744 PCB_LAYER_ID t_layer = F_Cu;
745 PCB_LAYER_ID b_layer = B_Cu;
746
747 if( GetViaType() != VIATYPE::THROUGH )
748 {
749 b_layer = m_bottomLayer;
750 t_layer = m_layer;
751
752 if( b_layer < t_layer )
753 std::swap( b_layer, t_layer );
754 }
755
756 if( top_layer )
757 *top_layer = t_layer;
758
759 if( bottom_layer )
760 *bottom_layer = b_layer;
761}
762
763
765{
766 return m_layer;
767}
768
769
771{
772 return m_bottomLayer;
773}
774
775
777{
778 if( GetViaType() == VIATYPE::THROUGH )
779 {
780 m_layer = F_Cu;
782 }
783
784 if( m_bottomLayer < m_layer )
785 std::swap( m_bottomLayer, m_layer );
786}
787
788
789bool PCB_VIA::FlashLayer( LSET aLayers ) const
790{
791 for( PCB_LAYER_ID layer : aLayers.Seq() )
792 {
793 if( FlashLayer( layer ) )
794 return true;
795 }
796
797 return false;
798}
799
800
801bool PCB_VIA::FlashLayer( int aLayer ) const
802{
803 // Return the "normal" shape if the caller doesn't specify a particular layer
804 if( aLayer == UNDEFINED_LAYER )
805 return true;
806
807 const BOARD* board = GetBoard();
808
809 if( !board )
810 return true;
811
812 if( !IsOnLayer( static_cast<PCB_LAYER_ID>( aLayer ) ) )
813 return false;
814
815 if( !m_removeUnconnectedLayer || !IsCopperLayer( aLayer ) )
816 return true;
817
818 if( m_keepStartEndLayer && ( aLayer == m_layer || aLayer == m_bottomLayer ) )
819 return true;
820
821 // Must be static to keep from raising its ugly head in performance profiles
822 static std::initializer_list<KICAD_T> connectedTypes = { PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T,
823 PCB_PAD_T };
824
825 if( m_zoneLayerOverrides[ aLayer ] == ZLO_FORCE_FLASHED )
826 return true;
827 else
828 return board->GetConnectivity()->IsConnectedOnLayer( this, aLayer, connectedTypes );
829}
830
831
833 PCB_LAYER_ID* aBottommost ) const
834{
835 *aTopmost = UNDEFINED_LAYER;
836 *aBottommost = UNDEFINED_LAYER;
837
838 static std::initializer_list<KICAD_T> connectedTypes = { PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T,
839 PCB_PAD_T };
840
841 for( int layer = TopLayer(); layer <= BottomLayer(); ++layer )
842 {
843 bool connected = false;
844
846 connected = true;
847 else if( GetBoard()->GetConnectivity()->IsConnectedOnLayer( this, layer, connectedTypes ) )
848 connected = true;
849
850 if( connected )
851 {
852 if( *aTopmost == UNDEFINED_LAYER )
853 *aTopmost = ToLAYER_ID( layer );
854
855 *aBottommost = ToLAYER_ID( layer );
856 }
857 }
858
859}
860
861
862void PCB_TRACK::ViewGetLayers( int aLayers[], int& aCount ) const
863{
864 // Show the track and its netname on different layers
865 aLayers[0] = GetLayer();
866 aLayers[1] = GetNetnameLayer( aLayers[0] );
867 aCount = 2;
868
869 if( IsLocked() )
870 aLayers[ aCount++ ] = LAYER_LOCKED_ITEM_SHADOW;
871}
872
873
874double PCB_TRACK::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
875{
876 constexpr double HIDE = std::numeric_limits<double>::max();
877
878 PCB_PAINTER* painter = static_cast<PCB_PAINTER*>( aView->GetPainter() );
879 PCB_RENDER_SETTINGS* renderSettings = painter->GetSettings();
880
881 if( !aView->IsLayerVisible( LAYER_TRACKS ) )
882 return HIDE;
883
884 if( IsNetnameLayer( aLayer ) )
885 {
887 return HIDE;
888
889 // Hide netnames on dimmed tracks
890 if( renderSettings->GetHighContrast() )
891 {
892 if( m_layer != renderSettings->GetPrimaryHighContrastLayer() )
893 return HIDE;
894 }
895
896 // Pick the approximate size of the netname (square chars)
897 wxString netName = GetUnescapedShortNetname();
898 size_t num_chars = netName.size();
899
900 if( GetLength() < num_chars * GetWidth() )
901 return HIDE;
902
903 // When drawing netnames, clip the track to the viewport
904 VECTOR2I start( GetStart() );
905 VECTOR2I end( GetEnd() );
906 BOX2D viewport = aView->GetViewport();
907 BOX2I clipBox( viewport.GetOrigin(), viewport.GetSize() );
908
909 ClipLine( &clipBox, start.x, start.y, end.x, end.y );
910
911 VECTOR2I line = ( end - start );
912
913 if( line.EuclideanNorm() == 0 )
914 return HIDE;
915
916 // Netnames will be shown only if zoom is appropriate
917 return ( double ) pcbIUScale.mmToIU( 4 ) / ( m_Width + 1 );
918 }
919
920 if( aLayer == LAYER_LOCKED_ITEM_SHADOW )
921 {
922 // Hide shadow if the main layer is not shown
923 if( !aView->IsLayerVisible( m_layer ) )
924 return HIDE;
925
926 // Hide shadow on dimmed tracks
927 if( renderSettings->GetHighContrast() )
928 {
929 if( m_layer != renderSettings->GetPrimaryHighContrastLayer() )
930 return HIDE;
931 }
932 }
933
934 // Other layers are shown without any conditions
935 return 0.0;
936}
937
938
940{
941 BOX2I bbox = GetBoundingBox();
942
943 if( const BOARD* board = GetBoard() )
944 bbox.Inflate( 2 * board->GetDesignSettings().GetBiggestClearanceValue() );
945 else
946 bbox.Inflate( GetWidth() ); // Add a bit extra for safety
947
948 return bbox;
949}
950
951
952void PCB_VIA::ViewGetLayers( int aLayers[], int& aCount ) const
953{
954 aLayers[0] = LAYER_VIA_HOLES;
955 aLayers[1] = LAYER_VIA_HOLEWALLS;
956 aLayers[2] = LAYER_VIA_NETNAMES;
957
958 // Just show it on common via & via holes layers
959 switch( GetViaType() )
960 {
961 case VIATYPE::THROUGH: aLayers[3] = LAYER_VIA_THROUGH; break;
962 case VIATYPE::BLIND_BURIED: aLayers[3] = LAYER_VIA_BBLIND; break;
963 case VIATYPE::MICROVIA: aLayers[3] = LAYER_VIA_MICROVIA; break;
964 default: aLayers[3] = LAYER_GP_OVERLAY; break;
965 }
966
967 aCount = 4;
968
969 if( IsLocked() )
970 aLayers[ aCount++ ] = LAYER_LOCKED_ITEM_SHADOW;
971
972 // Vias can also be on a solder mask layer. They are on these layers or not,
973 // depending on the plot and solder mask options
974 if( IsOnLayer( F_Mask ) )
975 aLayers[ aCount++ ] = F_Mask;
976
977 if( IsOnLayer( B_Mask ) )
978 aLayers[ aCount++ ] = B_Mask;
979}
980
981
982double PCB_VIA::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
983{
984 constexpr double HIDE = (double)std::numeric_limits<double>::max();
985
986 PCB_PAINTER* painter = static_cast<PCB_PAINTER*>( aView->GetPainter() );
987 PCB_RENDER_SETTINGS* renderSettings = painter->GetSettings();
988 LSET visible = LSET::AllLayersMask();
989
990 // Meta control for hiding all vias
991 if( !aView->IsLayerVisible( LAYER_VIAS ) )
992 return HIDE;
993
994 // Handle board visibility
995 if( const BOARD* board = GetBoard() )
996 visible = board->GetVisibleLayers() & board->GetEnabledLayers();
997
998 // In high contrast mode don't show vias that don't cross the high-contrast layer
999 if( renderSettings->GetHighContrast() )
1000 {
1001 PCB_LAYER_ID highContrastLayer = renderSettings->GetPrimaryHighContrastLayer();
1002
1003 if( LSET::FrontTechMask().Contains( highContrastLayer ) )
1004 highContrastLayer = F_Cu;
1005 else if( LSET::BackTechMask().Contains( highContrastLayer ) )
1006 highContrastLayer = B_Cu;
1007
1008 if( !GetLayerSet().Contains( highContrastLayer ) )
1009 return HIDE;
1010 }
1011
1012 if( IsHoleLayer( aLayer ) )
1013 {
1014 if( m_viaType == VIATYPE::BLIND_BURIED || m_viaType == VIATYPE::MICROVIA )
1015 {
1016 // Show a blind or micro via's hole if it crosses a visible layer
1017 if( !( visible & GetLayerSet() ).any() )
1018 return HIDE;
1019 }
1020 else
1021 {
1022 // Show a through via's hole if any physical layer is shown
1023 if( !( visible & LSET::PhysicalLayersMask() ).any() )
1024 return HIDE;
1025 }
1026 }
1027 else if( IsNetnameLayer( aLayer ) )
1028 {
1029 if( renderSettings->GetHighContrast() )
1030 {
1031 // Hide netnames unless via is flashed to a high-contrast layer
1032 if( !FlashLayer( renderSettings->GetPrimaryHighContrastLayer() ) )
1033 return HIDE;
1034 }
1035 else
1036 {
1037 // Hide netnames unless pad is flashed to a visible layer
1038 if( !FlashLayer( visible ) )
1039 return HIDE;
1040 }
1041
1042 // Netnames will be shown only if zoom is appropriate
1043 return m_Width == 0 ? HIDE : ( (double)pcbIUScale.mmToIU( 10 ) / m_Width );
1044 }
1045
1046 // Passed all tests; show.
1047 return 0.0;
1048}
1049
1050
1052{
1053 switch( Type() )
1054 {
1055 case PCB_ARC_T: return _( "Track (arc)" );
1056 case PCB_VIA_T: return _( "Via" );
1057 case PCB_TRACE_T:
1058 default: return _( "Track" );
1059 }
1060}
1061
1062
1063void PCB_TRACK::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>& aList )
1064{
1065 wxString msg;
1066 BOARD* board = GetBoard();
1067
1068 aList.emplace_back( _( "Type" ), GetFriendlyName() );
1069
1070 GetMsgPanelInfoBase_Common( aFrame, aList );
1071
1072 aList.emplace_back( _( "Layer" ), layerMaskDescribe() );
1073
1074 aList.emplace_back( _( "Width" ), aFrame->MessageTextFromValue( m_Width ) );
1075
1076 if( Type() == PCB_ARC_T )
1077 {
1078 double radius = static_cast<PCB_ARC*>( this )->GetRadius();
1079 aList.emplace_back( _( "Radius" ), aFrame->MessageTextFromValue( radius ) );
1080 }
1081
1082 aList.emplace_back( _( "Segment Length" ), aFrame->MessageTextFromValue( GetLength() ) );
1083
1084 // Display full track length (in Pcbnew)
1085 if( board && GetNetCode() > 0 )
1086 {
1087 int count;
1088 double trackLen;
1089 double lenPadToDie;
1090
1091 std::tie( count, trackLen, lenPadToDie ) = board->GetTrackLength( *this );
1092
1093 aList.emplace_back( _( "Routed Length" ), aFrame->MessageTextFromValue( trackLen ) );
1094
1095 if( lenPadToDie != 0 )
1096 {
1097 msg = aFrame->MessageTextFromValue( lenPadToDie );
1098 aList.emplace_back( _( "Pad To Die Length" ), msg );
1099
1100 msg = aFrame->MessageTextFromValue( trackLen + lenPadToDie );
1101 aList.emplace_back( _( "Full Length" ), msg );
1102 }
1103 }
1104
1105 wxString source;
1106 int clearance = GetOwnClearance( GetLayer(), &source );
1107
1108 aList.emplace_back( wxString::Format( _( "Min Clearance: %s" ),
1109 aFrame->MessageTextFromValue( clearance ) ),
1110 wxString::Format( _( "(from %s)" ), source ) );
1111
1112 MINOPTMAX<int> constraintValue = GetWidthConstraint( &source );
1113 msg = aFrame->MessageTextFromMinOptMax( constraintValue );
1114
1115 if( !msg.IsEmpty() )
1116 {
1117 aList.emplace_back( wxString::Format( _( "Width Constraints: %s" ), msg ),
1118 wxString::Format( _( "(from %s)" ), source ) );
1119 }
1120}
1121
1122
1123void PCB_VIA::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>& aList )
1124{
1125 wxString msg;
1126
1127 switch( GetViaType() )
1128 {
1129 case VIATYPE::MICROVIA: msg = _( "Micro Via" ); break;
1130 case VIATYPE::BLIND_BURIED: msg = _( "Blind/Buried Via" ); break;
1131 case VIATYPE::THROUGH: msg = _( "Through Via" ); break;
1132 default: msg = _( "Via" ); break;
1133 }
1134
1135 aList.emplace_back( _( "Type" ), msg );
1136
1137 GetMsgPanelInfoBase_Common( aFrame, aList );
1138
1139 aList.emplace_back( _( "Layer" ), layerMaskDescribe() );
1140 aList.emplace_back( _( "Diameter" ), aFrame->MessageTextFromValue( m_Width ) );
1141 aList.emplace_back( _( "Hole" ), aFrame->MessageTextFromValue( GetDrillValue() ) );
1142
1143 wxString source;
1144 int clearance = GetOwnClearance( GetLayer(), &source );
1145
1146 aList.emplace_back( wxString::Format( _( "Min Clearance: %s" ),
1147 aFrame->MessageTextFromValue( clearance ) ),
1148 wxString::Format( _( "(from %s)" ), source ) );
1149
1150 int minAnnulus = GetMinAnnulus( GetLayer(), &source );
1151
1152 aList.emplace_back( wxString::Format( _( "Min Annular Width: %s" ),
1153 aFrame->MessageTextFromValue( minAnnulus ) ),
1154 wxString::Format( _( "(from %s)" ), source ) );
1155}
1156
1157
1159 std::vector<MSG_PANEL_ITEM>& aList ) const
1160{
1161 aList.emplace_back( _( "Net" ), UnescapeString( GetNetname() ) );
1162
1163 aList.emplace_back( _( "Resolved Netclass" ),
1164 UnescapeString( GetEffectiveNetClass()->GetName() ) );
1165
1166#if 0 // Enable for debugging
1167 if( GetBoard() )
1168 aList.emplace_back( _( "NetCode" ), wxString::Format( wxT( "%d" ), GetNetCode() ) );
1169
1170 aList.emplace_back( wxT( "Flags" ), wxString::Format( wxT( "0x%08X" ), m_flags ) );
1171
1172 aList.emplace_back( wxT( "Start pos" ), wxString::Format( wxT( "%d %d" ),
1173 m_Start.x,
1174 m_Start.y ) );
1175 aList.emplace_back( wxT( "End pos" ), wxString::Format( wxT( "%d %d" ),
1176 m_End.x,
1177 m_End.y ) );
1178#endif
1179
1180 if( aFrame->GetName() == PCB_EDIT_FRAME_NAME && IsLocked() )
1181 aList.emplace_back( _( "Status" ), _( "Locked" ) );
1182}
1183
1184
1186{
1187 const BOARD* board = GetBoard();
1188 PCB_LAYER_ID top_layer;
1189 PCB_LAYER_ID bottom_layer;
1190
1191 LayerPair( &top_layer, &bottom_layer );
1192
1193 return board->GetLayerName( top_layer ) + wxT( " - " ) + board->GetLayerName( bottom_layer );
1194}
1195
1196
1197bool PCB_TRACK::HitTest( const VECTOR2I& aPosition, int aAccuracy ) const
1198{
1199 return TestSegmentHit( aPosition, m_Start, m_End, aAccuracy + ( m_Width / 2 ) );
1200}
1201
1202
1203bool PCB_ARC::HitTest( const VECTOR2I& aPosition, int aAccuracy ) const
1204{
1205 int max_dist = aAccuracy + ( m_Width / 2 );
1206
1207 // Short-circuit common cases where the arc is connected to a track or via at an endpoint
1208 if( EuclideanNorm( GetStart() - aPosition ) <= max_dist ||
1209 EuclideanNorm( GetEnd() - aPosition ) <= max_dist )
1210 {
1211 return true;
1212 }
1213
1214 VECTOR2I center = GetPosition();
1215 VECTOR2I relpos = aPosition - center;
1216 double dist = EuclideanNorm( relpos );
1217 double radius = GetRadius();
1218
1219 if( std::abs( dist - radius ) > max_dist )
1220 return false;
1221
1222 EDA_ANGLE arc_angle = GetAngle();
1223 EDA_ANGLE arc_angle_start = GetArcAngleStart(); // Always 0.0 ... 360 deg
1224 EDA_ANGLE arc_hittest( relpos );
1225
1226 // Calculate relative angle between the starting point of the arc, and the test point
1227 arc_hittest -= arc_angle_start;
1228
1229 // Normalise arc_hittest between 0 ... 360 deg
1230 arc_hittest.Normalize();
1231
1232 if( arc_angle < ANGLE_0 )
1233 return arc_hittest >= ANGLE_360 + arc_angle;
1234
1235 return arc_hittest <= arc_angle;
1236}
1237
1238
1239bool PCB_VIA::HitTest( const VECTOR2I& aPosition, int aAccuracy ) const
1240{
1241 int max_dist = aAccuracy + ( m_Width / 2 );
1242
1243 // rel_pos is aPosition relative to m_Start (or the center of the via)
1244 VECTOR2I rel_pos = aPosition - m_Start;
1245 double dist = (double) rel_pos.x * rel_pos.x + (double) rel_pos.y * rel_pos.y;
1246 return dist <= (double) max_dist * max_dist;
1247}
1248
1249
1250bool PCB_TRACK::HitTest( const BOX2I& aRect, bool aContained, int aAccuracy ) const
1251{
1252 BOX2I arect = aRect;
1253 arect.Inflate( aAccuracy );
1254
1255 if( aContained )
1256 return arect.Contains( GetStart() ) && arect.Contains( GetEnd() );
1257 else
1258 return arect.Intersects( GetStart(), GetEnd() );
1259}
1260
1261
1262bool PCB_ARC::HitTest( const BOX2I& aRect, bool aContained, int aAccuracy ) const
1263{
1264 BOX2I arect = aRect;
1265 arect.Inflate( aAccuracy );
1266
1267 BOX2I box( GetStart() );
1268 box.Merge( GetMid() );
1269 box.Merge( GetEnd() );
1270
1271 box.Inflate( GetWidth() / 2 );
1272
1273 if( aContained )
1274 return arect.Contains( box );
1275 else
1276 return arect.Intersects( box );
1277}
1278
1279
1280bool PCB_VIA::HitTest( const BOX2I& aRect, bool aContained, int aAccuracy ) const
1281{
1282 BOX2I arect = aRect;
1283 arect.Inflate( aAccuracy );
1284
1285 BOX2I box( GetStart() );
1286 box.Inflate( GetWidth() / 2 );
1287
1288 if( aContained )
1289 return arect.Contains( box );
1290 else
1291 return arect.IntersectsCircle( GetStart(), GetWidth() / 2 );
1292}
1293
1294
1295wxString PCB_TRACK::GetItemDescription( UNITS_PROVIDER* aUnitsProvider ) const
1296{
1297 return wxString::Format( Type() == PCB_ARC_T ? _("Track (arc) %s on %s, length %s" )
1298 : _("Track %s on %s, length %s" ),
1299 GetNetnameMsg(),
1300 GetLayerName(),
1301 aUnitsProvider->MessageTextFromValue( GetLength() ) );
1302}
1303
1304
1306{
1307 return BITMAPS::add_tracks;
1308}
1309
1311{
1312 assert( aImage->Type() == PCB_TRACE_T );
1313
1314 std::swap( *((PCB_TRACK*) this), *((PCB_TRACK*) aImage) );
1315}
1316
1318{
1319 assert( aImage->Type() == PCB_ARC_T );
1320
1321 std::swap( *this, *static_cast<PCB_ARC*>( aImage ) );
1322}
1323
1325{
1326 assert( aImage->Type() == PCB_VIA_T );
1327
1328 std::swap( *((PCB_VIA*) this), *((PCB_VIA*) aImage) );
1329}
1330
1331
1333{
1335 return center;
1336}
1337
1338
1340{
1341 auto center = CalcArcCenter( m_Start, m_Mid , m_End );
1342 return GetLineLength( center, m_Start );
1343}
1344
1345
1347{
1348 VECTOR2I center = GetPosition();
1349 EDA_ANGLE angle1 = EDA_ANGLE( m_Mid - center ) - EDA_ANGLE( m_Start - center );
1350 EDA_ANGLE angle2 = EDA_ANGLE( m_End - center ) - EDA_ANGLE( m_Mid - center );
1351
1352 return angle1.Normalize180() + angle2.Normalize180();
1353}
1354
1355
1357{
1358 EDA_ANGLE angleStart( m_Start - GetPosition() );
1359 return angleStart.Normalize();
1360}
1361
1362
1363// Note: used in python tests. Ignore CLion's claim that it's unused....
1365{
1366 EDA_ANGLE angleEnd( m_End - GetPosition() );
1367 return angleEnd.Normalize();
1368}
1369
1370bool PCB_ARC::IsDegenerated( int aThreshold ) const
1371{
1372 // Too small arcs cannot be really handled: arc center (and arc radius)
1373 // cannot be safely computed if the distance between mid and end points
1374 // is too small (a few internal units)
1375
1376 // len of both segments must be < aThreshold to be a very small degenerated arc
1377 return ( GetMid() - GetStart() ).EuclideanNorm() < aThreshold
1378 && ( GetMid() - GetEnd() ).EuclideanNorm() < aThreshold;
1379}
1380
1381
1383{
1384 if( a->GetNetCode() != b->GetNetCode() )
1385 return a->GetNetCode() < b->GetNetCode();
1386
1387 if( a->GetLayer() != b->GetLayer() )
1388 return a->GetLayer() < b->GetLayer();
1389
1390 if( a->Type() != b->Type() )
1391 return a->Type() < b->Type();
1392
1393 if( a->m_Uuid != b->m_Uuid )
1394 return a->m_Uuid < b->m_Uuid;
1395
1396 return a < b;
1397}
1398
1399
1400std::shared_ptr<SHAPE> PCB_TRACK::GetEffectiveShape( PCB_LAYER_ID aLayer, FLASHING aFlash ) const
1401{
1402 return std::make_shared<SHAPE_SEGMENT>( m_Start, m_End, m_Width );
1403}
1404
1405
1406std::shared_ptr<SHAPE> PCB_VIA::GetEffectiveShape( PCB_LAYER_ID aLayer, FLASHING aFlash ) const
1407{
1408 if( aFlash == FLASHING::ALWAYS_FLASHED
1409 || ( aFlash == FLASHING::DEFAULT && FlashLayer( aLayer ) ) )
1410 {
1411 return std::make_shared<SHAPE_CIRCLE>( m_Start, m_Width / 2 );
1412 }
1413 else
1414 {
1415 return std::make_shared<SHAPE_CIRCLE>( m_Start, GetDrillValue() / 2 );
1416 }
1417}
1418
1419
1420std::shared_ptr<SHAPE> PCB_ARC::GetEffectiveShape( PCB_LAYER_ID aLayer, FLASHING aFlash ) const
1421{
1422 return std::make_shared<SHAPE_ARC>( GetStart(), GetMid(), GetEnd(), GetWidth() );
1423}
1424
1425
1427 int aClearance, int aError, ERROR_LOC aErrorLoc,
1428 bool ignoreLineWidth ) const
1429{
1430 wxASSERT_MSG( !ignoreLineWidth, wxT( "IgnoreLineWidth has no meaning for tracks." ) );
1431
1432
1433 switch( Type() )
1434 {
1435 case PCB_VIA_T:
1436 {
1437 int radius = ( m_Width / 2 ) + aClearance;
1438 TransformCircleToPolygon( aBuffer, m_Start, radius, aError, aErrorLoc );
1439 break;
1440 }
1441
1442 case PCB_ARC_T:
1443 {
1444 const PCB_ARC* arc = static_cast<const PCB_ARC*>( this );
1445 int width = m_Width + ( 2 * aClearance );
1446
1447 TransformArcToPolygon( aBuffer, arc->GetStart(), arc->GetMid(), arc->GetEnd(), width,
1448 aError, aErrorLoc );
1449 break;
1450 }
1451
1452 default:
1453 {
1454 int width = m_Width + ( 2 * aClearance );
1455
1456 TransformOvalToPolygon( aBuffer, m_Start, m_End, width, aError, aErrorLoc );
1457 break;
1458 }
1459 }
1460}
1461
1462
1463static struct TRACK_VIA_DESC
1464{
1466 {
1468 .Undefined( VIATYPE::NOT_DEFINED )
1469 .Map( VIATYPE::THROUGH, _HKI( "Through" ) )
1470 .Map( VIATYPE::BLIND_BURIED, _HKI( "Blind/buried" ) )
1471 .Map( VIATYPE::MICROVIA, _HKI( "Micro" ) );
1472
1474
1475 if( layerEnum.Choices().GetCount() == 0 )
1476 {
1477 layerEnum.Undefined( UNDEFINED_LAYER );
1478
1479 for( LSEQ seq = LSET::AllLayersMask().Seq(); seq; ++seq )
1480 layerEnum.Map( *seq, LSET::Name( *seq ) );
1481 }
1482
1484
1485 // Track
1488
1489 propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "Width" ),
1490 &PCB_TRACK::SetWidth, &PCB_TRACK::GetWidth, PROPERTY_DISPLAY::PT_SIZE ) );
1491 propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Position X" ),
1493 &PCB_TRACK::SetX, &PCB_TRACK::GetX, PROPERTY_DISPLAY::PT_COORD,
1495 propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Position Y" ),
1497 &PCB_TRACK::SetY, &PCB_TRACK::GetY, PROPERTY_DISPLAY::PT_COORD,
1499 propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "End X" ),
1500 &PCB_TRACK::SetEndX, &PCB_TRACK::GetEndX, PROPERTY_DISPLAY::PT_COORD,
1502 propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "End Y" ),
1503 &PCB_TRACK::SetEndY, &PCB_TRACK::GetEndY, PROPERTY_DISPLAY::PT_COORD,
1505
1506 // Arc
1509
1510 // Via
1513
1514 // TODO test drill, use getdrillvalue?
1515 const wxString groupVia = _HKI( "Via Properties" );
1516
1517 propMgr.Mask( TYPE_HASH( PCB_VIA ), TYPE_HASH( BOARD_CONNECTED_ITEM ), _HKI( "Layer" ) );
1518
1519 propMgr.ReplaceProperty( TYPE_HASH( PCB_TRACK ), _HKI( "Width" ),
1520 new PROPERTY<PCB_VIA, int, PCB_TRACK>( _HKI( "Diameter" ),
1521 &PCB_VIA::SetWidth, &PCB_VIA::GetWidth, PROPERTY_DISPLAY::PT_SIZE ) );
1522 propMgr.AddProperty( new PROPERTY<PCB_VIA, int>( _HKI( "Hole" ),
1523 &PCB_VIA::SetDrill, &PCB_VIA::GetDrillValue, PROPERTY_DISPLAY::PT_SIZE ), groupVia );
1524 propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Layer" ),
1526 &PCB_VIA::SetLayer, &PCB_VIA::GetLayer ), groupVia );
1527 propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, PCB_LAYER_ID>( _HKI( "Layer Bottom" ),
1529 propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, VIATYPE>( _HKI( "Via Type" ),
1531 }
1533
constexpr EDA_IU_SCALE pcbIUScale
Definition: base_units.h:109
BITMAPS
A list of all bitmap identifiers.
Definition: bitmaps_list.h:33
@ ZLO_NONE
Definition: board_item.h:65
@ ZLO_FORCE_FLASHED
Definition: board_item.h:66
A base class derived from BOARD_ITEM for items that can be connected and have a net,...
wxString GetNetnameMsg() const
virtual NETCLASS * GetEffectiveNetClass() const
Return the NETCLASS for this item.
virtual int GetOwnClearance(PCB_LAYER_ID aLayer, wxString *aSource=nullptr) const
Return an item's "own" clearance in internal units.
wxString GetUnescapedShortNetname() const
Container for design settings for a BOARD object.
std::shared_ptr< DRC_ENGINE > m_DRCEngine
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition: board_item.h:77
virtual PCB_LAYER_ID GetLayer() const
Return the primary layer this item is on.
Definition: board_item.h:225
int GetY() const
Definition: board_item.h:101
PCB_LAYER_ID m_layer
Definition: board_item.h:387
int GetX() const
Definition: board_item.h:95
void SetX(int aX)
Definition: board_item.h:117
void SetY(int aY)
Definition: board_item.h:123
virtual void SetLayer(PCB_LAYER_ID aLayer)
Set the layer this item is on.
Definition: board_item.h:259
virtual const BOARD * GetBoard() const
Return the BOARD in which this BOARD_ITEM resides, or NULL if none.
Definition: board_item.cpp:45
virtual bool IsLocked() const
Definition: board_item.cpp:73
virtual wxString layerMaskDescribe() const
Return a string (to be shown to the user) describing a layer mask.
Definition: board_item.cpp:114
wxString GetLayerName() const
Return the name of the PCB layer on which the item resides.
Definition: board_item.cpp:102
Information pertinent to a Pcbnew printed circuit board.
Definition: board.h:276
int GetCopperLayerCount() const
Definition: board.cpp:625
const wxString GetLayerName(PCB_LAYER_ID aLayer) const
Return the name of a aLayer.
Definition: board.cpp:536
std::tuple< int, double, double > GetTrackLength(const PCB_TRACK &aTrack) const
Return data on the length and number of track segments connected to a given track.
Definition: board.cpp:2009
BOARD_DESIGN_SETTINGS & GetDesignSettings() const
Definition: board.cpp:766
std::shared_ptr< CONNECTIVITY_DATA > GetConnectivity() const
Return a list of missing connections between components/tracks.
Definition: board.h:441
const Vec & GetOrigin() const
Definition: box2.h:184
bool Intersects(const BOX2< Vec > &aRect) const
Definition: box2.h:270
coord_type GetTop() const
Definition: box2.h:195
bool IntersectsCircle(const Vec &aCenter, const int aRadius) const
Definition: box2.h:453
bool Contains(const Vec &aPoint) const
Definition: box2.h:142
BOX2< Vec > & Inflate(coord_type dx, coord_type dy)
Inflates the rectangle horizontally by dx and vertically by dy.
Definition: box2.h:507
coord_type GetRight() const
Definition: box2.h:190
coord_type GetLeft() const
Definition: box2.h:194
const Vec & GetSize() const
Definition: box2.h:180
coord_type GetBottom() const
Definition: box2.h:191
BOX2< Vec > & Merge(const BOX2< Vec > &aRect)
Modify the position and size of the rectangle in order to contain aRect.
Definition: box2.h:589
wxString GetName() const
Definition: drc_rule.h:149
MINOPTMAX< int > & Value()
Definition: drc_rule.h:142
EDA_ANGLE Normalize()
Definition: eda_angle.h:249
EDA_ANGLE Normalize180()
Definition: eda_angle.h:288
The base class for create windows for drawing purpose.
A base class for most all the KiCad significant classes used in schematics and boards.
Definition: eda_item.h:85
EDA_ITEM & operator=(const EDA_ITEM &aItem)
Assign the members of aItem to another object.
Definition: eda_item.cpp:258
const KIID m_Uuid
Definition: eda_item.h:482
KICAD_T Type() const
Returns the type of object.
Definition: eda_item.h:97
EDA_ITEM_FLAGS m_flags
Definition: eda_item.h:487
ENUM_MAP & Map(T aValue, const wxString &aName)
Definition: property.h:646
static ENUM_MAP< T > & Instance()
Definition: property.h:640
ENUM_MAP & Undefined(T aValue)
Definition: property.h:653
wxPGChoices & Choices()
Definition: property.h:689
Contains methods for drawing PCB-specific items.
Definition: pcb_painter.h:163
virtual PCB_RENDER_SETTINGS * GetSettings() override
Return a pointer to current settings that are going to be used when drawing items.
Definition: pcb_painter.h:168
PCB specific render settings.
Definition: pcb_painter.h:76
PCB_LAYER_ID GetPrimaryHighContrastLayer() const
Return the board layer which is in high-contrast mode.
bool GetHighContrast() const
Hold a (potentially large) number of VIEW_ITEMs and renders them on a graphics device provided by the...
Definition: view.h:68
BOX2D GetViewport() const
Return the current viewport visible area rectangle.
Definition: view.cpp:507
bool IsLayerVisible(int aLayer) const
Return information about visibility of a particular layer.
Definition: view.h:412
PAINTER * GetPainter() const
Return the painter object used by the view for drawing #VIEW_ITEMS.
Definition: view.h:215
Definition: kiid.h:49
LSEQ is a sequence (and therefore also a set) of PCB_LAYER_IDs.
Definition: layer_ids.h:513
LSET is a set of PCB_LAYER_IDs.
Definition: layer_ids.h:556
static LSET AllLayersMask()
Definition: lset.cpp:817
LSEQ Seq(const PCB_LAYER_ID *aWishListSequence, unsigned aCount) const
Return an LSEQ from the union of this LSET and a desired sequence.
Definition: lset.cpp:418
static LSET AllCuMask(int aCuLayerCount=MAX_CU_LAYERS)
Return a mask holding the requested number of Cu PCB_LAYER_IDs.
Definition: lset.cpp:782
static LSET PhysicalLayersMask()
Return a mask holding all layers which are physically realized.
Definition: lset.cpp:879
static const wxChar * Name(PCB_LAYER_ID aLayerId)
Return the fixed name association with aLayerId.
Definition: lset.cpp:89
static LSET FrontTechMask()
Return a mask holding all technical layers (no CU layer) on front side.
Definition: lset.cpp:836
static LSET BackTechMask()
Return a mask holding all technical layers (no CU layer) on back side.
Definition: lset.cpp:824
T Min() const
Definition: minoptmax.h:33
bool HasMin() const
Definition: minoptmax.h:37
A collection of nets and the parameters used to route or test these nets.
Definition: netclass.h:47
int GetViaDrill() const
Definition: netclass.h:84
int GetuViaDrill() const
Definition: netclass.h:92
static const int UNCONNECTED
Constant that holds the "unconnected net" number (typically 0) all items "connected" to this net are ...
Definition: netinfo.h:370
bool operator==(const BOARD_ITEM &aOther) const override
Definition: pcb_track.cpp:191
virtual VECTOR2I GetPosition() const override
Definition: pcb_track.cpp:1332
bool IsDegenerated(int aThreshold=5) const
Definition: pcb_track.cpp:1370
virtual void swapData(BOARD_ITEM *aImage) override
Definition: pcb_track.cpp:1317
bool IsCCW() const
Definition: pcb_track.cpp:574
EDA_ITEM * Clone() const override
Create a duplicate of this item with linked list members set to NULL.
Definition: pcb_track.cpp:74
EDA_ANGLE GetArcAngleStart() const
Definition: pcb_track.cpp:1356
virtual bool HitTest(const VECTOR2I &aPosition, int aAccuracy=0) const override
Test if aPosition is inside or on the boundary of this item.
Definition: pcb_track.cpp:1203
EDA_ANGLE GetArcAngleEnd() const
Definition: pcb_track.cpp:1364
double GetRadius() const
Definition: pcb_track.cpp:1339
EDA_ANGLE GetAngle() const
Definition: pcb_track.cpp:1346
const VECTOR2I & GetMid() const
Definition: pcb_track.h:319
PCB_ARC(BOARD_ITEM *aParent)
Definition: pcb_track.h:294
void Flip(const VECTOR2I &aCentre, bool aFlipLeftRight) override
Flip this object, i.e.
Definition: pcb_track.cpp:554
double Similarity(const BOARD_ITEM &aOther) const override
Return a measure of how likely the other object is to represent the same object.
Definition: pcb_track.cpp:203
VECTOR2I m_Mid
Arc mid point, halfway between start and end.
Definition: pcb_track.h:375
void Rotate(const VECTOR2I &aRotCentre, const EDA_ANGLE &aAngle) override
Rotate this object.
Definition: pcb_track.cpp:496
std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const override
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
Definition: pcb_track.cpp:1420
void Mirror(const VECTOR2I &aCentre, bool aMirrorAroundXAxis) override
Definition: pcb_track.cpp:519
double m_CachedScale
Last zoom scale used to draw this track's net.
Definition: pcb_track.h:287
double m_CachedLOD
Last LOD used to draw this track's net.
Definition: pcb_track.h:286
void Rotate(const VECTOR2I &aRotCentre, const EDA_ANGLE &aAngle) override
Rotate this object.
Definition: pcb_track.cpp:489
virtual void ViewGetLayers(int aLayers[], int &aCount) const override
Return the all the layers within the VIEW the object is painted on.
Definition: pcb_track.cpp:862
int GetLocalClearance(wxString *aSource) const override
Return any local clearance overrides set in the "classic" (ie: pre-rule) system.
Definition: pcb_track.cpp:298
void SetEndY(int aY)
Definition: pcb_track.h:116
void SetWidth(int aWidth)
Definition: pcb_track.h:106
double ViewGetLOD(int aLayer, KIGFX::VIEW *aView) const override
Return the level of detail (LOD) of the item.
Definition: pcb_track.cpp:874
virtual double GetLength() const
Get the length of the track using the hypotenuse calculation.
Definition: pcb_track.cpp:483
int GetWidth() const
Definition: pcb_track.h:107
virtual void swapData(BOARD_ITEM *aImage) override
Definition: pcb_track.cpp:1310
wxString GetItemDescription(UNITS_PROVIDER *aUnitsProvider) const override
Return a user-visible description string of this item.
Definition: pcb_track.cpp:1295
const BOX2I ViewBBox() const override
Return the bounding box of the item covering all its layers.
Definition: pcb_track.cpp:939
int GetEndX() const
Definition: pcb_track.h:118
INSPECT_RESULT Visit(INSPECTOR inspector, void *testData, const std::vector< KICAD_T > &aScanTypes) override
May be re-implemented for each derived class in order to handle all the types given by its member dat...
Definition: pcb_track.cpp:609
bool ApproxCollinear(const PCB_TRACK &aTrack)
Definition: pcb_track.cpp:290
VECTOR2I m_End
Line end point.
Definition: pcb_track.h:284
void GetMsgPanelInfo(EDA_DRAW_FRAME *aFrame, std::vector< MSG_PANEL_ITEM > &aList) override
Populate aList of MSG_PANEL_ITEM objects with it's internal state for display purposes.
Definition: pcb_track.cpp:1063
virtual EDA_ITEM * Clone() const override
Create a duplicate of this item with linked list members set to NULL.
Definition: pcb_track.cpp:59
const BOX2I GetBoundingBox() const override
Return the orthogonal bounding box of this object for display purposes.
Definition: pcb_track.cpp:437
void TransformShapeToPolygon(SHAPE_POLY_SET &aBuffer, PCB_LAYER_ID aLayer, int aClearance, int aError, ERROR_LOC aErrorLoc, bool ignoreLineWidth=false) const override
Convert the track shape to a closed polygon.
Definition: pcb_track.cpp:1426
const VECTOR2I & GetStart() const
Definition: pcb_track.h:113
virtual bool operator==(const BOARD_ITEM &aOther) const override
Definition: pcb_track.cpp:154
VECTOR2I m_Start
Line start point.
Definition: pcb_track.h:283
int GetEndY() const
Definition: pcb_track.h:119
wxString GetFriendlyName() const override
Definition: pcb_track.cpp:1051
BITMAPS GetMenuImage() const override
Return a pointer to an image to be used in menus.
Definition: pcb_track.cpp:1305
void Flip(const VECTOR2I &aCentre, bool aFlipLeftRight) override
Flip this object, i.e.
Definition: pcb_track.cpp:536
bool HitTest(const VECTOR2I &aPosition, int aAccuracy=0) const override
Test if aPosition is inside or on the boundary of this item.
Definition: pcb_track.cpp:1197
virtual double Similarity(const BOARD_ITEM &aOther) const override
Return a measure of how likely the other object is to represent the same object.
Definition: pcb_track.cpp:166
std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const override
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
Definition: pcb_track.cpp:1400
const VECTOR2I & GetEnd() const
Definition: pcb_track.h:110
PCB_TRACK(BOARD_ITEM *aParent, KICAD_T idtype=PCB_TRACE_T)
Definition: pcb_track.cpp:50
int m_Width
Thickness of track, or via diameter.
Definition: pcb_track.h:282
virtual MINOPTMAX< int > GetWidthConstraint(wxString *aSource=nullptr) const
Definition: pcb_track.cpp:305
void SetEndX(int aX)
Definition: pcb_track.h:115
virtual void Mirror(const VECTOR2I &aCentre, bool aMirrorAroundXAxis)
Definition: pcb_track.cpp:504
EDA_ITEM_FLAGS IsPointOnEnds(const VECTOR2I &point, int min_dist=0) const
Return STARTPOINT if point if near (dist = min_dist) start point, ENDPOINT if point if near (dist = m...
Definition: pcb_track.cpp:405
void GetMsgPanelInfoBase_Common(EDA_DRAW_FRAME *aFrame, std::vector< MSG_PANEL_ITEM > &aList) const
Definition: pcb_track.cpp:1158
bool IsTented() const override
Definition: pcb_track.cpp:631
PCB_LAYER_ID BottomLayer() const
Definition: pcb_track.cpp:770
BITMAPS GetMenuImage() const override
Return a pointer to an image to be used in menus.
Definition: pcb_track.cpp:148
std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const override
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
Definition: pcb_track.cpp:1406
bool FlashLayer(int aLayer) const
Check to see whether the via should have a pad on the specific layer.
Definition: pcb_track.cpp:801
void SetDrillDefault()
Set the drill value for vias to the default value UNDEFINED_DRILL_DIAMETER.
Definition: pcb_track.h:569
PCB_LAYER_ID m_bottomLayer
The bottom layer of the via (the top layer is in m_layer)
Definition: pcb_track.h:612
bool m_isFree
"Free" vias don't get their nets auto-updated
Definition: pcb_track.h:620
bool HitTest(const VECTOR2I &aPosition, int aAccuracy=0) const override
Test if aPosition is inside or on the boundary of this item.
Definition: pcb_track.cpp:1239
virtual void SetLayerSet(LSET aLayers) override
Note SetLayerSet() initialize the first and last copper layers connected by the via.
Definition: pcb_track.cpp:700
void SetBottomLayer(PCB_LAYER_ID aLayer)
Definition: pcb_track.cpp:736
std::array< ZONE_LAYER_OVERRIDE, MAX_CU_LAYERS > m_zoneLayerOverrides
Definition: pcb_track.h:623
int GetSolderMaskExpansion() const
Definition: pcb_track.cpp:640
void SetDrill(int aDrill)
Set the drill value for vias.
Definition: pcb_track.h:550
MINOPTMAX< int > GetDrillConstraint(wxString *aSource=nullptr) const
Definition: pcb_track.cpp:341
bool operator==(const BOARD_ITEM &aOther) const override
Definition: pcb_track.cpp:231
void GetMsgPanelInfo(EDA_DRAW_FRAME *aFrame, std::vector< MSG_PANEL_ITEM > &aList) override
Populate aList of MSG_PANEL_ITEM objects with it's internal state for display purposes.
Definition: pcb_track.cpp:1123
EDA_ITEM * Clone() const override
Create a duplicate of this item with linked list members set to NULL.
Definition: pcb_track.cpp:127
int m_drill
for vias: via drill (- 1 for default value)
Definition: pcb_track.h:616
double ViewGetLOD(int aLayer, KIGFX::VIEW *aView) const override
Return the level of detail (LOD) of the item.
Definition: pcb_track.cpp:982
void SetTopLayer(PCB_LAYER_ID aLayer)
Definition: pcb_track.cpp:730
std::shared_ptr< SHAPE_SEGMENT > GetEffectiveHoleShape() const override
Definition: pcb_track.cpp:625
void SetLayerPair(PCB_LAYER_ID aTopLayer, PCB_LAYER_ID aBottomLayer)
For a via m_layer contains the top layer, the other layer is in m_bottomLayer/.
Definition: pcb_track.cpp:721
double Similarity(const BOARD_ITEM &aOther) const override
Return a measure of how likely the other object is to represent the same object.
Definition: pcb_track.cpp:247
bool m_removeUnconnectedLayer
Remove annular rings on unconnected layers.
Definition: pcb_track.h:618
void GetOutermostConnectedLayers(PCB_LAYER_ID *aTopmost, PCB_LAYER_ID *aBottommost) const
Return the top-most and bottom-most connected layers.
Definition: pcb_track.cpp:832
void ViewGetLayers(int aLayers[], int &aCount) const override
Return the all the layers within the VIEW the object is painted on.
Definition: pcb_track.cpp:952
void SanitizeLayers()
Check so that the layers are correct depending on the type of via, and so that the top actually is on...
Definition: pcb_track.cpp:776
PCB_VIA & operator=(const PCB_VIA &aOther)
Definition: pcb_track.cpp:106
void swapData(BOARD_ITEM *aImage) override
Definition: pcb_track.cpp:1324
PCB_VIA(BOARD_ITEM *aParent)
Definition: pcb_track.cpp:80
wxString layerMaskDescribe() const override
Return a string (to be shown to the user) describing a layer mask.
Definition: pcb_track.cpp:1185
void SetViaType(VIATYPE aViaType)
Definition: pcb_track.h:411
int GetMinAnnulus(PCB_LAYER_ID aLayer, wxString *aSource) const
Definition: pcb_track.cpp:359
bool IsOnLayer(PCB_LAYER_ID aLayer) const override
Test to see if this object is on the given layer.
Definition: pcb_track.cpp:649
PCB_LAYER_ID TopLayer() const
Definition: pcb_track.cpp:764
wxString GetItemDescription(UNITS_PROVIDER *aUnitsProvider) const override
Return a user-visible description string of this item.
Definition: pcb_track.cpp:133
VIATYPE m_viaType
through, blind/buried or micro
Definition: pcb_track.h:614
bool m_keepStartEndLayer
Keep the start and end annular rings.
Definition: pcb_track.h:619
int GetDrillValue() const
Calculate the drill value for vias (m_drill if > 0, or default drill value for the board).
Definition: pcb_track.cpp:390
VIATYPE GetViaType() const
Definition: pcb_track.h:410
MINOPTMAX< int > GetWidthConstraint(wxString *aSource=nullptr) const override
Definition: pcb_track.cpp:323
virtual LSET GetLayerSet() const override
Return a std::bitset of all layers on which the item physically resides.
Definition: pcb_track.cpp:671
void LayerPair(PCB_LAYER_ID *top_layer, PCB_LAYER_ID *bottom_layer) const
Return the 2 layers used by the via (the via actually uses all layers between these 2 layers)
Definition: pcb_track.cpp:742
void Flip(const VECTOR2I &aCentre, bool aFlipLeftRight) override
Flip this object, i.e.
Definition: pcb_track.cpp:583
Provide class metadata.Helper macro to map type hashes to names.
Definition: property_mgr.h:85
void InheritsAfter(TYPE_ID aDerived, TYPE_ID aBase)
Declare an inheritance relationship between types.
void Mask(TYPE_ID aDerived, TYPE_ID aBase, const wxString &aName)
Sets a base class property as masked in a derived class.
static PROPERTY_MANAGER & Instance()
Definition: property_mgr.h:87
PROPERTY_BASE & AddProperty(PROPERTY_BASE *aProperty, const wxString &aGroup=wxEmptyString)
Register a property.
PROPERTY_BASE & ReplaceProperty(size_t aBase, const wxString &aName, PROPERTY_BASE *aNew, const wxString &aGroup=wxEmptyString)
Replace an existing property for a specific type.
Definition: seg.h:42
bool ApproxCollinear(const SEG &aSeg, int aDistanceThreshold=1) const
Definition: seg.cpp:392
const VECTOR2I & GetArcMid() const
Definition: shape_arc.h:114
const VECTOR2I & GetP1() const
Definition: shape_arc.h:113
const VECTOR2I & GetP0() const
Definition: shape_arc.h:112
Represent a set of closed polygons.
wxString MessageTextFromMinOptMax(const MINOPTMAX< int > &aValue) const
wxString MessageTextFromValue(double aValue, bool aAddUnitLabel=true, EDA_DATA_TYPE aType=EDA_DATA_TYPE::DISTANCE) const
A lower-precision version of StringFromValue().
T EuclideanNorm() const
Compute the Euclidean norm of the vector, which is defined as sqrt(x ** 2 + y ** 2).
Definition: vector2d.h:265
extended_type Cross(const VECTOR2< T > &aVector) const
Compute cross product of self with aVector.
Definition: vector2d.h:457
void TransformCircleToPolygon(SHAPE_LINE_CHAIN &aBuffer, const VECTOR2I &aCenter, int aRadius, int aError, ERROR_LOC aErrorLoc, int aMinSegCount=0)
Convert a circle to a polygon, using multiple straight lines.
void TransformArcToPolygon(SHAPE_POLY_SET &aBuffer, const VECTOR2I &aStart, const VECTOR2I &aMid, const VECTOR2I &aEnd, int aWidth, int aError, ERROR_LOC aErrorLoc)
Convert arc to multiple straight segments.
void TransformOvalToPolygon(SHAPE_POLY_SET &aBuffer, const VECTOR2I &aStart, const VECTOR2I &aEnd, int aWidth, int aError, ERROR_LOC aErrorLoc, int aMinSegCount=0)
Convert a oblong shape to a polygon, using multiple segments.
#define _HKI(x)
@ ANNULAR_WIDTH_CONSTRAINT
Definition: drc_rule.h:57
@ VIA_DIAMETER_CONSTRAINT
Definition: drc_rule.h:63
@ TRACK_WIDTH_CONSTRAINT
Definition: drc_rule.h:56
@ HOLE_SIZE_CONSTRAINT
Definition: drc_rule.h:51
#define _(s)
static constexpr EDA_ANGLE & ANGLE_360
Definition: eda_angle.h:443
static constexpr EDA_ANGLE & ANGLE_0
Definition: eda_angle.h:437
#define PCB_EDIT_FRAME_NAME
INSPECT_RESULT
Definition: eda_item.h:42
const INSPECTOR_FUNC & INSPECTOR
Definition: eda_item.h:78
#define ENDPOINT
ends. (Used to support dragging.)
std::uint32_t EDA_ITEM_FLAGS
#define STARTPOINT
When a line is selected, these flags indicate which.
static std::vector< KICAD_T > connectedTypes
ERROR_LOC
When approximating an arc or circle, should the error be placed on the outside or inside of the curve...
bool ClipLine(const BOX2I *aClipBox, int &x1, int &y1, int &x2, int &y2)
Test if any part of a line falls within the bounds of a rectangle.
@ LAYER_VIA_NETNAMES
Definition: layer_ids.h:169
FLASHING
Enum used during connectivity building to ensure we do not query connectivity while building the data...
Definition: layer_ids.h:148
int GetNetnameLayer(int aLayer)
Returns a netname layer corresponding to the given layer.
Definition: layer_ids.h:994
bool IsCopperLayer(int aLayerId)
Tests whether a layer is a copper layer.
Definition: layer_ids.h:853
@ LAYER_LOCKED_ITEM_SHADOW
shadow layer for locked items
Definition: layer_ids.h:240
@ LAYER_VIA_HOLEWALLS
Definition: layer_ids.h:235
@ LAYER_GP_OVERLAY
general purpose overlay
Definition: layer_ids.h:219
@ LAYER_TRACKS
Definition: layer_ids.h:213
@ LAYER_VIA_HOLES
to draw via holes (pad holes do not use this layer)
Definition: layer_ids.h:216
@ LAYER_VIA_MICROVIA
to draw micro vias
Definition: layer_ids.h:195
@ LAYER_VIA_THROUGH
to draw usual through hole vias
Definition: layer_ids.h:197
@ LAYER_VIAS
Meta control for all vias opacity/visibility.
Definition: layer_ids.h:194
@ LAYER_VIA_BBLIND
to draw blind/buried vias
Definition: layer_ids.h:196
bool IsNetnameLayer(int aLayer)
Test whether a layer is a netname layer.
Definition: layer_ids.h:1017
bool IsHoleLayer(int aLayer)
Definition: layer_ids.h:892
PCB_LAYER_ID
A quick note on layer IDs:
Definition: layer_ids.h:60
@ PCBNEW_LAYER_ID_START
Definition: layer_ids.h:64
@ B_Mask
Definition: layer_ids.h:107
@ B_Cu
Definition: layer_ids.h:96
@ F_Mask
Definition: layer_ids.h:108
@ UNDEFINED_LAYER
Definition: layer_ids.h:61
@ F_Cu
Definition: layer_ids.h:65
PCB_LAYER_ID ToLAYER_ID(int aLayer)
Definition: lset.cpp:941
PCB_LAYER_ID FlipLayer(PCB_LAYER_ID aLayerId, int aCopperLayersCount)
Definition: lset.cpp:553
void MIRROR(T &aPoint, const T &aMirrorRef)
Updates aPoint with the mirror of aPoint relative to the aMirrorRef.
Definition: mirror.h:40
EDA_ANGLE abs(const EDA_ANGLE &aAngle)
Definition: eda_angle.h:426
static struct TRACK_VIA_DESC _TRACK_VIA_DESC
VIATYPE
Definition: pcb_track.h:64
#define TYPE_HASH(x)
Definition: property.h:64
#define ENUM_TO_WXANY(type)
Macro to define read-only fields (no setter method available)
Definition: property.h:742
#define REGISTER_TYPE(x)
Definition: property_mgr.h:366
wxString UnescapeString(const wxString &aSource)
constexpr int mmToIU(double mm) const
Definition: base_units.h:89
bool operator()(const PCB_TRACK *aFirst, const PCB_TRACK *aSecond) const
Definition: pcb_track.cpp:1382
bool TestSegmentHit(const VECTOR2I &aRefPoint, const VECTOR2I &aStart, const VECTOR2I &aEnd, int aDist)
Test if aRefPoint is with aDistance on the line defined by aStart and aEnd.
Definition: trigo.cpp:174
void RotatePoint(int *pX, int *pY, const EDA_ANGLE &aAngle)
Calculate the new point of coord coord pX, pY, for a rotation center 0, 0.
Definition: trigo.cpp:228
const VECTOR2I CalcArcCenter(const VECTOR2I &aStart, const VECTOR2I &aMid, const VECTOR2I &aEnd)
Determine the center of an arc or circle given three points on its circumference.
Definition: trigo.cpp:520
double GetLineLength(const VECTOR2I &aPointA, const VECTOR2I &aPointB)
Return the length of a line segment defined by aPointA and aPointB.
Definition: trigo.h:194
double EuclideanNorm(const VECTOR2I &vector)
Definition: trigo.h:128
KICAD_T
The set of class identification values stored in EDA_ITEM::m_structType.
Definition: typeinfo.h:78
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
Definition: typeinfo.h:95
@ PCB_PAD_T
class PAD, a pad in a footprint
Definition: typeinfo.h:87
@ PCB_ARC_T
class PCB_ARC, an arc track segment on a copper layer
Definition: typeinfo.h:96
@ PCB_TRACE_T
class PCB_TRACK, a track segment (segment on a copper layer)
Definition: typeinfo.h:94
constexpr ret_type KiROUND(fp_type v)
Round a floating point number to an integer using "round halfway cases away from zero".
Definition: util.h:85
VECTOR2< int > VECTOR2I
Definition: vector2d.h:588