KiCad PCB EDA Suite
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pcb_track.cpp
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1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright (C) 2012 Jean-Pierre Charras, jp.charras at wanadoo.fr
5 * Copyright (C) 2012 SoftPLC Corporation, Dick Hollenbeck <[email protected]>
6 * Copyright (C) 2012 Wayne Stambaugh <[email protected]>
7 * Copyright (C) 1992-2024 KiCad Developers, see AUTHORS.txt for contributors.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, you may find one here:
21 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
22 * or you may search the http://www.gnu.org website for the version 2 license,
23 * or you may write to the Free Software Foundation, Inc.,
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
25 */
26#include <pcb_base_frame.h>
27#include <core/mirror.h>
29#include <board.h>
32#include <pcb_track.h>
33#include <base_units.h>
34#include <lset.h>
35#include <string_utils.h>
36#include <view/view.h>
39#include <geometry/seg.h>
42#include <geometry/shape_arc.h>
43#include <drc/drc_engine.h>
44#include <pcb_painter.h>
45#include <trigo.h>
46
47#include <google/protobuf/any.pb.h>
48#include <api/api_enums.h>
49#include <api/api_utils.h>
50#include <api/api_pcb_utils.h>
51#include <api/board/board_types.pb.h>
52
55
57 BOARD_CONNECTED_ITEM( aParent, idtype )
58{
59 m_Width = pcbIUScale.mmToIU( 0.2 ); // Gives a reasonable default width
60}
61
62
64{
65 return new PCB_TRACK( *this );
66}
67
68
69PCB_ARC::PCB_ARC( BOARD_ITEM* aParent, const SHAPE_ARC* aArc ) :
70 PCB_TRACK( aParent, PCB_ARC_T )
71{
72 m_Start = aArc->GetP0();
73 m_End = aArc->GetP1();
74 m_Mid = aArc->GetArcMid();
75}
76
77
79{
80 return new PCB_ARC( *this );
81}
82
83
85 PCB_TRACK( aParent, PCB_VIA_T ),
86 m_padStack( this )
87{
88 SetViaType( VIATYPE::THROUGH );
90 Padstack().Drill().end = B_Cu;
92
94
95 // Until vias support custom padstack; their layer set should always be cleared
97
98 // For now, vias are always circles
99 m_padStack.SetShape( PAD_SHAPE::CIRCLE );
100
102
103 m_isFree = false;
104}
105
106
107PCB_VIA::PCB_VIA( const PCB_VIA& aOther ) :
108 PCB_TRACK( aOther.GetParent(), PCB_VIA_T ),
109 m_padStack( this )
110{
111 PCB_VIA::operator=( aOther );
112
113 const_cast<KIID&>( m_Uuid ) = aOther.m_Uuid;
115}
116
117
119{
121
122 m_Width = aOther.m_Width;
123 m_Start = aOther.m_Start;
124 m_End = aOther.m_End;
125
126 m_viaType = aOther.m_viaType;
127 m_padStack = aOther.m_padStack;
128 m_isFree = aOther.m_isFree;
129
130 return *this;
131}
132
133
135{
136 return new PCB_VIA( *this );
137}
138
139
140wxString PCB_VIA::GetItemDescription( UNITS_PROVIDER* aUnitsProvider, bool aFull ) const
141{
142 wxString formatStr;
143
144 switch( GetViaType() )
145 {
146 case VIATYPE::BLIND_BURIED: formatStr = _( "Blind/Buried Via %s on %s" ); break;
147 case VIATYPE::MICROVIA: formatStr = _( "Micro Via %s on %s" ); break;
148 default: formatStr = _( "Via %s on %s" ); break;
149 }
150
151 return wxString::Format( formatStr, GetNetnameMsg(), layerMaskDescribe() );
152}
153
154
156{
157 return BITMAPS::via;
158}
159
160
161bool PCB_TRACK::operator==( const BOARD_ITEM& aBoardItem ) const
162{
163 if( aBoardItem.Type() != Type() )
164 return false;
165
166 const PCB_TRACK& other = static_cast<const PCB_TRACK&>( aBoardItem );
167
168 return *this == other;
169}
170
171
172bool PCB_TRACK::operator==( const PCB_TRACK& aOther ) const
173{
174 return m_Start == aOther.m_Start
175 && m_End == aOther.m_End
176 && m_layer == aOther.m_layer
177 && m_Width == aOther.m_Width;
178}
179
180
181double PCB_TRACK::Similarity( const BOARD_ITEM& aOther ) const
182{
183 if( aOther.Type() != Type() )
184 return 0.0;
185
186 const PCB_TRACK& other = static_cast<const PCB_TRACK&>( aOther );
187
188 double similarity = 1.0;
189
190 if( m_layer != other.m_layer )
191 similarity *= 0.9;
192
193 if( m_Width != other.m_Width )
194 similarity *= 0.9;
195
196 if( m_Start != other.m_Start )
197 similarity *= 0.9;
198
199 if( m_End != other.m_End )
200 similarity *= 0.9;
201
202 return similarity;
203}
204
205
206bool PCB_ARC::operator==( const BOARD_ITEM& aBoardItem ) const
207{
208 if( aBoardItem.Type() != Type() )
209 return false;
210
211 const PCB_ARC& other = static_cast<const PCB_ARC&>( aBoardItem );
212
213 return *this == other;
214}
215
216
217bool PCB_ARC::operator==( const PCB_ARC& aOther ) const
218{
219 return m_Start == aOther.m_Start
220 && m_End == aOther.m_End
221 && m_Mid == aOther.m_Mid
222 && m_layer == aOther.m_layer
223 && m_Width == aOther.m_Width;
224}
225
226
227double PCB_ARC::Similarity( const BOARD_ITEM& aOther ) const
228{
229 if( aOther.Type() != Type() )
230 return 0.0;
231
232 const PCB_ARC& other = static_cast<const PCB_ARC&>( aOther );
233
234 double similarity = 1.0;
235
236 if( m_layer != other.m_layer )
237 similarity *= 0.9;
238
239 if( m_Width != other.m_Width )
240 similarity *= 0.9;
241
242 if( m_Start != other.m_Start )
243 similarity *= 0.9;
244
245 if( m_End != other.m_End )
246 similarity *= 0.9;
247
248 if( m_Mid != other.m_Mid )
249 similarity *= 0.9;
250
251 return similarity;
252}
253
254
255bool PCB_VIA::operator==( const BOARD_ITEM& aBoardItem ) const
256{
257 if( aBoardItem.Type() != Type() )
258 return false;
259
260 const PCB_VIA& other = static_cast<const PCB_VIA&>( aBoardItem );
261
262 return *this == other;
263}
264
265
266bool PCB_VIA::operator==( const PCB_VIA& aOther ) const
267{
268 return m_Start == aOther.m_Start
269 && m_End == aOther.m_End
270 && m_layer == aOther.m_layer
271 && m_padStack == aOther.m_padStack
272 && m_Width == aOther.m_Width
273 && m_viaType == aOther.m_viaType
275}
276
277
278double PCB_VIA::Similarity( const BOARD_ITEM& aOther ) const
279{
280 if( aOther.Type() != Type() )
281 return 0.0;
282
283 const PCB_VIA& other = static_cast<const PCB_VIA&>( aOther );
284
285 double similarity = 1.0;
286
287 if( m_layer != other.m_layer )
288 similarity *= 0.9;
289
290 if( m_Width != other.m_Width )
291 similarity *= 0.9;
292
293 if( m_Start != other.m_Start )
294 similarity *= 0.9;
295
296 if( m_End != other.m_End )
297 similarity *= 0.9;
298
299 if( m_padStack != other.m_padStack )
300 similarity *= 0.9;
301
302 if( m_viaType != other.m_viaType )
303 similarity *= 0.9;
304
306 similarity *= 0.9;
307
308 return similarity;
309}
310
311
312void PCB_TRACK::Serialize( google::protobuf::Any &aContainer ) const
313{
314 kiapi::board::types::Track track;
315
316 track.mutable_id()->set_value( m_Uuid.AsStdString() );
317 track.mutable_start()->set_x_nm( GetStart().x );
318 track.mutable_start()->set_y_nm( GetStart().y );
319 track.mutable_end()->set_x_nm( GetEnd().x );
320 track.mutable_end()->set_y_nm( GetEnd().y );
321 track.mutable_width()->set_value_nm( GetWidth() );
322 track.set_layer( ToProtoEnum<PCB_LAYER_ID, kiapi::board::types::BoardLayer>( GetLayer() ) );
323 track.set_locked( IsLocked() ? kiapi::common::types::LockedState::LS_LOCKED
324 : kiapi::common::types::LockedState::LS_UNLOCKED );
325 track.mutable_net()->mutable_code()->set_value( GetNetCode() );
326 track.mutable_net()->set_name( GetNetname() );
327
328 aContainer.PackFrom( track );
329}
330
331
332bool PCB_TRACK::Deserialize( const google::protobuf::Any &aContainer )
333{
334 kiapi::board::types::Track track;
335
336 if( !aContainer.UnpackTo( &track ) )
337 return false;
338
339 const_cast<KIID&>( m_Uuid ) = KIID( track.id().value() );
340 SetStart( VECTOR2I( track.start().x_nm(), track.start().y_nm() ) );
341 SetEnd( VECTOR2I( track.end().x_nm(), track.end().y_nm() ) );
342 SetWidth( track.width().value_nm() );
343 SetLayer( FromProtoEnum<PCB_LAYER_ID, kiapi::board::types::BoardLayer>( track.layer() ) );
344 SetNetCode( track.net().code().value() );
345 SetLocked( track.locked() == kiapi::common::types::LockedState::LS_LOCKED );
346
347 return true;
348}
349
350
351void PCB_ARC::Serialize( google::protobuf::Any &aContainer ) const
352{
353 kiapi::board::types::Arc arc;
354
355 arc.mutable_id()->set_value( m_Uuid.AsStdString() );
356 arc.mutable_start()->set_x_nm( GetStart().x );
357 arc.mutable_start()->set_y_nm( GetStart().y );
358 arc.mutable_mid()->set_x_nm( GetMid().x );
359 arc.mutable_mid()->set_y_nm( GetMid().y );
360 arc.mutable_end()->set_x_nm( GetEnd().x );
361 arc.mutable_end()->set_y_nm( GetEnd().y );
362 arc.mutable_width()->set_value_nm( GetWidth() );
363 arc.set_layer( ToProtoEnum<PCB_LAYER_ID, kiapi::board::types::BoardLayer>( GetLayer() ) );
364 arc.set_locked( IsLocked() ? kiapi::common::types::LockedState::LS_LOCKED
365 : kiapi::common::types::LockedState::LS_UNLOCKED );
366 arc.mutable_net()->mutable_code()->set_value( GetNetCode() );
367 arc.mutable_net()->set_name( GetNetname() );
368
369 aContainer.PackFrom( arc );
370}
371
372
373bool PCB_ARC::Deserialize( const google::protobuf::Any &aContainer )
374{
375 kiapi::board::types::Arc arc;
376
377 if( !aContainer.UnpackTo( &arc ) )
378 return false;
379
380 const_cast<KIID&>( m_Uuid ) = KIID( arc.id().value() );
381 SetStart( VECTOR2I( arc.start().x_nm(), arc.start().y_nm() ) );
382 SetMid( VECTOR2I( arc.mid().x_nm(), arc.mid().y_nm() ) );
383 SetEnd( VECTOR2I( arc.end().x_nm(), arc.end().y_nm() ) );
384 SetWidth( arc.width().value_nm() );
385 SetLayer( FromProtoEnum<PCB_LAYER_ID, kiapi::board::types::BoardLayer>( arc.layer() ) );
386 SetNetCode( arc.net().code().value() );
387 SetLocked( arc.locked() == kiapi::common::types::LockedState::LS_LOCKED );
388
389 return true;
390}
391
392
393void PCB_VIA::Serialize( google::protobuf::Any &aContainer ) const
394{
395 kiapi::board::types::Via via;
396
397 via.mutable_id()->set_value( m_Uuid.AsStdString() );
398 via.mutable_position()->set_x_nm( GetPosition().x );
399 via.mutable_position()->set_y_nm( GetPosition().y );
400
401 PADSTACK padstack = Padstack();
402
403 // Via width is currently stored in PCB_TRACK::m_Width rather than in the
404 // padstack object; so hack it in here unless/until that changes
405 padstack.Size() = { m_Width, m_Width };
406
407 google::protobuf::Any padStackWrapper;
408 padstack.Serialize( padStackWrapper );
409 padStackWrapper.UnpackTo( via.mutable_pad_stack() );
410
411
412
413 via.set_type( ToProtoEnum<VIATYPE, kiapi::board::types::ViaType>( GetViaType() ) );
414 via.set_locked( IsLocked() ? kiapi::common::types::LockedState::LS_LOCKED
415 : kiapi::common::types::LockedState::LS_UNLOCKED );
416 via.mutable_net()->mutable_code()->set_value( GetNetCode() );
417 via.mutable_net()->set_name( GetNetname() );
418
419 aContainer.PackFrom( via );
420}
421
422
423bool PCB_VIA::Deserialize( const google::protobuf::Any &aContainer )
424{
425 kiapi::board::types::Via via;
426
427 if( !aContainer.UnpackTo( &via ) )
428 return false;
429
430 const_cast<KIID&>( m_Uuid ) = KIID( via.id().value() );
431 SetStart( VECTOR2I( via.position().x_nm(), via.position().y_nm() ) );
432 SetEnd( GetStart() );
433 SetDrill( via.pad_stack().drill_diameter().x_nm() );
434
435 google::protobuf::Any padStackWrapper;
436 padStackWrapper.PackFrom( via.pad_stack() );
437
438 if( !m_padStack.Deserialize( padStackWrapper ) )
439 return false;
440
441 // We don't yet support complex padstacks for vias
443 SetViaType( FromProtoEnum<VIATYPE>( via.type() ) );
444 SetNetCode( via.net().code().value() );
445 SetLocked( via.locked() == kiapi::common::types::LockedState::LS_LOCKED );
446
447 return true;
448}
449
450
452{
453 SEG a( m_Start, m_End );
454 SEG b( aTrack.GetStart(), aTrack.GetEnd() );
455 return a.ApproxCollinear( b );
456}
457
458
460{
461 DRC_CONSTRAINT constraint;
462
463 if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine )
464 {
466
467 constraint = bds.m_DRCEngine->EvalRules( TRACK_WIDTH_CONSTRAINT, this, nullptr, m_layer );
468 }
469
470 if( aSource )
471 *aSource = constraint.GetName();
472
473 return constraint.Value();
474}
475
476
478{
479 DRC_CONSTRAINT constraint;
480
481 if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine )
482 {
484
485 constraint = bds.m_DRCEngine->EvalRules( VIA_DIAMETER_CONSTRAINT, this, nullptr, m_layer );
486 }
487
488 if( aSource )
489 *aSource = constraint.GetName();
490
491 return constraint.Value();
492}
493
494
496{
497 DRC_CONSTRAINT constraint;
498
499 if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine )
500 {
502
503 constraint = bds.m_DRCEngine->EvalRules( HOLE_SIZE_CONSTRAINT, this, nullptr, m_layer );
504 }
505
506 if( aSource )
507 *aSource = constraint.GetName();
508
509 return constraint.Value();
510}
511
512
513int PCB_VIA::GetMinAnnulus( PCB_LAYER_ID aLayer, wxString* aSource ) const
514{
515 if( !FlashLayer( aLayer ) )
516 {
517 if( aSource )
518 *aSource = _( "removed annular ring" );
519
520 return 0;
521 }
522
523 DRC_CONSTRAINT constraint;
524
525 if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine )
526 {
528
529 constraint = bds.m_DRCEngine->EvalRules( ANNULAR_WIDTH_CONSTRAINT, this, nullptr, aLayer );
530 }
531
532 if( constraint.Value().HasMin() )
533 {
534 if( aSource )
535 *aSource = constraint.GetName();
536
537 return constraint.Value().Min();
538 }
539
540 return 0;
541}
542
543
545{
546 if( m_padStack.Drill().size.x > 0 ) // Use the specific value.
547 return m_padStack.Drill().size.x;
548
549 // Use the default value from the Netclass
550 NETCLASS* netclass = GetEffectiveNetClass();
551
552 if( GetViaType() == VIATYPE::MICROVIA )
553 return netclass->GetuViaDrill();
554
555 return netclass->GetViaDrill();
556}
557
558
559EDA_ITEM_FLAGS PCB_TRACK::IsPointOnEnds( const VECTOR2I& point, int min_dist ) const
560{
561 EDA_ITEM_FLAGS result = 0;
562
563 if( min_dist < 0 )
564 min_dist = m_Width / 2;
565
566 if( min_dist == 0 )
567 {
568 if( m_Start == point )
569 result |= STARTPOINT;
570
571 if( m_End == point )
572 result |= ENDPOINT;
573 }
574 else
575 {
576 double dist = m_Start.Distance( point );
577
578 if( min_dist >= dist )
579 result |= STARTPOINT;
580
581 dist = m_End.Distance( point );
582
583 if( min_dist >= dist )
584 result |= ENDPOINT;
585 }
586
587 return result;
588}
589
590
592{
593 // end of track is round, this is its radius, rounded up
594 int radius = ( m_Width + 1 ) / 2;
595 int ymax, xmax, ymin, xmin;
596
597 if( Type() == PCB_VIA_T )
598 {
599 ymax = m_Start.y;
600 xmax = m_Start.x;
601
602 ymin = m_Start.y;
603 xmin = m_Start.x;
604 }
605 else if( Type() == PCB_ARC_T )
606 {
607 std::shared_ptr<SHAPE> arc = GetEffectiveShape();
608 BOX2I bbox = arc->BBox();
609
610 xmin = bbox.GetLeft();
611 xmax = bbox.GetRight();
612 ymin = bbox.GetTop();
613 ymax = bbox.GetBottom();
614 }
615 else
616 {
617 ymax = std::max( m_Start.y, m_End.y );
618 xmax = std::max( m_Start.x, m_End.x );
619
620 ymin = std::min( m_Start.y, m_End.y );
621 xmin = std::min( m_Start.x, m_End.x );
622 }
623
624 ymax += radius;
625 xmax += radius;
626
627 ymin -= radius;
628 xmin -= radius;
629
630 // return a rectangle which is [pos,dim) in nature. therefore the +1
631 return BOX2ISafe( VECTOR2I( xmin, ymin ),
632 VECTOR2L( (int64_t) xmax - xmin + 1, (int64_t) ymax - ymin + 1 ) );
633}
634
635
637{
638 return m_Start.Distance( m_End );
639}
640
641
642void PCB_TRACK::Rotate( const VECTOR2I& aRotCentre, const EDA_ANGLE& aAngle )
643{
644 RotatePoint( m_Start, aRotCentre, aAngle );
645 RotatePoint( m_End, aRotCentre, aAngle );
646}
647
648
649void PCB_ARC::Rotate( const VECTOR2I& aRotCentre, const EDA_ANGLE& aAngle )
650{
651 RotatePoint( m_Start, aRotCentre, aAngle );
652 RotatePoint( m_End, aRotCentre, aAngle );
653 RotatePoint( m_Mid, aRotCentre, aAngle );
654}
655
656
657void PCB_TRACK::Mirror( const VECTOR2I& aCentre, bool aMirrorAroundXAxis )
658{
659 if( aMirrorAroundXAxis )
660 {
661 MIRROR( m_Start.y, aCentre.y );
662 MIRROR( m_End.y, aCentre.y );
663 }
664 else
665 {
666 MIRROR( m_Start.x, aCentre.x );
667 MIRROR( m_End.x, aCentre.x );
668 }
669}
670
671
672void PCB_ARC::Mirror( const VECTOR2I& aCentre, bool aMirrorAroundXAxis )
673{
674 if( aMirrorAroundXAxis )
675 {
676 MIRROR( m_Start.y, aCentre.y );
677 MIRROR( m_End.y, aCentre.y );
678 MIRROR( m_Mid.y, aCentre.y );
679 }
680 else
681 {
682 MIRROR( m_Start.x, aCentre.x );
683 MIRROR( m_End.x, aCentre.x );
684 MIRROR( m_Mid.x, aCentre.x );
685 }
686}
687
688
689void PCB_TRACK::Flip( const VECTOR2I& aCentre, bool aFlipLeftRight )
690{
691 if( aFlipLeftRight )
692 {
693 m_Start.x = aCentre.x - ( m_Start.x - aCentre.x );
694 m_End.x = aCentre.x - ( m_End.x - aCentre.x );
695 }
696 else
697 {
698 m_Start.y = aCentre.y - ( m_Start.y - aCentre.y );
699 m_End.y = aCentre.y - ( m_End.y - aCentre.y );
700 }
701
703}
704
705
706void PCB_ARC::Flip( const VECTOR2I& aCentre, bool aFlipLeftRight )
707{
708 if( aFlipLeftRight )
709 {
710 m_Start.x = aCentre.x - ( m_Start.x - aCentre.x );
711 m_End.x = aCentre.x - ( m_End.x - aCentre.x );
712 m_Mid.x = aCentre.x - ( m_Mid.x - aCentre.x );
713 }
714 else
715 {
716 m_Start.y = aCentre.y - ( m_Start.y - aCentre.y );
717 m_End.y = aCentre.y - ( m_End.y - aCentre.y );
718 m_Mid.y = aCentre.y - ( m_Mid.y - aCentre.y );
719 }
720
722}
723
724
725bool PCB_ARC::IsCCW() const
726{
727 VECTOR2L start = m_Start;
728 VECTOR2L start_end = m_End - start;
729 VECTOR2L start_mid = m_Mid - start;
730
731 return start_end.Cross( start_mid ) < 0;
732}
733
734
735void PCB_VIA::Flip( const VECTOR2I& aCentre, bool aFlipLeftRight )
736{
737 if( aFlipLeftRight )
738 {
739 m_Start.x = aCentre.x - ( m_Start.x - aCentre.x );
740 m_End.x = aCentre.x - ( m_End.x - aCentre.x );
741 }
742 else
743 {
744 m_Start.y = aCentre.y - ( m_Start.y - aCentre.y );
745 m_End.y = aCentre.y - ( m_End.y - aCentre.y );
746 }
747
748 if( GetViaType() != VIATYPE::THROUGH )
749 {
750 PCB_LAYER_ID top_layer;
751 PCB_LAYER_ID bottom_layer;
752 LayerPair( &top_layer, &bottom_layer );
753 top_layer = GetBoard()->FlipLayer( top_layer );
754 bottom_layer = GetBoard()->FlipLayer( bottom_layer );
755 SetLayerPair( top_layer, bottom_layer );
756 }
757}
758
759
760INSPECT_RESULT PCB_TRACK::Visit( INSPECTOR inspector, void* testData,
761 const std::vector<KICAD_T>& aScanTypes )
762{
763 for( KICAD_T scanType : aScanTypes )
764 {
765 if( scanType == Type() )
766 {
767 if( INSPECT_RESULT::QUIT == inspector( this, testData ) )
768 return INSPECT_RESULT::QUIT;
769 }
770 }
771
772 return INSPECT_RESULT::CONTINUE;
773}
774
775
776std::shared_ptr<SHAPE_SEGMENT> PCB_VIA::GetEffectiveHoleShape() const
777{
778 return std::make_shared<SHAPE_SEGMENT>( SEG( m_Start, m_Start ), Padstack().Drill().size.x );
779}
780
781
783{
784 switch( aMode )
785 {
786 case TENTING_MODE::FROM_RULES: m_padStack.FrontOuterLayers().has_solder_mask.reset(); break;
787 case TENTING_MODE::TENTED: m_padStack.FrontOuterLayers().has_solder_mask = true; break;
788 case TENTING_MODE::NOT_TENTED: m_padStack.FrontOuterLayers().has_solder_mask = false; break;
789 }
790}
791
792
794{
796 {
798 TENTING_MODE::TENTED : TENTING_MODE::NOT_TENTED;
799 }
800
801 return TENTING_MODE::FROM_RULES;
802}
803
804
806{
807 switch( aMode )
808 {
809 case TENTING_MODE::FROM_RULES: m_padStack.BackOuterLayers().has_solder_mask.reset(); break;
810 case TENTING_MODE::TENTED: m_padStack.BackOuterLayers().has_solder_mask = true; break;
811 case TENTING_MODE::NOT_TENTED: m_padStack.BackOuterLayers().has_solder_mask = false; break;
812 }
813}
814
815
817{
818 if( m_padStack.BackOuterLayers().has_solder_mask.has_value() )
819 {
821 TENTING_MODE::TENTED : TENTING_MODE::NOT_TENTED;
822 }
823
824 return TENTING_MODE::FROM_RULES;
825}
826
827
828bool PCB_VIA::IsTented( PCB_LAYER_ID aLayer ) const
829{
830 wxCHECK_MSG( IsFrontLayer( aLayer ) || IsBackLayer( aLayer ), true,
831 "Invalid layer passed to IsTented" );
832
833 bool front = IsFrontLayer( aLayer );
834
835 if( front && m_padStack.FrontOuterLayers().has_solder_mask.has_value() )
837
838 if( !front && m_padStack.BackOuterLayers().has_solder_mask.has_value() )
840
841 if( const BOARD* board = GetBoard() )
842 {
843 return front ? board->GetDesignSettings().m_TentViasFront
844 : board->GetDesignSettings().m_TentViasBack;
845 }
846
847 return true;
848}
849
850
852{
853 if( const BOARD* board = GetBoard() )
854 return board->GetDesignSettings().m_SolderMaskExpansion;
855 else
856 return 0;
857}
858
859
861{
862#if 0
863 // Nice and simple, but raises its ugly head in performance profiles....
864 return GetLayerSet().test( aLayer );
865#endif
866
867 if( aLayer >= Padstack().Drill().start && aLayer <= Padstack().Drill().end )
868 return true;
869
870 if( aLayer == F_Mask )
871 return !IsTented( F_Mask );
872 else if( aLayer == B_Mask )
873 return !IsTented( B_Mask );
874
875 return false;
876}
877
878
880{
881 return Padstack().Drill().start;
882}
883
884
886{
887 Padstack().Drill().start = aLayer;
888}
889
890
892{
893 LSET layermask;
894
895 if( Padstack().Drill().start < PCBNEW_LAYER_ID_START )
896 return layermask;
897
898 if( GetViaType() == VIATYPE::THROUGH )
899 layermask = LSET::AllCuMask();
900 else
901 wxASSERT( Padstack().Drill().start <= Padstack().Drill().end );
902
903 // PCB_LAYER_IDs are numbered from front to back, this is top to bottom.
904 for( int id = Padstack().Drill().start; id <= Padstack().Drill().end; ++id )
905 layermask.set( id );
906
907 if( !IsTented( F_Mask ) && layermask.test( F_Cu ) )
908 layermask.set( F_Mask );
909
910 if( !IsTented( B_Mask ) && layermask.test( B_Cu ) )
911 layermask.set( B_Mask );
912
913 return layermask;
914}
915
916
917void PCB_VIA::SetLayerSet( LSET aLayerSet )
918{
919 bool first = true;
920
921 aLayerSet.RunOnLayers(
922 [&]( PCB_LAYER_ID layer )
923 {
924 // m_layer and m_bottomLayer are copper layers, so consider only copper layers
925 if( IsCopperLayer( layer ) )
926 {
927 if( first )
928 {
929 Padstack().Drill().start = layer;
930 first = false;
931 }
932
933 Padstack().Drill().end = layer;
934 }
935 } );
936}
937
938
939void PCB_VIA::SetLayerPair( PCB_LAYER_ID aTopLayer, PCB_LAYER_ID aBottomLayer )
940{
941
942 Padstack().Drill().start = aTopLayer;
943 Padstack().Drill().end = aBottomLayer;
945}
946
947
949{
950 Padstack().Drill().start = aLayer;
951}
952
953
955{
956 Padstack().Drill().end = aLayer;
957}
958
959
960void PCB_VIA::LayerPair( PCB_LAYER_ID* top_layer, PCB_LAYER_ID* bottom_layer ) const
961{
962 PCB_LAYER_ID t_layer = F_Cu;
963 PCB_LAYER_ID b_layer = B_Cu;
964
965 if( GetViaType() != VIATYPE::THROUGH )
966 {
967 b_layer = Padstack().Drill().end;
968 t_layer = Padstack().Drill().start;
969
970 if( b_layer < t_layer )
971 std::swap( b_layer, t_layer );
972 }
973
974 if( top_layer )
975 *top_layer = t_layer;
976
977 if( bottom_layer )
978 *bottom_layer = b_layer;
979}
980
981
983{
984 return Padstack().Drill().start;
985}
986
987
989{
990 return Padstack().Drill().end;
991}
992
993
995{
996 if( GetViaType() == VIATYPE::THROUGH )
997 {
998 Padstack().Drill().start = F_Cu;
999 Padstack().Drill().end = B_Cu;
1000 }
1001
1002 if( Padstack().Drill().end < Padstack().Drill().start )
1003 std::swap( Padstack().Drill().end, Padstack().Drill().start );
1004}
1005
1006
1007bool PCB_VIA::FlashLayer( LSET aLayers ) const
1008{
1009 for( size_t ii = 0; ii < aLayers.size(); ++ii )
1010 {
1011 if( aLayers.test( ii ) )
1012 {
1013 PCB_LAYER_ID layer = PCB_LAYER_ID( ii );
1014
1015 if( FlashLayer( layer ) )
1016 return true;
1017 }
1018 }
1019
1020 return false;
1021}
1022
1023
1024bool PCB_VIA::FlashLayer( int aLayer ) const
1025{
1026 // Return the "normal" shape if the caller doesn't specify a particular layer
1027 if( aLayer == UNDEFINED_LAYER )
1028 return true;
1029
1030 const BOARD* board = GetBoard();
1031
1032 if( !board )
1033 return true;
1034
1035 if( !IsOnLayer( static_cast<PCB_LAYER_ID>( aLayer ) ) )
1036 return false;
1037
1038 if( !IsCopperLayer( aLayer ) )
1039 return true;
1040
1041 switch( Padstack().UnconnectedLayerMode() )
1042 {
1044 return true;
1045
1047 {
1048 if( aLayer == Padstack().Drill().start || aLayer == Padstack().Drill().end )
1049 return true;
1050
1051 // Check for removal below
1052 break;
1053 }
1054
1056 // Check for removal below
1057 break;
1058 }
1059
1060 // Must be static to keep from raising its ugly head in performance profiles
1061 static std::initializer_list<KICAD_T> connectedTypes = { PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T,
1062 PCB_PAD_T };
1063
1064 if( m_zoneLayerOverrides[ aLayer ] == ZLO_FORCE_FLASHED )
1065 return true;
1066 else
1067 return board->GetConnectivity()->IsConnectedOnLayer( this, aLayer, connectedTypes );
1068}
1069
1070
1072 PCB_LAYER_ID* aBottommost ) const
1073{
1074 *aTopmost = UNDEFINED_LAYER;
1075 *aBottommost = UNDEFINED_LAYER;
1076
1077 static std::initializer_list<KICAD_T> connectedTypes = { PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T,
1078 PCB_PAD_T };
1079
1080 for( int layer = TopLayer(); layer <= BottomLayer(); ++layer )
1081 {
1082 bool connected = false;
1083
1084 if( m_zoneLayerOverrides[ layer ] == ZLO_FORCE_FLASHED )
1085 connected = true;
1086 else if( GetBoard()->GetConnectivity()->IsConnectedOnLayer( this, layer, connectedTypes ) )
1087 connected = true;
1088
1089 if( connected )
1090 {
1091 if( *aTopmost == UNDEFINED_LAYER )
1092 *aTopmost = ToLAYER_ID( layer );
1093
1094 *aBottommost = ToLAYER_ID( layer );
1095 }
1096 }
1097
1098}
1099
1100
1101void PCB_TRACK::ViewGetLayers( int aLayers[], int& aCount ) const
1102{
1103 // Show the track and its netname on different layers
1104 aLayers[0] = GetLayer();
1105 aLayers[1] = GetNetnameLayer( aLayers[0] );
1106 aCount = 2;
1107
1108 if( IsLocked() )
1109 aLayers[ aCount++ ] = LAYER_LOCKED_ITEM_SHADOW;
1110}
1111
1112
1113double PCB_TRACK::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
1114{
1115 constexpr double HIDE = std::numeric_limits<double>::max();
1116
1117 PCB_PAINTER* painter = static_cast<PCB_PAINTER*>( aView->GetPainter() );
1118 PCB_RENDER_SETTINGS* renderSettings = painter->GetSettings();
1119
1120 if( !aView->IsLayerVisible( LAYER_TRACKS ) )
1121 return HIDE;
1122
1123 if( IsNetnameLayer( aLayer ) )
1124 {
1126 return HIDE;
1127
1128 // Hide netnames on dimmed tracks
1129 if( renderSettings->GetHighContrast() )
1130 {
1131 if( m_layer != renderSettings->GetPrimaryHighContrastLayer() )
1132 return HIDE;
1133 }
1134
1135 VECTOR2I start( GetStart() );
1136 VECTOR2I end( GetEnd() );
1137
1138 // Calc the approximate size of the netname (assume square chars)
1139 SEG::ecoord nameSize = GetDisplayNetname().size() * GetWidth();
1140
1141 if( VECTOR2I( end - start ).SquaredEuclideanNorm() < nameSize * nameSize )
1142 return HIDE;
1143
1144 BOX2I clipBox = BOX2ISafe( aView->GetViewport() );
1145
1146 ClipLine( &clipBox, start.x, start.y, end.x, end.y );
1147
1148 if( VECTOR2I( end - start ).SquaredEuclideanNorm() == 0 )
1149 return HIDE;
1150
1151 // Netnames will be shown only if zoom is appropriate
1152 return ( double ) pcbIUScale.mmToIU( 4 ) / ( m_Width + 1 );
1153 }
1154
1155 if( aLayer == LAYER_LOCKED_ITEM_SHADOW )
1156 {
1157 // Hide shadow if the main layer is not shown
1158 if( !aView->IsLayerVisible( m_layer ) )
1159 return HIDE;
1160
1161 // Hide shadow on dimmed tracks
1162 if( renderSettings->GetHighContrast() )
1163 {
1164 if( m_layer != renderSettings->GetPrimaryHighContrastLayer() )
1165 return HIDE;
1166 }
1167 }
1168
1169 // Other layers are shown without any conditions
1170 return 0.0;
1171}
1172
1173
1175{
1176 BOX2I bbox = GetBoundingBox();
1177
1178 if( const BOARD* board = GetBoard() )
1179 bbox.Inflate( 2 * board->GetDesignSettings().GetBiggestClearanceValue() );
1180 else
1181 bbox.Inflate( GetWidth() ); // Add a bit extra for safety
1182
1183 return bbox;
1184}
1185
1186
1187void PCB_VIA::ViewGetLayers( int aLayers[], int& aCount ) const
1188{
1189 aLayers[0] = LAYER_VIA_HOLES;
1190 aLayers[1] = LAYER_VIA_HOLEWALLS;
1191 aLayers[2] = LAYER_VIA_NETNAMES;
1192
1193 // Just show it on common via & via holes layers
1194 switch( GetViaType() )
1195 {
1196 case VIATYPE::THROUGH: aLayers[3] = LAYER_VIA_THROUGH; break;
1197 case VIATYPE::BLIND_BURIED: aLayers[3] = LAYER_VIA_BBLIND; break;
1198 case VIATYPE::MICROVIA: aLayers[3] = LAYER_VIA_MICROVIA; break;
1199 default: aLayers[3] = LAYER_GP_OVERLAY; break;
1200 }
1201
1202 aCount = 4;
1203
1204 if( IsLocked() )
1205 aLayers[ aCount++ ] = LAYER_LOCKED_ITEM_SHADOW;
1206
1207 // Vias can also be on a solder mask layer. They are on these layers or not,
1208 // depending on the plot and solder mask options
1209 if( IsOnLayer( F_Mask ) )
1210 aLayers[ aCount++ ] = F_Mask;
1211
1212 if( IsOnLayer( B_Mask ) )
1213 aLayers[ aCount++ ] = B_Mask;
1214}
1215
1216
1217double PCB_VIA::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
1218{
1219 constexpr double HIDE = (double)std::numeric_limits<double>::max();
1220
1221 PCB_PAINTER* painter = static_cast<PCB_PAINTER*>( aView->GetPainter() );
1222 PCB_RENDER_SETTINGS* renderSettings = painter->GetSettings();
1223 LSET visible = LSET::AllLayersMask();
1224
1225 // Meta control for hiding all vias
1226 if( !aView->IsLayerVisible( LAYER_VIAS ) )
1227 return HIDE;
1228
1229 // Handle board visibility
1230 if( const BOARD* board = GetBoard() )
1231 visible = board->GetVisibleLayers() & board->GetEnabledLayers();
1232
1233 // In high contrast mode don't show vias that don't cross the high-contrast layer
1234 if( renderSettings->GetHighContrast() )
1235 {
1236 PCB_LAYER_ID highContrastLayer = renderSettings->GetPrimaryHighContrastLayer();
1237
1238 if( LSET::FrontTechMask().Contains( highContrastLayer ) )
1239 highContrastLayer = F_Cu;
1240 else if( LSET::BackTechMask().Contains( highContrastLayer ) )
1241 highContrastLayer = B_Cu;
1242
1243 if( !IsCopperLayer( highContrastLayer ) )
1244 return HIDE;
1245
1246 if( GetViaType() != VIATYPE::THROUGH )
1247 {
1248 if( highContrastLayer < Padstack().Drill().start
1249 || highContrastLayer > Padstack().Drill().end )
1250 {
1251 return HIDE;
1252 }
1253 }
1254 }
1255
1256 if( IsHoleLayer( aLayer ) )
1257 {
1258 if( m_viaType == VIATYPE::BLIND_BURIED || m_viaType == VIATYPE::MICROVIA )
1259 {
1260 // Show a blind or micro via's hole if it crosses a visible layer
1261 if( !( visible & GetLayerSet() ).any() )
1262 return HIDE;
1263 }
1264 else
1265 {
1266 // Show a through via's hole if any physical layer is shown
1267 if( !( visible & LSET::PhysicalLayersMask() ).any() )
1268 return HIDE;
1269 }
1270
1271 // The hole won't be visible anyway at this scale
1272 return (double) pcbIUScale.mmToIU( 0.25 ) / GetDrillValue();
1273 }
1274 else if( IsNetnameLayer( aLayer ) )
1275 {
1276 if( renderSettings->GetHighContrast() )
1277 {
1278 // Hide netnames unless via is flashed to a high-contrast layer
1279 if( !FlashLayer( renderSettings->GetPrimaryHighContrastLayer() ) )
1280 return HIDE;
1281 }
1282 else
1283 {
1284 // Hide netnames unless pad is flashed to a visible layer
1285 if( !FlashLayer( visible ) )
1286 return HIDE;
1287 }
1288
1289 // Netnames will be shown only if zoom is appropriate
1290 return m_Width == 0 ? HIDE : ( (double)pcbIUScale.mmToIU( 10 ) / m_Width );
1291 }
1292
1293 if( IsCopperLayer( aLayer ) )
1294 return (double) pcbIUScale.mmToIU( 1 ) / m_Width;
1295 else
1296 return (double) pcbIUScale.mmToIU( 0.6 ) / m_Width;
1297}
1298
1299
1301{
1302 switch( Type() )
1303 {
1304 case PCB_ARC_T: return _( "Track (arc)" );
1305 case PCB_VIA_T: return _( "Via" );
1306 case PCB_TRACE_T:
1307 default: return _( "Track" );
1308 }
1309}
1310
1311
1312void PCB_TRACK::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>& aList )
1313{
1314 wxString msg;
1315 BOARD* board = GetBoard();
1316
1317 aList.emplace_back( _( "Type" ), GetFriendlyName() );
1318
1319 GetMsgPanelInfoBase_Common( aFrame, aList );
1320
1321 aList.emplace_back( _( "Layer" ), layerMaskDescribe() );
1322
1323 aList.emplace_back( _( "Width" ), aFrame->MessageTextFromValue( m_Width ) );
1324
1325 if( Type() == PCB_ARC_T )
1326 {
1327 double radius = static_cast<PCB_ARC*>( this )->GetRadius();
1328 aList.emplace_back( _( "Radius" ), aFrame->MessageTextFromValue( radius ) );
1329 }
1330
1331 aList.emplace_back( _( "Segment Length" ), aFrame->MessageTextFromValue( GetLength() ) );
1332
1333 // Display full track length (in Pcbnew)
1334 if( board && GetNetCode() > 0 )
1335 {
1336 int count;
1337 double trackLen;
1338 double lenPadToDie;
1339
1340 std::tie( count, trackLen, lenPadToDie ) = board->GetTrackLength( *this );
1341
1342 aList.emplace_back( _( "Routed Length" ), aFrame->MessageTextFromValue( trackLen ) );
1343
1344 if( lenPadToDie != 0 )
1345 {
1346 msg = aFrame->MessageTextFromValue( lenPadToDie );
1347 aList.emplace_back( _( "Pad To Die Length" ), msg );
1348
1349 msg = aFrame->MessageTextFromValue( trackLen + lenPadToDie );
1350 aList.emplace_back( _( "Full Length" ), msg );
1351 }
1352 }
1353
1354 wxString source;
1355 int clearance = GetOwnClearance( GetLayer(), &source );
1356
1357 aList.emplace_back( wxString::Format( _( "Min Clearance: %s" ),
1358 aFrame->MessageTextFromValue( clearance ) ),
1359 wxString::Format( _( "(from %s)" ), source ) );
1360
1361 MINOPTMAX<int> constraintValue = GetWidthConstraint( &source );
1362 msg = aFrame->MessageTextFromMinOptMax( constraintValue );
1363
1364 if( !msg.IsEmpty() )
1365 {
1366 aList.emplace_back( wxString::Format( _( "Width Constraints: %s" ), msg ),
1367 wxString::Format( _( "(from %s)" ), source ) );
1368 }
1369}
1370
1371
1372void PCB_VIA::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>& aList )
1373{
1374 wxString msg;
1375
1376 switch( GetViaType() )
1377 {
1378 case VIATYPE::MICROVIA: msg = _( "Micro Via" ); break;
1379 case VIATYPE::BLIND_BURIED: msg = _( "Blind/Buried Via" ); break;
1380 case VIATYPE::THROUGH: msg = _( "Through Via" ); break;
1381 default: msg = _( "Via" ); break;
1382 }
1383
1384 aList.emplace_back( _( "Type" ), msg );
1385
1386 GetMsgPanelInfoBase_Common( aFrame, aList );
1387
1388 aList.emplace_back( _( "Layer" ), layerMaskDescribe() );
1389 aList.emplace_back( _( "Diameter" ), aFrame->MessageTextFromValue( m_Width ) );
1390 aList.emplace_back( _( "Hole" ), aFrame->MessageTextFromValue( GetDrillValue() ) );
1391
1392 wxString source;
1393 int clearance = GetOwnClearance( GetLayer(), &source );
1394
1395 aList.emplace_back( wxString::Format( _( "Min Clearance: %s" ),
1396 aFrame->MessageTextFromValue( clearance ) ),
1397 wxString::Format( _( "(from %s)" ), source ) );
1398
1399 int minAnnulus = GetMinAnnulus( GetLayer(), &source );
1400
1401 aList.emplace_back( wxString::Format( _( "Min Annular Width: %s" ),
1402 aFrame->MessageTextFromValue( minAnnulus ) ),
1403 wxString::Format( _( "(from %s)" ), source ) );
1404}
1405
1406
1408 std::vector<MSG_PANEL_ITEM>& aList ) const
1409{
1410 aList.emplace_back( _( "Net" ), UnescapeString( GetNetname() ) );
1411
1412 aList.emplace_back( _( "Resolved Netclass" ),
1413 UnescapeString( GetEffectiveNetClass()->GetName() ) );
1414
1415#if 0 // Enable for debugging
1416 if( GetBoard() )
1417 aList.emplace_back( _( "NetCode" ), wxString::Format( wxT( "%d" ), GetNetCode() ) );
1418
1419 aList.emplace_back( wxT( "Flags" ), wxString::Format( wxT( "0x%08X" ), m_flags ) );
1420
1421 aList.emplace_back( wxT( "Start pos" ), wxString::Format( wxT( "%d %d" ),
1422 m_Start.x,
1423 m_Start.y ) );
1424 aList.emplace_back( wxT( "End pos" ), wxString::Format( wxT( "%d %d" ),
1425 m_End.x,
1426 m_End.y ) );
1427#endif
1428
1429 if( aFrame->GetName() == PCB_EDIT_FRAME_NAME && IsLocked() )
1430 aList.emplace_back( _( "Status" ), _( "Locked" ) );
1431}
1432
1433
1435{
1436 const BOARD* board = GetBoard();
1437 PCB_LAYER_ID top_layer;
1438 PCB_LAYER_ID bottom_layer;
1439
1440 LayerPair( &top_layer, &bottom_layer );
1441
1442 return board->GetLayerName( top_layer ) + wxT( " - " ) + board->GetLayerName( bottom_layer );
1443}
1444
1445
1446bool PCB_TRACK::HitTest( const VECTOR2I& aPosition, int aAccuracy ) const
1447{
1448 return TestSegmentHit( aPosition, m_Start, m_End, aAccuracy + ( m_Width / 2 ) );
1449}
1450
1451
1452bool PCB_ARC::HitTest( const VECTOR2I& aPosition, int aAccuracy ) const
1453{
1454 double max_dist = aAccuracy + ( m_Width / 2.0 );
1455
1456 // Short-circuit common cases where the arc is connected to a track or via at an endpoint
1457 if( GetStart().Distance( aPosition ) <= max_dist || GetEnd().Distance( aPosition ) <= max_dist )
1458 {
1459 return true;
1460 }
1461
1462 VECTOR2L center = GetPosition();
1463 VECTOR2L relpos = aPosition - center;
1464 int64_t dist = relpos.EuclideanNorm();
1465 double radius = GetRadius();
1466
1467 if( std::abs( dist - radius ) > max_dist )
1468 return false;
1469
1470 EDA_ANGLE arc_angle = GetAngle();
1471 EDA_ANGLE arc_angle_start = GetArcAngleStart(); // Always 0.0 ... 360 deg
1472 EDA_ANGLE arc_hittest( relpos );
1473
1474 // Calculate relative angle between the starting point of the arc, and the test point
1475 arc_hittest -= arc_angle_start;
1476
1477 // Normalise arc_hittest between 0 ... 360 deg
1478 arc_hittest.Normalize();
1479
1480 if( arc_angle < ANGLE_0 )
1481 return arc_hittest >= ANGLE_360 + arc_angle;
1482
1483 return arc_hittest <= arc_angle;
1484}
1485
1486
1487bool PCB_VIA::HitTest( const VECTOR2I& aPosition, int aAccuracy ) const
1488{
1489 int max_dist = aAccuracy + ( m_Width / 2 );
1490
1491 // rel_pos is aPosition relative to m_Start (or the center of the via)
1492 VECTOR2I rel_pos = aPosition - m_Start;
1493 double dist = (double) rel_pos.x * rel_pos.x + (double) rel_pos.y * rel_pos.y;
1494 return dist <= (double) max_dist * max_dist;
1495}
1496
1497
1498bool PCB_TRACK::HitTest( const BOX2I& aRect, bool aContained, int aAccuracy ) const
1499{
1500 BOX2I arect = aRect;
1501 arect.Inflate( aAccuracy );
1502
1503 if( aContained )
1504 return arect.Contains( GetStart() ) && arect.Contains( GetEnd() );
1505 else
1506 return arect.Intersects( GetStart(), GetEnd() );
1507}
1508
1509
1510bool PCB_ARC::HitTest( const BOX2I& aRect, bool aContained, int aAccuracy ) const
1511{
1512 BOX2I arect = aRect;
1513 arect.Inflate( aAccuracy );
1514
1515 BOX2I box( GetStart() );
1516 box.Merge( GetMid() );
1517 box.Merge( GetEnd() );
1518
1519 box.Inflate( GetWidth() / 2 );
1520
1521 if( aContained )
1522 return arect.Contains( box );
1523 else
1524 return arect.Intersects( box );
1525}
1526
1527
1528bool PCB_VIA::HitTest( const BOX2I& aRect, bool aContained, int aAccuracy ) const
1529{
1530 BOX2I arect = aRect;
1531 arect.Inflate( aAccuracy );
1532
1533 BOX2I box( GetStart() );
1534 box.Inflate( GetWidth() / 2 );
1535
1536 if( aContained )
1537 return arect.Contains( box );
1538 else
1539 return arect.IntersectsCircle( GetStart(), GetWidth() / 2 );
1540}
1541
1542
1543wxString PCB_TRACK::GetItemDescription( UNITS_PROVIDER* aUnitsProvider, bool aFull ) const
1544{
1545 return wxString::Format( Type() == PCB_ARC_T ? _("Track (arc) %s on %s, length %s" )
1546 : _("Track %s on %s, length %s" ),
1547 GetNetnameMsg(),
1548 GetLayerName(),
1549 aUnitsProvider->MessageTextFromValue( GetLength() ) );
1550}
1551
1552
1554{
1555 return BITMAPS::add_tracks;
1556}
1557
1559{
1560 assert( aImage->Type() == PCB_TRACE_T );
1561
1562 std::swap( *((PCB_TRACK*) this), *((PCB_TRACK*) aImage) );
1563}
1564
1566{
1567 assert( aImage->Type() == PCB_ARC_T );
1568
1569 std::swap( *this, *static_cast<PCB_ARC*>( aImage ) );
1570}
1571
1573{
1574 assert( aImage->Type() == PCB_VIA_T );
1575
1576 std::swap( *((PCB_VIA*) this), *((PCB_VIA*) aImage) );
1577}
1578
1579
1581{
1583 return center;
1584}
1585
1586
1588{
1589 auto center = CalcArcCenter( m_Start, m_Mid , m_End );
1590 return center.Distance( m_Start );
1591}
1592
1593
1595{
1596 VECTOR2D center = GetPosition();
1597 EDA_ANGLE angle1 = EDA_ANGLE( m_Mid - center ) - EDA_ANGLE( m_Start - center );
1598 EDA_ANGLE angle2 = EDA_ANGLE( m_End - center ) - EDA_ANGLE( m_Mid - center );
1599
1600 return angle1.Normalize180() + angle2.Normalize180();
1601}
1602
1603
1605{
1606 VECTOR2D pos( GetPosition() );
1607 EDA_ANGLE angleStart( m_Start - pos );
1608
1609 return angleStart.Normalize();
1610}
1611
1612
1613// Note: used in python tests. Ignore CLion's claim that it's unused....
1615{
1616 VECTOR2D pos( GetPosition() );
1617 EDA_ANGLE angleEnd( m_End - pos );
1618
1619 return angleEnd.Normalize();
1620}
1621
1622bool PCB_ARC::IsDegenerated( int aThreshold ) const
1623{
1624 // Too small arcs cannot be really handled: arc center (and arc radius)
1625 // cannot be safely computed if the distance between mid and end points
1626 // is too small (a few internal units)
1627
1628 // len of both segments must be < aThreshold to be a very small degenerated arc
1629 return ( GetMid() - GetStart() ).EuclideanNorm() < aThreshold
1630 && ( GetMid() - GetEnd() ).EuclideanNorm() < aThreshold;
1631}
1632
1633
1635{
1636 if( a->GetNetCode() != b->GetNetCode() )
1637 return a->GetNetCode() < b->GetNetCode();
1638
1639 if( a->GetLayer() != b->GetLayer() )
1640 return a->GetLayer() < b->GetLayer();
1641
1642 if( a->Type() != b->Type() )
1643 return a->Type() < b->Type();
1644
1645 if( a->m_Uuid != b->m_Uuid )
1646 return a->m_Uuid < b->m_Uuid;
1647
1648 return a < b;
1649}
1650
1651
1652std::shared_ptr<SHAPE> PCB_TRACK::GetEffectiveShape( PCB_LAYER_ID aLayer, FLASHING aFlash ) const
1653{
1654 return std::make_shared<SHAPE_SEGMENT>( m_Start, m_End, m_Width );
1655}
1656
1657
1658std::shared_ptr<SHAPE> PCB_VIA::GetEffectiveShape( PCB_LAYER_ID aLayer, FLASHING aFlash ) const
1659{
1660 if( aFlash == FLASHING::ALWAYS_FLASHED
1661 || ( aFlash == FLASHING::DEFAULT && FlashLayer( aLayer ) ) )
1662 {
1663 return std::make_shared<SHAPE_CIRCLE>( m_Start, m_Width / 2 );
1664 }
1665 else
1666 {
1667 return std::make_shared<SHAPE_CIRCLE>( m_Start, GetDrillValue() / 2 );
1668 }
1669}
1670
1671
1672std::shared_ptr<SHAPE> PCB_ARC::GetEffectiveShape( PCB_LAYER_ID aLayer, FLASHING aFlash ) const
1673{
1674 return std::make_shared<SHAPE_ARC>( GetStart(), GetMid(), GetEnd(), GetWidth() );
1675}
1676
1677
1679 int aClearance, int aError, ERROR_LOC aErrorLoc,
1680 bool ignoreLineWidth ) const
1681{
1682 wxASSERT_MSG( !ignoreLineWidth, wxT( "IgnoreLineWidth has no meaning for tracks." ) );
1683
1684
1685 switch( Type() )
1686 {
1687 case PCB_VIA_T:
1688 {
1689 int radius = ( m_Width / 2 ) + aClearance;
1690 TransformCircleToPolygon( aBuffer, m_Start, radius, aError, aErrorLoc );
1691 break;
1692 }
1693
1694 case PCB_ARC_T:
1695 {
1696 const PCB_ARC* arc = static_cast<const PCB_ARC*>( this );
1697 int width = m_Width + ( 2 * aClearance );
1698
1699 TransformArcToPolygon( aBuffer, arc->GetStart(), arc->GetMid(), arc->GetEnd(), width,
1700 aError, aErrorLoc );
1701 break;
1702 }
1703
1704 default:
1705 {
1706 int width = m_Width + ( 2 * aClearance );
1707
1708 TransformOvalToPolygon( aBuffer, m_Start, m_End, width, aError, aErrorLoc );
1709 break;
1710 }
1711 }
1712}
1713
1714
1715static struct TRACK_VIA_DESC
1716{
1718 {
1720 .Undefined( VIATYPE::NOT_DEFINED )
1721 .Map( VIATYPE::THROUGH, _HKI( "Through" ) )
1722 .Map( VIATYPE::BLIND_BURIED, _HKI( "Blind/buried" ) )
1723 .Map( VIATYPE::MICROVIA, _HKI( "Micro" ) );
1724
1726 .Undefined( TENTING_MODE::FROM_RULES )
1727 .Map( TENTING_MODE::FROM_RULES, _HKI( "From design rules" ) )
1728 .Map( TENTING_MODE::TENTED, _HKI( "Tented" ) )
1729 .Map( TENTING_MODE::NOT_TENTED, _HKI( "Not tented" ) );
1730
1732
1733 if( layerEnum.Choices().GetCount() == 0 )
1734 {
1735 layerEnum.Undefined( UNDEFINED_LAYER );
1736
1737 for( PCB_LAYER_ID layer : LSET::AllLayersMask().Seq() )
1738 layerEnum.Map( layer, LSET::Name( layer ) );
1739 }
1740
1742
1743 // Track
1746
1747 propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "Width" ),
1748 &PCB_TRACK::SetWidth, &PCB_TRACK::GetWidth, PROPERTY_DISPLAY::PT_SIZE ) );
1749 propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Position X" ),
1751 &PCB_TRACK::SetX, &PCB_TRACK::GetX, PROPERTY_DISPLAY::PT_COORD,
1753 propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Position Y" ),
1755 &PCB_TRACK::SetY, &PCB_TRACK::GetY, PROPERTY_DISPLAY::PT_COORD,
1757 propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "End X" ),
1758 &PCB_TRACK::SetEndX, &PCB_TRACK::GetEndX, PROPERTY_DISPLAY::PT_COORD,
1760 propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "End Y" ),
1761 &PCB_TRACK::SetEndY, &PCB_TRACK::GetEndY, PROPERTY_DISPLAY::PT_COORD,
1763
1764 // Arc
1767
1768 // Via
1771
1772 // TODO test drill, use getdrillvalue?
1773 const wxString groupVia = _HKI( "Via Properties" );
1774
1775 propMgr.Mask( TYPE_HASH( PCB_VIA ), TYPE_HASH( BOARD_CONNECTED_ITEM ), _HKI( "Layer" ) );
1776
1777 propMgr.ReplaceProperty( TYPE_HASH( PCB_TRACK ), _HKI( "Width" ),
1778 new PROPERTY<PCB_VIA, int, PCB_TRACK>( _HKI( "Diameter" ),
1779 &PCB_VIA::SetWidth, &PCB_VIA::GetWidth, PROPERTY_DISPLAY::PT_SIZE ) );
1780 propMgr.AddProperty( new PROPERTY<PCB_VIA, int>( _HKI( "Hole" ),
1781 &PCB_VIA::SetDrill, &PCB_VIA::GetDrillValue, PROPERTY_DISPLAY::PT_SIZE ), groupVia );
1782 propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, PCB_LAYER_ID>( _HKI( "Layer Top" ),
1783 &PCB_VIA::SetLayer, &PCB_VIA::GetLayer ), groupVia );
1784 propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, PCB_LAYER_ID>( _HKI( "Layer Bottom" ),
1786 propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, VIATYPE>( _HKI( "Via Type" ),
1788 propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, TENTING_MODE>( _HKI( "Front tenting" ),
1790 propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, TENTING_MODE>( _HKI( "Back tenting" ),
1792 }
1794
constexpr EDA_IU_SCALE pcbIUScale
Definition: base_units.h:108
BITMAPS
A list of all bitmap identifiers.
Definition: bitmaps_list.h:33
@ ZLO_NONE
Definition: board_item.h:67
@ ZLO_FORCE_FLASHED
Definition: board_item.h:68
BOX2I BOX2ISafe(const BOX2D &aInput)
Definition: box2.h:883
BASE_SET & set(size_t pos=std::numeric_limits< size_t >::max(), bool value=true)
Definition: base_set.h:61
bool test(size_t pos) const
Definition: base_set.h:47
BASE_SET & reset(size_t pos=std::numeric_limits< size_t >::max())
Definition: base_set.h:76
size_t size() const
Definition: base_set.h:108
A base class derived from BOARD_ITEM for items that can be connected and have a net,...
wxString GetNetnameMsg() const
virtual NETCLASS * GetEffectiveNetClass() const
Return the NETCLASS for this item.
bool SetNetCode(int aNetCode, bool aNoAssert)
Set net using a net code.
const wxString & GetDisplayNetname() const
virtual int GetOwnClearance(PCB_LAYER_ID aLayer, wxString *aSource=nullptr) const
Return an item's "own" clearance in internal units.
Container for design settings for a BOARD object.
std::shared_ptr< DRC_ENGINE > m_DRCEngine
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition: board_item.h:79
virtual PCB_LAYER_ID GetLayer() const
Return the primary layer this item is on.
Definition: board_item.h:240
int GetY() const
Definition: board_item.h:103
virtual void SetLocked(bool aLocked)
Definition: board_item.h:316
PCB_LAYER_ID m_layer
Definition: board_item.h:409
int GetX() const
Definition: board_item.h:97
void SetX(int aX)
Definition: board_item.h:119
void SetY(int aY)
Definition: board_item.h:125
virtual void SetLayer(PCB_LAYER_ID aLayer)
Set the layer this item is on.
Definition: board_item.h:276
virtual const BOARD * GetBoard() const
Return the BOARD in which this BOARD_ITEM resides, or NULL if none.
Definition: board_item.cpp:47
virtual bool IsLocked() const
Definition: board_item.cpp:75
virtual wxString layerMaskDescribe() const
Return a string (to be shown to the user) describing a layer mask.
Definition: board_item.cpp:131
wxString GetLayerName() const
Return the name of the PCB layer on which the item resides.
Definition: board_item.cpp:104
Information pertinent to a Pcbnew printed circuit board.
Definition: board.h:289
PCB_LAYER_ID FlipLayer(PCB_LAYER_ID aLayer) const
Definition: board.cpp:727
const wxString GetLayerName(PCB_LAYER_ID aLayer) const
Return the name of a aLayer.
Definition: board.cpp:575
std::tuple< int, double, double > GetTrackLength(const PCB_TRACK &aTrack) const
Return data on the length and number of track segments connected to a given track.
Definition: board.cpp:2278
BOARD_DESIGN_SETTINGS & GetDesignSettings() const
Definition: board.cpp:874
std::shared_ptr< CONNECTIVITY_DATA > GetConnectivity() const
Return a list of missing connections between components/tracks.
Definition: board.h:474
bool Intersects(const BOX2< Vec > &aRect) const
Definition: box2.h:294
coord_type GetTop() const
Definition: box2.h:219
bool IntersectsCircle(const Vec &aCenter, const int aRadius) const
Definition: box2.h:487
bool Contains(const Vec &aPoint) const
Definition: box2.h:158
BOX2< Vec > & Inflate(coord_type dx, coord_type dy)
Inflates the rectangle horizontally by dx and vertically by dy.
Definition: box2.h:541
coord_type GetRight() const
Definition: box2.h:207
coord_type GetLeft() const
Definition: box2.h:218
coord_type GetBottom() const
Definition: box2.h:212
BOX2< Vec > & Merge(const BOX2< Vec > &aRect)
Modify the position and size of the rectangle in order to contain aRect.
Definition: box2.h:623
wxString GetName() const
Definition: drc_rule.h:150
MINOPTMAX< int > & Value()
Definition: drc_rule.h:143
EDA_ANGLE Normalize()
Definition: eda_angle.h:221
EDA_ANGLE Normalize180()
Definition: eda_angle.h:260
The base class for create windows for drawing purpose.
A base class for most all the KiCad significant classes used in schematics and boards.
Definition: eda_item.h:89
EDA_ITEM & operator=(const EDA_ITEM &aItem)
Assign the members of aItem to another object.
Definition: eda_item.cpp:258
const KIID m_Uuid
Definition: eda_item.h:489
KICAD_T Type() const
Returns the type of object.
Definition: eda_item.h:101
EDA_ITEM_FLAGS m_flags
Definition: eda_item.h:499
ENUM_MAP & Map(T aValue, const wxString &aName)
Definition: property.h:669
static ENUM_MAP< T > & Instance()
Definition: property.h:663
ENUM_MAP & Undefined(T aValue)
Definition: property.h:676
wxPGChoices & Choices()
Definition: property.h:712
Contains methods for drawing PCB-specific items.
Definition: pcb_painter.h:175
virtual PCB_RENDER_SETTINGS * GetSettings() override
Return a pointer to current settings that are going to be used when drawing items.
Definition: pcb_painter.h:180
PCB specific render settings.
Definition: pcb_painter.h:78
PCB_LAYER_ID GetPrimaryHighContrastLayer() const
Return the board layer which is in high-contrast mode.
bool GetHighContrast() const
Hold a (potentially large) number of VIEW_ITEMs and renders them on a graphics device provided by the...
Definition: view.h:68
BOX2D GetViewport() const
Return the current viewport visible area rectangle.
Definition: view.cpp:547
bool IsLayerVisible(int aLayer) const
Return information about visibility of a particular layer.
Definition: view.h:418
PAINTER * GetPainter() const
Return the painter object used by the view for drawing #VIEW_ITEMS.
Definition: view.h:221
Definition: kiid.h:49
std::string AsStdString() const
Definition: kiid.cpp:252
LSET is a set of PCB_LAYER_IDs.
Definition: lset.h:35
static LSET AllLayersMask()
Definition: lset.cpp:767
void RunOnLayers(const std::function< void(PCB_LAYER_ID)> &aFunction) const
Execute a function on each layer of the LSET.
Definition: lset.h:252
static LSET AllCuMask(int aCuLayerCount=MAX_CU_LAYERS)
Return a mask holding the requested number of Cu PCB_LAYER_IDs.
Definition: lset.cpp:732
static LSET PhysicalLayersMask()
Return a mask holding all layers which are physically realized.
Definition: lset.cpp:822
static const wxChar * Name(PCB_LAYER_ID aLayerId)
Return the fixed name association with aLayerId.
Definition: lset.cpp:63
static LSET FrontTechMask()
Return a mask holding all technical layers (no CU layer) on front side.
Definition: lset.cpp:786
static LSET BackTechMask()
Return a mask holding all technical layers (no CU layer) on back side.
Definition: lset.cpp:774
T Min() const
Definition: minoptmax.h:33
bool HasMin() const
Definition: minoptmax.h:37
A collection of nets and the parameters used to route or test these nets.
Definition: netclass.h:44
int GetViaDrill() const
Definition: netclass.h:81
int GetuViaDrill() const
Definition: netclass.h:89
static const int UNCONNECTED
Constant that holds the "unconnected net" number (typically 0) all items "connected" to this net are ...
Definition: netinfo.h:381
A PADSTACK defines the characteristics of a single or multi-layer pad, in the IPC sense of the word.
Definition: padstack.h:117
bool Deserialize(const google::protobuf::Any &aContainer) override
Deserializes the given protobuf message into this object.
Definition: padstack.cpp:89
MASK_LAYER_PROPS & FrontOuterLayers()
Definition: padstack.h:278
void SetUnconnectedLayerMode(UNCONNECTED_LAYER_MODE aMode)
Definition: padstack.h:273
const LSET & LayerSet() const
Definition: padstack.h:246
DRILL_PROPS & Drill()
Definition: padstack.h:266
VECTOR2I & Size(PCB_LAYER_ID aLayer=F_Cu)
Definition: padstack.cpp:273
MASK_LAYER_PROPS & BackOuterLayers()
Definition: padstack.h:281
void Serialize(google::protobuf::Any &aContainer) const override
Serializes this object to the given Any message.
Definition: padstack.cpp:153
void SetShape(PAD_SHAPE aShape, PCB_LAYER_ID aLayer=F_Cu)
Definition: padstack.cpp:267
virtual VECTOR2I GetPosition() const override
Definition: pcb_track.cpp:1580
bool IsDegenerated(int aThreshold=5) const
Definition: pcb_track.cpp:1622
virtual void swapData(BOARD_ITEM *aImage) override
Definition: pcb_track.cpp:1565
bool IsCCW() const
Definition: pcb_track.cpp:725
void Serialize(google::protobuf::Any &aContainer) const override
Serializes this object to the given Any message.
Definition: pcb_track.cpp:351
EDA_ITEM * Clone() const override
Create a duplicate of this item with linked list members set to NULL.
Definition: pcb_track.cpp:78
EDA_ANGLE GetArcAngleStart() const
Definition: pcb_track.cpp:1604
virtual bool HitTest(const VECTOR2I &aPosition, int aAccuracy=0) const override
Test if aPosition is inside or on the boundary of this item.
Definition: pcb_track.cpp:1452
EDA_ANGLE GetArcAngleEnd() const
Definition: pcb_track.cpp:1614
bool Deserialize(const google::protobuf::Any &aContainer) override
Deserializes the given protobuf message into this object.
Definition: pcb_track.cpp:373
void SetMid(const VECTOR2I &aMid)
Definition: pcb_track.h:280
double GetRadius() const
Definition: pcb_track.cpp:1587
EDA_ANGLE GetAngle() const
Definition: pcb_track.cpp:1594
const VECTOR2I & GetMid() const
Definition: pcb_track.h:281
PCB_ARC(BOARD_ITEM *aParent)
Definition: pcb_track.h:256
void Flip(const VECTOR2I &aCentre, bool aFlipLeftRight) override
Flip this object, i.e.
Definition: pcb_track.cpp:706
double Similarity(const BOARD_ITEM &aOther) const override
Return a measure of how likely the other object is to represent the same object.
Definition: pcb_track.cpp:227
VECTOR2I m_Mid
Arc mid point, halfway between start and end.
Definition: pcb_track.h:342
void Rotate(const VECTOR2I &aRotCentre, const EDA_ANGLE &aAngle) override
Rotate this object.
Definition: pcb_track.cpp:649
std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const override
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
Definition: pcb_track.cpp:1672
bool operator==(const PCB_ARC &aOther) const
Definition: pcb_track.cpp:217
void Mirror(const VECTOR2I &aCentre, bool aMirrorAroundXAxis) override
Definition: pcb_track.cpp:672
void Rotate(const VECTOR2I &aRotCentre, const EDA_ANGLE &aAngle) override
Rotate this object.
Definition: pcb_track.cpp:642
virtual void ViewGetLayers(int aLayers[], int &aCount) const override
Return the all the layers within the VIEW the object is painted on.
Definition: pcb_track.cpp:1101
void Serialize(google::protobuf::Any &aContainer) const override
Serializes this object to the given Any message.
Definition: pcb_track.cpp:312
void SetEndY(int aY)
Definition: pcb_track.h:125
void SetWidth(int aWidth)
Definition: pcb_track.h:115
double ViewGetLOD(int aLayer, KIGFX::VIEW *aView) const override
Return the level of detail (LOD) of the item.
Definition: pcb_track.cpp:1113
virtual double GetLength() const
Get the length of the track using the hypotenuse calculation.
Definition: pcb_track.cpp:636
int GetWidth() const
Definition: pcb_track.h:116
virtual void swapData(BOARD_ITEM *aImage) override
Definition: pcb_track.cpp:1558
void SetEnd(const VECTOR2I &aEnd)
Definition: pcb_track.h:118
void SetStart(const VECTOR2I &aStart)
Definition: pcb_track.h:121
const BOX2I ViewBBox() const override
Return the bounding box of the item covering all its layers.
Definition: pcb_track.cpp:1174
int GetEndX() const
Definition: pcb_track.h:127
wxString GetItemDescription(UNITS_PROVIDER *aUnitsProvider, bool aFull) const override
Return a user-visible description string of this item.
Definition: pcb_track.cpp:1543
bool Deserialize(const google::protobuf::Any &aContainer) override
Deserializes the given protobuf message into this object.
Definition: pcb_track.cpp:332
INSPECT_RESULT Visit(INSPECTOR inspector, void *testData, const std::vector< KICAD_T > &aScanTypes) override
May be re-implemented for each derived class in order to handle all the types given by its member dat...
Definition: pcb_track.cpp:760
bool ApproxCollinear(const PCB_TRACK &aTrack)
Definition: pcb_track.cpp:451
VECTOR2I m_End
Line end point.
Definition: pcb_track.h:249
void GetMsgPanelInfo(EDA_DRAW_FRAME *aFrame, std::vector< MSG_PANEL_ITEM > &aList) override
Populate aList of MSG_PANEL_ITEM objects with it's internal state for display purposes.
Definition: pcb_track.cpp:1312
virtual EDA_ITEM * Clone() const override
Create a duplicate of this item with linked list members set to NULL.
Definition: pcb_track.cpp:63
const BOX2I GetBoundingBox() const override
Return the orthogonal bounding box of this object for display purposes.
Definition: pcb_track.cpp:591
void TransformShapeToPolygon(SHAPE_POLY_SET &aBuffer, PCB_LAYER_ID aLayer, int aClearance, int aError, ERROR_LOC aErrorLoc, bool ignoreLineWidth=false) const override
Convert the track shape to a closed polygon.
Definition: pcb_track.cpp:1678
const VECTOR2I & GetStart() const
Definition: pcb_track.h:122
virtual bool operator==(const BOARD_ITEM &aOther) const override
Definition: pcb_track.cpp:161
VECTOR2I m_Start
Line start point.
Definition: pcb_track.h:248
int GetEndY() const
Definition: pcb_track.h:128
wxString GetFriendlyName() const override
Definition: pcb_track.cpp:1300
BITMAPS GetMenuImage() const override
Return a pointer to an image to be used in menus.
Definition: pcb_track.cpp:1553
void Flip(const VECTOR2I &aCentre, bool aFlipLeftRight) override
Flip this object, i.e.
Definition: pcb_track.cpp:689
bool HitTest(const VECTOR2I &aPosition, int aAccuracy=0) const override
Test if aPosition is inside or on the boundary of this item.
Definition: pcb_track.cpp:1446
virtual double Similarity(const BOARD_ITEM &aOther) const override
Return a measure of how likely the other object is to represent the same object.
Definition: pcb_track.cpp:181
std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const override
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
Definition: pcb_track.cpp:1652
const VECTOR2I & GetEnd() const
Definition: pcb_track.h:119
PCB_TRACK(BOARD_ITEM *aParent, KICAD_T idtype=PCB_TRACE_T)
Definition: pcb_track.cpp:56
int m_Width
Thickness of track, or via diameter.
Definition: pcb_track.h:247
virtual MINOPTMAX< int > GetWidthConstraint(wxString *aSource=nullptr) const
Definition: pcb_track.cpp:459
void SetEndX(int aX)
Definition: pcb_track.h:124
virtual void Mirror(const VECTOR2I &aCentre, bool aMirrorAroundXAxis)
Definition: pcb_track.cpp:657
EDA_ITEM_FLAGS IsPointOnEnds(const VECTOR2I &point, int min_dist=0) const
Return STARTPOINT if point if near (dist = min_dist) start point, ENDPOINT if point if near (dist = m...
Definition: pcb_track.cpp:559
void GetMsgPanelInfoBase_Common(EDA_DRAW_FRAME *aFrame, std::vector< MSG_PANEL_ITEM > &aList) const
Definition: pcb_track.cpp:1407
PCB_LAYER_ID BottomLayer() const
Definition: pcb_track.cpp:988
BITMAPS GetMenuImage() const override
Return a pointer to an image to be used in menus.
Definition: pcb_track.cpp:155
VECTOR2I GetPosition() const override
Definition: pcb_track.h:449
bool IsTented(PCB_LAYER_ID aLayer) const override
Checks if the given object is tented (its copper shape is covered by solder mask) on a given side of ...
Definition: pcb_track.cpp:828
std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const override
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
Definition: pcb_track.cpp:1658
bool Deserialize(const google::protobuf::Any &aContainer) override
Deserializes the given protobuf message into this object.
Definition: pcb_track.cpp:423
bool FlashLayer(int aLayer) const
Check to see whether the via should have a pad on the specific layer.
Definition: pcb_track.cpp:1024
void SetDrillDefault()
Set the drill value for vias to the default value UNDEFINED_DRILL_DIAMETER.
Definition: pcb_track.h:586
const PADSTACK & Padstack() const
Definition: pcb_track.h:380
void SetFrontTentingMode(TENTING_MODE aMode)
Definition: pcb_track.cpp:782
bool m_isFree
"Free" vias don't get their nets auto-updated
Definition: pcb_track.h:639
bool HitTest(const VECTOR2I &aPosition, int aAccuracy=0) const override
Test if aPosition is inside or on the boundary of this item.
Definition: pcb_track.cpp:1487
TENTING_MODE GetFrontTentingMode() const
Definition: pcb_track.cpp:793
virtual void SetLayerSet(LSET aLayers) override
Note SetLayerSet() initialize the first and last copper layers connected by the via.
Definition: pcb_track.cpp:917
void SetBottomLayer(PCB_LAYER_ID aLayer)
Definition: pcb_track.cpp:954
std::array< ZONE_LAYER_OVERRIDE, MAX_CU_LAYERS > m_zoneLayerOverrides
Definition: pcb_track.h:642
int GetSolderMaskExpansion() const
Definition: pcb_track.cpp:851
void SetDrill(int aDrill)
Set the drill value for vias.
Definition: pcb_track.h:564
MINOPTMAX< int > GetDrillConstraint(wxString *aSource=nullptr) const
Definition: pcb_track.cpp:495
void SetBackTentingMode(TENTING_MODE aMode)
Definition: pcb_track.cpp:805
void GetMsgPanelInfo(EDA_DRAW_FRAME *aFrame, std::vector< MSG_PANEL_ITEM > &aList) override
Populate aList of MSG_PANEL_ITEM objects with it's internal state for display purposes.
Definition: pcb_track.cpp:1372
EDA_ITEM * Clone() const override
Create a duplicate of this item with linked list members set to NULL.
Definition: pcb_track.cpp:134
bool operator==(const PCB_VIA &aOther) const
Definition: pcb_track.cpp:266
PCB_LAYER_ID GetLayer() const override
Return the primary layer this item is on.
Definition: pcb_track.cpp:879
double ViewGetLOD(int aLayer, KIGFX::VIEW *aView) const override
Return the level of detail (LOD) of the item.
Definition: pcb_track.cpp:1217
void SetTopLayer(PCB_LAYER_ID aLayer)
Definition: pcb_track.cpp:948
std::shared_ptr< SHAPE_SEGMENT > GetEffectiveHoleShape() const override
Definition: pcb_track.cpp:776
void SetLayerPair(PCB_LAYER_ID aTopLayer, PCB_LAYER_ID aBottomLayer)
For a via m_layer contains the top layer, the other layer is in m_bottomLayer/.
Definition: pcb_track.cpp:939
wxString GetItemDescription(UNITS_PROVIDER *aUnitsProvider, bool aFull) const override
Return a user-visible description string of this item.
Definition: pcb_track.cpp:140
double Similarity(const BOARD_ITEM &aOther) const override
Return a measure of how likely the other object is to represent the same object.
Definition: pcb_track.cpp:278
void SetLayer(PCB_LAYER_ID aLayer) override
Set the layer this item is on.
Definition: pcb_track.cpp:885
void GetOutermostConnectedLayers(PCB_LAYER_ID *aTopmost, PCB_LAYER_ID *aBottommost) const
Return the top-most and bottom-most connected layers.
Definition: pcb_track.cpp:1071
void ViewGetLayers(int aLayers[], int &aCount) const override
Return the all the layers within the VIEW the object is painted on.
Definition: pcb_track.cpp:1187
void SanitizeLayers()
Check so that the layers are correct depending on the type of via, and so that the top actually is on...
Definition: pcb_track.cpp:994
PCB_VIA & operator=(const PCB_VIA &aOther)
Definition: pcb_track.cpp:118
void swapData(BOARD_ITEM *aImage) override
Definition: pcb_track.cpp:1572
void Serialize(google::protobuf::Any &aContainer) const override
Serializes this object to the given Any message.
Definition: pcb_track.cpp:393
PCB_VIA(BOARD_ITEM *aParent)
Definition: pcb_track.cpp:84
wxString layerMaskDescribe() const override
Return a string (to be shown to the user) describing a layer mask.
Definition: pcb_track.cpp:1434
void SetViaType(VIATYPE aViaType)
Definition: pcb_track.h:378
int GetMinAnnulus(PCB_LAYER_ID aLayer, wxString *aSource) const
Definition: pcb_track.cpp:513
bool IsOnLayer(PCB_LAYER_ID aLayer) const override
Test to see if this object is on the given layer.
Definition: pcb_track.cpp:860
TENTING_MODE GetBackTentingMode() const
Definition: pcb_track.cpp:816
PCB_LAYER_ID TopLayer() const
Definition: pcb_track.cpp:982
VIATYPE m_viaType
through, blind/buried or micro
Definition: pcb_track.h:635
PADSTACK m_padStack
Definition: pcb_track.h:637
int GetDrillValue() const
Calculate the drill value for vias (m_drill if > 0, or default drill value for the board).
Definition: pcb_track.cpp:544
VIATYPE GetViaType() const
Definition: pcb_track.h:377
MINOPTMAX< int > GetWidthConstraint(wxString *aSource=nullptr) const override
Definition: pcb_track.cpp:477
virtual LSET GetLayerSet() const override
Return a std::bitset of all layers on which the item physically resides.
Definition: pcb_track.cpp:891
void LayerPair(PCB_LAYER_ID *top_layer, PCB_LAYER_ID *bottom_layer) const
Return the 2 layers used by the via (the via actually uses all layers between these 2 layers)
Definition: pcb_track.cpp:960
void Flip(const VECTOR2I &aCentre, bool aFlipLeftRight) override
Flip this object, i.e.
Definition: pcb_track.cpp:735
Provide class metadata.Helper macro to map type hashes to names.
Definition: property_mgr.h:85
void InheritsAfter(TYPE_ID aDerived, TYPE_ID aBase)
Declare an inheritance relationship between types.
void Mask(TYPE_ID aDerived, TYPE_ID aBase, const wxString &aName)
Sets a base class property as masked in a derived class.
static PROPERTY_MANAGER & Instance()
Definition: property_mgr.h:87
PROPERTY_BASE & AddProperty(PROPERTY_BASE *aProperty, const wxString &aGroup=wxEmptyString)
Register a property.
PROPERTY_BASE & ReplaceProperty(size_t aBase, const wxString &aName, PROPERTY_BASE *aNew, const wxString &aGroup=wxEmptyString)
Replace an existing property for a specific type.
Definition: seg.h:42
VECTOR2I::extended_type ecoord
Definition: seg.h:44
bool ApproxCollinear(const SEG &aSeg, int aDistanceThreshold=1) const
Definition: seg.cpp:449
const VECTOR2I & GetArcMid() const
Definition: shape_arc.h:115
const VECTOR2I & GetP1() const
Definition: shape_arc.h:114
const VECTOR2I & GetP0() const
Definition: shape_arc.h:113
Represent a set of closed polygons.
wxString MessageTextFromMinOptMax(const MINOPTMAX< int > &aValue) const
wxString MessageTextFromValue(double aValue, bool aAddUnitLabel=true, EDA_DATA_TYPE aType=EDA_DATA_TYPE::DISTANCE) const
A lower-precision version of StringFromValue().
double Distance(const VECTOR2< extended_type > &aVector) const
Compute the distance between two vectors.
Definition: vector2d.h:550
T EuclideanNorm() const
Compute the Euclidean norm of the vector, which is defined as sqrt(x ** 2 + y ** 2).
Definition: vector2d.h:278
extended_type Cross(const VECTOR2< T > &aVector) const
Compute cross product of self with aVector.
Definition: vector2d.h:535
void TransformCircleToPolygon(SHAPE_LINE_CHAIN &aBuffer, const VECTOR2I &aCenter, int aRadius, int aError, ERROR_LOC aErrorLoc, int aMinSegCount=0)
Convert a circle to a polygon, using multiple straight lines.
void TransformArcToPolygon(SHAPE_POLY_SET &aBuffer, const VECTOR2I &aStart, const VECTOR2I &aMid, const VECTOR2I &aEnd, int aWidth, int aError, ERROR_LOC aErrorLoc)
Convert arc to multiple straight segments.
void TransformOvalToPolygon(SHAPE_POLY_SET &aBuffer, const VECTOR2I &aStart, const VECTOR2I &aEnd, int aWidth, int aError, ERROR_LOC aErrorLoc, int aMinSegCount=0)
Convert a oblong shape to a polygon, using multiple segments.
#define _HKI(x)
@ ANNULAR_WIDTH_CONSTRAINT
Definition: drc_rule.h:58
@ VIA_DIAMETER_CONSTRAINT
Definition: drc_rule.h:64
@ TRACK_WIDTH_CONSTRAINT
Definition: drc_rule.h:57
@ HOLE_SIZE_CONSTRAINT
Definition: drc_rule.h:52
#define _(s)
static constexpr EDA_ANGLE ANGLE_0
Definition: eda_angle.h:401
static constexpr EDA_ANGLE ANGLE_360
Definition: eda_angle.h:407
#define PCB_EDIT_FRAME_NAME
INSPECT_RESULT
Definition: eda_item.h:43
const INSPECTOR_FUNC & INSPECTOR
Definition: eda_item.h:82
#define ENDPOINT
ends. (Used to support dragging.)
std::uint32_t EDA_ITEM_FLAGS
#define STARTPOINT
When a line is selected, these flags indicate which.
static std::vector< KICAD_T > connectedTypes
ERROR_LOC
When approximating an arc or circle, should the error be placed on the outside or inside of the curve...
bool ClipLine(const BOX2I *aClipBox, int &x1, int &y1, int &x2, int &y2)
Test if any part of a line falls within the bounds of a rectangle.
PCB_LAYER_ID FlipLayer(PCB_LAYER_ID aLayerId, int aCopperLayersCount)
Definition: layer_id.cpp:202
@ LAYER_VIA_NETNAMES
Definition: layer_ids.h:170
constexpr PCB_LAYER_ID PCBNEW_LAYER_ID_START
Definition: layer_ids.h:140
bool IsFrontLayer(PCB_LAYER_ID aLayerId)
Layer classification: check if it's a front layer.
Definition: layer_ids.h:605
FLASHING
Enum used during connectivity building to ensure we do not query connectivity while building the data...
Definition: layer_ids.h:149
bool IsBackLayer(PCB_LAYER_ID aLayerId)
Layer classification: check if it's a back layer.
Definition: layer_ids.h:628
int GetNetnameLayer(int aLayer)
Returns a netname layer corresponding to the given layer.
Definition: layer_ids.h:661
bool IsCopperLayer(int aLayerId)
Tests whether a layer is a copper layer.
Definition: layer_ids.h:531
@ LAYER_LOCKED_ITEM_SHADOW
shadow layer for locked items
Definition: layer_ids.h:243
@ LAYER_VIA_HOLEWALLS
Definition: layer_ids.h:238
@ LAYER_GP_OVERLAY
general purpose overlay
Definition: layer_ids.h:222
@ LAYER_TRACKS
Definition: layer_ids.h:216
@ LAYER_VIA_HOLES
to draw via holes (pad holes do not use this layer)
Definition: layer_ids.h:219
@ LAYER_VIA_MICROVIA
to draw micro vias
Definition: layer_ids.h:198
@ LAYER_VIA_THROUGH
to draw usual through hole vias
Definition: layer_ids.h:200
@ LAYER_VIAS
Meta control for all vias opacity/visibility.
Definition: layer_ids.h:197
@ LAYER_VIA_BBLIND
to draw blind/buried vias
Definition: layer_ids.h:199
bool IsNetnameLayer(int aLayer)
Test whether a layer is a netname layer.
Definition: layer_ids.h:684
bool IsHoleLayer(int aLayer)
Definition: layer_ids.h:570
PCB_LAYER_ID
A quick note on layer IDs:
Definition: layer_ids.h:60
@ B_Mask
Definition: layer_ids.h:106
@ B_Cu
Definition: layer_ids.h:95
@ F_Mask
Definition: layer_ids.h:107
@ UNDEFINED_LAYER
Definition: layer_ids.h:61
@ F_Cu
Definition: layer_ids.h:64
PCB_LAYER_ID ToLAYER_ID(int aLayer)
Definition: lset.cpp:875
void MIRROR(T &aPoint, const T &aMirrorRef)
Updates aPoint with the mirror of aPoint relative to the aMirrorRef.
Definition: mirror.h:40
EDA_ANGLE abs(const EDA_ANGLE &aAngle)
Definition: eda_angle.h:390
static struct TRACK_VIA_DESC _TRACK_VIA_DESC
VIATYPE
Definition: pcb_track.h:66
TENTING_MODE
Definition: pcb_track.h:75
#define TYPE_HASH(x)
Definition: property.h:71
#define ENUM_TO_WXANY(type)
Macro to define read-only fields (no setter method available)
Definition: property.h:765
#define REGISTER_TYPE(x)
Definition: property_mgr.h:371
wxString UnescapeString(const wxString &aSource)
constexpr int mmToIU(double mm) const
Definition: base_units.h:88
PCB_LAYER_ID start
Definition: padstack.h:228
PCB_LAYER_ID end
Definition: padstack.h:229
VECTOR2I size
Drill diameter (x == y) or slot dimensions (x != y)
Definition: padstack.h:226
std::optional< bool > has_solder_mask
True if this outer layer has mask (is not tented)
Definition: padstack.h:217
bool operator()(const PCB_TRACK *aFirst, const PCB_TRACK *aSecond) const
Definition: pcb_track.cpp:1634
bool TestSegmentHit(const VECTOR2I &aRefPoint, const VECTOR2I &aStart, const VECTOR2I &aEnd, int aDist)
Test if aRefPoint is with aDistance on the line defined by aStart and aEnd.
Definition: trigo.cpp:174
void RotatePoint(int *pX, int *pY, const EDA_ANGLE &aAngle)
Calculate the new point of coord coord pX, pY, for a rotation center 0, 0.
Definition: trigo.cpp:228
const VECTOR2I CalcArcCenter(const VECTOR2I &aStart, const VECTOR2I &aMid, const VECTOR2I &aEnd)
Determine the center of an arc or circle given three points on its circumference.
Definition: trigo.cpp:520
KICAD_T
The set of class identification values stored in EDA_ITEM::m_structType.
Definition: typeinfo.h:78
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
Definition: typeinfo.h:97
@ PCB_PAD_T
class PAD, a pad in a footprint
Definition: typeinfo.h:87
@ PCB_ARC_T
class PCB_ARC, an arc track segment on a copper layer
Definition: typeinfo.h:98
@ PCB_TRACE_T
class PCB_TRACK, a track segment (segment on a copper layer)
Definition: typeinfo.h:96
VECTOR2< int32_t > VECTOR2I
Definition: vector2d.h:673
VECTOR2< int64_t > VECTOR2L
Definition: vector2d.h:674