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pcb_track.cpp
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1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright (C) 2012 Jean-Pierre Charras, jp.charras at wanadoo.fr
5 * Copyright (C) 2012 SoftPLC Corporation, Dick Hollenbeck <dick@softplc.com>
6 * Copyright (C) 2012 Wayne Stambaugh <stambaughw@gmail.com>
7 * Copyright (C) 1992-2024 KiCad Developers, see AUTHORS.txt for contributors.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, you may find one here:
21 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
22 * or you may search the http://www.gnu.org website for the version 2 license,
23 * or you may write to the Free Software Foundation, Inc.,
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
25 */
26
27#include "pcb_track.h"
28
29#include <pcb_base_frame.h>
30#include <core/mirror.h>
32#include <board.h>
35#include <base_units.h>
36#include <layer_range.h>
37#include <lset.h>
38#include <string_utils.h>
39#include <view/view.h>
43#include <geometry/seg.h>
46#include <geometry/shape_arc.h>
47#include <drc/drc_engine.h>
48#include <pcb_painter.h>
49#include <trigo.h>
50
51#include <google/protobuf/any.pb.h>
52#include <api/api_enums.h>
53#include <api/api_utils.h>
54#include <api/api_pcb_utils.h>
55#include <api/board/board_types.pb.h>
56
59
61 BOARD_CONNECTED_ITEM( aParent, idtype )
62{
63 m_width = pcbIUScale.mmToIU( 0.2 ); // Gives a reasonable default width
64 m_hasSolderMask = false;
65}
66
67
69{
70 return new PCB_TRACK( *this );
71}
72
73
74PCB_ARC::PCB_ARC( BOARD_ITEM* aParent, const SHAPE_ARC* aArc ) :
75 PCB_TRACK( aParent, PCB_ARC_T )
76{
77 m_Start = aArc->GetP0();
78 m_End = aArc->GetP1();
79 m_Mid = aArc->GetArcMid();
80}
81
82
84{
85 return new PCB_ARC( *this );
86}
87
88
90 PCB_TRACK( aParent, PCB_VIA_T ),
91 m_padStack( this )
92{
93 SetViaType( VIATYPE::THROUGH );
95 Padstack().Drill().end = B_Cu;
97
99
100 // Padstack layerset is not used for vias right now
102
103 // For now, vias are always circles
104 m_padStack.SetShape( PAD_SHAPE::CIRCLE, PADSTACK::ALL_LAYERS );
105
108
109 m_isFree = false;
110}
111
112
113PCB_VIA::PCB_VIA( const PCB_VIA& aOther ) :
114 PCB_TRACK( aOther.GetParent(), PCB_VIA_T ),
115 m_padStack( this )
116{
117 PCB_VIA::operator=( aOther );
118
119 const_cast<KIID&>( m_Uuid ) = aOther.m_Uuid;
121}
122
123
125{
127
128 m_Start = aOther.m_Start;
129 m_End = aOther.m_End;
130
131 m_viaType = aOther.m_viaType;
132 m_padStack = aOther.m_padStack;
133 m_isFree = aOther.m_isFree;
134
135 return *this;
136}
137
138
140{
141 return new PCB_VIA( *this );
142}
143
144
145wxString PCB_VIA::GetItemDescription( UNITS_PROVIDER* aUnitsProvider, bool aFull ) const
146{
147 wxString formatStr;
148
149 switch( GetViaType() )
150 {
151 case VIATYPE::BLIND_BURIED: formatStr = _( "Blind/Buried Via %s on %s" ); break;
152 case VIATYPE::MICROVIA: formatStr = _( "Micro Via %s on %s" ); break;
153 default: formatStr = _( "Via %s on %s" ); break;
154 }
155
156 return wxString::Format( formatStr, GetNetnameMsg(), layerMaskDescribe() );
157}
158
159
161{
162 return BITMAPS::via;
163}
164
165
166bool PCB_TRACK::operator==( const BOARD_ITEM& aBoardItem ) const
167{
168 if( aBoardItem.Type() != Type() )
169 return false;
170
171 const PCB_TRACK& other = static_cast<const PCB_TRACK&>( aBoardItem );
172
173 return *this == other;
174}
175
176
177bool PCB_TRACK::operator==( const PCB_TRACK& aOther ) const
178{
179 return m_Start == aOther.m_Start
180 && m_End == aOther.m_End
181 && m_layer == aOther.m_layer
182 && m_width == aOther.m_width
185}
186
187
188double PCB_TRACK::Similarity( const BOARD_ITEM& aOther ) const
189{
190 if( aOther.Type() != Type() )
191 return 0.0;
192
193 const PCB_TRACK& other = static_cast<const PCB_TRACK&>( aOther );
194
195 double similarity = 1.0;
196
197 if( m_layer != other.m_layer )
198 similarity *= 0.9;
199
200 if( m_width != other.m_width )
201 similarity *= 0.9;
202
203 if( m_Start != other.m_Start )
204 similarity *= 0.9;
205
206 if( m_End != other.m_End )
207 similarity *= 0.9;
208
209 if( m_hasSolderMask != other.m_hasSolderMask )
210 similarity *= 0.9;
211
213 similarity *= 0.9;
214
215 return similarity;
216}
217
218
219bool PCB_ARC::operator==( const BOARD_ITEM& aBoardItem ) const
220{
221 if( aBoardItem.Type() != Type() )
222 return false;
223
224 const PCB_ARC& other = static_cast<const PCB_ARC&>( aBoardItem );
225
226 return *this == other;
227}
228
229
230bool PCB_ARC::operator==( const PCB_TRACK& aOther ) const
231{
232 if( aOther.Type() != Type() )
233 return false;
234
235 const PCB_ARC& other = static_cast<const PCB_ARC&>( aOther );
236
237 return *this == other;
238}
239
240
241bool PCB_ARC::operator==( const PCB_ARC& aOther ) const
242{
243 return m_Start == aOther.m_Start
244 && m_End == aOther.m_End
245 && m_Mid == aOther.m_Mid
246 && m_layer == aOther.m_layer
247 && GetWidth() == aOther.GetWidth()
250}
251
252
253double PCB_ARC::Similarity( const BOARD_ITEM& aOther ) const
254{
255 if( aOther.Type() != Type() )
256 return 0.0;
257
258 const PCB_ARC& other = static_cast<const PCB_ARC&>( aOther );
259
260 double similarity = 1.0;
261
262 if( m_layer != other.m_layer )
263 similarity *= 0.9;
264
265 if( GetWidth() != other.GetWidth() )
266 similarity *= 0.9;
267
268 if( m_Start != other.m_Start )
269 similarity *= 0.9;
270
271 if( m_End != other.m_End )
272 similarity *= 0.9;
273
274 if( m_Mid != other.m_Mid )
275 similarity *= 0.9;
276
277 if( m_hasSolderMask != other.m_hasSolderMask )
278 similarity *= 0.9;
279
281 similarity *= 0.9;
282
283 return similarity;
284}
285
286
287bool PCB_VIA::operator==( const BOARD_ITEM& aBoardItem ) const
288{
289 if( aBoardItem.Type() != Type() )
290 return false;
291
292 const PCB_VIA& other = static_cast<const PCB_VIA&>( aBoardItem );
293
294 return *this == other;
295}
296
297
298bool PCB_VIA::operator==( const PCB_TRACK& aOther ) const
299{
300 if( aOther.Type() != Type() )
301 return false;
302
303 const PCB_VIA& other = static_cast<const PCB_VIA&>( aOther );
304
305 return *this == other;
306}
307
308
309bool PCB_VIA::operator==( const PCB_VIA& aOther ) const
310{
311 return m_Start == aOther.m_Start
312 && m_End == aOther.m_End
313 && m_layer == aOther.m_layer
314 && m_padStack == aOther.m_padStack
315 && m_viaType == aOther.m_viaType
317}
318
319
320double PCB_VIA::Similarity( const BOARD_ITEM& aOther ) const
321{
322 if( aOther.Type() != Type() )
323 return 0.0;
324
325 const PCB_VIA& other = static_cast<const PCB_VIA&>( aOther );
326
327 double similarity = 1.0;
328
329 if( m_layer != other.m_layer )
330 similarity *= 0.9;
331
332 if( m_Start != other.m_Start )
333 similarity *= 0.9;
334
335 if( m_End != other.m_End )
336 similarity *= 0.9;
337
338 if( m_padStack != other.m_padStack )
339 similarity *= 0.9;
340
341 if( m_viaType != other.m_viaType )
342 similarity *= 0.9;
343
345 similarity *= 0.9;
346
347 return similarity;
348}
349
350
351void PCB_VIA::SetWidth( int aWidth )
352{
353 // This is present because of the parent class. It should never be actually called on a via.
354 wxASSERT_MSG( false, "Warning: PCB_VIA::SetWidth called without a layer argument" );
355 m_padStack.SetSize( { aWidth, aWidth }, PADSTACK::ALL_LAYERS );
356}
357
358
360{
361 // This is present because of the parent class. It should never be actually called on a via.
362 wxASSERT_MSG( false, "Warning: PCB_VIA::GetWidth called without a layer argument" );
364}
365
366
367void PCB_VIA::SetWidth( PCB_LAYER_ID aLayer, int aWidth )
368{
369 m_padStack.SetSize( { aWidth, aWidth }, aLayer );
370}
371
372
374{
375 return m_padStack.Size( aLayer ).x;
376}
377
378
379void PCB_TRACK::Serialize( google::protobuf::Any &aContainer ) const
380{
381 kiapi::board::types::Track track;
382
383 track.mutable_id()->set_value( m_Uuid.AsStdString() );
384 track.mutable_start()->set_x_nm( GetStart().x );
385 track.mutable_start()->set_y_nm( GetStart().y );
386 track.mutable_end()->set_x_nm( GetEnd().x );
387 track.mutable_end()->set_y_nm( GetEnd().y );
388 track.mutable_width()->set_value_nm( GetWidth() );
389 track.set_layer( ToProtoEnum<PCB_LAYER_ID, kiapi::board::types::BoardLayer>( GetLayer() ) );
390 track.set_locked( IsLocked() ? kiapi::common::types::LockedState::LS_LOCKED
391 : kiapi::common::types::LockedState::LS_UNLOCKED );
392 track.mutable_net()->mutable_code()->set_value( GetNetCode() );
393 track.mutable_net()->set_name( GetNetname() );
394 // TODO m_hasSolderMask and m_solderMaskMargin
395
396 aContainer.PackFrom( track );
397}
398
399
400bool PCB_TRACK::Deserialize( const google::protobuf::Any &aContainer )
401{
402 kiapi::board::types::Track track;
403
404 if( !aContainer.UnpackTo( &track ) )
405 return false;
406
407 const_cast<KIID&>( m_Uuid ) = KIID( track.id().value() );
408 SetStart( VECTOR2I( track.start().x_nm(), track.start().y_nm() ) );
409 SetEnd( VECTOR2I( track.end().x_nm(), track.end().y_nm() ) );
410 SetWidth( track.width().value_nm() );
411 SetLayer( FromProtoEnum<PCB_LAYER_ID, kiapi::board::types::BoardLayer>( track.layer() ) );
412 SetNetCode( track.net().code().value() );
413 SetLocked( track.locked() == kiapi::common::types::LockedState::LS_LOCKED );
414 // TODO m_hasSolderMask and m_solderMaskMargin
415
416 return true;
417}
418
419
420void PCB_ARC::Serialize( google::protobuf::Any &aContainer ) const
421{
422 kiapi::board::types::Arc arc;
423
424 arc.mutable_id()->set_value( m_Uuid.AsStdString() );
425 arc.mutable_start()->set_x_nm( GetStart().x );
426 arc.mutable_start()->set_y_nm( GetStart().y );
427 arc.mutable_mid()->set_x_nm( GetMid().x );
428 arc.mutable_mid()->set_y_nm( GetMid().y );
429 arc.mutable_end()->set_x_nm( GetEnd().x );
430 arc.mutable_end()->set_y_nm( GetEnd().y );
431 arc.mutable_width()->set_value_nm( GetWidth() );
432 arc.set_layer( ToProtoEnum<PCB_LAYER_ID, kiapi::board::types::BoardLayer>( GetLayer() ) );
433 arc.set_locked( IsLocked() ? kiapi::common::types::LockedState::LS_LOCKED
434 : kiapi::common::types::LockedState::LS_UNLOCKED );
435 arc.mutable_net()->mutable_code()->set_value( GetNetCode() );
436 arc.mutable_net()->set_name( GetNetname() );
437 // TODO m_hasSolderMask and m_solderMaskMargin
438
439 aContainer.PackFrom( arc );
440}
441
442
443bool PCB_ARC::Deserialize( const google::protobuf::Any &aContainer )
444{
445 kiapi::board::types::Arc arc;
446
447 if( !aContainer.UnpackTo( &arc ) )
448 return false;
449
450 const_cast<KIID&>( m_Uuid ) = KIID( arc.id().value() );
451 SetStart( VECTOR2I( arc.start().x_nm(), arc.start().y_nm() ) );
452 SetMid( VECTOR2I( arc.mid().x_nm(), arc.mid().y_nm() ) );
453 SetEnd( VECTOR2I( arc.end().x_nm(), arc.end().y_nm() ) );
454 SetWidth( arc.width().value_nm() );
455 SetLayer( FromProtoEnum<PCB_LAYER_ID, kiapi::board::types::BoardLayer>( arc.layer() ) );
456 SetNetCode( arc.net().code().value() );
457 SetLocked( arc.locked() == kiapi::common::types::LockedState::LS_LOCKED );
458 // TODO m_hasSolderMask and m_solderMaskMargin
459
460 return true;
461}
462
463
464void PCB_VIA::Serialize( google::protobuf::Any &aContainer ) const
465{
466 kiapi::board::types::Via via;
467
468 via.mutable_id()->set_value( m_Uuid.AsStdString() );
469 via.mutable_position()->set_x_nm( GetPosition().x );
470 via.mutable_position()->set_y_nm( GetPosition().y );
471
472 PADSTACK padstack = Padstack();
473
474 google::protobuf::Any padStackWrapper;
475 padstack.Serialize( padStackWrapper );
476 padStackWrapper.UnpackTo( via.mutable_pad_stack() );
477
478 // PADSTACK::m_layerSet is not used by vias
479 via.mutable_pad_stack()->clear_layers();
480 kiapi::board::PackLayerSet( *via.mutable_pad_stack()->mutable_layers(), GetLayerSet() );
481
482 via.set_type( ToProtoEnum<VIATYPE, kiapi::board::types::ViaType>( GetViaType() ) );
483 via.set_locked( IsLocked() ? kiapi::common::types::LockedState::LS_LOCKED
484 : kiapi::common::types::LockedState::LS_UNLOCKED );
485 via.mutable_net()->mutable_code()->set_value( GetNetCode() );
486 via.mutable_net()->set_name( GetNetname() );
487
488 aContainer.PackFrom( via );
489}
490
491
492bool PCB_VIA::Deserialize( const google::protobuf::Any &aContainer )
493{
494 kiapi::board::types::Via via;
495
496 if( !aContainer.UnpackTo( &via ) )
497 return false;
498
499 const_cast<KIID&>( m_Uuid ) = KIID( via.id().value() );
500 SetStart( VECTOR2I( via.position().x_nm(), via.position().y_nm() ) );
501 SetEnd( GetStart() );
502
503 google::protobuf::Any padStackWrapper;
504 padStackWrapper.PackFrom( via.pad_stack() );
505
506 if( !m_padStack.Deserialize( padStackWrapper ) )
507 return false;
508
509 // PADSTACK::m_layerSet is not used by vias
511
512 SetViaType( FromProtoEnum<VIATYPE>( via.type() ) );
513 SetNetCode( via.net().code().value() );
514 SetLocked( via.locked() == kiapi::common::types::LockedState::LS_LOCKED );
515
516 return true;
517}
518
519
521{
522 SEG a( m_Start, m_End );
523 SEG b( aTrack.GetStart(), aTrack.GetEnd() );
524 return a.ApproxCollinear( b );
525}
526
527
529{
530 DRC_CONSTRAINT constraint;
531
532 if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine )
533 {
535
536 constraint = bds.m_DRCEngine->EvalRules( TRACK_WIDTH_CONSTRAINT, this, nullptr, m_layer );
537 }
538
539 if( aSource )
540 *aSource = constraint.GetName();
541
542 return constraint.Value();
543}
544
545
547{
548 DRC_CONSTRAINT constraint;
549
550 if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine )
551 {
553
554 constraint = bds.m_DRCEngine->EvalRules( VIA_DIAMETER_CONSTRAINT, this, nullptr, m_layer );
555 }
556
557 if( aSource )
558 *aSource = constraint.GetName();
559
560 return constraint.Value();
561}
562
563
565{
566 DRC_CONSTRAINT constraint;
567
568 if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine )
569 {
571
572 constraint = bds.m_DRCEngine->EvalRules( HOLE_SIZE_CONSTRAINT, this, nullptr, m_layer );
573 }
574
575 if( aSource )
576 *aSource = constraint.GetName();
577
578 return constraint.Value();
579}
580
581
582int PCB_VIA::GetMinAnnulus( PCB_LAYER_ID aLayer, wxString* aSource ) const
583{
584 if( !FlashLayer( aLayer ) )
585 {
586 if( aSource )
587 *aSource = _( "removed annular ring" );
588
589 return 0;
590 }
591
592 DRC_CONSTRAINT constraint;
593
594 if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine )
595 {
597
598 constraint = bds.m_DRCEngine->EvalRules( ANNULAR_WIDTH_CONSTRAINT, this, nullptr, aLayer );
599 }
600
601 if( constraint.Value().HasMin() )
602 {
603 if( aSource )
604 *aSource = constraint.GetName();
605
606 return constraint.Value().Min();
607 }
608
609 return 0;
610}
611
612
614{
615 if( m_padStack.Drill().size.x > 0 ) // Use the specific value.
616 return m_padStack.Drill().size.x;
617
618 // Use the default value from the Netclass
619 NETCLASS* netclass = GetEffectiveNetClass();
620
621 if( GetViaType() == VIATYPE::MICROVIA )
622 return netclass->GetuViaDrill();
623
624 return netclass->GetViaDrill();
625}
626
627
628EDA_ITEM_FLAGS PCB_TRACK::IsPointOnEnds( const VECTOR2I& point, int min_dist ) const
629{
630 EDA_ITEM_FLAGS result = 0;
631
632 if( min_dist < 0 )
633 min_dist = m_width / 2;
634
635 if( min_dist == 0 )
636 {
637 if( m_Start == point )
638 result |= STARTPOINT;
639
640 if( m_End == point )
641 result |= ENDPOINT;
642 }
643 else
644 {
645 double dist = m_Start.Distance( point );
646
647 if( min_dist >= dist )
648 result |= STARTPOINT;
649
650 dist = m_End.Distance( point );
651
652 if( min_dist >= dist )
653 result |= ENDPOINT;
654 }
655
656 return result;
657}
658
659
661{
662 // end of track is round, this is its radius, rounded up
663 int radius = ( m_width + 1 ) / 2;
664 int ymax, xmax, ymin, xmin;
665
666 if( Type() == PCB_VIA_T )
667 {
668 ymax = m_Start.y;
669 xmax = m_Start.x;
670
671 ymin = m_Start.y;
672 xmin = m_Start.x;
673 }
674 else if( Type() == PCB_ARC_T )
675 {
676 std::shared_ptr<SHAPE> arc = GetEffectiveShape();
677 BOX2I bbox = arc->BBox();
678
679 xmin = bbox.GetLeft();
680 xmax = bbox.GetRight();
681 ymin = bbox.GetTop();
682 ymax = bbox.GetBottom();
683 }
684 else
685 {
686 ymax = std::max( m_Start.y, m_End.y );
687 xmax = std::max( m_Start.x, m_End.x );
688
689 ymin = std::min( m_Start.y, m_End.y );
690 xmin = std::min( m_Start.x, m_End.x );
691 }
692
693 ymax += radius;
694 xmax += radius;
695
696 ymin -= radius;
697 xmin -= radius;
698
699 // return a rectangle which is [pos,dim) in nature. therefore the +1
700 return BOX2ISafe( VECTOR2I( xmin, ymin ),
701 VECTOR2L( (int64_t) xmax - xmin + 1, (int64_t) ymax - ymin + 1 ) );
702}
703
704
706{
707 int radius = 0;
708
710 [&]( PCB_LAYER_ID aLayer )
711 {
712 radius = std::max( radius, GetWidth( aLayer ) );
713 } );
714
715 // via is round, this is its radius, rounded up
716 radius = ( radius + 1 ) / 2;
717
718 int ymax = m_Start.y + radius;
719 int xmax = m_Start.x + radius;
720
721 int ymin = m_Start.y - radius;
722 int xmin = m_Start.x - radius;
723
724 // return a rectangle which is [pos,dim) in nature. therefore the +1
725 return BOX2ISafe( VECTOR2I( xmin, ymin ),
726 VECTOR2L( (int64_t) xmax - xmin + 1, (int64_t) ymax - ymin + 1 ) );
727}
728
729
731{
732 return m_Start.Distance( m_End );
733}
734
735
736void PCB_TRACK::Rotate( const VECTOR2I& aRotCentre, const EDA_ANGLE& aAngle )
737{
738 RotatePoint( m_Start, aRotCentre, aAngle );
739 RotatePoint( m_End, aRotCentre, aAngle );
740}
741
742
743void PCB_ARC::Rotate( const VECTOR2I& aRotCentre, const EDA_ANGLE& aAngle )
744{
745 RotatePoint( m_Start, aRotCentre, aAngle );
746 RotatePoint( m_End, aRotCentre, aAngle );
747 RotatePoint( m_Mid, aRotCentre, aAngle );
748}
749
750
751void PCB_TRACK::Mirror( const VECTOR2I& aCentre, FLIP_DIRECTION aFlipDirection )
752{
753 MIRROR( m_Start, aCentre, aFlipDirection );
754 MIRROR( m_End, aCentre, aFlipDirection );
755}
756
757
758void PCB_ARC::Mirror( const VECTOR2I& aCentre, FLIP_DIRECTION aFlipDirection )
759{
760 MIRROR( m_Start, aCentre, aFlipDirection );
761 MIRROR( m_End, aCentre, aFlipDirection );
762 MIRROR( m_Mid, aCentre, aFlipDirection );
763}
764
765
766void PCB_TRACK::Flip( const VECTOR2I& aCentre, FLIP_DIRECTION aFlipDirection )
767{
768 if( aFlipDirection == FLIP_DIRECTION::LEFT_RIGHT )
769 {
770 m_Start.x = aCentre.x - ( m_Start.x - aCentre.x );
771 m_End.x = aCentre.x - ( m_End.x - aCentre.x );
772 }
773 else
774 {
775 m_Start.y = aCentre.y - ( m_Start.y - aCentre.y );
776 m_End.y = aCentre.y - ( m_End.y - aCentre.y );
777 }
778
780}
781
782
783void PCB_ARC::Flip( const VECTOR2I& aCentre, FLIP_DIRECTION aFlipDirection )
784{
785 if( aFlipDirection == FLIP_DIRECTION::LEFT_RIGHT )
786 {
787 m_Start.x = aCentre.x - ( m_Start.x - aCentre.x );
788 m_End.x = aCentre.x - ( m_End.x - aCentre.x );
789 m_Mid.x = aCentre.x - ( m_Mid.x - aCentre.x );
790 }
791 else
792 {
793 m_Start.y = aCentre.y - ( m_Start.y - aCentre.y );
794 m_End.y = aCentre.y - ( m_End.y - aCentre.y );
795 m_Mid.y = aCentre.y - ( m_Mid.y - aCentre.y );
796 }
797
799}
800
801
802bool PCB_ARC::IsCCW() const
803{
804 VECTOR2L start = m_Start;
805 VECTOR2L start_end = m_End - start;
806 VECTOR2L start_mid = m_Mid - start;
807
808 return start_end.Cross( start_mid ) < 0;
809}
810
811
812void PCB_VIA::Flip( const VECTOR2I& aCentre, FLIP_DIRECTION aFlipDirection )
813{
814 if( aFlipDirection == FLIP_DIRECTION::LEFT_RIGHT )
815 {
816 m_Start.x = aCentre.x - ( m_Start.x - aCentre.x );
817 m_End.x = aCentre.x - ( m_End.x - aCentre.x );
818 }
819 else
820 {
821 m_Start.y = aCentre.y - ( m_Start.y - aCentre.y );
822 m_End.y = aCentre.y - ( m_End.y - aCentre.y );
823 }
824
825 if( GetViaType() != VIATYPE::THROUGH )
826 {
827 PCB_LAYER_ID top_layer;
828 PCB_LAYER_ID bottom_layer;
829 LayerPair( &top_layer, &bottom_layer );
830 top_layer = GetBoard()->FlipLayer( top_layer );
831 bottom_layer = GetBoard()->FlipLayer( bottom_layer );
832 SetLayerPair( top_layer, bottom_layer );
833 }
834}
835
836
837INSPECT_RESULT PCB_TRACK::Visit( INSPECTOR inspector, void* testData,
838 const std::vector<KICAD_T>& aScanTypes )
839{
840 for( KICAD_T scanType : aScanTypes )
841 {
842 if( scanType == Type() )
843 {
844 if( INSPECT_RESULT::QUIT == inspector( this, testData ) )
845 return INSPECT_RESULT::QUIT;
846 }
847 }
848
849 return INSPECT_RESULT::CONTINUE;
850}
851
852
853std::shared_ptr<SHAPE_SEGMENT> PCB_VIA::GetEffectiveHoleShape() const
854{
855 return std::make_shared<SHAPE_SEGMENT>( SEG( m_Start, m_Start ), Padstack().Drill().size.x );
856}
857
858
860{
861 switch( aMode )
862 {
863 case TENTING_MODE::FROM_RULES: m_padStack.FrontOuterLayers().has_solder_mask.reset(); break;
864 case TENTING_MODE::TENTED: m_padStack.FrontOuterLayers().has_solder_mask = true; break;
865 case TENTING_MODE::NOT_TENTED: m_padStack.FrontOuterLayers().has_solder_mask = false; break;
866 }
867}
868
869
871{
873 {
875 TENTING_MODE::TENTED : TENTING_MODE::NOT_TENTED;
876 }
877
878 return TENTING_MODE::FROM_RULES;
879}
880
881
883{
884 switch( aMode )
885 {
886 case TENTING_MODE::FROM_RULES: m_padStack.BackOuterLayers().has_solder_mask.reset(); break;
887 case TENTING_MODE::TENTED: m_padStack.BackOuterLayers().has_solder_mask = true; break;
888 case TENTING_MODE::NOT_TENTED: m_padStack.BackOuterLayers().has_solder_mask = false; break;
889 }
890}
891
892
894{
895 if( m_padStack.BackOuterLayers().has_solder_mask.has_value() )
896 {
898 TENTING_MODE::TENTED : TENTING_MODE::NOT_TENTED;
899 }
900
901 return TENTING_MODE::FROM_RULES;
902}
903
904
905bool PCB_VIA::IsTented( PCB_LAYER_ID aLayer ) const
906{
907 wxCHECK_MSG( IsFrontLayer( aLayer ) || IsBackLayer( aLayer ), true,
908 "Invalid layer passed to IsTented" );
909
910 bool front = IsFrontLayer( aLayer );
911
912 if( front && m_padStack.FrontOuterLayers().has_solder_mask.has_value() )
914
915 if( !front && m_padStack.BackOuterLayers().has_solder_mask.has_value() )
917
918 if( const BOARD* board = GetBoard() )
919 {
920 return front ? board->GetDesignSettings().m_TentViasFront
921 : board->GetDesignSettings().m_TentViasBack;
922 }
923
924 return true;
925}
926
927
929{
930 if( const BOARD* board = GetBoard() )
931 return board->GetDesignSettings().m_SolderMaskExpansion;
932 else
933 return 0;
934}
935
936
938{
939 int margin = m_solderMaskMargin.value_or( 0 );
940
941 // If no local margin is set, get the board's solder mask expansion value
942 if( !m_solderMaskMargin.has_value() )
943 {
944 const BOARD* board = GetBoard();
945
946 if( board )
948 }
949
950 // Ensure the resulting mask opening has a non-negative size
951 if( margin < 0 )
952 margin = std::max( margin, -m_width / 2 );
953
954 return margin;
955}
956
957
959{
960 if( aLayer == m_layer )
961 {
962 return true;
963 }
964
966 && ( ( aLayer == F_Mask && m_layer == F_Cu )
967 || ( aLayer == B_Mask && m_layer == B_Cu ) ) )
968 {
969 return true;
970 }
971
972 return false;
973}
974
975
977{
978#if 0
979 // Nice and simple, but raises its ugly head in performance profiles....
980 return GetLayerSet().test( aLayer );
981#endif
982 if( IsCopperLayer( aLayer ) &&
983 LAYER_RANGE::Contains( Padstack().Drill().start, Padstack().Drill().end, aLayer ) )
984 {
985 return true;
986 }
987
988 // Test for via on mask layers: a via on on a mask layer if not tented and if
989 // it is on the corresponding external copper layer
990 if( aLayer == F_Mask )
991 return Padstack().Drill().start == F_Cu && !IsTented( F_Mask );
992 else if( aLayer == B_Mask )
993 return Padstack().Drill().end == B_Cu && !IsTented( B_Mask );
994
995 return false;
996}
997
998
999bool PCB_VIA::HasValidLayerPair( int aCopperLayerCount )
1000{
1001 // return true if top and bottom layers are valid, depending on the copper layer count
1002 // aCopperLayerCount is expected >= 2
1003
1004 int layer_id = aCopperLayerCount*2;
1005
1006 if( Padstack().Drill().start > B_Cu )
1007 {
1008 if( Padstack().Drill().start > layer_id )
1009 return false;
1010 }
1011 if( Padstack().Drill().end > B_Cu )
1012 {
1013 if( Padstack().Drill().end > layer_id )
1014 return false;
1015 }
1016
1017 return true;
1018}
1019
1020
1022{
1023 return Padstack().Drill().start;
1024}
1025
1026
1028{
1029 Padstack().Drill().start = aLayer;
1030}
1031
1032
1033void PCB_TRACK::SetLayerSet( const LSET& aLayerSet )
1034{
1035 aLayerSet.RunOnLayers(
1036 [&]( PCB_LAYER_ID layer )
1037 {
1038 if( IsCopperLayer( layer ) )
1039 SetLayer( layer );
1040 else if( IsSolderMaskLayer( layer ) )
1041 SetHasSolderMask( true );
1042 } );
1043}
1044
1045
1047{
1048 LSET layermask( { m_layer } );
1049
1050 if( m_hasSolderMask )
1051 {
1052 if( layermask.test( F_Cu ) )
1053 layermask.set( F_Mask );
1054 else if( layermask.test( B_Cu ) )
1055 layermask.set( B_Mask );
1056 }
1057
1058 return layermask;
1059}
1060
1061
1063{
1064 LSET layermask;
1065
1066 if( Padstack().Drill().start < PCBNEW_LAYER_ID_START )
1067 return layermask;
1068
1069 if( GetViaType() == VIATYPE::THROUGH )
1070 {
1071 layermask = LSET::AllCuMask( BoardCopperLayerCount() );
1072 }
1073 else
1074 {
1075 LAYER_RANGE range( Padstack().Drill().start, Padstack().Drill().end, BoardCopperLayerCount() );
1076
1077 int cnt = BoardCopperLayerCount();
1078 // PCB_LAYER_IDs are numbered from front to back, this is top to bottom.
1079 for( PCB_LAYER_ID id : range )
1080 {
1081 layermask.set( id );
1082
1083 if( --cnt <= 0 )
1084 break;
1085 }
1086 }
1087
1088 if( !IsTented( F_Mask ) && layermask.test( F_Cu ) )
1089 layermask.set( F_Mask );
1090
1091 if( !IsTented( B_Mask ) && layermask.test( B_Cu ) )
1092 layermask.set( B_Mask );
1093
1094 return layermask;
1095}
1096
1097
1098void PCB_VIA::SetLayerSet( const LSET& aLayerSet )
1099{
1100 // Vias do not use a LSET, just a top and bottom layer pair
1101 // So we need to set these 2 layers according to the allowed layers in aLayerSet
1102
1103 // For via through, only F_Cu and B_Cu are allowed. aLayerSet is ignored
1104 if( GetViaType() == VIATYPE::THROUGH )
1105 {
1106 Padstack().Drill().start = F_Cu;
1107 Padstack().Drill().end = B_Cu;
1108 return;
1109 }
1110
1111 // For blind buried vias, find the top and bottom layers
1112 bool top_found = false;
1113 bool bottom_found = false;
1114
1115 aLayerSet.RunOnLayers(
1116 [&]( PCB_LAYER_ID layer )
1117 {
1118 // tpo layer and bottom Layer are copper layers, so consider only copper layers
1119 if( IsCopperLayer( layer ) )
1120 {
1121 // The top layer is the first layer found in list and
1122 // cannot the B_Cu
1123 if( !top_found && layer != B_Cu )
1124 {
1125 Padstack().Drill().start = layer;
1126 top_found = true;
1127 }
1128
1129 // The bottom layer is the last layer found in list or B_Cu
1130 if( !bottom_found )
1131 Padstack().Drill().end = layer;
1132
1133 if( layer == B_Cu )
1134 bottom_found = true;
1135 }
1136 } );
1137}
1138
1139
1140void PCB_VIA::SetLayerPair( PCB_LAYER_ID aTopLayer, PCB_LAYER_ID aBottomLayer )
1141{
1142
1143 Padstack().Drill().start = aTopLayer;
1144 Padstack().Drill().end = aBottomLayer;
1146}
1147
1148
1150{
1151 Padstack().Drill().start = aLayer;
1152}
1153
1154
1156{
1157 Padstack().Drill().end = aLayer;
1158}
1159
1160
1161void PCB_VIA::LayerPair( PCB_LAYER_ID* top_layer, PCB_LAYER_ID* bottom_layer ) const
1162{
1163 PCB_LAYER_ID t_layer = F_Cu;
1164 PCB_LAYER_ID b_layer = B_Cu;
1165
1166 if( GetViaType() != VIATYPE::THROUGH )
1167 {
1168 b_layer = Padstack().Drill().end;
1169 t_layer = Padstack().Drill().start;
1170
1171 if( !IsCopperLayerLowerThan( b_layer, t_layer ) )
1172 std::swap( b_layer, t_layer );
1173 }
1174
1175 if( top_layer )
1176 *top_layer = t_layer;
1177
1178 if( bottom_layer )
1179 *bottom_layer = b_layer;
1180}
1181
1182
1184{
1185 return Padstack().Drill().start;
1186}
1187
1188
1190{
1191 return Padstack().Drill().end;
1192}
1193
1194
1196{
1197 if( GetViaType() == VIATYPE::THROUGH )
1198 {
1199 Padstack().Drill().start = F_Cu;
1200 Padstack().Drill().end = B_Cu;
1201 }
1202
1203 if( !IsCopperLayerLowerThan( Padstack().Drill().end, Padstack().Drill().start) )
1204 std::swap( Padstack().Drill().end, Padstack().Drill().start );
1205}
1206
1207
1208bool PCB_VIA::FlashLayer( LSET aLayers ) const
1209{
1210 for( size_t ii = 0; ii < aLayers.size(); ++ii )
1211 {
1212 if( aLayers.test( ii ) )
1213 {
1214 PCB_LAYER_ID layer = PCB_LAYER_ID( ii );
1215
1216 if( FlashLayer( layer ) )
1217 return true;
1218 }
1219 }
1220
1221 return false;
1222}
1223
1224
1225bool PCB_VIA::FlashLayer( int aLayer ) const
1226{
1227 // Return the "normal" shape if the caller doesn't specify a particular layer
1228 if( aLayer == UNDEFINED_LAYER )
1229 return true;
1230
1231 const BOARD* board = GetBoard();
1232
1233 if( !board )
1234 return true;
1235
1236 if( !IsOnLayer( static_cast<PCB_LAYER_ID>( aLayer ) ) )
1237 return false;
1238
1239 if( !IsCopperLayer( aLayer ) )
1240 return true;
1241
1242 switch( Padstack().UnconnectedLayerMode() )
1243 {
1245 return true;
1246
1248 {
1249 if( aLayer == Padstack().Drill().start || aLayer == Padstack().Drill().end )
1250 return true;
1251
1252 // Check for removal below
1253 break;
1254 }
1255
1257 // Check for removal below
1258 break;
1259 }
1260
1261 // Must be static to keep from raising its ugly head in performance profiles
1262 static std::initializer_list<KICAD_T> connectedTypes = { PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T,
1263 PCB_PAD_T };
1264
1265 if( GetZoneLayerOverride( static_cast<PCB_LAYER_ID>( aLayer ) ) == ZLO_FORCE_FLASHED )
1266 return true;
1267 else
1268 return board->GetConnectivity()->IsConnectedOnLayer( this, static_cast<PCB_LAYER_ID>( aLayer ), connectedTypes );
1269}
1270
1271
1273{
1274 std::unique_lock<std::mutex> cacheLock( m_zoneLayerOverridesMutex );
1275
1278}
1279
1280
1282{
1283 static const ZONE_LAYER_OVERRIDE defaultOverride = ZLO_NONE;
1284 auto it = m_zoneLayerOverrides.find( aLayer );
1285 return it != m_zoneLayerOverrides.end() ? it->second : defaultOverride;
1286}
1287
1288
1290{
1291 std::unique_lock<std::mutex> cacheLock( m_zoneLayerOverridesMutex );
1292 m_zoneLayerOverrides[aLayer] = aOverride;
1293}
1294
1295
1297 PCB_LAYER_ID* aBottommost ) const
1298{
1299 *aTopmost = UNDEFINED_LAYER;
1300 *aBottommost = UNDEFINED_LAYER;
1301
1302 static std::initializer_list<KICAD_T> connectedTypes = { PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T,
1303 PCB_PAD_T };
1304
1305 for( int layer = TopLayer(); layer <= BottomLayer(); ++layer )
1306 {
1307 bool connected = false;
1308
1309 if( GetZoneLayerOverride( static_cast<PCB_LAYER_ID>( layer ) ) == ZLO_FORCE_FLASHED )
1310 connected = true;
1311 else if( GetBoard()->GetConnectivity()->IsConnectedOnLayer( this, layer, connectedTypes ) )
1312 connected = true;
1313
1314 if( connected )
1315 {
1316 if( *aTopmost == UNDEFINED_LAYER )
1317 *aTopmost = ToLAYER_ID( layer );
1318
1319 *aBottommost = ToLAYER_ID( layer );
1320 }
1321 }
1322
1323}
1324
1325
1326std::vector<int> PCB_TRACK::ViewGetLayers() const
1327{
1328 // Show the track and its netname on different layers
1329 std::vector<int> layers { GetLayer(), GetNetnameLayer( GetLayer() ) };
1330
1331 layers.reserve( 5 );
1332
1333 if( m_hasSolderMask )
1334 {
1335 if( m_layer == F_Cu )
1336 layers.push_back( F_Mask );
1337 else if( m_layer == B_Cu )
1338 layers.push_back( B_Mask );
1339 }
1340
1341 if( IsLocked() )
1342 layers.push_back( LAYER_LOCKED_ITEM_SHADOW );
1343
1344 return layers;
1345}
1346
1347
1348double PCB_TRACK::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
1349{
1350 constexpr double HIDE = std::numeric_limits<double>::max();
1351
1352 PCB_PAINTER* painter = static_cast<PCB_PAINTER*>( aView->GetPainter() );
1353 PCB_RENDER_SETTINGS* renderSettings = painter->GetSettings();
1354
1355 if( !aView->IsLayerVisible( LAYER_TRACKS ) )
1356 return HIDE;
1357
1358 if( IsNetnameLayer( aLayer ) )
1359 {
1361 return HIDE;
1362
1363 // Hide netnames on dimmed tracks
1364 if( renderSettings->GetHighContrast() )
1365 {
1366 if( m_layer != renderSettings->GetPrimaryHighContrastLayer() )
1367 return HIDE;
1368 }
1369
1370 VECTOR2I start( GetStart() );
1371 VECTOR2I end( GetEnd() );
1372
1373 // Calc the approximate size of the netname (assume square chars)
1374 SEG::ecoord nameSize = GetDisplayNetname().size() * GetWidth();
1375
1376 if( VECTOR2I( end - start ).SquaredEuclideanNorm() < nameSize * nameSize )
1377 return HIDE;
1378
1379 BOX2I clipBox = BOX2ISafe( aView->GetViewport() );
1380
1381 ClipLine( &clipBox, start.x, start.y, end.x, end.y );
1382
1383 if( VECTOR2I( end - start ).SquaredEuclideanNorm() == 0 )
1384 return HIDE;
1385
1386 // Netnames will be shown only if zoom is appropriate
1387 return ( double ) pcbIUScale.mmToIU( 4 ) / ( m_width + 1 );
1388 }
1389
1390 if( aLayer == LAYER_LOCKED_ITEM_SHADOW )
1391 {
1392 // Hide shadow if the main layer is not shown
1393 if( !aView->IsLayerVisible( m_layer ) )
1394 return HIDE;
1395
1396 // Hide shadow on dimmed tracks
1397 if( renderSettings->GetHighContrast() )
1398 {
1399 if( m_layer != renderSettings->GetPrimaryHighContrastLayer() )
1400 return HIDE;
1401 }
1402 }
1403
1404 // Other layers are shown without any conditions
1405 return 0.0;
1406}
1407
1408
1410{
1411 BOX2I bbox = GetBoundingBox();
1412
1413 if( const BOARD* board = GetBoard() )
1414 bbox.Inflate( 2 * board->GetDesignSettings().GetBiggestClearanceValue() );
1415 else
1416 bbox.Inflate( GetWidth() ); // Add a bit extra for safety
1417
1418 return bbox;
1419}
1420
1421
1422std::vector<int> PCB_VIA::ViewGetLayers() const
1423{
1424 LAYER_RANGE layers( Padstack().Drill().start, Padstack().Drill().end, MAX_CU_LAYERS );
1425 std::vector<int> ret_layers{ LAYER_VIA_HOLES, LAYER_VIA_HOLEWALLS, LAYER_VIA_NETNAMES };
1426 ret_layers.reserve( MAX_CU_LAYERS + 6 );
1427
1428 // TODO(JE) Rendering order issue
1429#if 0
1430 // Blind/buried vias (and microvias) use a different net name layer
1431 PCB_LAYER_ID layerTop, layerBottom;
1432 LayerPair( &layerTop, &layerBottom );
1433
1434 bool isBlindBuried =
1435 m_viaType == VIATYPE::BLIND_BURIED
1436 || ( m_viaType == VIATYPE::MICROVIA && ( layerTop != F_Cu || layerBottom != B_Cu ) );
1437#endif
1438 LSET cuMask = LSET::AllCuMask();
1439
1440 if( const BOARD* board = GetBoard() )
1441 cuMask = board->GetEnabledLayers();
1442
1443 for( PCB_LAYER_ID layer : layers )
1444 {
1445 if( !cuMask.Contains( layer ) )
1446 continue;
1447
1448 ret_layers.push_back( LAYER_VIA_COPPER_START + layer );
1449 }
1450
1451 if( IsLocked() )
1452 ret_layers.push_back( LAYER_LOCKED_ITEM_SHADOW );
1453
1454 // Vias can also be on a solder mask layer. They are on these layers or not,
1455 // depending on the plot and solder mask options
1456 if( IsOnLayer( F_Mask ) )
1457 ret_layers.push_back( F_Mask );
1458
1459 if( IsOnLayer( B_Mask ) )
1460 ret_layers.push_back( B_Mask );
1461
1462 return ret_layers;
1463}
1464
1465
1466double PCB_VIA::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
1467{
1468 constexpr double HIDE = (double)std::numeric_limits<double>::max();
1469
1470 PCB_PAINTER* painter = static_cast<PCB_PAINTER*>( aView->GetPainter() );
1471 PCB_RENDER_SETTINGS* renderSettings = painter->GetSettings();
1472 LSET visible = LSET::AllLayersMask();
1473
1474 // Meta control for hiding all vias
1475 if( !aView->IsLayerVisible( LAYER_VIAS ) )
1476 return HIDE;
1477
1478 // Handle board visibility
1479 if( const BOARD* board = GetBoard() )
1480 visible = board->GetVisibleLayers() & board->GetEnabledLayers();
1481
1482 int width = GetWidth( ToLAYER_ID( aLayer ) );
1483
1484 // In high contrast mode don't show vias that don't cross the high-contrast layer
1485 if( renderSettings->GetHighContrast() )
1486 {
1487 PCB_LAYER_ID highContrastLayer = renderSettings->GetPrimaryHighContrastLayer();
1488
1489 if( LSET::FrontTechMask().Contains( highContrastLayer ) )
1490 highContrastLayer = F_Cu;
1491 else if( LSET::BackTechMask().Contains( highContrastLayer ) )
1492 highContrastLayer = B_Cu;
1493
1494 if( !IsCopperLayer( highContrastLayer ) )
1495 return HIDE;
1496
1497 if( GetViaType() != VIATYPE::THROUGH )
1498 {
1499 if( IsCopperLayerLowerThan( Padstack().Drill().start, highContrastLayer )
1500 || IsCopperLayerLowerThan( highContrastLayer, Padstack().Drill().end ) )
1501 {
1502 return HIDE;
1503 }
1504 }
1505 }
1506
1507 if( IsHoleLayer( aLayer ) )
1508 {
1509 if( m_viaType == VIATYPE::THROUGH )
1510 {
1511 // Show a through via's hole if any physical layer is shown
1512 if( !( visible & LSET::PhysicalLayersMask() ).any() )
1513 return HIDE;
1514 }
1515 else
1516 {
1517 // Show a blind or micro via's hole if it crosses a visible layer
1518 if( !( visible & GetLayerSet() ).any() )
1519 return HIDE;
1520 }
1521
1522 // The hole won't be visible anyway at this scale
1523 return (double) pcbIUScale.mmToIU( 0.25 ) / GetDrillValue();
1524 }
1525 else if( IsNetnameLayer( aLayer ) )
1526 {
1527 if( renderSettings->GetHighContrast() )
1528 {
1529 // Hide netnames unless via is flashed to a high-contrast layer
1530 if( !FlashLayer( renderSettings->GetPrimaryHighContrastLayer() ) )
1531 return HIDE;
1532 }
1533 else
1534 {
1535 // Hide netnames unless pad is flashed to a visible layer
1536 if( !FlashLayer( visible ) )
1537 return HIDE;
1538 }
1539
1540 // Netnames will be shown only if zoom is appropriate
1541 return width == 0 ? HIDE : ( (double)pcbIUScale.mmToIU( 10 ) / width );
1542 }
1543
1544 if( !IsCopperLayer( aLayer ) )
1545 return (double) pcbIUScale.mmToIU( 0.6 ) / width;
1546
1547 return 0.0;
1548}
1549
1550
1552{
1553 switch( Type() )
1554 {
1555 case PCB_ARC_T: return _( "Track (arc)" );
1556 case PCB_VIA_T: return _( "Via" );
1557 case PCB_TRACE_T:
1558 default: return _( "Track" );
1559 }
1560}
1561
1562
1563void PCB_TRACK::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>& aList )
1564{
1565 wxString msg;
1566 BOARD* board = GetBoard();
1567
1568 aList.emplace_back( _( "Type" ), GetFriendlyName() );
1569
1570 GetMsgPanelInfoBase_Common( aFrame, aList );
1571
1572 aList.emplace_back( _( "Layer" ), layerMaskDescribe() );
1573
1574 aList.emplace_back( _( "Width" ), aFrame->MessageTextFromValue( m_width ) );
1575
1576 if( Type() == PCB_ARC_T )
1577 {
1578 double radius = static_cast<PCB_ARC*>( this )->GetRadius();
1579 aList.emplace_back( _( "Radius" ), aFrame->MessageTextFromValue( radius ) );
1580 }
1581
1582 aList.emplace_back( _( "Segment Length" ), aFrame->MessageTextFromValue( GetLength() ) );
1583
1584 // Display full track length (in Pcbnew)
1585 if( board && GetNetCode() > 0 )
1586 {
1587 int count;
1588 double trackLen;
1589 double lenPadToDie;
1590
1591 std::tie( count, trackLen, lenPadToDie ) = board->GetTrackLength( *this );
1592
1593 aList.emplace_back( _( "Routed Length" ), aFrame->MessageTextFromValue( trackLen ) );
1594
1595 if( lenPadToDie != 0 )
1596 {
1597 msg = aFrame->MessageTextFromValue( lenPadToDie );
1598 aList.emplace_back( _( "Pad To Die Length" ), msg );
1599
1600 msg = aFrame->MessageTextFromValue( trackLen + lenPadToDie );
1601 aList.emplace_back( _( "Full Length" ), msg );
1602 }
1603 }
1604
1605 wxString source;
1606 int clearance = GetOwnClearance( GetLayer(), &source );
1607
1608 aList.emplace_back( wxString::Format( _( "Min Clearance: %s" ),
1609 aFrame->MessageTextFromValue( clearance ) ),
1610 wxString::Format( _( "(from %s)" ), source ) );
1611
1612 MINOPTMAX<int> constraintValue = GetWidthConstraint( &source );
1613 msg = aFrame->MessageTextFromMinOptMax( constraintValue );
1614
1615 if( !msg.IsEmpty() )
1616 {
1617 aList.emplace_back( wxString::Format( _( "Width Constraints: %s" ), msg ),
1618 wxString::Format( _( "(from %s)" ), source ) );
1619 }
1620}
1621
1622
1623void PCB_VIA::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>& aList )
1624{
1625 wxString msg;
1626
1627 switch( GetViaType() )
1628 {
1629 case VIATYPE::MICROVIA: msg = _( "Micro Via" ); break;
1630 case VIATYPE::BLIND_BURIED: msg = _( "Blind/Buried Via" ); break;
1631 case VIATYPE::THROUGH: msg = _( "Through Via" ); break;
1632 default: msg = _( "Via" ); break;
1633 }
1634
1635 aList.emplace_back( _( "Type" ), msg );
1636
1637 GetMsgPanelInfoBase_Common( aFrame, aList );
1638
1639 aList.emplace_back( _( "Layer" ), layerMaskDescribe() );
1640 // TODO(JE) padstacks
1641 aList.emplace_back( _( "Diameter" ),
1643 aList.emplace_back( _( "Hole" ), aFrame->MessageTextFromValue( GetDrillValue() ) );
1644
1645 wxString source;
1646 int clearance = GetOwnClearance( GetLayer(), &source );
1647
1648 aList.emplace_back( wxString::Format( _( "Min Clearance: %s" ),
1649 aFrame->MessageTextFromValue( clearance ) ),
1650 wxString::Format( _( "(from %s)" ), source ) );
1651
1652 int minAnnulus = GetMinAnnulus( GetLayer(), &source );
1653
1654 aList.emplace_back( wxString::Format( _( "Min Annular Width: %s" ),
1655 aFrame->MessageTextFromValue( minAnnulus ) ),
1656 wxString::Format( _( "(from %s)" ), source ) );
1657}
1658
1659
1661 std::vector<MSG_PANEL_ITEM>& aList ) const
1662{
1663 aList.emplace_back( _( "Net" ), UnescapeString( GetNetname() ) );
1664
1665 aList.emplace_back( _( "Resolved Netclass" ),
1666 UnescapeString( GetEffectiveNetClass()->GetName() ) );
1667
1668#if 0 // Enable for debugging
1669 if( GetBoard() )
1670 aList.emplace_back( _( "NetCode" ), wxString::Format( wxT( "%d" ), GetNetCode() ) );
1671
1672 aList.emplace_back( wxT( "Flags" ), wxString::Format( wxT( "0x%08X" ), m_flags ) );
1673
1674 aList.emplace_back( wxT( "Start pos" ), wxString::Format( wxT( "%d %d" ),
1675 m_Start.x,
1676 m_Start.y ) );
1677 aList.emplace_back( wxT( "End pos" ), wxString::Format( wxT( "%d %d" ),
1678 m_End.x,
1679 m_End.y ) );
1680#endif
1681
1682 if( aFrame->GetName() == PCB_EDIT_FRAME_NAME && IsLocked() )
1683 aList.emplace_back( _( "Status" ), _( "Locked" ) );
1684}
1685
1686
1688{
1689 const BOARD* board = GetBoard();
1690 PCB_LAYER_ID top_layer;
1691 PCB_LAYER_ID bottom_layer;
1692
1693 LayerPair( &top_layer, &bottom_layer );
1694
1695 return board->GetLayerName( top_layer ) + wxT( " - " ) + board->GetLayerName( bottom_layer );
1696}
1697
1698
1699bool PCB_TRACK::HitTest( const VECTOR2I& aPosition, int aAccuracy ) const
1700{
1701 return TestSegmentHit( aPosition, m_Start, m_End, aAccuracy + ( m_width / 2 ) );
1702}
1703
1704
1705bool PCB_ARC::HitTest( const VECTOR2I& aPosition, int aAccuracy ) const
1706{
1707 double max_dist = aAccuracy + ( GetWidth() / 2.0 );
1708
1709 // Short-circuit common cases where the arc is connected to a track or via at an endpoint
1710 if( GetStart().Distance( aPosition ) <= max_dist || GetEnd().Distance( aPosition ) <= max_dist )
1711 {
1712 return true;
1713 }
1714
1715 VECTOR2L center = GetPosition();
1716 VECTOR2L relpos = aPosition - center;
1717 int64_t dist = relpos.EuclideanNorm();
1718 double radius = GetRadius();
1719
1720 if( std::abs( dist - radius ) > max_dist )
1721 return false;
1722
1723 EDA_ANGLE arc_angle = GetAngle();
1724 EDA_ANGLE arc_angle_start = GetArcAngleStart(); // Always 0.0 ... 360 deg
1725 EDA_ANGLE arc_hittest( relpos );
1726
1727 // Calculate relative angle between the starting point of the arc, and the test point
1728 arc_hittest -= arc_angle_start;
1729
1730 // Normalise arc_hittest between 0 ... 360 deg
1731 arc_hittest.Normalize();
1732
1733 if( arc_angle < ANGLE_0 )
1734 return arc_hittest >= ANGLE_360 + arc_angle;
1735
1736 return arc_hittest <= arc_angle;
1737}
1738
1739
1740bool PCB_VIA::HitTest( const VECTOR2I& aPosition, int aAccuracy ) const
1741{
1742 bool hit = false;
1743
1745 [&]( PCB_LAYER_ID aLayer )
1746 {
1747 if( hit )
1748 return;
1749
1750 int max_dist = aAccuracy + ( GetWidth( aLayer ) / 2 );
1751
1752 // rel_pos is aPosition relative to m_Start (or the center of the via)
1753 VECTOR2D rel_pos = aPosition - m_Start;
1754 double dist = rel_pos.x * rel_pos.x + rel_pos.y * rel_pos.y;
1755
1756 if( dist <= static_cast<double>( max_dist ) * max_dist )
1757 hit = true;
1758 } );
1759
1760 return hit;
1761}
1762
1763
1764bool PCB_TRACK::HitTest( const BOX2I& aRect, bool aContained, int aAccuracy ) const
1765{
1766 BOX2I arect = aRect;
1767 arect.Inflate( aAccuracy );
1768
1769 if( aContained )
1770 return arect.Contains( GetStart() ) && arect.Contains( GetEnd() );
1771 else
1772 return arect.Intersects( GetStart(), GetEnd() );
1773}
1774
1775
1776bool PCB_ARC::HitTest( const BOX2I& aRect, bool aContained, int aAccuracy ) const
1777{
1778 BOX2I arect = aRect;
1779 arect.Inflate( aAccuracy );
1780
1781 BOX2I box( GetStart() );
1782 box.Merge( GetMid() );
1783 box.Merge( GetEnd() );
1784
1785 box.Inflate( GetWidth() / 2 );
1786
1787 if( aContained )
1788 return arect.Contains( box );
1789 else
1790 return arect.Intersects( box );
1791}
1792
1793
1794bool PCB_VIA::HitTest( const BOX2I& aRect, bool aContained, int aAccuracy ) const
1795{
1796 BOX2I arect = aRect;
1797 arect.Inflate( aAccuracy );
1798
1799 bool hit = false;
1800
1802 [&]( PCB_LAYER_ID aLayer )
1803 {
1804 if( hit )
1805 return;
1806
1807 BOX2I box( GetStart() );
1808 box.Inflate( GetWidth( aLayer ) / 2 );
1809
1810 if( aContained )
1811 hit = arect.Contains( box );
1812 else
1813 hit = arect.IntersectsCircle( GetStart(), GetWidth( aLayer ) / 2 );
1814 } );
1815
1816 return hit;
1817}
1818
1819
1820wxString PCB_TRACK::GetItemDescription( UNITS_PROVIDER* aUnitsProvider, bool aFull ) const
1821{
1822 return wxString::Format( Type() == PCB_ARC_T ? _("Track (arc) %s on %s, length %s" )
1823 : _("Track %s on %s, length %s" ),
1824 GetNetnameMsg(),
1825 GetLayerName(),
1826 aUnitsProvider->MessageTextFromValue( GetLength() ) );
1827}
1828
1829
1831{
1832 return BITMAPS::add_tracks;
1833}
1834
1836{
1837 assert( aImage->Type() == PCB_TRACE_T );
1838
1839 std::swap( *((PCB_TRACK*) this), *((PCB_TRACK*) aImage) );
1840}
1841
1843{
1844 assert( aImage->Type() == PCB_ARC_T );
1845
1846 std::swap( *this, *static_cast<PCB_ARC*>( aImage ) );
1847}
1848
1850{
1851 assert( aImage->Type() == PCB_VIA_T );
1852
1853 std::swap( *((PCB_VIA*) this), *((PCB_VIA*) aImage) );
1854}
1855
1856
1858{
1860 return center;
1861}
1862
1863
1865{
1866 auto center = CalcArcCenter( m_Start, m_Mid , m_End );
1867 return center.Distance( m_Start );
1868}
1869
1870
1872{
1873 VECTOR2D center = GetPosition();
1874 EDA_ANGLE angle1 = EDA_ANGLE( m_Mid - center ) - EDA_ANGLE( m_Start - center );
1875 EDA_ANGLE angle2 = EDA_ANGLE( m_End - center ) - EDA_ANGLE( m_Mid - center );
1876
1877 return angle1.Normalize180() + angle2.Normalize180();
1878}
1879
1880
1882{
1883 VECTOR2D pos( GetPosition() );
1884 EDA_ANGLE angleStart( m_Start - pos );
1885
1886 return angleStart.Normalize();
1887}
1888
1889
1890// Note: used in python tests. Ignore CLion's claim that it's unused....
1892{
1893 VECTOR2D pos( GetPosition() );
1894 EDA_ANGLE angleEnd( m_End - pos );
1895
1896 return angleEnd.Normalize();
1897}
1898
1899bool PCB_ARC::IsDegenerated( int aThreshold ) const
1900{
1901 // Too small arcs cannot be really handled: arc center (and arc radius)
1902 // cannot be safely computed if the distance between mid and end points
1903 // is too small (a few internal units)
1904
1905 // len of both segments must be < aThreshold to be a very small degenerated arc
1906 return ( GetMid() - GetStart() ).EuclideanNorm() < aThreshold
1907 && ( GetMid() - GetEnd() ).EuclideanNorm() < aThreshold;
1908}
1909
1910
1912{
1913 if( a->GetNetCode() != b->GetNetCode() )
1914 return a->GetNetCode() < b->GetNetCode();
1915
1916 if( a->GetLayer() != b->GetLayer() )
1917 return a->GetLayer() < b->GetLayer();
1918
1919 if( a->Type() != b->Type() )
1920 return a->Type() < b->Type();
1921
1922 if( a->m_Uuid != b->m_Uuid )
1923 return a->m_Uuid < b->m_Uuid;
1924
1925 return a < b;
1926}
1927
1928
1929std::shared_ptr<SHAPE> PCB_TRACK::GetEffectiveShape( PCB_LAYER_ID aLayer, FLASHING aFlash ) const
1930{
1931 int width = m_width;
1932
1933 if( IsSolderMaskLayer( aLayer ) )
1934 width += 2 * GetSolderMaskExpansion();
1935
1936 return std::make_shared<SHAPE_SEGMENT>( m_Start, m_End, width );
1937}
1938
1939
1940std::shared_ptr<SHAPE> PCB_VIA::GetEffectiveShape( PCB_LAYER_ID aLayer, FLASHING aFlash ) const
1941{
1942 if( aFlash == FLASHING::ALWAYS_FLASHED
1943 || ( aFlash == FLASHING::DEFAULT && FlashLayer( aLayer ) ) )
1944 {
1945 int width = 0;
1946
1947 if( aLayer == UNDEFINED_LAYER )
1948 {
1949 Padstack().ForEachUniqueLayer(
1950 [&]( PCB_LAYER_ID layer )
1951 {
1952 width = std::max( width, GetWidth( layer ) );
1953 } );
1954
1955 width /= 2;
1956 }
1957 else
1958 {
1959 PCB_LAYER_ID cuLayer = m_padStack.EffectiveLayerFor( aLayer );
1960 width = GetWidth( cuLayer ) / 2;
1961 }
1962
1963 return std::make_shared<SHAPE_CIRCLE>( m_Start, width );
1964 }
1965 else
1966 {
1967 return std::make_shared<SHAPE_CIRCLE>( m_Start, GetDrillValue() / 2 );
1968 }
1969}
1970
1971
1972std::shared_ptr<SHAPE> PCB_ARC::GetEffectiveShape( PCB_LAYER_ID aLayer, FLASHING aFlash ) const
1973{
1974 int width = GetWidth();
1975
1976 if( IsSolderMaskLayer( aLayer ) )
1977 width += 2 * GetSolderMaskExpansion();
1978
1979 return std::make_shared<SHAPE_ARC>( GetStart(), GetMid(), GetEnd(), width );
1980}
1981
1982
1984 int aClearance, int aError, ERROR_LOC aErrorLoc,
1985 bool ignoreLineWidth ) const
1986{
1987 wxASSERT_MSG( !ignoreLineWidth, wxT( "IgnoreLineWidth has no meaning for tracks." ) );
1988
1989
1990 switch( Type() )
1991 {
1992 case PCB_VIA_T:
1993 {
1994 int radius = ( static_cast<const PCB_VIA*>( this )->GetWidth( aLayer ) / 2 ) + aClearance;
1995 TransformCircleToPolygon( aBuffer, m_Start, radius, aError, aErrorLoc );
1996 break;
1997 }
1998
1999 case PCB_ARC_T:
2000 {
2001 const PCB_ARC* arc = static_cast<const PCB_ARC*>( this );
2002 int width = m_width + ( 2 * aClearance );
2003
2004 if( IsSolderMaskLayer( aLayer ) )
2005 width += 2 * GetSolderMaskExpansion();
2006
2007 TransformArcToPolygon( aBuffer, arc->GetStart(), arc->GetMid(), arc->GetEnd(), width,
2008 aError, aErrorLoc );
2009 break;
2010 }
2011
2012 default:
2013 {
2014 int width = m_width + ( 2 * aClearance );
2015
2016 if( IsSolderMaskLayer( aLayer ) )
2017 width += 2 * GetSolderMaskExpansion();
2018
2019 TransformOvalToPolygon( aBuffer, m_Start, m_End, width, aError, aErrorLoc );
2020
2021 break;
2022 }
2023 }
2024}
2025
2026
2027static struct TRACK_VIA_DESC
2028{
2030 {
2032 .Undefined( VIATYPE::NOT_DEFINED )
2033 .Map( VIATYPE::THROUGH, _HKI( "Through" ) )
2034 .Map( VIATYPE::BLIND_BURIED, _HKI( "Blind/buried" ) )
2035 .Map( VIATYPE::MICROVIA, _HKI( "Micro" ) );
2036
2038 .Undefined( TENTING_MODE::FROM_RULES )
2039 .Map( TENTING_MODE::FROM_RULES, _HKI( "From design rules" ) )
2040 .Map( TENTING_MODE::TENTED, _HKI( "Tented" ) )
2041 .Map( TENTING_MODE::NOT_TENTED, _HKI( "Not tented" ) );
2042
2044
2045 if( layerEnum.Choices().GetCount() == 0 )
2046 {
2047 layerEnum.Undefined( UNDEFINED_LAYER );
2048
2049 for( PCB_LAYER_ID layer : LSET::AllLayersMask().Seq() )
2050 layerEnum.Map( layer, LSET::Name( layer ) );
2051 }
2052
2054
2055 // Track
2058
2059 propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "Width" ),
2060 &PCB_TRACK::SetWidth, &PCB_TRACK::GetWidth, PROPERTY_DISPLAY::PT_SIZE ) );
2061 propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Position X" ),
2062 new PROPERTY<PCB_TRACK, int>( _HKI( "Start X" ),
2063 &PCB_TRACK::SetStartX, &PCB_TRACK::GetStartX, PROPERTY_DISPLAY::PT_COORD,
2065 propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Position Y" ),
2066 new PROPERTY<PCB_TRACK, int>( _HKI( "Start Y" ),
2067 &PCB_TRACK::SetStartY, &PCB_TRACK::GetStartY, PROPERTY_DISPLAY::PT_COORD,
2069 propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "End X" ),
2070 &PCB_TRACK::SetEndX, &PCB_TRACK::GetEndX, PROPERTY_DISPLAY::PT_COORD,
2072 propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "End Y" ),
2073 &PCB_TRACK::SetEndY, &PCB_TRACK::GetEndY, PROPERTY_DISPLAY::PT_COORD,
2075
2076 const wxString groupTechLayers = _HKI( "Technical Layers" );
2077
2078 auto isExternalLayerTrack =
2079 []( INSPECTABLE* aItem )
2080 {
2081 if( auto track = dynamic_cast<PCB_TRACK*>( aItem ) )
2082 return track->GetLayer() == F_Cu || track->GetLayer() == B_Cu;
2083
2084 return false;
2085 };
2086
2087 propMgr.AddProperty( new PROPERTY<PCB_TRACK, bool>( _HKI( "Soldermask" ),
2089 .SetAvailableFunc( isExternalLayerTrack );
2090 propMgr.AddProperty( new PROPERTY<PCB_TRACK, std::optional<int>>( _HKI( "Soldermask Margin Override" ),
2092 PROPERTY_DISPLAY::PT_SIZE ), groupTechLayers )
2093 .SetAvailableFunc( isExternalLayerTrack );
2094
2095 // Arc
2098
2099 // Via
2102
2103 // TODO test drill, use getdrillvalue?
2104 const wxString groupVia = _HKI( "Via Properties" );
2105
2106 propMgr.Mask( TYPE_HASH( PCB_VIA ), TYPE_HASH( BOARD_CONNECTED_ITEM ), _HKI( "Layer" ) );
2107
2108 propMgr.AddProperty( new PROPERTY<PCB_VIA, int>( _HKI( "Diameter" ),
2109 &PCB_VIA::SetFrontWidth, &PCB_VIA::GetFrontWidth, PROPERTY_DISPLAY::PT_SIZE ), groupVia );
2110 propMgr.AddProperty( new PROPERTY<PCB_VIA, int>( _HKI( "Hole" ),
2111 &PCB_VIA::SetDrill, &PCB_VIA::GetDrillValue, PROPERTY_DISPLAY::PT_SIZE ), groupVia );
2112 propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, PCB_LAYER_ID>( _HKI( "Layer Top" ),
2113 &PCB_VIA::SetLayer, &PCB_VIA::GetLayer ), groupVia );
2114 propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, PCB_LAYER_ID>( _HKI( "Layer Bottom" ),
2116 propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, VIATYPE>( _HKI( "Via Type" ),
2118 propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, TENTING_MODE>( _HKI( "Front tenting" ),
2120 propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, TENTING_MODE>( _HKI( "Back tenting" ),
2122 }
2124
ERROR_LOC
When approximating an arc or circle, should the error be placed on the outside or inside of the curve...
Definition: approximation.h:32
constexpr EDA_IU_SCALE pcbIUScale
Definition: base_units.h:108
BITMAPS
A list of all bitmap identifiers.
Definition: bitmaps_list.h:33
ZONE_LAYER_OVERRIDE
Conditionally flashed vias and pads that interact with zones of different priority can be very squirr...
Definition: board_item.h:66
@ ZLO_NONE
Definition: board_item.h:67
@ ZLO_FORCE_FLASHED
Definition: board_item.h:68
constexpr BOX2I BOX2ISafe(const BOX2D &aInput)
Definition: box2.h:929
BASE_SET & reset(size_t pos)
Definition: base_set.h:142
BASE_SET & set(size_t pos)
Definition: base_set.h:115
A base class derived from BOARD_ITEM for items that can be connected and have a net,...
wxString GetNetnameMsg() const
virtual NETCLASS * GetEffectiveNetClass() const
Return the NETCLASS for this item.
bool SetNetCode(int aNetCode, bool aNoAssert)
Set net using a net code.
const wxString & GetDisplayNetname() const
virtual int GetOwnClearance(PCB_LAYER_ID aLayer, wxString *aSource=nullptr) const
Return an item's "own" clearance in internal units.
Container for design settings for a BOARD object.
std::shared_ptr< DRC_ENGINE > m_DRCEngine
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition: board_item.h:79
virtual PCB_LAYER_ID GetLayer() const
Return the primary layer this item is on.
Definition: board_item.h:237
virtual void SetLocked(bool aLocked)
Definition: board_item.h:328
PCB_LAYER_ID m_layer
Definition: board_item.h:436
virtual void SetLayer(PCB_LAYER_ID aLayer)
Set the layer this item is on.
Definition: board_item.h:288
virtual const BOARD * GetBoard() const
Return the BOARD in which this BOARD_ITEM resides, or NULL if none.
Definition: board_item.cpp:47
virtual bool IsLocked() const
Definition: board_item.cpp:75
virtual int BoardCopperLayerCount() const
Return the total number of copper layers for the board that this item resides on.
Definition: board_item.cpp:117
virtual wxString layerMaskDescribe() const
Return a string (to be shown to the user) describing a layer mask.
Definition: board_item.cpp:166
wxString GetLayerName() const
Return the name of the PCB layer on which the item resides.
Definition: board_item.cpp:139
Information pertinent to a Pcbnew printed circuit board.
Definition: board.h:290
PCB_LAYER_ID FlipLayer(PCB_LAYER_ID aLayer) const
Definition: board.cpp:734
const wxString GetLayerName(PCB_LAYER_ID aLayer) const
Return the name of a aLayer.
Definition: board.cpp:574
std::tuple< int, double, double > GetTrackLength(const PCB_TRACK &aTrack) const
Return data on the length and number of track segments connected to a given track.
Definition: board.cpp:2302
BOARD_DESIGN_SETTINGS & GetDesignSettings() const
Definition: board.cpp:895
std::shared_ptr< CONNECTIVITY_DATA > GetConnectivity() const
Return a list of missing connections between components/tracks.
Definition: board.h:475
constexpr BOX2< Vec > & Inflate(coord_type dx, coord_type dy)
Inflates the rectangle horizontally by dx and vertically by dy.
Definition: box2.h:558
constexpr BOX2< Vec > & Merge(const BOX2< Vec > &aRect)
Modify the position and size of the rectangle in order to contain aRect.
Definition: box2.h:658
bool IntersectsCircle(const Vec &aCenter, const int aRadius) const
Definition: box2.h:504
constexpr coord_type GetLeft() const
Definition: box2.h:228
constexpr bool Contains(const Vec &aPoint) const
Definition: box2.h:168
constexpr coord_type GetRight() const
Definition: box2.h:217
constexpr coord_type GetTop() const
Definition: box2.h:229
constexpr bool Intersects(const BOX2< Vec > &aRect) const
Definition: box2.h:311
constexpr coord_type GetBottom() const
Definition: box2.h:222
wxString GetName() const
Definition: drc_rule.h:160
MINOPTMAX< int > & Value()
Definition: drc_rule.h:153
EDA_ANGLE Normalize()
Definition: eda_angle.h:221
EDA_ANGLE Normalize180()
Definition: eda_angle.h:260
The base class for create windows for drawing purpose.
A base class for most all the KiCad significant classes used in schematics and boards.
Definition: eda_item.h:89
EDA_ITEM & operator=(const EDA_ITEM &aItem)
Assign the members of aItem to another object.
Definition: eda_item.cpp:261
const KIID m_Uuid
Definition: eda_item.h:489
KICAD_T Type() const
Returns the type of object.
Definition: eda_item.h:101
EDA_ITEM_FLAGS m_flags
Definition: eda_item.h:499
ENUM_MAP & Map(T aValue, const wxString &aName)
Definition: property.h:686
static ENUM_MAP< T > & Instance()
Definition: property.h:680
ENUM_MAP & Undefined(T aValue)
Definition: property.h:693
wxPGChoices & Choices()
Definition: property.h:729
Class that other classes need to inherit from, in order to be inspectable.
Definition: inspectable.h:36
Contains methods for drawing PCB-specific items.
Definition: pcb_painter.h:180
virtual PCB_RENDER_SETTINGS * GetSettings() override
Return a pointer to current settings that are going to be used when drawing items.
Definition: pcb_painter.h:185
PCB specific render settings.
Definition: pcb_painter.h:78
PCB_LAYER_ID GetPrimaryHighContrastLayer() const
Return the board layer which is in high-contrast mode.
bool GetHighContrast() const
Hold a (potentially large) number of VIEW_ITEMs and renders them on a graphics device provided by the...
Definition: view.h:68
BOX2D GetViewport() const
Return the current viewport visible area rectangle.
Definition: view.cpp:522
bool IsLayerVisible(int aLayer) const
Return information about visibility of a particular layer.
Definition: view.h:419
PAINTER * GetPainter() const
Return the painter object used by the view for drawing #VIEW_ITEMS.
Definition: view.h:217
Definition: kiid.h:49
std::string AsStdString() const
Definition: kiid.cpp:252
static bool Contains(int aStart_layer, int aEnd_layer, int aTest_layer)
Definition: layer_range.h:130
LSET is a set of PCB_LAYER_IDs.
Definition: lset.h:36
static LSET AllLayersMask()
Definition: lset.cpp:711
void RunOnLayers(const std::function< void(PCB_LAYER_ID)> &aFunction) const
Execute a function on each layer of the LSET.
Definition: lset.h:243
static LSET AllCuMask(int aCuLayerCount=MAX_CU_LAYERS)
Return a mask holding the requested number of Cu PCB_LAYER_IDs.
Definition: lset.cpp:686
static LSET PhysicalLayersMask()
Return a mask holding all layers which are physically realized.
Definition: lset.cpp:766
static LSET FrontTechMask()
Return a mask holding all technical layers (no CU layer) on front side.
Definition: lset.cpp:730
static LSET BackTechMask()
Return a mask holding all technical layers (no CU layer) on back side.
Definition: lset.cpp:718
static wxString Name(PCB_LAYER_ID aLayerId)
Return the fixed name association with aLayerId.
Definition: lset.cpp:193
bool Contains(PCB_LAYER_ID aLayer) const
See if the layer set contains a PCB layer.
Definition: lset.h:62
T Min() const
Definition: minoptmax.h:33
bool HasMin() const
Definition: minoptmax.h:37
A collection of nets and the parameters used to route or test these nets.
Definition: netclass.h:44
int GetViaDrill() const
Definition: netclass.h:128
int GetuViaDrill() const
Definition: netclass.h:144
static const int UNCONNECTED
Constant that holds the "unconnected net" number (typically 0) all items "connected" to this net are ...
Definition: netinfo.h:381
A PADSTACK defines the characteristics of a single or multi-layer pad, in the IPC sense of the word.
Definition: padstack.h:124
bool Deserialize(const google::protobuf::Any &aContainer) override
Deserializes the given protobuf message into this object.
Definition: padstack.cpp:211
MASK_LAYER_PROPS & FrontOuterLayers()
Definition: padstack.h:312
void ForEachUniqueLayer(const std::function< void(PCB_LAYER_ID)> &aMethod) const
Runs the given callable for each active unique copper layer in this padstack, meaning F_Cu for MODE::...
Definition: padstack.cpp:870
void SetUnconnectedLayerMode(UNCONNECTED_LAYER_MODE aMode)
Definition: padstack.h:307
const LSET & LayerSet() const
Definition: padstack.h:274
void SetShape(PAD_SHAPE aShape, PCB_LAYER_ID aLayer)
Definition: padstack.cpp:1034
DRILL_PROPS & Drill()
Definition: padstack.h:300
const VECTOR2I & Size(PCB_LAYER_ID aLayer) const
Definition: padstack.cpp:1049
MASK_LAYER_PROPS & BackOuterLayers()
Definition: padstack.h:315
void Serialize(google::protobuf::Any &aContainer) const override
Serializes this object to the given Any message.
Definition: padstack.cpp:422
void SetSize(const VECTOR2I &aSize, PCB_LAYER_ID aLayer)
Definition: padstack.cpp:1040
static constexpr PCB_LAYER_ID ALL_LAYERS
! Temporary layer identifier to identify code that is not padstack-aware
Definition: padstack.h:144
virtual VECTOR2I GetPosition() const override
Definition: pcb_track.cpp:1857
bool IsDegenerated(int aThreshold=5) const
Definition: pcb_track.cpp:1899
virtual void swapData(BOARD_ITEM *aImage) override
Definition: pcb_track.cpp:1842
bool IsCCW() const
Definition: pcb_track.cpp:802
void Serialize(google::protobuf::Any &aContainer) const override
Serializes this object to the given Any message.
Definition: pcb_track.cpp:420
EDA_ITEM * Clone() const override
Create a duplicate of this item with linked list members set to NULL.
Definition: pcb_track.cpp:83
void Flip(const VECTOR2I &aCentre, FLIP_DIRECTION aFlipDirection) override
Flip this object, i.e.
Definition: pcb_track.cpp:783
EDA_ANGLE GetArcAngleStart() const
Definition: pcb_track.cpp:1881
void Mirror(const VECTOR2I &aCentre, FLIP_DIRECTION aFlipDirection) override
Mirror this object relative to a given horizontal axis the layer is not changed.
Definition: pcb_track.cpp:758
virtual bool HitTest(const VECTOR2I &aPosition, int aAccuracy=0) const override
Test if aPosition is inside or on the boundary of this item.
Definition: pcb_track.cpp:1705
EDA_ANGLE GetArcAngleEnd() const
Definition: pcb_track.cpp:1891
bool Deserialize(const google::protobuf::Any &aContainer) override
Deserializes the given protobuf message into this object.
Definition: pcb_track.cpp:443
void SetMid(const VECTOR2I &aMid)
Definition: pcb_track.h:304
double GetRadius() const
Definition: pcb_track.cpp:1864
EDA_ANGLE GetAngle() const
Definition: pcb_track.cpp:1871
const VECTOR2I & GetMid() const
Definition: pcb_track.h:305
PCB_ARC(BOARD_ITEM *aParent)
Definition: pcb_track.h:280
double Similarity(const BOARD_ITEM &aOther) const override
Return a measure of how likely the other object is to represent the same object.
Definition: pcb_track.cpp:253
VECTOR2I m_Mid
Arc mid point, halfway between start and end.
Definition: pcb_track.h:369
void Rotate(const VECTOR2I &aRotCentre, const EDA_ANGLE &aAngle) override
Rotate this object.
Definition: pcb_track.cpp:743
std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const override
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
Definition: pcb_track.cpp:1972
bool operator==(const PCB_ARC &aOther) const
Definition: pcb_track.cpp:241
virtual LSET GetLayerSet() const override
Return a std::bitset of all layers on which the item physically resides.
Definition: pcb_track.cpp:1046
virtual void SetLayerSet(const LSET &aLayers) override
Definition: pcb_track.cpp:1033
int GetSolderMaskExpansion() const
Definition: pcb_track.cpp:937
void Rotate(const VECTOR2I &aRotCentre, const EDA_ANGLE &aAngle) override
Rotate this object.
Definition: pcb_track.cpp:736
void Serialize(google::protobuf::Any &aContainer) const override
Serializes this object to the given Any message.
Definition: pcb_track.cpp:379
void SetEndY(int aY)
Definition: pcb_track.h:131
double ViewGetLOD(int aLayer, KIGFX::VIEW *aView) const override
Return the level of detail (LOD) of the item.
Definition: pcb_track.cpp:1348
void SetHasSolderMask(bool aVal)
Definition: pcb_track.h:145
virtual double GetLength() const
Get the length of the track using the hypotenuse calculation.
Definition: pcb_track.cpp:730
virtual void swapData(BOARD_ITEM *aImage) override
Definition: pcb_track.cpp:1835
void SetEnd(const VECTOR2I &aEnd)
Definition: pcb_track.h:118
bool HasSolderMask() const
Definition: pcb_track.h:146
void SetStart(const VECTOR2I &aStart)
Definition: pcb_track.h:121
const BOX2I ViewBBox() const override
Return the bounding box of the item covering all its layers.
Definition: pcb_track.cpp:1409
int GetStartY() const
Definition: pcb_track.h:128
int GetEndX() const
Definition: pcb_track.h:133
wxString GetItemDescription(UNITS_PROVIDER *aUnitsProvider, bool aFull) const override
Return a user-visible description string of this item.
Definition: pcb_track.cpp:1820
virtual void Mirror(const VECTOR2I &aCentre, FLIP_DIRECTION aFlipDirection) override
Mirror this object relative to a given horizontal axis the layer is not changed.
Definition: pcb_track.cpp:751
bool Deserialize(const google::protobuf::Any &aContainer) override
Deserializes the given protobuf message into this object.
Definition: pcb_track.cpp:400
INSPECT_RESULT Visit(INSPECTOR inspector, void *testData, const std::vector< KICAD_T > &aScanTypes) override
May be re-implemented for each derived class in order to handle all the types given by its member dat...
Definition: pcb_track.cpp:837
bool ApproxCollinear(const PCB_TRACK &aTrack)
Definition: pcb_track.cpp:520
VECTOR2I m_End
Line end point.
Definition: pcb_track.h:267
void SetLocalSolderMaskMargin(std::optional< int > aMargin)
Definition: pcb_track.h:148
std::optional< int > m_solderMaskMargin
Definition: pcb_track.h:270
std::optional< int > GetLocalSolderMaskMargin() const
Definition: pcb_track.h:149
void GetMsgPanelInfo(EDA_DRAW_FRAME *aFrame, std::vector< MSG_PANEL_ITEM > &aList) override
Populate aList of MSG_PANEL_ITEM objects with it's internal state for display purposes.
Definition: pcb_track.cpp:1563
virtual EDA_ITEM * Clone() const override
Create a duplicate of this item with linked list members set to NULL.
Definition: pcb_track.cpp:68
const BOX2I GetBoundingBox() const override
Return the orthogonal bounding box of this object for display purposes.
Definition: pcb_track.cpp:660
void TransformShapeToPolygon(SHAPE_POLY_SET &aBuffer, PCB_LAYER_ID aLayer, int aClearance, int aError, ERROR_LOC aErrorLoc, bool ignoreLineWidth=false) const override
Convert the track shape to a closed polygon.
Definition: pcb_track.cpp:1983
const VECTOR2I & GetStart() const
Definition: pcb_track.h:122
virtual bool operator==(const BOARD_ITEM &aOther) const override
Definition: pcb_track.cpp:166
VECTOR2I m_Start
Line start point.
Definition: pcb_track.h:266
int GetEndY() const
Definition: pcb_track.h:134
wxString GetFriendlyName() const override
Definition: pcb_track.cpp:1551
virtual std::vector< int > ViewGetLayers() const override
Return the all the layers within the VIEW the object is painted on.
Definition: pcb_track.cpp:1326
BITMAPS GetMenuImage() const override
Return a pointer to an image to be used in menus.
Definition: pcb_track.cpp:1830
bool HitTest(const VECTOR2I &aPosition, int aAccuracy=0) const override
Test if aPosition is inside or on the boundary of this item.
Definition: pcb_track.cpp:1699
void Flip(const VECTOR2I &aCentre, FLIP_DIRECTION aFlipDirection) override
Flip this object, i.e.
Definition: pcb_track.cpp:766
virtual double Similarity(const BOARD_ITEM &aOther) const override
Return a measure of how likely the other object is to represent the same object.
Definition: pcb_track.cpp:188
bool m_hasSolderMask
Definition: pcb_track.h:269
std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const override
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
Definition: pcb_track.cpp:1929
void SetStartX(int aX)
Definition: pcb_track.h:124
const VECTOR2I & GetEnd() const
Definition: pcb_track.h:119
PCB_TRACK(BOARD_ITEM *aParent, KICAD_T idtype=PCB_TRACE_T)
Definition: pcb_track.cpp:60
void SetStartY(int aY)
Definition: pcb_track.h:125
bool IsOnLayer(PCB_LAYER_ID aLayer) const override
Test to see if this object is on the given layer.
Definition: pcb_track.cpp:958
virtual MINOPTMAX< int > GetWidthConstraint(wxString *aSource=nullptr) const
Definition: pcb_track.cpp:528
void SetEndX(int aX)
Definition: pcb_track.h:130
int GetStartX() const
Definition: pcb_track.h:127
int m_width
Thickness of track (or arc) – no longer the width of a via.
Definition: pcb_track.h:273
EDA_ITEM_FLAGS IsPointOnEnds(const VECTOR2I &point, int min_dist=0) const
Return STARTPOINT if point if near (dist = min_dist) start point, ENDPOINT if point if near (dist = m...
Definition: pcb_track.cpp:628
virtual void SetWidth(int aWidth)
Definition: pcb_track.h:115
virtual int GetWidth() const
Definition: pcb_track.h:116
void GetMsgPanelInfoBase_Common(EDA_DRAW_FRAME *aFrame, std::vector< MSG_PANEL_ITEM > &aList) const
Definition: pcb_track.cpp:1660
PCB_LAYER_ID BottomLayer() const
Definition: pcb_track.cpp:1189
BITMAPS GetMenuImage() const override
Return a pointer to an image to be used in menus.
Definition: pcb_track.cpp:160
VECTOR2I GetPosition() const override
Definition: pcb_track.h:493
bool IsTented(PCB_LAYER_ID aLayer) const override
Checks if the given object is tented (its copper shape is covered by solder mask) on a given side of ...
Definition: pcb_track.cpp:905
std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const override
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
Definition: pcb_track.cpp:1940
bool Deserialize(const google::protobuf::Any &aContainer) override
Deserializes the given protobuf message into this object.
Definition: pcb_track.cpp:492
bool FlashLayer(int aLayer) const
Check to see whether the via should have a pad on the specific layer.
Definition: pcb_track.cpp:1225
void SetDrillDefault()
Set the drill value for vias to the default value UNDEFINED_DRILL_DIAMETER.
Definition: pcb_track.h:630
std::map< PCB_LAYER_ID, ZONE_LAYER_OVERRIDE > m_zoneLayerOverrides
Definition: pcb_track.h:679
void ClearZoneLayerOverrides()
Definition: pcb_track.cpp:1272
const PADSTACK & Padstack() const
Definition: pcb_track.h:412
void SetFrontTentingMode(TENTING_MODE aMode)
Definition: pcb_track.cpp:859
bool m_isFree
"Free" vias don't get their nets auto-updated
Definition: pcb_track.h:676
bool HitTest(const VECTOR2I &aPosition, int aAccuracy=0) const override
Test if aPosition is inside or on the boundary of this item.
Definition: pcb_track.cpp:1740
TENTING_MODE GetFrontTentingMode() const
Definition: pcb_track.cpp:870
void SetBottomLayer(PCB_LAYER_ID aLayer)
Definition: pcb_track.cpp:1155
int GetSolderMaskExpansion() const
Definition: pcb_track.cpp:928
void SetDrill(int aDrill)
Set the drill value for vias.
Definition: pcb_track.h:608
MINOPTMAX< int > GetDrillConstraint(wxString *aSource=nullptr) const
Definition: pcb_track.cpp:564
void SetBackTentingMode(TENTING_MODE aMode)
Definition: pcb_track.cpp:882
void Flip(const VECTOR2I &aCentre, FLIP_DIRECTION aFlipDirection) override
Flip this object, i.e.
Definition: pcb_track.cpp:812
void GetMsgPanelInfo(EDA_DRAW_FRAME *aFrame, std::vector< MSG_PANEL_ITEM > &aList) override
Populate aList of MSG_PANEL_ITEM objects with it's internal state for display purposes.
Definition: pcb_track.cpp:1623
EDA_ITEM * Clone() const override
Create a duplicate of this item with linked list members set to NULL.
Definition: pcb_track.cpp:139
bool operator==(const PCB_VIA &aOther) const
Definition: pcb_track.cpp:309
PCB_LAYER_ID GetLayer() const override
Return the primary layer this item is on.
Definition: pcb_track.cpp:1021
double ViewGetLOD(int aLayer, KIGFX::VIEW *aView) const override
Return the level of detail (LOD) of the item.
Definition: pcb_track.cpp:1466
std::mutex m_zoneLayerOverridesMutex
Definition: pcb_track.h:678
void SetTopLayer(PCB_LAYER_ID aLayer)
Definition: pcb_track.cpp:1149
std::shared_ptr< SHAPE_SEGMENT > GetEffectiveHoleShape() const override
Definition: pcb_track.cpp:853
int GetFrontWidth() const
Definition: pcb_track.h:426
void SetLayerPair(PCB_LAYER_ID aTopLayer, PCB_LAYER_ID aBottomLayer)
For a via m_layer contains the top layer, the other layer is in m_bottomLayer/.
Definition: pcb_track.cpp:1140
wxString GetItemDescription(UNITS_PROVIDER *aUnitsProvider, bool aFull) const override
Return a user-visible description string of this item.
Definition: pcb_track.cpp:145
double Similarity(const BOARD_ITEM &aOther) const override
Return a measure of how likely the other object is to represent the same object.
Definition: pcb_track.cpp:320
void SetLayer(PCB_LAYER_ID aLayer) override
Set the layer this item is on.
Definition: pcb_track.cpp:1027
virtual void SetLayerSet(const LSET &aLayers) override
Note SetLayerSet() initialize the first and last copper layers connected by the via.
Definition: pcb_track.cpp:1098
void GetOutermostConnectedLayers(PCB_LAYER_ID *aTopmost, PCB_LAYER_ID *aBottommost) const
Return the top-most and bottom-most connected layers.
Definition: pcb_track.cpp:1296
void SanitizeLayers()
Check so that the layers are correct depending on the type of via, and so that the top actually is on...
Definition: pcb_track.cpp:1195
int GetWidth() const override
Definition: pcb_track.cpp:359
PCB_VIA & operator=(const PCB_VIA &aOther)
Definition: pcb_track.cpp:124
void swapData(BOARD_ITEM *aImage) override
Definition: pcb_track.cpp:1849
void Serialize(google::protobuf::Any &aContainer) const override
Serializes this object to the given Any message.
Definition: pcb_track.cpp:464
PCB_VIA(BOARD_ITEM *aParent)
Definition: pcb_track.cpp:89
wxString layerMaskDescribe() const override
Return a string (to be shown to the user) describing a layer mask.
Definition: pcb_track.cpp:1687
std::vector< int > ViewGetLayers() const override
Return the all the layers within the VIEW the object is painted on.
Definition: pcb_track.cpp:1422
void SetViaType(VIATYPE aViaType)
Definition: pcb_track.h:410
int GetMinAnnulus(PCB_LAYER_ID aLayer, wxString *aSource) const
Definition: pcb_track.cpp:582
bool IsOnLayer(PCB_LAYER_ID aLayer) const override
Test to see if this object is on the given layer.
Definition: pcb_track.cpp:976
TENTING_MODE GetBackTentingMode() const
Definition: pcb_track.cpp:893
PCB_LAYER_ID TopLayer() const
Definition: pcb_track.cpp:1183
VIATYPE m_viaType
through, blind/buried or micro
Definition: pcb_track.h:672
PADSTACK m_padStack
Definition: pcb_track.h:674
int GetDrillValue() const
Calculate the drill value for vias (m_drill if > 0, or default drill value for the board).
Definition: pcb_track.cpp:613
void SetZoneLayerOverride(PCB_LAYER_ID aLayer, ZONE_LAYER_OVERRIDE aOverride)
Definition: pcb_track.cpp:1289
void SetFrontWidth(int aWidth)
Definition: pcb_track.h:425
VIATYPE GetViaType() const
Definition: pcb_track.h:409
MINOPTMAX< int > GetWidthConstraint(wxString *aSource=nullptr) const override
Definition: pcb_track.cpp:546
void SetWidth(int aWidth) override
Definition: pcb_track.cpp:351
virtual LSET GetLayerSet() const override
Return a std::bitset of all layers on which the item physically resides.
Definition: pcb_track.cpp:1062
const ZONE_LAYER_OVERRIDE & GetZoneLayerOverride(PCB_LAYER_ID aLayer) const
Definition: pcb_track.cpp:1281
void LayerPair(PCB_LAYER_ID *top_layer, PCB_LAYER_ID *bottom_layer) const
Return the 2 layers used by the via (the via actually uses all layers between these 2 layers)
Definition: pcb_track.cpp:1161
bool HasValidLayerPair(int aCopperLayerCount)
Definition: pcb_track.cpp:999
const BOX2I GetBoundingBox() const override
Return the orthogonal bounding box of this object for display purposes.
Definition: pcb_track.cpp:705
Provide class metadata.Helper macro to map type hashes to names.
Definition: property_mgr.h:85
void InheritsAfter(TYPE_ID aDerived, TYPE_ID aBase)
Declare an inheritance relationship between types.
void Mask(TYPE_ID aDerived, TYPE_ID aBase, const wxString &aName)
Sets a base class property as masked in a derived class.
static PROPERTY_MANAGER & Instance()
Definition: property_mgr.h:87
PROPERTY_BASE & AddProperty(PROPERTY_BASE *aProperty, const wxString &aGroup=wxEmptyString)
Register a property.
PROPERTY_BASE & ReplaceProperty(size_t aBase, const wxString &aName, PROPERTY_BASE *aNew, const wxString &aGroup=wxEmptyString)
Replace an existing property for a specific type.
Definition: seg.h:42
VECTOR2I::extended_type ecoord
Definition: seg.h:44
bool ApproxCollinear(const SEG &aSeg, int aDistanceThreshold=1) const
Definition: seg.cpp:477
const VECTOR2I & GetArcMid() const
Definition: shape_arc.h:116
const VECTOR2I & GetP1() const
Definition: shape_arc.h:115
const VECTOR2I & GetP0() const
Definition: shape_arc.h:114
Represent a set of closed polygons.
wxString MessageTextFromMinOptMax(const MINOPTMAX< int > &aValue) const
wxString MessageTextFromValue(double aValue, bool aAddUnitLabel=true, EDA_DATA_TYPE aType=EDA_DATA_TYPE::DISTANCE) const
A lower-precision version of StringFromValue().
constexpr extended_type Cross(const VECTOR2< T > &aVector) const
Compute cross product of self with aVector.
Definition: vector2d.h:542
double Distance(const VECTOR2< extended_type > &aVector) const
Compute the distance between two vectors.
Definition: vector2d.h:557
T EuclideanNorm() const
Compute the Euclidean norm of the vector, which is defined as sqrt(x ** 2 + y ** 2).
Definition: vector2d.h:283
void TransformCircleToPolygon(SHAPE_LINE_CHAIN &aBuffer, const VECTOR2I &aCenter, int aRadius, int aError, ERROR_LOC aErrorLoc, int aMinSegCount=0)
Convert a circle to a polygon, using multiple straight lines.
void TransformArcToPolygon(SHAPE_POLY_SET &aBuffer, const VECTOR2I &aStart, const VECTOR2I &aMid, const VECTOR2I &aEnd, int aWidth, int aError, ERROR_LOC aErrorLoc)
Convert arc to multiple straight segments.
void TransformOvalToPolygon(SHAPE_POLY_SET &aBuffer, const VECTOR2I &aStart, const VECTOR2I &aEnd, int aWidth, int aError, ERROR_LOC aErrorLoc, int aMinSegCount=0)
Convert a oblong shape to a polygon, using multiple segments.
#define _HKI(x)
@ ANNULAR_WIDTH_CONSTRAINT
Definition: drc_rule.h:61
@ VIA_DIAMETER_CONSTRAINT
Definition: drc_rule.h:67
@ TRACK_WIDTH_CONSTRAINT
Definition: drc_rule.h:59
@ HOLE_SIZE_CONSTRAINT
Definition: drc_rule.h:54
#define _(s)
static constexpr EDA_ANGLE ANGLE_0
Definition: eda_angle.h:401
static constexpr EDA_ANGLE ANGLE_360
Definition: eda_angle.h:407
#define PCB_EDIT_FRAME_NAME
INSPECT_RESULT
Definition: eda_item.h:43
const INSPECTOR_FUNC & INSPECTOR
Definition: eda_item.h:82
#define ENDPOINT
ends. (Used to support dragging.)
std::uint32_t EDA_ITEM_FLAGS
#define STARTPOINT
When a line is selected, these flags indicate which.
static std::vector< KICAD_T > connectedTypes
a few functions useful in geometry calculations.
bool ClipLine(const BOX2I *aClipBox, int &x1, int &y1, int &x2, int &y2)
Test if any part of a line falls within the bounds of a rectangle.
PCB_LAYER_ID FlipLayer(PCB_LAYER_ID aLayerId, int aCopperLayersCount)
Definition: layer_id.cpp:209
bool IsSolderMaskLayer(int aLayer)
Definition: layer_ids.h:612
@ LAYER_VIA_NETNAMES
Definition: layer_ids.h:168
bool IsCopperLayerLowerThan(PCB_LAYER_ID aLayerA, PCB_LAYER_ID aLayerB)
Returns true if copper aLayerA is placed lower than aLayerB, false otherwise.
Definition: layer_ids.h:687
constexpr PCB_LAYER_ID PCBNEW_LAYER_ID_START
Definition: layer_ids.h:138
bool IsFrontLayer(PCB_LAYER_ID aLayerId)
Layer classification: check if it's a front layer.
Definition: layer_ids.h:643
FLASHING
Enum used during connectivity building to ensure we do not query connectivity while building the data...
Definition: layer_ids.h:147
bool IsBackLayer(PCB_LAYER_ID aLayerId)
Layer classification: check if it's a back layer.
Definition: layer_ids.h:666
#define MAX_CU_LAYERS
Definition: layer_ids.h:140
int GetNetnameLayer(int aLayer)
Returns a netname layer corresponding to the given layer.
Definition: layer_ids.h:717
bool IsCopperLayer(int aLayerId)
Tests whether a layer is a copper layer.
Definition: layer_ids.h:542
@ LAYER_LOCKED_ITEM_SHADOW
shadow layer for locked items
Definition: layer_ids.h:241
@ LAYER_VIA_HOLEWALLS
Definition: layer_ids.h:236
@ LAYER_VIA_COPPER_START
Virtual layers for via copper on a given copper layer.
Definition: layer_ids.h:266
@ LAYER_TRACKS
Definition: layer_ids.h:214
@ LAYER_VIA_HOLES
to draw via holes (pad holes do not use this layer)
Definition: layer_ids.h:217
@ LAYER_VIAS
Meta control for all vias opacity/visibility.
Definition: layer_ids.h:195
bool IsNetnameLayer(int aLayer)
Test whether a layer is a netname layer.
Definition: layer_ids.h:732
bool IsHoleLayer(int aLayer)
Definition: layer_ids.h:603
PCB_LAYER_ID
A quick note on layer IDs:
Definition: layer_ids.h:60
@ B_Mask
Definition: layer_ids.h:98
@ B_Cu
Definition: layer_ids.h:65
@ F_Mask
Definition: layer_ids.h:97
@ UNDEFINED_LAYER
Definition: layer_ids.h:61
@ F_Cu
Definition: layer_ids.h:64
PCB_LAYER_ID ToLAYER_ID(int aLayer)
Definition: lset.cpp:820
constexpr void MIRROR(T &aPoint, const T &aMirrorRef)
Updates aPoint with the mirror of aPoint relative to the aMirrorRef.
Definition: mirror.h:45
FLIP_DIRECTION
Definition: mirror.h:27
void PackLayerSet(google::protobuf::RepeatedField< int > &aOutput, const LSET &aLayerSet)
EDA_ANGLE abs(const EDA_ANGLE &aAngle)
Definition: eda_angle.h:390
static struct TRACK_VIA_DESC _TRACK_VIA_DESC
VIATYPE
Definition: pcb_track.h:66
TENTING_MODE
Definition: pcb_track.h:75
#define TYPE_HASH(x)
Definition: property.h:71
#define ENUM_TO_WXANY(type)
Macro to define read-only fields (no setter method available)
Definition: property.h:782
#define REGISTER_TYPE(x)
Definition: property_mgr.h:371
wxString UnescapeString(const wxString &aSource)
constexpr int mmToIU(double mm) const
Definition: base_units.h:88
PCB_LAYER_ID start
Definition: padstack.h:242
PCB_LAYER_ID end
Definition: padstack.h:243
VECTOR2I size
Drill diameter (x == y) or slot dimensions (x != y)
Definition: padstack.h:240
std::optional< bool > has_solder_mask
True if this outer layer has mask (is not tented)
Definition: padstack.h:231
bool operator()(const PCB_TRACK *aFirst, const PCB_TRACK *aSecond) const
Definition: pcb_track.cpp:1911
bool TestSegmentHit(const VECTOR2I &aRefPoint, const VECTOR2I &aStart, const VECTOR2I &aEnd, int aDist)
Test if aRefPoint is with aDistance on the line defined by aStart and aEnd.
Definition: trigo.cpp:175
void RotatePoint(int *pX, int *pY, const EDA_ANGLE &aAngle)
Calculate the new point of coord coord pX, pY, for a rotation center 0, 0.
Definition: trigo.cpp:229
const VECTOR2I CalcArcCenter(const VECTOR2I &aStart, const VECTOR2I &aMid, const VECTOR2I &aEnd)
Determine the center of an arc or circle given three points on its circumference.
Definition: trigo.cpp:521
KICAD_T
The set of class identification values stored in EDA_ITEM::m_structType.
Definition: typeinfo.h:78
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
Definition: typeinfo.h:97
@ PCB_PAD_T
class PAD, a pad in a footprint
Definition: typeinfo.h:87
@ PCB_ARC_T
class PCB_ARC, an arc track segment on a copper layer
Definition: typeinfo.h:98
@ PCB_TRACE_T
class PCB_TRACK, a track segment (segment on a copper layer)
Definition: typeinfo.h:96
VECTOR2< int32_t > VECTOR2I
Definition: vector2d.h:691
VECTOR2< int64_t > VECTOR2L
Definition: vector2d.h:692