KiCad PCB EDA Suite
Loading...
Searching...
No Matches
pcb_track.cpp
Go to the documentation of this file.
1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright (C) 2012 Jean-Pierre Charras, jp.charras at wanadoo.fr
5 * Copyright (C) 2012 SoftPLC Corporation, Dick Hollenbeck <[email protected]>
6 * Copyright (C) 2012 Wayne Stambaugh <[email protected]>
7 * Copyright (C) 1992-2024 KiCad Developers, see AUTHORS.txt for contributors.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, you may find one here:
21 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
22 * or you may search the http://www.gnu.org website for the version 2 license,
23 * or you may write to the Free Software Foundation, Inc.,
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
25 */
26#include <pcb_base_frame.h>
27#include <core/mirror.h>
29#include <board.h>
32#include <pcb_track.h>
33#include <base_units.h>
34#include <lset.h>
35#include <string_utils.h>
36#include <view/view.h>
39#include <geometry/seg.h>
42#include <geometry/shape_arc.h>
43#include <drc/drc_engine.h>
44#include <pcb_painter.h>
45#include <trigo.h>
46
47#include <google/protobuf/any.pb.h>
48#include <api/api_enums.h>
49#include <api/api_utils.h>
50#include <api/api_pcb_utils.h>
51#include <api/board/board_types.pb.h>
52
55
57 BOARD_CONNECTED_ITEM( aParent, idtype )
58{
59 m_Width = pcbIUScale.mmToIU( 0.2 ); // Gives a reasonable default width
60}
61
62
64{
65 return new PCB_TRACK( *this );
66}
67
68
69PCB_ARC::PCB_ARC( BOARD_ITEM* aParent, const SHAPE_ARC* aArc ) :
70 PCB_TRACK( aParent, PCB_ARC_T )
71{
72 m_Start = aArc->GetP0();
73 m_End = aArc->GetP1();
74 m_Mid = aArc->GetArcMid();
75}
76
77
79{
80 return new PCB_ARC( *this );
81}
82
83
85 PCB_TRACK( aParent, PCB_VIA_T ),
86 m_padStack( this )
87{
88 SetViaType( VIATYPE::THROUGH );
90 Padstack().Drill().end = B_Cu;
92
94
95 // Until vias support custom padstack; their layer set should always be cleared
97
98 // For now, vias are always circles
99 m_padStack.SetShape( PAD_SHAPE::CIRCLE );
100
102
103 m_isFree = false;
104}
105
106
107PCB_VIA::PCB_VIA( const PCB_VIA& aOther ) :
108 PCB_TRACK( aOther.GetParent(), PCB_VIA_T ),
109 m_padStack( this )
110{
111 PCB_VIA::operator=( aOther );
112
113 const_cast<KIID&>( m_Uuid ) = aOther.m_Uuid;
115}
116
117
119{
121
122 m_Start = aOther.m_Start;
123 m_End = aOther.m_End;
124
125 m_viaType = aOther.m_viaType;
126 m_padStack = aOther.m_padStack;
127 m_isFree = aOther.m_isFree;
128
129 return *this;
130}
131
132
134{
135 return new PCB_VIA( *this );
136}
137
138
139wxString PCB_VIA::GetItemDescription( UNITS_PROVIDER* aUnitsProvider, bool aFull ) const
140{
141 wxString formatStr;
142
143 switch( GetViaType() )
144 {
145 case VIATYPE::BLIND_BURIED: formatStr = _( "Blind/Buried Via %s on %s" ); break;
146 case VIATYPE::MICROVIA: formatStr = _( "Micro Via %s on %s" ); break;
147 default: formatStr = _( "Via %s on %s" ); break;
148 }
149
150 return wxString::Format( formatStr, GetNetnameMsg(), layerMaskDescribe() );
151}
152
153
155{
156 return BITMAPS::via;
157}
158
159
160bool PCB_TRACK::operator==( const BOARD_ITEM& aBoardItem ) const
161{
162 if( aBoardItem.Type() != Type() )
163 return false;
164
165 const PCB_TRACK& other = static_cast<const PCB_TRACK&>( aBoardItem );
166
167 return *this == other;
168}
169
170
171bool PCB_TRACK::operator==( const PCB_TRACK& aOther ) const
172{
173 return m_Start == aOther.m_Start
174 && m_End == aOther.m_End
175 && m_layer == aOther.m_layer
176 && m_Width == aOther.m_Width;
177}
178
179
180double PCB_TRACK::Similarity( const BOARD_ITEM& aOther ) const
181{
182 if( aOther.Type() != Type() )
183 return 0.0;
184
185 const PCB_TRACK& other = static_cast<const PCB_TRACK&>( aOther );
186
187 double similarity = 1.0;
188
189 if( m_layer != other.m_layer )
190 similarity *= 0.9;
191
192 if( m_Width != other.m_Width )
193 similarity *= 0.9;
194
195 if( m_Start != other.m_Start )
196 similarity *= 0.9;
197
198 if( m_End != other.m_End )
199 similarity *= 0.9;
200
201 return similarity;
202}
203
204
205bool PCB_ARC::operator==( const BOARD_ITEM& aBoardItem ) const
206{
207 if( aBoardItem.Type() != Type() )
208 return false;
209
210 const PCB_ARC& other = static_cast<const PCB_ARC&>( aBoardItem );
211
212 return *this == other;
213}
214
215
216bool PCB_ARC::operator==( const PCB_ARC& aOther ) const
217{
218 return m_Start == aOther.m_Start
219 && m_End == aOther.m_End
220 && m_Mid == aOther.m_Mid
221 && m_layer == aOther.m_layer
222 && m_Width == aOther.m_Width;
223}
224
225
226double PCB_ARC::Similarity( const BOARD_ITEM& aOther ) const
227{
228 if( aOther.Type() != Type() )
229 return 0.0;
230
231 const PCB_ARC& other = static_cast<const PCB_ARC&>( aOther );
232
233 double similarity = 1.0;
234
235 if( m_layer != other.m_layer )
236 similarity *= 0.9;
237
238 if( m_Width != other.m_Width )
239 similarity *= 0.9;
240
241 if( m_Start != other.m_Start )
242 similarity *= 0.9;
243
244 if( m_End != other.m_End )
245 similarity *= 0.9;
246
247 if( m_Mid != other.m_Mid )
248 similarity *= 0.9;
249
250 return similarity;
251}
252
253
254bool PCB_VIA::operator==( const BOARD_ITEM& aBoardItem ) const
255{
256 if( aBoardItem.Type() != Type() )
257 return false;
258
259 const PCB_VIA& other = static_cast<const PCB_VIA&>( aBoardItem );
260
261 return *this == other;
262}
263
264
265bool PCB_VIA::operator==( const PCB_VIA& aOther ) const
266{
267 return m_Start == aOther.m_Start
268 && m_End == aOther.m_End
269 && m_layer == aOther.m_layer
270 && m_padStack == aOther.m_padStack
271 && m_viaType == aOther.m_viaType
273}
274
275
276double PCB_VIA::Similarity( const BOARD_ITEM& aOther ) const
277{
278 if( aOther.Type() != Type() )
279 return 0.0;
280
281 const PCB_VIA& other = static_cast<const PCB_VIA&>( aOther );
282
283 double similarity = 1.0;
284
285 if( m_layer != other.m_layer )
286 similarity *= 0.9;
287
288 if( m_Start != other.m_Start )
289 similarity *= 0.9;
290
291 if( m_End != other.m_End )
292 similarity *= 0.9;
293
294 if( m_padStack != other.m_padStack )
295 similarity *= 0.9;
296
297 if( m_viaType != other.m_viaType )
298 similarity *= 0.9;
299
301 similarity *= 0.9;
302
303 return similarity;
304}
305
306
307void PCB_VIA::SetWidth( int aWidth )
308{
309 m_padStack.Size() = { aWidth, aWidth };
310}
311
312
314{
315 return m_padStack.Size().x;
316}
317
318
319void PCB_TRACK::Serialize( google::protobuf::Any &aContainer ) const
320{
321 kiapi::board::types::Track track;
322
323 track.mutable_id()->set_value( m_Uuid.AsStdString() );
324 track.mutable_start()->set_x_nm( GetStart().x );
325 track.mutable_start()->set_y_nm( GetStart().y );
326 track.mutable_end()->set_x_nm( GetEnd().x );
327 track.mutable_end()->set_y_nm( GetEnd().y );
328 track.mutable_width()->set_value_nm( GetWidth() );
329 track.set_layer( ToProtoEnum<PCB_LAYER_ID, kiapi::board::types::BoardLayer>( GetLayer() ) );
330 track.set_locked( IsLocked() ? kiapi::common::types::LockedState::LS_LOCKED
331 : kiapi::common::types::LockedState::LS_UNLOCKED );
332 track.mutable_net()->mutable_code()->set_value( GetNetCode() );
333 track.mutable_net()->set_name( GetNetname() );
334
335 aContainer.PackFrom( track );
336}
337
338
339bool PCB_TRACK::Deserialize( const google::protobuf::Any &aContainer )
340{
341 kiapi::board::types::Track track;
342
343 if( !aContainer.UnpackTo( &track ) )
344 return false;
345
346 const_cast<KIID&>( m_Uuid ) = KIID( track.id().value() );
347 SetStart( VECTOR2I( track.start().x_nm(), track.start().y_nm() ) );
348 SetEnd( VECTOR2I( track.end().x_nm(), track.end().y_nm() ) );
349 SetWidth( track.width().value_nm() );
350 SetLayer( FromProtoEnum<PCB_LAYER_ID, kiapi::board::types::BoardLayer>( track.layer() ) );
351 SetNetCode( track.net().code().value() );
352 SetLocked( track.locked() == kiapi::common::types::LockedState::LS_LOCKED );
353
354 return true;
355}
356
357
358void PCB_ARC::Serialize( google::protobuf::Any &aContainer ) const
359{
360 kiapi::board::types::Arc arc;
361
362 arc.mutable_id()->set_value( m_Uuid.AsStdString() );
363 arc.mutable_start()->set_x_nm( GetStart().x );
364 arc.mutable_start()->set_y_nm( GetStart().y );
365 arc.mutable_mid()->set_x_nm( GetMid().x );
366 arc.mutable_mid()->set_y_nm( GetMid().y );
367 arc.mutable_end()->set_x_nm( GetEnd().x );
368 arc.mutable_end()->set_y_nm( GetEnd().y );
369 arc.mutable_width()->set_value_nm( GetWidth() );
370 arc.set_layer( ToProtoEnum<PCB_LAYER_ID, kiapi::board::types::BoardLayer>( GetLayer() ) );
371 arc.set_locked( IsLocked() ? kiapi::common::types::LockedState::LS_LOCKED
372 : kiapi::common::types::LockedState::LS_UNLOCKED );
373 arc.mutable_net()->mutable_code()->set_value( GetNetCode() );
374 arc.mutable_net()->set_name( GetNetname() );
375
376 aContainer.PackFrom( arc );
377}
378
379
380bool PCB_ARC::Deserialize( const google::protobuf::Any &aContainer )
381{
382 kiapi::board::types::Arc arc;
383
384 if( !aContainer.UnpackTo( &arc ) )
385 return false;
386
387 const_cast<KIID&>( m_Uuid ) = KIID( arc.id().value() );
388 SetStart( VECTOR2I( arc.start().x_nm(), arc.start().y_nm() ) );
389 SetMid( VECTOR2I( arc.mid().x_nm(), arc.mid().y_nm() ) );
390 SetEnd( VECTOR2I( arc.end().x_nm(), arc.end().y_nm() ) );
391 SetWidth( arc.width().value_nm() );
392 SetLayer( FromProtoEnum<PCB_LAYER_ID, kiapi::board::types::BoardLayer>( arc.layer() ) );
393 SetNetCode( arc.net().code().value() );
394 SetLocked( arc.locked() == kiapi::common::types::LockedState::LS_LOCKED );
395
396 return true;
397}
398
399
400void PCB_VIA::Serialize( google::protobuf::Any &aContainer ) const
401{
402 kiapi::board::types::Via via;
403
404 via.mutable_id()->set_value( m_Uuid.AsStdString() );
405 via.mutable_position()->set_x_nm( GetPosition().x );
406 via.mutable_position()->set_y_nm( GetPosition().y );
407
408 PADSTACK padstack = Padstack();
409
410 google::protobuf::Any padStackWrapper;
411 padstack.Serialize( padStackWrapper );
412 padStackWrapper.UnpackTo( via.mutable_pad_stack() );
413
414
415
416 via.set_type( ToProtoEnum<VIATYPE, kiapi::board::types::ViaType>( GetViaType() ) );
417 via.set_locked( IsLocked() ? kiapi::common::types::LockedState::LS_LOCKED
418 : kiapi::common::types::LockedState::LS_UNLOCKED );
419 via.mutable_net()->mutable_code()->set_value( GetNetCode() );
420 via.mutable_net()->set_name( GetNetname() );
421
422 aContainer.PackFrom( via );
423}
424
425
426bool PCB_VIA::Deserialize( const google::protobuf::Any &aContainer )
427{
428 kiapi::board::types::Via via;
429
430 if( !aContainer.UnpackTo( &via ) )
431 return false;
432
433 const_cast<KIID&>( m_Uuid ) = KIID( via.id().value() );
434 SetStart( VECTOR2I( via.position().x_nm(), via.position().y_nm() ) );
435 SetEnd( GetStart() );
436 SetDrill( via.pad_stack().drill_diameter().x_nm() );
437
438 google::protobuf::Any padStackWrapper;
439 padStackWrapper.PackFrom( via.pad_stack() );
440
441 if( !m_padStack.Deserialize( padStackWrapper ) )
442 return false;
443
444 // We don't yet support complex padstacks for vias
446 SetViaType( FromProtoEnum<VIATYPE>( via.type() ) );
447 SetNetCode( via.net().code().value() );
448 SetLocked( via.locked() == kiapi::common::types::LockedState::LS_LOCKED );
449
450 return true;
451}
452
453
455{
456 SEG a( m_Start, m_End );
457 SEG b( aTrack.GetStart(), aTrack.GetEnd() );
458 return a.ApproxCollinear( b );
459}
460
461
463{
464 DRC_CONSTRAINT constraint;
465
466 if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine )
467 {
469
470 constraint = bds.m_DRCEngine->EvalRules( TRACK_WIDTH_CONSTRAINT, this, nullptr, m_layer );
471 }
472
473 if( aSource )
474 *aSource = constraint.GetName();
475
476 return constraint.Value();
477}
478
479
481{
482 DRC_CONSTRAINT constraint;
483
484 if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine )
485 {
487
488 constraint = bds.m_DRCEngine->EvalRules( VIA_DIAMETER_CONSTRAINT, this, nullptr, m_layer );
489 }
490
491 if( aSource )
492 *aSource = constraint.GetName();
493
494 return constraint.Value();
495}
496
497
499{
500 DRC_CONSTRAINT constraint;
501
502 if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine )
503 {
505
506 constraint = bds.m_DRCEngine->EvalRules( HOLE_SIZE_CONSTRAINT, this, nullptr, m_layer );
507 }
508
509 if( aSource )
510 *aSource = constraint.GetName();
511
512 return constraint.Value();
513}
514
515
516int PCB_VIA::GetMinAnnulus( PCB_LAYER_ID aLayer, wxString* aSource ) const
517{
518 if( !FlashLayer( aLayer ) )
519 {
520 if( aSource )
521 *aSource = _( "removed annular ring" );
522
523 return 0;
524 }
525
526 DRC_CONSTRAINT constraint;
527
528 if( GetBoard() && GetBoard()->GetDesignSettings().m_DRCEngine )
529 {
531
532 constraint = bds.m_DRCEngine->EvalRules( ANNULAR_WIDTH_CONSTRAINT, this, nullptr, aLayer );
533 }
534
535 if( constraint.Value().HasMin() )
536 {
537 if( aSource )
538 *aSource = constraint.GetName();
539
540 return constraint.Value().Min();
541 }
542
543 return 0;
544}
545
546
548{
549 if( m_padStack.Drill().size.x > 0 ) // Use the specific value.
550 return m_padStack.Drill().size.x;
551
552 // Use the default value from the Netclass
553 NETCLASS* netclass = GetEffectiveNetClass();
554
555 if( GetViaType() == VIATYPE::MICROVIA )
556 return netclass->GetuViaDrill();
557
558 return netclass->GetViaDrill();
559}
560
561
562EDA_ITEM_FLAGS PCB_TRACK::IsPointOnEnds( const VECTOR2I& point, int min_dist ) const
563{
564 EDA_ITEM_FLAGS result = 0;
565
566 if( min_dist < 0 )
567 min_dist = m_Width / 2;
568
569 if( min_dist == 0 )
570 {
571 if( m_Start == point )
572 result |= STARTPOINT;
573
574 if( m_End == point )
575 result |= ENDPOINT;
576 }
577 else
578 {
579 double dist = m_Start.Distance( point );
580
581 if( min_dist >= dist )
582 result |= STARTPOINT;
583
584 dist = m_End.Distance( point );
585
586 if( min_dist >= dist )
587 result |= ENDPOINT;
588 }
589
590 return result;
591}
592
593
595{
596 // end of track is round, this is its radius, rounded up
597 int radius = ( m_Width + 1 ) / 2;
598 int ymax, xmax, ymin, xmin;
599
600 if( Type() == PCB_VIA_T )
601 {
602 ymax = m_Start.y;
603 xmax = m_Start.x;
604
605 ymin = m_Start.y;
606 xmin = m_Start.x;
607 }
608 else if( Type() == PCB_ARC_T )
609 {
610 std::shared_ptr<SHAPE> arc = GetEffectiveShape();
611 BOX2I bbox = arc->BBox();
612
613 xmin = bbox.GetLeft();
614 xmax = bbox.GetRight();
615 ymin = bbox.GetTop();
616 ymax = bbox.GetBottom();
617 }
618 else
619 {
620 ymax = std::max( m_Start.y, m_End.y );
621 xmax = std::max( m_Start.x, m_End.x );
622
623 ymin = std::min( m_Start.y, m_End.y );
624 xmin = std::min( m_Start.x, m_End.x );
625 }
626
627 ymax += radius;
628 xmax += radius;
629
630 ymin -= radius;
631 xmin -= radius;
632
633 // return a rectangle which is [pos,dim) in nature. therefore the +1
634 return BOX2ISafe( VECTOR2I( xmin, ymin ),
635 VECTOR2L( (int64_t) xmax - xmin + 1, (int64_t) ymax - ymin + 1 ) );
636}
637
638
640{
641 return m_Start.Distance( m_End );
642}
643
644
645void PCB_TRACK::Rotate( const VECTOR2I& aRotCentre, const EDA_ANGLE& aAngle )
646{
647 RotatePoint( m_Start, aRotCentre, aAngle );
648 RotatePoint( m_End, aRotCentre, aAngle );
649}
650
651
652void PCB_ARC::Rotate( const VECTOR2I& aRotCentre, const EDA_ANGLE& aAngle )
653{
654 RotatePoint( m_Start, aRotCentre, aAngle );
655 RotatePoint( m_End, aRotCentre, aAngle );
656 RotatePoint( m_Mid, aRotCentre, aAngle );
657}
658
659
660void PCB_TRACK::Mirror( const VECTOR2I& aCentre, bool aMirrorAroundXAxis )
661{
662 if( aMirrorAroundXAxis )
663 {
664 MIRROR( m_Start.y, aCentre.y );
665 MIRROR( m_End.y, aCentre.y );
666 }
667 else
668 {
669 MIRROR( m_Start.x, aCentre.x );
670 MIRROR( m_End.x, aCentre.x );
671 }
672}
673
674
675void PCB_ARC::Mirror( const VECTOR2I& aCentre, bool aMirrorAroundXAxis )
676{
677 if( aMirrorAroundXAxis )
678 {
679 MIRROR( m_Start.y, aCentre.y );
680 MIRROR( m_End.y, aCentre.y );
681 MIRROR( m_Mid.y, aCentre.y );
682 }
683 else
684 {
685 MIRROR( m_Start.x, aCentre.x );
686 MIRROR( m_End.x, aCentre.x );
687 MIRROR( m_Mid.x, aCentre.x );
688 }
689}
690
691
692void PCB_TRACK::Flip( const VECTOR2I& aCentre, bool aFlipLeftRight )
693{
694 if( aFlipLeftRight )
695 {
696 m_Start.x = aCentre.x - ( m_Start.x - aCentre.x );
697 m_End.x = aCentre.x - ( m_End.x - aCentre.x );
698 }
699 else
700 {
701 m_Start.y = aCentre.y - ( m_Start.y - aCentre.y );
702 m_End.y = aCentre.y - ( m_End.y - aCentre.y );
703 }
704
706}
707
708
709void PCB_ARC::Flip( const VECTOR2I& aCentre, bool aFlipLeftRight )
710{
711 if( aFlipLeftRight )
712 {
713 m_Start.x = aCentre.x - ( m_Start.x - aCentre.x );
714 m_End.x = aCentre.x - ( m_End.x - aCentre.x );
715 m_Mid.x = aCentre.x - ( m_Mid.x - aCentre.x );
716 }
717 else
718 {
719 m_Start.y = aCentre.y - ( m_Start.y - aCentre.y );
720 m_End.y = aCentre.y - ( m_End.y - aCentre.y );
721 m_Mid.y = aCentre.y - ( m_Mid.y - aCentre.y );
722 }
723
725}
726
727
728bool PCB_ARC::IsCCW() const
729{
730 VECTOR2L start = m_Start;
731 VECTOR2L start_end = m_End - start;
732 VECTOR2L start_mid = m_Mid - start;
733
734 return start_end.Cross( start_mid ) < 0;
735}
736
737
738void PCB_VIA::Flip( const VECTOR2I& aCentre, bool aFlipLeftRight )
739{
740 if( aFlipLeftRight )
741 {
742 m_Start.x = aCentre.x - ( m_Start.x - aCentre.x );
743 m_End.x = aCentre.x - ( m_End.x - aCentre.x );
744 }
745 else
746 {
747 m_Start.y = aCentre.y - ( m_Start.y - aCentre.y );
748 m_End.y = aCentre.y - ( m_End.y - aCentre.y );
749 }
750
751 if( GetViaType() != VIATYPE::THROUGH )
752 {
753 PCB_LAYER_ID top_layer;
754 PCB_LAYER_ID bottom_layer;
755 LayerPair( &top_layer, &bottom_layer );
756 top_layer = GetBoard()->FlipLayer( top_layer );
757 bottom_layer = GetBoard()->FlipLayer( bottom_layer );
758 SetLayerPair( top_layer, bottom_layer );
759 }
760}
761
762
763INSPECT_RESULT PCB_TRACK::Visit( INSPECTOR inspector, void* testData,
764 const std::vector<KICAD_T>& aScanTypes )
765{
766 for( KICAD_T scanType : aScanTypes )
767 {
768 if( scanType == Type() )
769 {
770 if( INSPECT_RESULT::QUIT == inspector( this, testData ) )
771 return INSPECT_RESULT::QUIT;
772 }
773 }
774
775 return INSPECT_RESULT::CONTINUE;
776}
777
778
779std::shared_ptr<SHAPE_SEGMENT> PCB_VIA::GetEffectiveHoleShape() const
780{
781 return std::make_shared<SHAPE_SEGMENT>( SEG( m_Start, m_Start ), Padstack().Drill().size.x );
782}
783
784
786{
787 switch( aMode )
788 {
789 case TENTING_MODE::FROM_RULES: m_padStack.FrontOuterLayers().has_solder_mask.reset(); break;
790 case TENTING_MODE::TENTED: m_padStack.FrontOuterLayers().has_solder_mask = true; break;
791 case TENTING_MODE::NOT_TENTED: m_padStack.FrontOuterLayers().has_solder_mask = false; break;
792 }
793}
794
795
797{
799 {
801 TENTING_MODE::TENTED : TENTING_MODE::NOT_TENTED;
802 }
803
804 return TENTING_MODE::FROM_RULES;
805}
806
807
809{
810 switch( aMode )
811 {
812 case TENTING_MODE::FROM_RULES: m_padStack.BackOuterLayers().has_solder_mask.reset(); break;
813 case TENTING_MODE::TENTED: m_padStack.BackOuterLayers().has_solder_mask = true; break;
814 case TENTING_MODE::NOT_TENTED: m_padStack.BackOuterLayers().has_solder_mask = false; break;
815 }
816}
817
818
820{
821 if( m_padStack.BackOuterLayers().has_solder_mask.has_value() )
822 {
824 TENTING_MODE::TENTED : TENTING_MODE::NOT_TENTED;
825 }
826
827 return TENTING_MODE::FROM_RULES;
828}
829
830
831bool PCB_VIA::IsTented( PCB_LAYER_ID aLayer ) const
832{
833 wxCHECK_MSG( IsFrontLayer( aLayer ) || IsBackLayer( aLayer ), true,
834 "Invalid layer passed to IsTented" );
835
836 bool front = IsFrontLayer( aLayer );
837
838 if( front && m_padStack.FrontOuterLayers().has_solder_mask.has_value() )
840
841 if( !front && m_padStack.BackOuterLayers().has_solder_mask.has_value() )
843
844 if( const BOARD* board = GetBoard() )
845 {
846 return front ? board->GetDesignSettings().m_TentViasFront
847 : board->GetDesignSettings().m_TentViasBack;
848 }
849
850 return true;
851}
852
853
855{
856 if( const BOARD* board = GetBoard() )
857 return board->GetDesignSettings().m_SolderMaskExpansion;
858 else
859 return 0;
860}
861
862
864{
865#if 0
866 // Nice and simple, but raises its ugly head in performance profiles....
867 return GetLayerSet().test( aLayer );
868#endif
869
870 if( aLayer >= Padstack().Drill().start && aLayer <= Padstack().Drill().end )
871 return true;
872
873 if( aLayer == F_Mask )
874 return !IsTented( F_Mask );
875 else if( aLayer == B_Mask )
876 return !IsTented( B_Mask );
877
878 return false;
879}
880
881
883{
884 return Padstack().Drill().start;
885}
886
887
889{
890 Padstack().Drill().start = aLayer;
891}
892
893
895{
896 LSET layermask;
897
898 if( Padstack().Drill().start < PCBNEW_LAYER_ID_START )
899 return layermask;
900
901 if( GetViaType() == VIATYPE::THROUGH )
902 layermask = LSET::AllCuMask();
903 else
904 wxASSERT( Padstack().Drill().start <= Padstack().Drill().end );
905
906 // PCB_LAYER_IDs are numbered from front to back, this is top to bottom.
907 for( int id = Padstack().Drill().start; id <= Padstack().Drill().end; ++id )
908 layermask.set( id );
909
910 if( !IsTented( F_Mask ) && layermask.test( F_Cu ) )
911 layermask.set( F_Mask );
912
913 if( !IsTented( B_Mask ) && layermask.test( B_Cu ) )
914 layermask.set( B_Mask );
915
916 return layermask;
917}
918
919
920void PCB_VIA::SetLayerSet( LSET aLayerSet )
921{
922 bool first = true;
923
924 aLayerSet.RunOnLayers(
925 [&]( PCB_LAYER_ID layer )
926 {
927 // m_layer and m_bottomLayer are copper layers, so consider only copper layers
928 if( IsCopperLayer( layer ) )
929 {
930 if( first )
931 {
932 Padstack().Drill().start = layer;
933 first = false;
934 }
935
936 Padstack().Drill().end = layer;
937 }
938 } );
939}
940
941
942void PCB_VIA::SetLayerPair( PCB_LAYER_ID aTopLayer, PCB_LAYER_ID aBottomLayer )
943{
944
945 Padstack().Drill().start = aTopLayer;
946 Padstack().Drill().end = aBottomLayer;
948}
949
950
952{
953 Padstack().Drill().start = aLayer;
954}
955
956
958{
959 Padstack().Drill().end = aLayer;
960}
961
962
963void PCB_VIA::LayerPair( PCB_LAYER_ID* top_layer, PCB_LAYER_ID* bottom_layer ) const
964{
965 PCB_LAYER_ID t_layer = F_Cu;
966 PCB_LAYER_ID b_layer = B_Cu;
967
968 if( GetViaType() != VIATYPE::THROUGH )
969 {
970 b_layer = Padstack().Drill().end;
971 t_layer = Padstack().Drill().start;
972
973 if( b_layer < t_layer )
974 std::swap( b_layer, t_layer );
975 }
976
977 if( top_layer )
978 *top_layer = t_layer;
979
980 if( bottom_layer )
981 *bottom_layer = b_layer;
982}
983
984
986{
987 return Padstack().Drill().start;
988}
989
990
992{
993 return Padstack().Drill().end;
994}
995
996
998{
999 if( GetViaType() == VIATYPE::THROUGH )
1000 {
1001 Padstack().Drill().start = F_Cu;
1002 Padstack().Drill().end = B_Cu;
1003 }
1004
1005 if( Padstack().Drill().end < Padstack().Drill().start )
1006 std::swap( Padstack().Drill().end, Padstack().Drill().start );
1007}
1008
1009
1010bool PCB_VIA::FlashLayer( LSET aLayers ) const
1011{
1012 for( size_t ii = 0; ii < aLayers.size(); ++ii )
1013 {
1014 if( aLayers.test( ii ) )
1015 {
1016 PCB_LAYER_ID layer = PCB_LAYER_ID( ii );
1017
1018 if( FlashLayer( layer ) )
1019 return true;
1020 }
1021 }
1022
1023 return false;
1024}
1025
1026
1027bool PCB_VIA::FlashLayer( int aLayer ) const
1028{
1029 // Return the "normal" shape if the caller doesn't specify a particular layer
1030 if( aLayer == UNDEFINED_LAYER )
1031 return true;
1032
1033 const BOARD* board = GetBoard();
1034
1035 if( !board )
1036 return true;
1037
1038 if( !IsOnLayer( static_cast<PCB_LAYER_ID>( aLayer ) ) )
1039 return false;
1040
1041 if( !IsCopperLayer( aLayer ) )
1042 return true;
1043
1044 switch( Padstack().UnconnectedLayerMode() )
1045 {
1047 return true;
1048
1050 {
1051 if( aLayer == Padstack().Drill().start || aLayer == Padstack().Drill().end )
1052 return true;
1053
1054 // Check for removal below
1055 break;
1056 }
1057
1059 // Check for removal below
1060 break;
1061 }
1062
1063 // Must be static to keep from raising its ugly head in performance profiles
1064 static std::initializer_list<KICAD_T> connectedTypes = { PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T,
1065 PCB_PAD_T };
1066
1067 if( m_zoneLayerOverrides[ aLayer ] == ZLO_FORCE_FLASHED )
1068 return true;
1069 else
1070 return board->GetConnectivity()->IsConnectedOnLayer( this, aLayer, connectedTypes );
1071}
1072
1073
1075 PCB_LAYER_ID* aBottommost ) const
1076{
1077 *aTopmost = UNDEFINED_LAYER;
1078 *aBottommost = UNDEFINED_LAYER;
1079
1080 static std::initializer_list<KICAD_T> connectedTypes = { PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T,
1081 PCB_PAD_T };
1082
1083 for( int layer = TopLayer(); layer <= BottomLayer(); ++layer )
1084 {
1085 bool connected = false;
1086
1087 if( m_zoneLayerOverrides[ layer ] == ZLO_FORCE_FLASHED )
1088 connected = true;
1089 else if( GetBoard()->GetConnectivity()->IsConnectedOnLayer( this, layer, connectedTypes ) )
1090 connected = true;
1091
1092 if( connected )
1093 {
1094 if( *aTopmost == UNDEFINED_LAYER )
1095 *aTopmost = ToLAYER_ID( layer );
1096
1097 *aBottommost = ToLAYER_ID( layer );
1098 }
1099 }
1100
1101}
1102
1103
1104void PCB_TRACK::ViewGetLayers( int aLayers[], int& aCount ) const
1105{
1106 // Show the track and its netname on different layers
1107 aLayers[0] = GetLayer();
1108 aLayers[1] = GetNetnameLayer( aLayers[0] );
1109 aCount = 2;
1110
1111 if( IsLocked() )
1112 aLayers[ aCount++ ] = LAYER_LOCKED_ITEM_SHADOW;
1113}
1114
1115
1116double PCB_TRACK::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
1117{
1118 constexpr double HIDE = std::numeric_limits<double>::max();
1119
1120 PCB_PAINTER* painter = static_cast<PCB_PAINTER*>( aView->GetPainter() );
1121 PCB_RENDER_SETTINGS* renderSettings = painter->GetSettings();
1122
1123 if( !aView->IsLayerVisible( LAYER_TRACKS ) )
1124 return HIDE;
1125
1126 if( IsNetnameLayer( aLayer ) )
1127 {
1129 return HIDE;
1130
1131 // Hide netnames on dimmed tracks
1132 if( renderSettings->GetHighContrast() )
1133 {
1134 if( m_layer != renderSettings->GetPrimaryHighContrastLayer() )
1135 return HIDE;
1136 }
1137
1138 VECTOR2I start( GetStart() );
1139 VECTOR2I end( GetEnd() );
1140
1141 // Calc the approximate size of the netname (assume square chars)
1142 SEG::ecoord nameSize = GetDisplayNetname().size() * GetWidth();
1143
1144 if( VECTOR2I( end - start ).SquaredEuclideanNorm() < nameSize * nameSize )
1145 return HIDE;
1146
1147 BOX2I clipBox = BOX2ISafe( aView->GetViewport() );
1148
1149 ClipLine( &clipBox, start.x, start.y, end.x, end.y );
1150
1151 if( VECTOR2I( end - start ).SquaredEuclideanNorm() == 0 )
1152 return HIDE;
1153
1154 // Netnames will be shown only if zoom is appropriate
1155 return ( double ) pcbIUScale.mmToIU( 4 ) / ( m_Width + 1 );
1156 }
1157
1158 if( aLayer == LAYER_LOCKED_ITEM_SHADOW )
1159 {
1160 // Hide shadow if the main layer is not shown
1161 if( !aView->IsLayerVisible( m_layer ) )
1162 return HIDE;
1163
1164 // Hide shadow on dimmed tracks
1165 if( renderSettings->GetHighContrast() )
1166 {
1167 if( m_layer != renderSettings->GetPrimaryHighContrastLayer() )
1168 return HIDE;
1169 }
1170 }
1171
1172 // Other layers are shown without any conditions
1173 return 0.0;
1174}
1175
1176
1178{
1179 BOX2I bbox = GetBoundingBox();
1180
1181 if( const BOARD* board = GetBoard() )
1182 bbox.Inflate( 2 * board->GetDesignSettings().GetBiggestClearanceValue() );
1183 else
1184 bbox.Inflate( GetWidth() ); // Add a bit extra for safety
1185
1186 return bbox;
1187}
1188
1189
1190void PCB_VIA::ViewGetLayers( int aLayers[], int& aCount ) const
1191{
1192 aLayers[0] = LAYER_VIA_HOLES;
1193 aLayers[1] = LAYER_VIA_HOLEWALLS;
1194 aLayers[2] = LAYER_VIA_NETNAMES;
1195
1196 // Just show it on common via & via holes layers
1197 switch( GetViaType() )
1198 {
1199 case VIATYPE::THROUGH: aLayers[3] = LAYER_VIA_THROUGH; break;
1200 case VIATYPE::BLIND_BURIED: aLayers[3] = LAYER_VIA_BBLIND; break;
1201 case VIATYPE::MICROVIA: aLayers[3] = LAYER_VIA_MICROVIA; break;
1202 default: aLayers[3] = LAYER_GP_OVERLAY; break;
1203 }
1204
1205 aCount = 4;
1206
1207 if( IsLocked() )
1208 aLayers[ aCount++ ] = LAYER_LOCKED_ITEM_SHADOW;
1209
1210 // Vias can also be on a solder mask layer. They are on these layers or not,
1211 // depending on the plot and solder mask options
1212 if( IsOnLayer( F_Mask ) )
1213 aLayers[ aCount++ ] = F_Mask;
1214
1215 if( IsOnLayer( B_Mask ) )
1216 aLayers[ aCount++ ] = B_Mask;
1217}
1218
1219
1220double PCB_VIA::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
1221{
1222 constexpr double HIDE = (double)std::numeric_limits<double>::max();
1223
1224 PCB_PAINTER* painter = static_cast<PCB_PAINTER*>( aView->GetPainter() );
1225 PCB_RENDER_SETTINGS* renderSettings = painter->GetSettings();
1226 LSET visible = LSET::AllLayersMask();
1227
1228 // Meta control for hiding all vias
1229 if( !aView->IsLayerVisible( LAYER_VIAS ) )
1230 return HIDE;
1231
1232 // Handle board visibility
1233 if( const BOARD* board = GetBoard() )
1234 visible = board->GetVisibleLayers() & board->GetEnabledLayers();
1235
1236 int width = GetWidth();
1237
1238 // In high contrast mode don't show vias that don't cross the high-contrast layer
1239 if( renderSettings->GetHighContrast() )
1240 {
1241 PCB_LAYER_ID highContrastLayer = renderSettings->GetPrimaryHighContrastLayer();
1242
1243 if( LSET::FrontTechMask().Contains( highContrastLayer ) )
1244 highContrastLayer = F_Cu;
1245 else if( LSET::BackTechMask().Contains( highContrastLayer ) )
1246 highContrastLayer = B_Cu;
1247
1248 if( !IsCopperLayer( highContrastLayer ) )
1249 return HIDE;
1250
1251 if( GetViaType() != VIATYPE::THROUGH )
1252 {
1253 if( highContrastLayer < Padstack().Drill().start
1254 || highContrastLayer > Padstack().Drill().end )
1255 {
1256 return HIDE;
1257 }
1258 }
1259 }
1260
1261 if( IsHoleLayer( aLayer ) )
1262 {
1263 if( m_viaType == VIATYPE::BLIND_BURIED || m_viaType == VIATYPE::MICROVIA )
1264 {
1265 // Show a blind or micro via's hole if it crosses a visible layer
1266 if( !( visible & GetLayerSet() ).any() )
1267 return HIDE;
1268 }
1269 else
1270 {
1271 // Show a through via's hole if any physical layer is shown
1272 if( !( visible & LSET::PhysicalLayersMask() ).any() )
1273 return HIDE;
1274 }
1275
1276 // The hole won't be visible anyway at this scale
1277 return (double) pcbIUScale.mmToIU( 0.25 ) / GetDrillValue();
1278 }
1279 else if( IsNetnameLayer( aLayer ) )
1280 {
1281 if( renderSettings->GetHighContrast() )
1282 {
1283 // Hide netnames unless via is flashed to a high-contrast layer
1284 if( !FlashLayer( renderSettings->GetPrimaryHighContrastLayer() ) )
1285 return HIDE;
1286 }
1287 else
1288 {
1289 // Hide netnames unless pad is flashed to a visible layer
1290 if( !FlashLayer( visible ) )
1291 return HIDE;
1292 }
1293
1294 // Netnames will be shown only if zoom is appropriate
1295 return width == 0 ? HIDE : ( (double)pcbIUScale.mmToIU( 10 ) / width );
1296 }
1297
1298 if( IsCopperLayer( aLayer ) )
1299 return (double) pcbIUScale.mmToIU( 1 ) / width;
1300 else
1301 return (double) pcbIUScale.mmToIU( 0.6 ) / width;
1302}
1303
1304
1306{
1307 switch( Type() )
1308 {
1309 case PCB_ARC_T: return _( "Track (arc)" );
1310 case PCB_VIA_T: return _( "Via" );
1311 case PCB_TRACE_T:
1312 default: return _( "Track" );
1313 }
1314}
1315
1316
1317void PCB_TRACK::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>& aList )
1318{
1319 wxString msg;
1320 BOARD* board = GetBoard();
1321
1322 aList.emplace_back( _( "Type" ), GetFriendlyName() );
1323
1324 GetMsgPanelInfoBase_Common( aFrame, aList );
1325
1326 aList.emplace_back( _( "Layer" ), layerMaskDescribe() );
1327
1328 aList.emplace_back( _( "Width" ), aFrame->MessageTextFromValue( m_Width ) );
1329
1330 if( Type() == PCB_ARC_T )
1331 {
1332 double radius = static_cast<PCB_ARC*>( this )->GetRadius();
1333 aList.emplace_back( _( "Radius" ), aFrame->MessageTextFromValue( radius ) );
1334 }
1335
1336 aList.emplace_back( _( "Segment Length" ), aFrame->MessageTextFromValue( GetLength() ) );
1337
1338 // Display full track length (in Pcbnew)
1339 if( board && GetNetCode() > 0 )
1340 {
1341 int count;
1342 double trackLen;
1343 double lenPadToDie;
1344
1345 std::tie( count, trackLen, lenPadToDie ) = board->GetTrackLength( *this );
1346
1347 aList.emplace_back( _( "Routed Length" ), aFrame->MessageTextFromValue( trackLen ) );
1348
1349 if( lenPadToDie != 0 )
1350 {
1351 msg = aFrame->MessageTextFromValue( lenPadToDie );
1352 aList.emplace_back( _( "Pad To Die Length" ), msg );
1353
1354 msg = aFrame->MessageTextFromValue( trackLen + lenPadToDie );
1355 aList.emplace_back( _( "Full Length" ), msg );
1356 }
1357 }
1358
1359 wxString source;
1360 int clearance = GetOwnClearance( GetLayer(), &source );
1361
1362 aList.emplace_back( wxString::Format( _( "Min Clearance: %s" ),
1363 aFrame->MessageTextFromValue( clearance ) ),
1364 wxString::Format( _( "(from %s)" ), source ) );
1365
1366 MINOPTMAX<int> constraintValue = GetWidthConstraint( &source );
1367 msg = aFrame->MessageTextFromMinOptMax( constraintValue );
1368
1369 if( !msg.IsEmpty() )
1370 {
1371 aList.emplace_back( wxString::Format( _( "Width Constraints: %s" ), msg ),
1372 wxString::Format( _( "(from %s)" ), source ) );
1373 }
1374}
1375
1376
1377void PCB_VIA::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>& aList )
1378{
1379 wxString msg;
1380
1381 switch( GetViaType() )
1382 {
1383 case VIATYPE::MICROVIA: msg = _( "Micro Via" ); break;
1384 case VIATYPE::BLIND_BURIED: msg = _( "Blind/Buried Via" ); break;
1385 case VIATYPE::THROUGH: msg = _( "Through Via" ); break;
1386 default: msg = _( "Via" ); break;
1387 }
1388
1389 aList.emplace_back( _( "Type" ), msg );
1390
1391 GetMsgPanelInfoBase_Common( aFrame, aList );
1392
1393 aList.emplace_back( _( "Layer" ), layerMaskDescribe() );
1394 aList.emplace_back( _( "Diameter" ), aFrame->MessageTextFromValue( GetWidth() ) );
1395 aList.emplace_back( _( "Hole" ), aFrame->MessageTextFromValue( GetDrillValue() ) );
1396
1397 wxString source;
1398 int clearance = GetOwnClearance( GetLayer(), &source );
1399
1400 aList.emplace_back( wxString::Format( _( "Min Clearance: %s" ),
1401 aFrame->MessageTextFromValue( clearance ) ),
1402 wxString::Format( _( "(from %s)" ), source ) );
1403
1404 int minAnnulus = GetMinAnnulus( GetLayer(), &source );
1405
1406 aList.emplace_back( wxString::Format( _( "Min Annular Width: %s" ),
1407 aFrame->MessageTextFromValue( minAnnulus ) ),
1408 wxString::Format( _( "(from %s)" ), source ) );
1409}
1410
1411
1413 std::vector<MSG_PANEL_ITEM>& aList ) const
1414{
1415 aList.emplace_back( _( "Net" ), UnescapeString( GetNetname() ) );
1416
1417 aList.emplace_back( _( "Resolved Netclass" ),
1418 UnescapeString( GetEffectiveNetClass()->GetName() ) );
1419
1420#if 0 // Enable for debugging
1421 if( GetBoard() )
1422 aList.emplace_back( _( "NetCode" ), wxString::Format( wxT( "%d" ), GetNetCode() ) );
1423
1424 aList.emplace_back( wxT( "Flags" ), wxString::Format( wxT( "0x%08X" ), m_flags ) );
1425
1426 aList.emplace_back( wxT( "Start pos" ), wxString::Format( wxT( "%d %d" ),
1427 m_Start.x,
1428 m_Start.y ) );
1429 aList.emplace_back( wxT( "End pos" ), wxString::Format( wxT( "%d %d" ),
1430 m_End.x,
1431 m_End.y ) );
1432#endif
1433
1434 if( aFrame->GetName() == PCB_EDIT_FRAME_NAME && IsLocked() )
1435 aList.emplace_back( _( "Status" ), _( "Locked" ) );
1436}
1437
1438
1440{
1441 const BOARD* board = GetBoard();
1442 PCB_LAYER_ID top_layer;
1443 PCB_LAYER_ID bottom_layer;
1444
1445 LayerPair( &top_layer, &bottom_layer );
1446
1447 return board->GetLayerName( top_layer ) + wxT( " - " ) + board->GetLayerName( bottom_layer );
1448}
1449
1450
1451bool PCB_TRACK::HitTest( const VECTOR2I& aPosition, int aAccuracy ) const
1452{
1453 return TestSegmentHit( aPosition, m_Start, m_End, aAccuracy + ( m_Width / 2 ) );
1454}
1455
1456
1457bool PCB_ARC::HitTest( const VECTOR2I& aPosition, int aAccuracy ) const
1458{
1459 double max_dist = aAccuracy + ( m_Width / 2.0 );
1460
1461 // Short-circuit common cases where the arc is connected to a track or via at an endpoint
1462 if( GetStart().Distance( aPosition ) <= max_dist || GetEnd().Distance( aPosition ) <= max_dist )
1463 {
1464 return true;
1465 }
1466
1467 VECTOR2L center = GetPosition();
1468 VECTOR2L relpos = aPosition - center;
1469 int64_t dist = relpos.EuclideanNorm();
1470 double radius = GetRadius();
1471
1472 if( std::abs( dist - radius ) > max_dist )
1473 return false;
1474
1475 EDA_ANGLE arc_angle = GetAngle();
1476 EDA_ANGLE arc_angle_start = GetArcAngleStart(); // Always 0.0 ... 360 deg
1477 EDA_ANGLE arc_hittest( relpos );
1478
1479 // Calculate relative angle between the starting point of the arc, and the test point
1480 arc_hittest -= arc_angle_start;
1481
1482 // Normalise arc_hittest between 0 ... 360 deg
1483 arc_hittest.Normalize();
1484
1485 if( arc_angle < ANGLE_0 )
1486 return arc_hittest >= ANGLE_360 + arc_angle;
1487
1488 return arc_hittest <= arc_angle;
1489}
1490
1491
1492bool PCB_VIA::HitTest( const VECTOR2I& aPosition, int aAccuracy ) const
1493{
1494 int max_dist = aAccuracy + ( GetWidth() / 2 );
1495
1496 // rel_pos is aPosition relative to m_Start (or the center of the via)
1497 VECTOR2I rel_pos = aPosition - m_Start;
1498 double dist = (double) rel_pos.x * rel_pos.x + (double) rel_pos.y * rel_pos.y;
1499 return dist <= (double) max_dist * max_dist;
1500}
1501
1502
1503bool PCB_TRACK::HitTest( const BOX2I& aRect, bool aContained, int aAccuracy ) const
1504{
1505 BOX2I arect = aRect;
1506 arect.Inflate( aAccuracy );
1507
1508 if( aContained )
1509 return arect.Contains( GetStart() ) && arect.Contains( GetEnd() );
1510 else
1511 return arect.Intersects( GetStart(), GetEnd() );
1512}
1513
1514
1515bool PCB_ARC::HitTest( const BOX2I& aRect, bool aContained, int aAccuracy ) const
1516{
1517 BOX2I arect = aRect;
1518 arect.Inflate( aAccuracy );
1519
1520 BOX2I box( GetStart() );
1521 box.Merge( GetMid() );
1522 box.Merge( GetEnd() );
1523
1524 box.Inflate( GetWidth() / 2 );
1525
1526 if( aContained )
1527 return arect.Contains( box );
1528 else
1529 return arect.Intersects( box );
1530}
1531
1532
1533bool PCB_VIA::HitTest( const BOX2I& aRect, bool aContained, int aAccuracy ) const
1534{
1535 BOX2I arect = aRect;
1536 arect.Inflate( aAccuracy );
1537
1538 BOX2I box( GetStart() );
1539 box.Inflate( GetWidth() / 2 );
1540
1541 if( aContained )
1542 return arect.Contains( box );
1543 else
1544 return arect.IntersectsCircle( GetStart(), GetWidth() / 2 );
1545}
1546
1547
1548wxString PCB_TRACK::GetItemDescription( UNITS_PROVIDER* aUnitsProvider, bool aFull ) const
1549{
1550 return wxString::Format( Type() == PCB_ARC_T ? _("Track (arc) %s on %s, length %s" )
1551 : _("Track %s on %s, length %s" ),
1552 GetNetnameMsg(),
1553 GetLayerName(),
1554 aUnitsProvider->MessageTextFromValue( GetLength() ) );
1555}
1556
1557
1559{
1560 return BITMAPS::add_tracks;
1561}
1562
1564{
1565 assert( aImage->Type() == PCB_TRACE_T );
1566
1567 std::swap( *((PCB_TRACK*) this), *((PCB_TRACK*) aImage) );
1568}
1569
1571{
1572 assert( aImage->Type() == PCB_ARC_T );
1573
1574 std::swap( *this, *static_cast<PCB_ARC*>( aImage ) );
1575}
1576
1578{
1579 assert( aImage->Type() == PCB_VIA_T );
1580
1581 std::swap( *((PCB_VIA*) this), *((PCB_VIA*) aImage) );
1582}
1583
1584
1586{
1588 return center;
1589}
1590
1591
1593{
1594 auto center = CalcArcCenter( m_Start, m_Mid , m_End );
1595 return center.Distance( m_Start );
1596}
1597
1598
1600{
1601 VECTOR2D center = GetPosition();
1602 EDA_ANGLE angle1 = EDA_ANGLE( m_Mid - center ) - EDA_ANGLE( m_Start - center );
1603 EDA_ANGLE angle2 = EDA_ANGLE( m_End - center ) - EDA_ANGLE( m_Mid - center );
1604
1605 return angle1.Normalize180() + angle2.Normalize180();
1606}
1607
1608
1610{
1611 VECTOR2D pos( GetPosition() );
1612 EDA_ANGLE angleStart( m_Start - pos );
1613
1614 return angleStart.Normalize();
1615}
1616
1617
1618// Note: used in python tests. Ignore CLion's claim that it's unused....
1620{
1621 VECTOR2D pos( GetPosition() );
1622 EDA_ANGLE angleEnd( m_End - pos );
1623
1624 return angleEnd.Normalize();
1625}
1626
1627bool PCB_ARC::IsDegenerated( int aThreshold ) const
1628{
1629 // Too small arcs cannot be really handled: arc center (and arc radius)
1630 // cannot be safely computed if the distance between mid and end points
1631 // is too small (a few internal units)
1632
1633 // len of both segments must be < aThreshold to be a very small degenerated arc
1634 return ( GetMid() - GetStart() ).EuclideanNorm() < aThreshold
1635 && ( GetMid() - GetEnd() ).EuclideanNorm() < aThreshold;
1636}
1637
1638
1640{
1641 if( a->GetNetCode() != b->GetNetCode() )
1642 return a->GetNetCode() < b->GetNetCode();
1643
1644 if( a->GetLayer() != b->GetLayer() )
1645 return a->GetLayer() < b->GetLayer();
1646
1647 if( a->Type() != b->Type() )
1648 return a->Type() < b->Type();
1649
1650 if( a->m_Uuid != b->m_Uuid )
1651 return a->m_Uuid < b->m_Uuid;
1652
1653 return a < b;
1654}
1655
1656
1657std::shared_ptr<SHAPE> PCB_TRACK::GetEffectiveShape( PCB_LAYER_ID aLayer, FLASHING aFlash ) const
1658{
1659 return std::make_shared<SHAPE_SEGMENT>( m_Start, m_End, m_Width );
1660}
1661
1662
1663std::shared_ptr<SHAPE> PCB_VIA::GetEffectiveShape( PCB_LAYER_ID aLayer, FLASHING aFlash ) const
1664{
1665 if( aFlash == FLASHING::ALWAYS_FLASHED
1666 || ( aFlash == FLASHING::DEFAULT && FlashLayer( aLayer ) ) )
1667 {
1668 return std::make_shared<SHAPE_CIRCLE>( m_Start, GetWidth() / 2 );
1669 }
1670 else
1671 {
1672 return std::make_shared<SHAPE_CIRCLE>( m_Start, GetDrillValue() / 2 );
1673 }
1674}
1675
1676
1677std::shared_ptr<SHAPE> PCB_ARC::GetEffectiveShape( PCB_LAYER_ID aLayer, FLASHING aFlash ) const
1678{
1679 return std::make_shared<SHAPE_ARC>( GetStart(), GetMid(), GetEnd(), GetWidth() );
1680}
1681
1682
1684 int aClearance, int aError, ERROR_LOC aErrorLoc,
1685 bool ignoreLineWidth ) const
1686{
1687 wxASSERT_MSG( !ignoreLineWidth, wxT( "IgnoreLineWidth has no meaning for tracks." ) );
1688
1689
1690 switch( Type() )
1691 {
1692 case PCB_VIA_T:
1693 {
1694 int radius = ( static_cast<const PCB_VIA*>( this )->GetWidth() / 2 ) + aClearance;
1695 TransformCircleToPolygon( aBuffer, m_Start, radius, aError, aErrorLoc );
1696 break;
1697 }
1698
1699 case PCB_ARC_T:
1700 {
1701 const PCB_ARC* arc = static_cast<const PCB_ARC*>( this );
1702 int width = m_Width + ( 2 * aClearance );
1703
1704 TransformArcToPolygon( aBuffer, arc->GetStart(), arc->GetMid(), arc->GetEnd(), width,
1705 aError, aErrorLoc );
1706 break;
1707 }
1708
1709 default:
1710 {
1711 int width = m_Width + ( 2 * aClearance );
1712
1713 TransformOvalToPolygon( aBuffer, m_Start, m_End, width, aError, aErrorLoc );
1714 break;
1715 }
1716 }
1717}
1718
1719
1720static struct TRACK_VIA_DESC
1721{
1723 {
1725 .Undefined( VIATYPE::NOT_DEFINED )
1726 .Map( VIATYPE::THROUGH, _HKI( "Through" ) )
1727 .Map( VIATYPE::BLIND_BURIED, _HKI( "Blind/buried" ) )
1728 .Map( VIATYPE::MICROVIA, _HKI( "Micro" ) );
1729
1731 .Undefined( TENTING_MODE::FROM_RULES )
1732 .Map( TENTING_MODE::FROM_RULES, _HKI( "From design rules" ) )
1733 .Map( TENTING_MODE::TENTED, _HKI( "Tented" ) )
1734 .Map( TENTING_MODE::NOT_TENTED, _HKI( "Not tented" ) );
1735
1737
1738 if( layerEnum.Choices().GetCount() == 0 )
1739 {
1740 layerEnum.Undefined( UNDEFINED_LAYER );
1741
1742 for( PCB_LAYER_ID layer : LSET::AllLayersMask().Seq() )
1743 layerEnum.Map( layer, LSET::Name( layer ) );
1744 }
1745
1747
1748 // Track
1751
1752 propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "Width" ),
1753 &PCB_TRACK::SetWidth, &PCB_TRACK::GetWidth, PROPERTY_DISPLAY::PT_SIZE ) );
1754 propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Position X" ),
1756 &PCB_TRACK::SetX, &PCB_TRACK::GetX, PROPERTY_DISPLAY::PT_COORD,
1758 propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Position Y" ),
1760 &PCB_TRACK::SetY, &PCB_TRACK::GetY, PROPERTY_DISPLAY::PT_COORD,
1762 propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "End X" ),
1763 &PCB_TRACK::SetEndX, &PCB_TRACK::GetEndX, PROPERTY_DISPLAY::PT_COORD,
1765 propMgr.AddProperty( new PROPERTY<PCB_TRACK, int>( _HKI( "End Y" ),
1766 &PCB_TRACK::SetEndY, &PCB_TRACK::GetEndY, PROPERTY_DISPLAY::PT_COORD,
1768
1769 // Arc
1772
1773 // Via
1776
1777 // TODO test drill, use getdrillvalue?
1778 const wxString groupVia = _HKI( "Via Properties" );
1779
1780 propMgr.Mask( TYPE_HASH( PCB_VIA ), TYPE_HASH( BOARD_CONNECTED_ITEM ), _HKI( "Layer" ) );
1781
1782 propMgr.AddProperty( new PROPERTY<PCB_VIA, int>( _HKI( "Diameter" ),
1783 &PCB_VIA::SetWidth, &PCB_VIA::GetWidth, PROPERTY_DISPLAY::PT_SIZE ), groupVia );
1784 propMgr.AddProperty( new PROPERTY<PCB_VIA, int>( _HKI( "Hole" ),
1785 &PCB_VIA::SetDrill, &PCB_VIA::GetDrillValue, PROPERTY_DISPLAY::PT_SIZE ), groupVia );
1786 propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, PCB_LAYER_ID>( _HKI( "Layer Top" ),
1787 &PCB_VIA::SetLayer, &PCB_VIA::GetLayer ), groupVia );
1788 propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, PCB_LAYER_ID>( _HKI( "Layer Bottom" ),
1790 propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, VIATYPE>( _HKI( "Via Type" ),
1792 propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, TENTING_MODE>( _HKI( "Front tenting" ),
1794 propMgr.AddProperty( new PROPERTY_ENUM<PCB_VIA, TENTING_MODE>( _HKI( "Back tenting" ),
1796 }
1798
constexpr EDA_IU_SCALE pcbIUScale
Definition: base_units.h:108
BITMAPS
A list of all bitmap identifiers.
Definition: bitmaps_list.h:33
@ ZLO_NONE
Definition: board_item.h:67
@ ZLO_FORCE_FLASHED
Definition: board_item.h:68
BOX2I BOX2ISafe(const BOX2D &aInput)
Definition: box2.h:883
BASE_SET & set(size_t pos=std::numeric_limits< size_t >::max(), bool value=true)
Definition: base_set.h:62
bool test(size_t pos) const
Definition: base_set.h:48
BASE_SET & reset(size_t pos=std::numeric_limits< size_t >::max())
Definition: base_set.h:77
size_t size() const
Definition: base_set.h:109
A base class derived from BOARD_ITEM for items that can be connected and have a net,...
wxString GetNetnameMsg() const
virtual NETCLASS * GetEffectiveNetClass() const
Return the NETCLASS for this item.
bool SetNetCode(int aNetCode, bool aNoAssert)
Set net using a net code.
const wxString & GetDisplayNetname() const
virtual int GetOwnClearance(PCB_LAYER_ID aLayer, wxString *aSource=nullptr) const
Return an item's "own" clearance in internal units.
Container for design settings for a BOARD object.
std::shared_ptr< DRC_ENGINE > m_DRCEngine
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition: board_item.h:79
virtual PCB_LAYER_ID GetLayer() const
Return the primary layer this item is on.
Definition: board_item.h:240
int GetY() const
Definition: board_item.h:103
virtual void SetLocked(bool aLocked)
Definition: board_item.h:316
PCB_LAYER_ID m_layer
Definition: board_item.h:409
int GetX() const
Definition: board_item.h:97
void SetX(int aX)
Definition: board_item.h:119
void SetY(int aY)
Definition: board_item.h:125
virtual void SetLayer(PCB_LAYER_ID aLayer)
Set the layer this item is on.
Definition: board_item.h:276
virtual const BOARD * GetBoard() const
Return the BOARD in which this BOARD_ITEM resides, or NULL if none.
Definition: board_item.cpp:47
virtual bool IsLocked() const
Definition: board_item.cpp:75
virtual wxString layerMaskDescribe() const
Return a string (to be shown to the user) describing a layer mask.
Definition: board_item.cpp:133
wxString GetLayerName() const
Return the name of the PCB layer on which the item resides.
Definition: board_item.cpp:106
Information pertinent to a Pcbnew printed circuit board.
Definition: board.h:289
PCB_LAYER_ID FlipLayer(PCB_LAYER_ID aLayer) const
Definition: board.cpp:728
const wxString GetLayerName(PCB_LAYER_ID aLayer) const
Return the name of a aLayer.
Definition: board.cpp:575
std::tuple< int, double, double > GetTrackLength(const PCB_TRACK &aTrack) const
Return data on the length and number of track segments connected to a given track.
Definition: board.cpp:2279
BOARD_DESIGN_SETTINGS & GetDesignSettings() const
Definition: board.cpp:875
std::shared_ptr< CONNECTIVITY_DATA > GetConnectivity() const
Return a list of missing connections between components/tracks.
Definition: board.h:474
bool Intersects(const BOX2< Vec > &aRect) const
Definition: box2.h:294
coord_type GetTop() const
Definition: box2.h:219
bool IntersectsCircle(const Vec &aCenter, const int aRadius) const
Definition: box2.h:487
bool Contains(const Vec &aPoint) const
Definition: box2.h:158
BOX2< Vec > & Inflate(coord_type dx, coord_type dy)
Inflates the rectangle horizontally by dx and vertically by dy.
Definition: box2.h:541
coord_type GetRight() const
Definition: box2.h:207
coord_type GetLeft() const
Definition: box2.h:218
coord_type GetBottom() const
Definition: box2.h:212
BOX2< Vec > & Merge(const BOX2< Vec > &aRect)
Modify the position and size of the rectangle in order to contain aRect.
Definition: box2.h:623
wxString GetName() const
Definition: drc_rule.h:150
MINOPTMAX< int > & Value()
Definition: drc_rule.h:143
EDA_ANGLE Normalize()
Definition: eda_angle.h:221
EDA_ANGLE Normalize180()
Definition: eda_angle.h:260
The base class for create windows for drawing purpose.
A base class for most all the KiCad significant classes used in schematics and boards.
Definition: eda_item.h:89
EDA_ITEM & operator=(const EDA_ITEM &aItem)
Assign the members of aItem to another object.
Definition: eda_item.cpp:258
const KIID m_Uuid
Definition: eda_item.h:489
KICAD_T Type() const
Returns the type of object.
Definition: eda_item.h:101
EDA_ITEM_FLAGS m_flags
Definition: eda_item.h:499
ENUM_MAP & Map(T aValue, const wxString &aName)
Definition: property.h:669
static ENUM_MAP< T > & Instance()
Definition: property.h:663
ENUM_MAP & Undefined(T aValue)
Definition: property.h:676
wxPGChoices & Choices()
Definition: property.h:712
Contains methods for drawing PCB-specific items.
Definition: pcb_painter.h:175
virtual PCB_RENDER_SETTINGS * GetSettings() override
Return a pointer to current settings that are going to be used when drawing items.
Definition: pcb_painter.h:180
PCB specific render settings.
Definition: pcb_painter.h:78
PCB_LAYER_ID GetPrimaryHighContrastLayer() const
Return the board layer which is in high-contrast mode.
bool GetHighContrast() const
Hold a (potentially large) number of VIEW_ITEMs and renders them on a graphics device provided by the...
Definition: view.h:68
BOX2D GetViewport() const
Return the current viewport visible area rectangle.
Definition: view.cpp:547
bool IsLayerVisible(int aLayer) const
Return information about visibility of a particular layer.
Definition: view.h:418
PAINTER * GetPainter() const
Return the painter object used by the view for drawing #VIEW_ITEMS.
Definition: view.h:221
Definition: kiid.h:49
std::string AsStdString() const
Definition: kiid.cpp:252
LSET is a set of PCB_LAYER_IDs.
Definition: lset.h:35
static LSET AllLayersMask()
Definition: lset.cpp:767
void RunOnLayers(const std::function< void(PCB_LAYER_ID)> &aFunction) const
Execute a function on each layer of the LSET.
Definition: lset.h:252
static LSET AllCuMask(int aCuLayerCount=MAX_CU_LAYERS)
Return a mask holding the requested number of Cu PCB_LAYER_IDs.
Definition: lset.cpp:732
static LSET PhysicalLayersMask()
Return a mask holding all layers which are physically realized.
Definition: lset.cpp:822
static const wxChar * Name(PCB_LAYER_ID aLayerId)
Return the fixed name association with aLayerId.
Definition: lset.cpp:63
static LSET FrontTechMask()
Return a mask holding all technical layers (no CU layer) on front side.
Definition: lset.cpp:786
static LSET BackTechMask()
Return a mask holding all technical layers (no CU layer) on back side.
Definition: lset.cpp:774
T Min() const
Definition: minoptmax.h:33
bool HasMin() const
Definition: minoptmax.h:37
A collection of nets and the parameters used to route or test these nets.
Definition: netclass.h:44
int GetViaDrill() const
Definition: netclass.h:81
int GetuViaDrill() const
Definition: netclass.h:89
static const int UNCONNECTED
Constant that holds the "unconnected net" number (typically 0) all items "connected" to this net are ...
Definition: netinfo.h:381
A PADSTACK defines the characteristics of a single or multi-layer pad, in the IPC sense of the word.
Definition: padstack.h:117
bool Deserialize(const google::protobuf::Any &aContainer) override
Deserializes the given protobuf message into this object.
Definition: padstack.cpp:89
MASK_LAYER_PROPS & FrontOuterLayers()
Definition: padstack.h:278
void SetUnconnectedLayerMode(UNCONNECTED_LAYER_MODE aMode)
Definition: padstack.h:273
const LSET & LayerSet() const
Definition: padstack.h:246
DRILL_PROPS & Drill()
Definition: padstack.h:266
VECTOR2I & Size(PCB_LAYER_ID aLayer=F_Cu)
Definition: padstack.cpp:492
MASK_LAYER_PROPS & BackOuterLayers()
Definition: padstack.h:281
void Serialize(google::protobuf::Any &aContainer) const override
Serializes this object to the given Any message.
Definition: padstack.cpp:294
void SetShape(PAD_SHAPE aShape, PCB_LAYER_ID aLayer=F_Cu)
Definition: padstack.cpp:486
virtual VECTOR2I GetPosition() const override
Definition: pcb_track.cpp:1585
bool IsDegenerated(int aThreshold=5) const
Definition: pcb_track.cpp:1627
virtual void swapData(BOARD_ITEM *aImage) override
Definition: pcb_track.cpp:1570
bool IsCCW() const
Definition: pcb_track.cpp:728
void Serialize(google::protobuf::Any &aContainer) const override
Serializes this object to the given Any message.
Definition: pcb_track.cpp:358
EDA_ITEM * Clone() const override
Create a duplicate of this item with linked list members set to NULL.
Definition: pcb_track.cpp:78
EDA_ANGLE GetArcAngleStart() const
Definition: pcb_track.cpp:1609
virtual bool HitTest(const VECTOR2I &aPosition, int aAccuracy=0) const override
Test if aPosition is inside or on the boundary of this item.
Definition: pcb_track.cpp:1457
EDA_ANGLE GetArcAngleEnd() const
Definition: pcb_track.cpp:1619
bool Deserialize(const google::protobuf::Any &aContainer) override
Deserializes the given protobuf message into this object.
Definition: pcb_track.cpp:380
void SetMid(const VECTOR2I &aMid)
Definition: pcb_track.h:280
double GetRadius() const
Definition: pcb_track.cpp:1592
EDA_ANGLE GetAngle() const
Definition: pcb_track.cpp:1599
const VECTOR2I & GetMid() const
Definition: pcb_track.h:281
PCB_ARC(BOARD_ITEM *aParent)
Definition: pcb_track.h:256
void Flip(const VECTOR2I &aCentre, bool aFlipLeftRight) override
Flip this object, i.e.
Definition: pcb_track.cpp:709
double Similarity(const BOARD_ITEM &aOther) const override
Return a measure of how likely the other object is to represent the same object.
Definition: pcb_track.cpp:226
VECTOR2I m_Mid
Arc mid point, halfway between start and end.
Definition: pcb_track.h:342
void Rotate(const VECTOR2I &aRotCentre, const EDA_ANGLE &aAngle) override
Rotate this object.
Definition: pcb_track.cpp:652
std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const override
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
Definition: pcb_track.cpp:1677
bool operator==(const PCB_ARC &aOther) const
Definition: pcb_track.cpp:216
void Mirror(const VECTOR2I &aCentre, bool aMirrorAroundXAxis) override
Definition: pcb_track.cpp:675
void Rotate(const VECTOR2I &aRotCentre, const EDA_ANGLE &aAngle) override
Rotate this object.
Definition: pcb_track.cpp:645
virtual void ViewGetLayers(int aLayers[], int &aCount) const override
Return the all the layers within the VIEW the object is painted on.
Definition: pcb_track.cpp:1104
void Serialize(google::protobuf::Any &aContainer) const override
Serializes this object to the given Any message.
Definition: pcb_track.cpp:319
void SetEndY(int aY)
Definition: pcb_track.h:125
double ViewGetLOD(int aLayer, KIGFX::VIEW *aView) const override
Return the level of detail (LOD) of the item.
Definition: pcb_track.cpp:1116
virtual double GetLength() const
Get the length of the track using the hypotenuse calculation.
Definition: pcb_track.cpp:639
virtual void swapData(BOARD_ITEM *aImage) override
Definition: pcb_track.cpp:1563
void SetEnd(const VECTOR2I &aEnd)
Definition: pcb_track.h:118
void SetStart(const VECTOR2I &aStart)
Definition: pcb_track.h:121
const BOX2I ViewBBox() const override
Return the bounding box of the item covering all its layers.
Definition: pcb_track.cpp:1177
int GetEndX() const
Definition: pcb_track.h:127
wxString GetItemDescription(UNITS_PROVIDER *aUnitsProvider, bool aFull) const override
Return a user-visible description string of this item.
Definition: pcb_track.cpp:1548
bool Deserialize(const google::protobuf::Any &aContainer) override
Deserializes the given protobuf message into this object.
Definition: pcb_track.cpp:339
INSPECT_RESULT Visit(INSPECTOR inspector, void *testData, const std::vector< KICAD_T > &aScanTypes) override
May be re-implemented for each derived class in order to handle all the types given by its member dat...
Definition: pcb_track.cpp:763
bool ApproxCollinear(const PCB_TRACK &aTrack)
Definition: pcb_track.cpp:454
VECTOR2I m_End
Line end point.
Definition: pcb_track.h:249
void GetMsgPanelInfo(EDA_DRAW_FRAME *aFrame, std::vector< MSG_PANEL_ITEM > &aList) override
Populate aList of MSG_PANEL_ITEM objects with it's internal state for display purposes.
Definition: pcb_track.cpp:1317
virtual EDA_ITEM * Clone() const override
Create a duplicate of this item with linked list members set to NULL.
Definition: pcb_track.cpp:63
const BOX2I GetBoundingBox() const override
Return the orthogonal bounding box of this object for display purposes.
Definition: pcb_track.cpp:594
void TransformShapeToPolygon(SHAPE_POLY_SET &aBuffer, PCB_LAYER_ID aLayer, int aClearance, int aError, ERROR_LOC aErrorLoc, bool ignoreLineWidth=false) const override
Convert the track shape to a closed polygon.
Definition: pcb_track.cpp:1683
const VECTOR2I & GetStart() const
Definition: pcb_track.h:122
virtual bool operator==(const BOARD_ITEM &aOther) const override
Definition: pcb_track.cpp:160
VECTOR2I m_Start
Line start point.
Definition: pcb_track.h:248
int GetEndY() const
Definition: pcb_track.h:128
wxString GetFriendlyName() const override
Definition: pcb_track.cpp:1305
BITMAPS GetMenuImage() const override
Return a pointer to an image to be used in menus.
Definition: pcb_track.cpp:1558
void Flip(const VECTOR2I &aCentre, bool aFlipLeftRight) override
Flip this object, i.e.
Definition: pcb_track.cpp:692
bool HitTest(const VECTOR2I &aPosition, int aAccuracy=0) const override
Test if aPosition is inside or on the boundary of this item.
Definition: pcb_track.cpp:1451
virtual double Similarity(const BOARD_ITEM &aOther) const override
Return a measure of how likely the other object is to represent the same object.
Definition: pcb_track.cpp:180
std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const override
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
Definition: pcb_track.cpp:1657
const VECTOR2I & GetEnd() const
Definition: pcb_track.h:119
PCB_TRACK(BOARD_ITEM *aParent, KICAD_T idtype=PCB_TRACE_T)
Definition: pcb_track.cpp:56
int m_Width
Thickness of track.
Definition: pcb_track.h:247
virtual MINOPTMAX< int > GetWidthConstraint(wxString *aSource=nullptr) const
Definition: pcb_track.cpp:462
void SetEndX(int aX)
Definition: pcb_track.h:124
virtual void Mirror(const VECTOR2I &aCentre, bool aMirrorAroundXAxis)
Definition: pcb_track.cpp:660
EDA_ITEM_FLAGS IsPointOnEnds(const VECTOR2I &point, int min_dist=0) const
Return STARTPOINT if point if near (dist = min_dist) start point, ENDPOINT if point if near (dist = m...
Definition: pcb_track.cpp:562
virtual void SetWidth(int aWidth)
Definition: pcb_track.h:115
virtual int GetWidth() const
Definition: pcb_track.h:116
void GetMsgPanelInfoBase_Common(EDA_DRAW_FRAME *aFrame, std::vector< MSG_PANEL_ITEM > &aList) const
Definition: pcb_track.cpp:1412
PCB_LAYER_ID BottomLayer() const
Definition: pcb_track.cpp:991
BITMAPS GetMenuImage() const override
Return a pointer to an image to be used in menus.
Definition: pcb_track.cpp:154
VECTOR2I GetPosition() const override
Definition: pcb_track.h:452
bool IsTented(PCB_LAYER_ID aLayer) const override
Checks if the given object is tented (its copper shape is covered by solder mask) on a given side of ...
Definition: pcb_track.cpp:831
std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const override
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
Definition: pcb_track.cpp:1663
bool Deserialize(const google::protobuf::Any &aContainer) override
Deserializes the given protobuf message into this object.
Definition: pcb_track.cpp:426
bool FlashLayer(int aLayer) const
Check to see whether the via should have a pad on the specific layer.
Definition: pcb_track.cpp:1027
void SetDrillDefault()
Set the drill value for vias to the default value UNDEFINED_DRILL_DIAMETER.
Definition: pcb_track.h:589
const PADSTACK & Padstack() const
Definition: pcb_track.h:380
void SetFrontTentingMode(TENTING_MODE aMode)
Definition: pcb_track.cpp:785
bool m_isFree
"Free" vias don't get their nets auto-updated
Definition: pcb_track.h:642
bool HitTest(const VECTOR2I &aPosition, int aAccuracy=0) const override
Test if aPosition is inside or on the boundary of this item.
Definition: pcb_track.cpp:1492
TENTING_MODE GetFrontTentingMode() const
Definition: pcb_track.cpp:796
virtual void SetLayerSet(LSET aLayers) override
Note SetLayerSet() initialize the first and last copper layers connected by the via.
Definition: pcb_track.cpp:920
void SetBottomLayer(PCB_LAYER_ID aLayer)
Definition: pcb_track.cpp:957
std::array< ZONE_LAYER_OVERRIDE, MAX_CU_LAYERS > m_zoneLayerOverrides
Definition: pcb_track.h:645
int GetSolderMaskExpansion() const
Definition: pcb_track.cpp:854
void SetDrill(int aDrill)
Set the drill value for vias.
Definition: pcb_track.h:567
MINOPTMAX< int > GetDrillConstraint(wxString *aSource=nullptr) const
Definition: pcb_track.cpp:498
void SetBackTentingMode(TENTING_MODE aMode)
Definition: pcb_track.cpp:808
void GetMsgPanelInfo(EDA_DRAW_FRAME *aFrame, std::vector< MSG_PANEL_ITEM > &aList) override
Populate aList of MSG_PANEL_ITEM objects with it's internal state for display purposes.
Definition: pcb_track.cpp:1377
EDA_ITEM * Clone() const override
Create a duplicate of this item with linked list members set to NULL.
Definition: pcb_track.cpp:133
bool operator==(const PCB_VIA &aOther) const
Definition: pcb_track.cpp:265
PCB_LAYER_ID GetLayer() const override
Return the primary layer this item is on.
Definition: pcb_track.cpp:882
double ViewGetLOD(int aLayer, KIGFX::VIEW *aView) const override
Return the level of detail (LOD) of the item.
Definition: pcb_track.cpp:1220
void SetTopLayer(PCB_LAYER_ID aLayer)
Definition: pcb_track.cpp:951
std::shared_ptr< SHAPE_SEGMENT > GetEffectiveHoleShape() const override
Definition: pcb_track.cpp:779
void SetLayerPair(PCB_LAYER_ID aTopLayer, PCB_LAYER_ID aBottomLayer)
For a via m_layer contains the top layer, the other layer is in m_bottomLayer/.
Definition: pcb_track.cpp:942
wxString GetItemDescription(UNITS_PROVIDER *aUnitsProvider, bool aFull) const override
Return a user-visible description string of this item.
Definition: pcb_track.cpp:139
double Similarity(const BOARD_ITEM &aOther) const override
Return a measure of how likely the other object is to represent the same object.
Definition: pcb_track.cpp:276
void SetLayer(PCB_LAYER_ID aLayer) override
Set the layer this item is on.
Definition: pcb_track.cpp:888
void GetOutermostConnectedLayers(PCB_LAYER_ID *aTopmost, PCB_LAYER_ID *aBottommost) const
Return the top-most and bottom-most connected layers.
Definition: pcb_track.cpp:1074
void ViewGetLayers(int aLayers[], int &aCount) const override
Return the all the layers within the VIEW the object is painted on.
Definition: pcb_track.cpp:1190
void SanitizeLayers()
Check so that the layers are correct depending on the type of via, and so that the top actually is on...
Definition: pcb_track.cpp:997
int GetWidth() const override
Definition: pcb_track.cpp:313
PCB_VIA & operator=(const PCB_VIA &aOther)
Definition: pcb_track.cpp:118
void swapData(BOARD_ITEM *aImage) override
Definition: pcb_track.cpp:1577
void Serialize(google::protobuf::Any &aContainer) const override
Serializes this object to the given Any message.
Definition: pcb_track.cpp:400
PCB_VIA(BOARD_ITEM *aParent)
Definition: pcb_track.cpp:84
wxString layerMaskDescribe() const override
Return a string (to be shown to the user) describing a layer mask.
Definition: pcb_track.cpp:1439
void SetViaType(VIATYPE aViaType)
Definition: pcb_track.h:378
int GetMinAnnulus(PCB_LAYER_ID aLayer, wxString *aSource) const
Definition: pcb_track.cpp:516
bool IsOnLayer(PCB_LAYER_ID aLayer) const override
Test to see if this object is on the given layer.
Definition: pcb_track.cpp:863
TENTING_MODE GetBackTentingMode() const
Definition: pcb_track.cpp:819
PCB_LAYER_ID TopLayer() const
Definition: pcb_track.cpp:985
VIATYPE m_viaType
through, blind/buried or micro
Definition: pcb_track.h:638
PADSTACK m_padStack
Definition: pcb_track.h:640
int GetDrillValue() const
Calculate the drill value for vias (m_drill if > 0, or default drill value for the board).
Definition: pcb_track.cpp:547
VIATYPE GetViaType() const
Definition: pcb_track.h:377
MINOPTMAX< int > GetWidthConstraint(wxString *aSource=nullptr) const override
Definition: pcb_track.cpp:480
void SetWidth(int aWidth) override
Definition: pcb_track.cpp:307
virtual LSET GetLayerSet() const override
Return a std::bitset of all layers on which the item physically resides.
Definition: pcb_track.cpp:894
void LayerPair(PCB_LAYER_ID *top_layer, PCB_LAYER_ID *bottom_layer) const
Return the 2 layers used by the via (the via actually uses all layers between these 2 layers)
Definition: pcb_track.cpp:963
void Flip(const VECTOR2I &aCentre, bool aFlipLeftRight) override
Flip this object, i.e.
Definition: pcb_track.cpp:738
Provide class metadata.Helper macro to map type hashes to names.
Definition: property_mgr.h:85
void InheritsAfter(TYPE_ID aDerived, TYPE_ID aBase)
Declare an inheritance relationship between types.
void Mask(TYPE_ID aDerived, TYPE_ID aBase, const wxString &aName)
Sets a base class property as masked in a derived class.
static PROPERTY_MANAGER & Instance()
Definition: property_mgr.h:87
PROPERTY_BASE & AddProperty(PROPERTY_BASE *aProperty, const wxString &aGroup=wxEmptyString)
Register a property.
PROPERTY_BASE & ReplaceProperty(size_t aBase, const wxString &aName, PROPERTY_BASE *aNew, const wxString &aGroup=wxEmptyString)
Replace an existing property for a specific type.
Definition: seg.h:42
VECTOR2I::extended_type ecoord
Definition: seg.h:44
bool ApproxCollinear(const SEG &aSeg, int aDistanceThreshold=1) const
Definition: seg.cpp:468
const VECTOR2I & GetArcMid() const
Definition: shape_arc.h:115
const VECTOR2I & GetP1() const
Definition: shape_arc.h:114
const VECTOR2I & GetP0() const
Definition: shape_arc.h:113
Represent a set of closed polygons.
wxString MessageTextFromMinOptMax(const MINOPTMAX< int > &aValue) const
wxString MessageTextFromValue(double aValue, bool aAddUnitLabel=true, EDA_DATA_TYPE aType=EDA_DATA_TYPE::DISTANCE) const
A lower-precision version of StringFromValue().
double Distance(const VECTOR2< extended_type > &aVector) const
Compute the distance between two vectors.
Definition: vector2d.h:553
T EuclideanNorm() const
Compute the Euclidean norm of the vector, which is defined as sqrt(x ** 2 + y ** 2).
Definition: vector2d.h:281
extended_type Cross(const VECTOR2< T > &aVector) const
Compute cross product of self with aVector.
Definition: vector2d.h:538
void TransformCircleToPolygon(SHAPE_LINE_CHAIN &aBuffer, const VECTOR2I &aCenter, int aRadius, int aError, ERROR_LOC aErrorLoc, int aMinSegCount=0)
Convert a circle to a polygon, using multiple straight lines.
void TransformArcToPolygon(SHAPE_POLY_SET &aBuffer, const VECTOR2I &aStart, const VECTOR2I &aMid, const VECTOR2I &aEnd, int aWidth, int aError, ERROR_LOC aErrorLoc)
Convert arc to multiple straight segments.
void TransformOvalToPolygon(SHAPE_POLY_SET &aBuffer, const VECTOR2I &aStart, const VECTOR2I &aEnd, int aWidth, int aError, ERROR_LOC aErrorLoc, int aMinSegCount=0)
Convert a oblong shape to a polygon, using multiple segments.
#define _HKI(x)
@ ANNULAR_WIDTH_CONSTRAINT
Definition: drc_rule.h:58
@ VIA_DIAMETER_CONSTRAINT
Definition: drc_rule.h:64
@ TRACK_WIDTH_CONSTRAINT
Definition: drc_rule.h:57
@ HOLE_SIZE_CONSTRAINT
Definition: drc_rule.h:52
#define _(s)
static constexpr EDA_ANGLE ANGLE_0
Definition: eda_angle.h:401
static constexpr EDA_ANGLE ANGLE_360
Definition: eda_angle.h:407
#define PCB_EDIT_FRAME_NAME
INSPECT_RESULT
Definition: eda_item.h:43
const INSPECTOR_FUNC & INSPECTOR
Definition: eda_item.h:82
#define ENDPOINT
ends. (Used to support dragging.)
std::uint32_t EDA_ITEM_FLAGS
#define STARTPOINT
When a line is selected, these flags indicate which.
static std::vector< KICAD_T > connectedTypes
ERROR_LOC
When approximating an arc or circle, should the error be placed on the outside or inside of the curve...
bool ClipLine(const BOX2I *aClipBox, int &x1, int &y1, int &x2, int &y2)
Test if any part of a line falls within the bounds of a rectangle.
PCB_LAYER_ID FlipLayer(PCB_LAYER_ID aLayerId, int aCopperLayersCount)
Definition: layer_id.cpp:202
@ LAYER_VIA_NETNAMES
Definition: layer_ids.h:170
constexpr PCB_LAYER_ID PCBNEW_LAYER_ID_START
Definition: layer_ids.h:140
bool IsFrontLayer(PCB_LAYER_ID aLayerId)
Layer classification: check if it's a front layer.
Definition: layer_ids.h:605
FLASHING
Enum used during connectivity building to ensure we do not query connectivity while building the data...
Definition: layer_ids.h:149
bool IsBackLayer(PCB_LAYER_ID aLayerId)
Layer classification: check if it's a back layer.
Definition: layer_ids.h:628
int GetNetnameLayer(int aLayer)
Returns a netname layer corresponding to the given layer.
Definition: layer_ids.h:661
bool IsCopperLayer(int aLayerId)
Tests whether a layer is a copper layer.
Definition: layer_ids.h:531
@ LAYER_LOCKED_ITEM_SHADOW
shadow layer for locked items
Definition: layer_ids.h:243
@ LAYER_VIA_HOLEWALLS
Definition: layer_ids.h:238
@ LAYER_GP_OVERLAY
general purpose overlay
Definition: layer_ids.h:222
@ LAYER_TRACKS
Definition: layer_ids.h:216
@ LAYER_VIA_HOLES
to draw via holes (pad holes do not use this layer)
Definition: layer_ids.h:219
@ LAYER_VIA_MICROVIA
to draw micro vias
Definition: layer_ids.h:198
@ LAYER_VIA_THROUGH
to draw usual through hole vias
Definition: layer_ids.h:200
@ LAYER_VIAS
Meta control for all vias opacity/visibility.
Definition: layer_ids.h:197
@ LAYER_VIA_BBLIND
to draw blind/buried vias
Definition: layer_ids.h:199
bool IsNetnameLayer(int aLayer)
Test whether a layer is a netname layer.
Definition: layer_ids.h:684
bool IsHoleLayer(int aLayer)
Definition: layer_ids.h:570
PCB_LAYER_ID
A quick note on layer IDs:
Definition: layer_ids.h:60
@ B_Mask
Definition: layer_ids.h:106
@ B_Cu
Definition: layer_ids.h:95
@ F_Mask
Definition: layer_ids.h:107
@ UNDEFINED_LAYER
Definition: layer_ids.h:61
@ F_Cu
Definition: layer_ids.h:64
PCB_LAYER_ID ToLAYER_ID(int aLayer)
Definition: lset.cpp:875
void MIRROR(T &aPoint, const T &aMirrorRef)
Updates aPoint with the mirror of aPoint relative to the aMirrorRef.
Definition: mirror.h:40
EDA_ANGLE abs(const EDA_ANGLE &aAngle)
Definition: eda_angle.h:390
static struct TRACK_VIA_DESC _TRACK_VIA_DESC
VIATYPE
Definition: pcb_track.h:66
TENTING_MODE
Definition: pcb_track.h:75
#define TYPE_HASH(x)
Definition: property.h:71
#define ENUM_TO_WXANY(type)
Macro to define read-only fields (no setter method available)
Definition: property.h:765
#define REGISTER_TYPE(x)
Definition: property_mgr.h:371
wxString UnescapeString(const wxString &aSource)
constexpr int mmToIU(double mm) const
Definition: base_units.h:88
PCB_LAYER_ID start
Definition: padstack.h:228
PCB_LAYER_ID end
Definition: padstack.h:229
VECTOR2I size
Drill diameter (x == y) or slot dimensions (x != y)
Definition: padstack.h:226
std::optional< bool > has_solder_mask
True if this outer layer has mask (is not tented)
Definition: padstack.h:217
bool operator()(const PCB_TRACK *aFirst, const PCB_TRACK *aSecond) const
Definition: pcb_track.cpp:1639
bool TestSegmentHit(const VECTOR2I &aRefPoint, const VECTOR2I &aStart, const VECTOR2I &aEnd, int aDist)
Test if aRefPoint is with aDistance on the line defined by aStart and aEnd.
Definition: trigo.cpp:175
void RotatePoint(int *pX, int *pY, const EDA_ANGLE &aAngle)
Calculate the new point of coord coord pX, pY, for a rotation center 0, 0.
Definition: trigo.cpp:229
const VECTOR2I CalcArcCenter(const VECTOR2I &aStart, const VECTOR2I &aMid, const VECTOR2I &aEnd)
Determine the center of an arc or circle given three points on its circumference.
Definition: trigo.cpp:521
KICAD_T
The set of class identification values stored in EDA_ITEM::m_structType.
Definition: typeinfo.h:78
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
Definition: typeinfo.h:97
@ PCB_PAD_T
class PAD, a pad in a footprint
Definition: typeinfo.h:87
@ PCB_ARC_T
class PCB_ARC, an arc track segment on a copper layer
Definition: typeinfo.h:98
@ PCB_TRACE_T
class PCB_TRACK, a track segment (segment on a copper layer)
Definition: typeinfo.h:96
VECTOR2< int32_t > VECTOR2I
Definition: vector2d.h:676
VECTOR2< int64_t > VECTOR2L
Definition: vector2d.h:677