KiCad PCB EDA Suite
Loading...
Searching...
No Matches
drc_test_provider_disallow.cpp
Go to the documentation of this file.
1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright The KiCad Developers.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, you may find one here:
18 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
19 * or you may search the http://www.gnu.org website for the version 2 license,
20 * or you may write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
22 */
23
24#include <atomic>
25#include <common.h>
27#include <drc/drc_rtree.h>
28#include <drc/drc_engine.h>
29#include <drc/drc_item.h>
30#include <drc/drc_rule.h>
32#include <pad.h>
33#include <progress_reporter.h>
34#include <thread_pool.h>
35#include <zone.h>
36#include <pcb_track.h>
37#include <mutex>
38
39
40/*
41 "Disallow" test. Goes through all items, matching types/conditions drop errors.
42 Errors generated:
43 - DRCE_ALLOWED_ITEMS
44 - DRCE_TEXT_ON_EDGECUTS
45*/
46
48{
49public:
52
53 virtual ~DRC_TEST_PROVIDER_DISALLOW() = default;
54
55 virtual bool Run() override;
56
57 virtual const wxString GetName() const override { return wxT( "disallow" ); };
58};
59
60
62{
63 if( !reportPhase( _( "Checking keepouts & disallow constraints..." ) ) )
64 return false; // DRC cancelled
65
66 BOARD* board = m_drcEngine->GetBoard();
68
69 // First build out the board's cache of copper-keepout to copper-zone caches. This is where
70 // the bulk of the time is spent, and we can do this in parallel.
71 //
72 std::vector<ZONE*> antiCopperKeepouts;
73 std::vector<ZONE*> copperZones;
74 std::vector<std::pair<ZONE*, ZONE*>> toCache;
75 std::atomic<size_t> done( 1 );
76 int totalCount = 0;
77 std::unique_ptr<DRC_RTREE> antiTrackKeepouts = std::make_unique<DRC_RTREE>();
78
80 [&]( BOARD_ITEM* item ) -> bool
81 {
82 ZONE* zone = static_cast<ZONE*>( item );
83
84 if( zone->GetIsRuleArea() && zone->GetDoNotAllowZoneFills() )
85 {
86 antiCopperKeepouts.push_back( zone );
87 }
88 else if( zone->GetIsRuleArea() && zone->GetDoNotAllowTracks() )
89 {
90 for( PCB_LAYER_ID layer : zone->GetLayerSet() )
91 antiTrackKeepouts->Insert( zone, layer );
92 }
93 else if( zone->IsOnCopperLayer() )
94 {
95 copperZones.push_back( zone );
96 }
97
98 totalCount++;
99
100 return true;
101 } );
102
103 antiTrackKeepouts->Build();
104
105 for( ZONE* ruleArea : antiCopperKeepouts )
106 {
107 for( ZONE* copperZone : copperZones )
108 {
109 toCache.push_back( { ruleArea, copperZone } );
110 totalCount++;
111 }
112 }
113
114 auto query_areas =
115 [&]( const int idx ) -> size_t
116 {
117 if( m_drcEngine->IsCancelled() )
118 return 0;
119 const auto& areaZonePair = toCache[idx];
120 ZONE* ruleArea = areaZonePair.first;
121 ZONE* copperZone = areaZonePair.second;
122 BOX2I areaBBox = ruleArea->GetBoundingBox();
123 BOX2I copperBBox = copperZone->GetBoundingBox();
124 bool isInside = false;
125
126 if( copperZone->IsFilled() && areaBBox.Intersects( copperBBox ) )
127 {
128 // Collisions include touching, so we need to deflate outline by enough to
129 // exclude it. This is particularly important for detecting copper fills as
130 // they will be exactly touching along the entire exclusion border.
131 SHAPE_POLY_SET areaPoly = ruleArea->Outline()->CloneDropTriangulation();
132 areaPoly.Fracture();
134
135 DRC_RTREE* zoneRTree = board->m_CopperZoneRTreeCache[ copperZone ].get();
136
137 if( zoneRTree )
138 {
139 for( size_t ii = 0; ii < ruleArea->GetLayerSet().size(); ++ii )
140 {
141 if( ruleArea->GetLayerSet().test( ii ) )
142 {
143 PCB_LAYER_ID layer = PCB_LAYER_ID( ii );
144
145 if( zoneRTree->QueryColliding( areaBBox, &areaPoly, layer ) )
146 {
147 isInside = true;
148 break;
149 }
150
151 if( m_drcEngine->IsCancelled() )
152 return 0;
153 }
154 }
155 }
156 }
157
158 if( m_drcEngine->IsCancelled() )
159 return 0;
160
161 PTR_PTR_LAYER_CACHE_KEY key = { ruleArea, copperZone, UNDEFINED_LAYER };
162
163 {
164 std::unique_lock<std::shared_mutex> writeLock( board->m_CachesMutex );
165 board->m_IntersectsAreaCache[ key ] = isInside;
166 }
167
168 done.fetch_add( 1 );
169
170 return 1;
171 };
172
174 auto futures = tp.submit_loop( 0, toCache.size(), query_areas, toCache.size() );
175
176 for( auto& ret : futures )
177 {
178 std::future_status status = ret.wait_for( std::chrono::milliseconds( 250 ) );
179
180 while( status != std::future_status::ready )
181 {
182 reportProgress( done, toCache.size() );
183 status = ret.wait_for( std::chrono::milliseconds( 250 ) );
184 }
185 }
186
187 if( m_drcEngine->IsCancelled() )
188 return false;
189
190 // Now go through all the board objects calling the DRC_ENGINE to run the actual disallow
191 // tests. These should be reasonably quick using the caches generated above.
192 //
193 // Collect items first, then process in parallel.
194 std::vector<BOARD_ITEM*> allItems;
195
197 [&]( BOARD_ITEM* item ) -> bool
198 {
199 allItems.push_back( item );
200 return true;
201 } );
202
203 std::atomic<size_t> itemsDone( 0 );
204 size_t itemCount = allItems.size();
205
206 auto checkTextOnEdgeCuts =
207 []( BOARD_ITEM* item ) -> bool
208 {
209 if( item->Type() == PCB_FIELD_T
210 || item->Type() == PCB_TEXT_T
211 || item->Type() == PCB_TEXTBOX_T
212 || BaseType( item->Type() ) == PCB_DIMENSION_T )
213 {
214 return item->GetLayer() == Edge_Cuts;
215 }
216
217 return false;
218 };
219
220 auto processItem =
221 [&]( const int idx ) -> size_t
222 {
223 if( m_drcEngine->IsCancelled() )
224 {
225 itemsDone.fetch_add( 1 );
226 return 0;
227 }
228
229 bool testTextOnEdge = !m_drcEngine->IsErrorLimitExceeded( DRCE_TEXT_ON_EDGECUTS );
230 bool testDisallow = !m_drcEngine->IsErrorLimitExceeded( DRCE_ALLOWED_ITEMS );
231
232 if( !testTextOnEdge && !testDisallow )
233 {
234 itemsDone.fetch_add( 1 );
235 return 0;
236 }
237
238 BOARD_ITEM* item = allItems[idx];
239
240 if( testTextOnEdge && checkTextOnEdgeCuts( item ) )
241 {
242 std::shared_ptr<DRC_ITEM> drc = DRC_ITEM::Create( DRCE_TEXT_ON_EDGECUTS );
243 drc->SetItems( item );
245 }
246
247 if( testDisallow )
248 {
249 if( item->Type() == PCB_ZONE_T )
250 {
251 ZONE* zone = static_cast<ZONE*>( item );
252
253 if( zone->GetIsRuleArea() && zone->HasKeepoutParametersSet() )
254 {
255 itemsDone.fetch_add( 1 );
256 return 1;
257 }
258 }
259
260 item->ClearFlags( HOLE_PROXY );
261
262 if( item->Type() == PCB_TRACE_T || item->Type() == PCB_ARC_T )
263 {
264 PCB_TRACK* track = static_cast<PCB_TRACK*>( item );
265 PCB_LAYER_ID layer = track->GetLayer();
266
267 antiTrackKeepouts->QueryColliding( track, layer, layer,
268 [&]( BOARD_ITEM* other ) -> bool
269 {
270 return true;
271 },
272 [&]( BOARD_ITEM* other ) -> bool
273 {
274 std::shared_ptr<SHAPE> shape = track->GetEffectiveShape();
275 int dummyActual;
276 VECTOR2I pos;
277
278 if( static_cast<ZONE*>( other )->Outline()->Collide(
279 shape.get(), board->m_DRCMaxClearance,
280 &dummyActual, &pos ) )
281 {
282 std::shared_ptr<DRC_ITEM> drcItem =
284 drcItem->SetItems( track );
285 reportViolation( drcItem, pos,
286 track->GetLayerSet().ExtractLayer() );
287 }
288
289 return !m_drcEngine->IsCancelled();
290 },
292 }
293
294 DRC_CONSTRAINT constraint = m_drcEngine->EvalRules( DISALLOW_CONSTRAINT,
295 item, nullptr,
297
298 if( constraint.m_DisallowFlags
299 && constraint.GetSeverity() != RPT_SEVERITY_IGNORE )
300 {
301 if( !constraint.GetParentRule()->IsImplicit() )
302 {
303 std::shared_ptr<DRC_ITEM> drcItem =
305 PCB_LAYER_ID layer = item->GetLayerSet().ExtractLayer();
306
307 drcItem->SetErrorDetail(
308 wxString::Format( wxS( "(%s)" ), constraint.GetName() ) );
309 drcItem->SetItems( item );
310 drcItem->SetViolatingRule( constraint.GetParentRule() );
311 reportViolation( drcItem, item->GetPosition(), layer );
312 }
313 }
314
315 // N.B. HOLE_PROXY is set/cleared on the item's flags for
316 // EvalRules to distinguish hole-specific disallow constraints.
317 // This is a non-atomic read-modify-write on m_flags, so this
318 // provider must run with each item processed by only one thread
319 // at a time (guaranteed by submit_loop's work partitioning).
320 if( item->HasHole() )
321 {
322 item->SetFlags( HOLE_PROXY );
323
324 constraint = m_drcEngine->EvalRules( DISALLOW_CONSTRAINT, item,
325 nullptr, UNDEFINED_LAYER );
326
327 if( constraint.m_DisallowFlags
328 && constraint.GetSeverity() != RPT_SEVERITY_IGNORE )
329 {
330 if( !constraint.GetParentRule()->IsImplicit() )
331 {
332 std::shared_ptr<DRC_ITEM> drcItem =
334 PCB_LAYER_ID layer = item->GetLayerSet().ExtractLayer();
335
336 drcItem->SetErrorDetail( wxString::Format( wxS( "(%s)" ),
337 constraint.GetName() ) );
338 drcItem->SetItems( item );
339 drcItem->SetViolatingRule( constraint.GetParentRule() );
340 reportViolation( drcItem, item->GetPosition(), layer );
341 }
342 }
343
344 item->ClearFlags( HOLE_PROXY );
345 }
346 }
347
348 itemsDone.fetch_add( 1 );
349 return 1;
350 };
351
352 auto itemFutures = tp.submit_loop( 0, itemCount, processItem, itemCount );
353
354 while( itemsDone < itemCount )
355 {
356 reportProgress( itemsDone, itemCount );
357
358 if( m_drcEngine->IsCancelled() )
359 {
360 for( auto& f : itemFutures )
361 f.wait();
362
363 break;
364 }
365
366 std::this_thread::sleep_for( std::chrono::milliseconds( 250 ) );
367 }
368
369 return !m_drcEngine->IsCancelled();
370}
371
372
373namespace detail
374{
376}
constexpr int ARC_LOW_DEF
Definition base_units.h:127
BOX2< VECTOR2I > BOX2I
Definition box2.h:922
PCB_LAYER_ID GetLayer() const override
Return the primary layer this item is on.
int GetDRCEpsilon() const
Return an epsilon which accounts for rounding errors, etc.
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition board_item.h:84
virtual LSET GetLayerSet() const
Return a std::bitset of all layers on which the item physically resides.
Definition board_item.h:288
virtual bool HasHole() const
Definition board_item.h:180
Information pertinent to a Pcbnew printed circuit board.
Definition board.h:323
int m_DRCMaxPhysicalClearance
Definition board.h:1566
int m_DRCMaxClearance
Definition board.h:1565
std::unordered_map< ZONE *, std::unique_ptr< DRC_RTREE > > m_CopperZoneRTreeCache
Definition board.h:1546
BOARD_DESIGN_SETTINGS & GetDesignSettings() const
Definition board.cpp:1091
std::shared_mutex m_CachesMutex
Definition board.h:1539
std::unordered_map< PTR_PTR_LAYER_CACHE_KEY, bool > m_IntersectsAreaCache
Definition board.h:1543
constexpr bool Intersects(const BOX2< Vec > &aRect) const
Definition box2.h:311
wxString GetName() const
Definition drc_rule.h:204
int m_DisallowFlags
Definition drc_rule.h:241
SEVERITY GetSeverity() const
Definition drc_rule.h:217
DRC_RULE * GetParentRule() const
Definition drc_rule.h:200
static std::shared_ptr< DRC_ITEM > Create(int aErrorCode)
Constructs a DRC_ITEM for the given error code.
Definition drc_item.cpp:407
Implement an R-tree for fast spatial and layer indexing of connectable items.
Definition drc_rtree.h:50
int QueryColliding(BOARD_ITEM *aRefItem, PCB_LAYER_ID aRefLayer, PCB_LAYER_ID aTargetLayer, std::function< bool(BOARD_ITEM *)> aFilter=nullptr, std::function< bool(BOARD_ITEM *)> aVisitor=nullptr, int aClearance=0) const
This is a fast test which essentially does bounding-box overlap given a worst-case clearance.
Definition drc_rtree.h:229
bool IsImplicit() const
Definition drc_rule.h:144
virtual ~DRC_TEST_PROVIDER_DISALLOW()=default
virtual const wxString GetName() const override
virtual bool Run() override
Run this provider against the given PCB with configured options (if any).
virtual bool reportPhase(const wxString &aStageName)
int forEachGeometryItem(const std::vector< KICAD_T > &aTypes, const LSET &aLayers, const std::function< bool(BOARD_ITEM *)> &aFunc)
void reportViolation(std::shared_ptr< DRC_ITEM > &item, const VECTOR2I &aMarkerPos, int aMarkerLayer, const std::function< void(PCB_MARKER *)> &aPathGenerator=[](PCB_MARKER *){})
virtual bool reportProgress(size_t aCount, size_t aSize, size_t aDelta=1)
virtual VECTOR2I GetPosition() const
Definition eda_item.h:279
void SetFlags(EDA_ITEM_FLAGS aMask)
Definition eda_item.h:149
KICAD_T Type() const
Returns the type of object.
Definition eda_item.h:112
void ClearFlags(EDA_ITEM_FLAGS aMask=EDA_ITEM_ALL_FLAGS)
Definition eda_item.h:151
PCB_LAYER_ID ExtractLayer() const
Find the first set PCB_LAYER_ID.
Definition lset.cpp:542
static const LSET & AllLayersMask()
Definition lset.cpp:641
virtual LSET GetLayerSet() const override
Return a std::bitset of all layers on which the item physically resides.
std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const override
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
Represent a set of closed polygons.
void Deflate(int aAmount, CORNER_STRATEGY aCornerStrategy, int aMaxError)
void Fracture(bool aSimplify=true)
Convert a set of polygons with holes to a single outline with "slits"/"fractures" connecting the oute...
SHAPE_POLY_SET CloneDropTriangulation() const
Handle a list of polygons defining a copper zone.
Definition zone.h:74
bool GetIsRuleArea() const
Accessors to parameters used in Rule Area zones:
Definition zone.h:716
const BOX2I GetBoundingBox() const override
Definition zone.cpp:651
bool GetDoNotAllowTracks() const
Definition zone.h:728
bool IsFilled() const
Definition zone.h:293
SHAPE_POLY_SET * Outline()
Definition zone.h:336
virtual LSET GetLayerSet() const override
Return a std::bitset of all layers on which the item physically resides.
Definition zone.h:137
bool HasKeepoutParametersSet() const
Accessor to determine if any keepout parameters are set.
Definition zone.h:707
bool GetDoNotAllowZoneFills() const
Definition zone.h:726
bool IsOnCopperLayer() const override
Definition zone.cpp:543
The common library.
@ ALLOW_ACUTE_CORNERS
just inflate the polygon. Acute angles create spikes
@ DRCE_TEXT_ON_EDGECUTS
Definition drc_item.h:43
@ DRCE_ALLOWED_ITEMS
Definition drc_item.h:42
@ DISALLOW_CONSTRAINT
Definition drc_rule.h:75
#define _(s)
#define HOLE_PROXY
Indicates the BOARD_ITEM is a proxy for its hole.
PCB_LAYER_ID
A quick note on layer IDs:
Definition layer_ids.h:60
@ Edge_Cuts
Definition layer_ids.h:112
@ UNDEFINED_LAYER
Definition layer_ids.h:61
static DRC_REGISTER_TEST_PROVIDER< DRC_TEST_PROVIDER_ANNULAR_WIDTH > dummy
@ RPT_SEVERITY_IGNORE
const double epsilon
static bool Collide(const SHAPE_CIRCLE &aA, const SHAPE_CIRCLE &aB, int aClearance, int *aActual, VECTOR2I *aLocation, VECTOR2I *aMTV)
thread_pool & GetKiCadThreadPool()
Get a reference to the current thread pool.
static thread_pool * tp
BS::priority_thread_pool thread_pool
Definition thread_pool.h:31
constexpr KICAD_T BaseType(const KICAD_T aType)
Return the underlying type of the given type.
Definition typeinfo.h:251
@ PCB_TEXTBOX_T
class PCB_TEXTBOX, wrapped text on a layer
Definition typeinfo.h:90
@ PCB_ZONE_T
class ZONE, a copper pour area
Definition typeinfo.h:105
@ PCB_TEXT_T
class PCB_TEXT, text on a layer
Definition typeinfo.h:89
@ PCB_FIELD_T
class PCB_FIELD, text associated with a footprint property
Definition typeinfo.h:87
@ PCB_ARC_T
class PCB_ARC, an arc track segment on a copper layer
Definition typeinfo.h:95
@ PCB_DIMENSION_T
class PCB_DIMENSION_BASE: abstract dimension meta-type
Definition typeinfo.h:97
@ PCB_TRACE_T
class PCB_TRACK, a track segment (segment on a copper layer)
Definition typeinfo.h:93
VECTOR2< int32_t > VECTOR2I
Definition vector2d.h:687