KiCad PCB EDA Suite
drc_test_provider_disallow.cpp
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23 
24 #include <common.h>
25 #include <drc/drc_engine.h>
26 #include <drc/drc_item.h>
27 #include <drc/drc_rule.h>
28 #include <drc/drc_test_provider.h>
29 #include <pad.h>
30 #include <zone.h>
31 
32 /*
33  "Disallow" test. Goes through all items, matching types/conditions drop errors.
34  Errors generated:
35  - DRCE_ALLOWED_ITEMS
36  - DRCE_TEXT_ON_EDGECUTS
37 */
38 
40 {
41 public:
43  {
44  }
45 
47  {
48  }
49 
50  virtual bool Run() override;
51 
52  virtual const wxString GetName() const override
53  {
54  return "disallow";
55  };
56 
57  virtual const wxString GetDescription() const override
58  {
59  return "Tests for disallowed items (e.g. keepouts)";
60  }
61 
62  virtual std::set<DRC_CONSTRAINT_T> GetConstraintTypes() const override;
63 
64  int GetNumPhases() const override;
65 };
66 
67 
69 {
70  if( !reportPhase( _( "Checking keepouts & disallow constraints..." ) ) )
71  return false; // DRC cancelled
72 
73  // Zones can be expensive (particularly when multi-layer), so we run the progress bar on them
74  BOARD* board = m_drcEngine->GetBoard();
75  int boardZoneCount = board->Zones().size();
76  int delta = std::max( 1, boardZoneCount / board->GetCopperLayerCount() );
77  int ii = 0;
78 
79  auto doCheckItem =
80  [&]( BOARD_ITEM* item )
81  {
82  auto constraint = m_drcEngine->EvalRules( DISALLOW_CONSTRAINT, item, nullptr,
84 
85  if( constraint.m_DisallowFlags )
86  {
87  std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_ALLOWED_ITEMS );
88 
89  m_msg.Printf( drcItem->GetErrorText() + wxS( " (%s)" ),
90  constraint.GetName() );
91 
92  drcItem->SetErrorMessage( m_msg );
93  drcItem->SetItems( item );
94  drcItem->SetViolatingRule( constraint.GetParentRule() );
95 
96  reportViolation( drcItem, item->GetPosition() );
97  }
98  };
99 
100  auto checkItem =
101  [&]( BOARD_ITEM* item ) -> bool
102  {
104  && item->GetLayer() == Edge_Cuts )
105  {
106  switch( item->Type() )
107  {
108  case PCB_TEXT_T:
109  case PCB_DIM_ALIGNED_T:
110  case PCB_DIM_CENTER_T:
112  case PCB_DIM_LEADER_T:
113  {
114  std::shared_ptr<DRC_ITEM> drc = DRC_ITEM::Create( DRCE_TEXT_ON_EDGECUTS );
115  drc->SetItems( item );
116  reportViolation( drc, item->GetPosition() );
117  }
118  break;
119 
120  default:
121  break;
122  }
123  }
124 
126  return false;
127 
128  if( item->Type() == PCB_ZONE_T || item->Type() == PCB_FP_ZONE_T )
129  {
130  ZONE* zone = static_cast<ZONE*>( item );
131 
132  if( zone->GetIsRuleArea() )
133  return true;
134 
135  if( item->Type() == PCB_ZONE_T )
136  {
137  if( !reportProgress( ii++, boardZoneCount, delta ) )
138  return false; // DRC cancelled
139  }
140  }
141 
142  item->ClearFlags( HOLE_PROXY );
143  doCheckItem( item );
144 
145  bool hasHole;
146 
147  switch( item->Type() )
148  {
149  case PCB_VIA_T: hasHole = true; break;
150  case PCB_PAD_T: hasHole = static_cast<PAD*>( item )->GetDrillSizeX() > 0; break;
151  default: hasHole = false; break;
152  }
153 
154  if( hasHole )
155  {
156  item->SetFlags( HOLE_PROXY );
157  doCheckItem( item );
158  item->ClearFlags( HOLE_PROXY );
159  }
160 
161  return true;
162  };
163 
164  forEachGeometryItem( {}, LSET::AllLayersMask(), checkItem );
165 
167 
168  return true;
169 }
170 
171 
173 {
174  return 1;
175 }
176 
177 
178 std::set<DRC_CONSTRAINT_T> DRC_TEST_PROVIDER_DISALLOW::GetConstraintTypes() const
179 {
180  return { DISALLOW_CONSTRAINT };
181 }
182 
183 
184 namespace detail
185 {
187 }
class PCB_DIM_ALIGNED, a linear dimension (graphic item)
Definition: typeinfo.h:100
class PCB_DIM_LEADER, a leader dimension (graphic item)
Definition: typeinfo.h:101
static std::shared_ptr< DRC_ITEM > Create(int aErrorCode)
Constructs a DRC_ITEM for the given error code.
Definition: drc_item.cpp:266
ZONES & Zones()
Definition: board.h:240
virtual std::set< DRC_CONSTRAINT_T > GetConstraintTypes() const override
bool GetIsRuleArea() const
Accessors to parameters used in Rule Area zones:
Definition: zone.h:733
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition: board_item.h:49
virtual void reportViolation(std::shared_ptr< DRC_ITEM > &item, const wxPoint &aMarkerPos)
class PCB_DIM_CENTER, a center point marking (graphic item)
Definition: typeinfo.h:102
bool IsErrorLimitExceeded(int error_code)
class PCB_TEXT, text on a layer
Definition: typeinfo.h:91
virtual bool reportProgress(int aCount, int aSize, int aDelta)
class PAD, a pad in a footprint
Definition: typeinfo.h:89
virtual void reportRuleStatistics()
static DRC_REGISTER_TEST_PROVIDER< DRC_TEST_PROVIDER_ANNULAR_WIDTH > dummy
#define HOLE_PROXY
Indicates the BOARD_ITEM is a proxy for its hole.
virtual const wxString GetName() const override
BOARD * GetBoard() const
Definition: drc_engine.h:88
virtual bool reportPhase(const wxString &aStageName)
virtual const wxString GetDescription() const override
#define _(s)
static LSET AllLayersMask()
Definition: lset.cpp:787
Handle a list of polygons defining a copper zone.
Definition: zone.h:56
class ZONE, a copper pour area
Definition: typeinfo.h:105
DRC_CONSTRAINT EvalRules(DRC_CONSTRAINT_T aConstraintType, const BOARD_ITEM *a, const BOARD_ITEM *b, PCB_LAYER_ID aLayer, REPORTER *aReporter=nullptr)
Definition: drc_engine.cpp:760
int forEachGeometryItem(const std::vector< KICAD_T > &aTypes, LSET aLayers, const std::function< bool(BOARD_ITEM *)> &aFunc)
Represent a DRC "provider" which runs some DRC functions over a BOARD and spits out #DRC_ITEMs and po...
Information pertinent to a Pcbnew printed circuit board.
Definition: board.h:191
DRC_ENGINE * m_drcEngine
int GetCopperLayerCount() const
Definition: board.cpp:455
class ZONE, managed by a footprint
Definition: typeinfo.h:94
The common library.
constexpr int delta
virtual bool Run() override
Run this provider against the given PCB with configured options (if any).
class PCB_DIM_ORTHOGONAL, a linear dimension constrained to x/y
Definition: typeinfo.h:103
class PCB_VIA, a via (like a track segment on a copper layer)
Definition: typeinfo.h:96