KiCad PCB EDA Suite
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drc_test_provider_disallow.cpp
Go to the documentation of this file.
1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright The KiCad Developers.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, you may find one here:
18 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
19 * or you may search the http://www.gnu.org website for the version 2 license,
20 * or you may write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
22 */
23
24#include <atomic>
25#include <common.h>
27#include <drc/drc_rtree.h>
28#include <drc/drc_engine.h>
29#include <drc/drc_item.h>
30#include <drc/drc_rule.h>
32#include <pad.h>
33#include <progress_reporter.h>
34#include <thread_pool.h>
35#include <zone.h>
36#include <pcb_track.h>
37#include <mutex>
38
39
40/*
41 "Disallow" test. Goes through all items, matching types/conditions drop errors.
42 Errors generated:
43 - DRCE_ALLOWED_ITEMS
44 - DRCE_TEXT_ON_EDGECUTS
45*/
46
48{
49public:
52
53 virtual ~DRC_TEST_PROVIDER_DISALLOW() = default;
54
55 virtual bool Run() override;
56
57 virtual const wxString GetName() const override { return wxT( "disallow" ); };
58};
59
60
62{
63 if( !reportPhase( _( "Checking keepouts & disallow constraints..." ) ) )
64 return false; // DRC cancelled
65
66 BOARD* board = m_drcEngine->GetBoard();
68
69 // First build out the board's cache of copper-keepout to copper-zone caches. This is where
70 // the bulk of the time is spent, and we can do this in parallel.
71 //
72 std::vector<ZONE*> antiCopperKeepouts;
73 std::vector<ZONE*> copperZones;
74 std::vector<std::pair<ZONE*, ZONE*>> toCache;
75 std::atomic<size_t> done( 1 );
76 int totalCount = 0;
77 std::unique_ptr<DRC_RTREE> antiTrackKeepouts = std::make_unique<DRC_RTREE>();
78
80 [&]( BOARD_ITEM* item ) -> bool
81 {
82 ZONE* zone = static_cast<ZONE*>( item );
83
84 if( zone->GetIsRuleArea() && zone->GetDoNotAllowZoneFills() )
85 {
86 antiCopperKeepouts.push_back( zone );
87 }
88 else if( zone->GetIsRuleArea() && zone->GetDoNotAllowTracks() )
89 {
90 for( PCB_LAYER_ID layer : zone->GetLayerSet() )
91 antiTrackKeepouts->Insert( zone, layer );
92 }
93 else if( zone->IsOnCopperLayer() )
94 {
95 copperZones.push_back( zone );
96 }
97
98 totalCount++;
99
100 return true;
101 } );
102
103 for( ZONE* ruleArea : antiCopperKeepouts )
104 {
105 for( ZONE* copperZone : copperZones )
106 {
107 toCache.push_back( { ruleArea, copperZone } );
108 totalCount++;
109 }
110 }
111
112 auto query_areas =
113 [&]( const int idx ) -> size_t
114 {
115 if( m_drcEngine->IsCancelled() )
116 return 0;
117 const auto& areaZonePair = toCache[idx];
118 ZONE* ruleArea = areaZonePair.first;
119 ZONE* copperZone = areaZonePair.second;
120 BOX2I areaBBox = ruleArea->GetBoundingBox();
121 BOX2I copperBBox = copperZone->GetBoundingBox();
122 bool isInside = false;
123
124 if( copperZone->IsFilled() && areaBBox.Intersects( copperBBox ) )
125 {
126 // Collisions include touching, so we need to deflate outline by enough to
127 // exclude it. This is particularly important for detecting copper fills as
128 // they will be exactly touching along the entire exclusion border.
129 SHAPE_POLY_SET areaPoly = ruleArea->Outline()->CloneDropTriangulation();
130 areaPoly.Fracture();
132
133 DRC_RTREE* zoneRTree = board->m_CopperZoneRTreeCache[ copperZone ].get();
134
135 if( zoneRTree )
136 {
137 for( size_t ii = 0; ii < ruleArea->GetLayerSet().size(); ++ii )
138 {
139 if( ruleArea->GetLayerSet().test( ii ) )
140 {
141 PCB_LAYER_ID layer = PCB_LAYER_ID( ii );
142
143 if( zoneRTree->QueryColliding( areaBBox, &areaPoly, layer ) )
144 {
145 isInside = true;
146 break;
147 }
148
149 if( m_drcEngine->IsCancelled() )
150 return 0;
151 }
152 }
153 }
154 }
155
156 if( m_drcEngine->IsCancelled() )
157 return 0;
158
159 PTR_PTR_LAYER_CACHE_KEY key = { ruleArea, copperZone, UNDEFINED_LAYER };
160
161 {
162 std::unique_lock<std::shared_mutex> writeLock( board->m_CachesMutex );
163 board->m_IntersectsAreaCache[ key ] = isInside;
164 }
165
166 done.fetch_add( 1 );
167
168 return 1;
169 };
170
172 auto futures = tp.submit_loop( 0, toCache.size(), query_areas );
173
174 for( auto& ret : futures )
175 {
176 std::future_status status = ret.wait_for( std::chrono::milliseconds( 250 ) );
177
178 while( status != std::future_status::ready )
179 {
180 reportProgress( done, toCache.size() );
181 status = ret.wait_for( std::chrono::milliseconds( 250 ) );
182 }
183 }
184
185 if( m_drcEngine->IsCancelled() )
186 return false;
187
188 // Now go through all the board objects calling the DRC_ENGINE to run the actual disallow
189 // tests. These should be reasonably quick using the caches generated above.
190 //
191 const int progressDelta = 250;
192 int ii = static_cast<int>( toCache.size() );
193
194 auto checkTextOnEdgeCuts =
195 [&]( BOARD_ITEM* item )
196 {
197 if( item->Type() == PCB_FIELD_T
198 || item->Type() == PCB_TEXT_T
199 || item->Type() == PCB_TEXTBOX_T
200 || BaseType( item->Type() ) == PCB_DIMENSION_T )
201 {
202 if( item->GetLayer() == Edge_Cuts )
203 {
204 std::shared_ptr<DRC_ITEM> drc = DRC_ITEM::Create( DRCE_TEXT_ON_EDGECUTS );
205 drc->SetItems( item );
206 reportViolation( drc, item->GetPosition(), Edge_Cuts );
207 }
208 }
209 };
210
211 auto checkAntiTrackKeepout =
212 [&]( PCB_TRACK* track, ZONE* keepout )
213 {
214 std::shared_ptr<SHAPE> shape = track->GetEffectiveShape();
215 int dummyActual;
216 VECTOR2I pos;
217
218 if( keepout->Outline()->Collide( shape.get(), board->m_DRCMaxClearance,
219 &dummyActual, &pos ) )
220 {
221 std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_ALLOWED_ITEMS );
222
223 drcItem->SetItems( track );
224 reportViolation( drcItem, pos, track->GetLayerSet().ExtractLayer() );
225 }
226 };
227
228 auto checkDisallow =
229 [&]( BOARD_ITEM* item )
230 {
231 DRC_CONSTRAINT constraint = m_drcEngine->EvalRules( DISALLOW_CONSTRAINT, item,
232 nullptr, UNDEFINED_LAYER );
233
234 if( constraint.m_DisallowFlags && constraint.GetSeverity() != RPT_SEVERITY_IGNORE )
235 {
236 std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_ALLOWED_ITEMS );
237 PCB_LAYER_ID layer = item->GetLayerSet().ExtractLayer();
238 wxString msg;
239
240 // Implicit rules reported in checkAntiTrackKeepout
241 if( constraint.GetParentRule()->m_Implicit )
242 return;
243
244 msg.Printf( drcItem->GetErrorText() + wxS( " (%s)" ), constraint.GetName() );
245
246 drcItem->SetErrorMessage( msg );
247 drcItem->SetItems( item );
248 drcItem->SetViolatingRule( constraint.GetParentRule() );
249
250 reportViolation( drcItem, item->GetPosition(), layer );
251 }
252 };
253
255 [&]( BOARD_ITEM* item ) -> bool
256 {
257 if( !m_drcEngine->IsErrorLimitExceeded( DRCE_TEXT_ON_EDGECUTS ) )
258 checkTextOnEdgeCuts( item );
259
260 if( !m_drcEngine->IsErrorLimitExceeded( DRCE_ALLOWED_ITEMS ) )
261 {
262 if( ZONE* zone = dynamic_cast<ZONE*>( item ) )
263 {
264 if( zone->GetIsRuleArea() && zone->HasKeepoutParametersSet() )
265 return true;
266 }
267
268 item->ClearFlags( HOLE_PROXY ); // Just in case
269
270 if( item->Type() == PCB_TRACE_T || item->Type() == PCB_ARC_T )
271 {
272 PCB_TRACK* track = static_cast<PCB_TRACK*>( item );
273 PCB_LAYER_ID layer = track->GetLayer();
274
275 antiTrackKeepouts->QueryColliding( track, layer, layer,
276 // Filter:
277 [&]( BOARD_ITEM* other ) -> bool
278 {
279 return true;
280 },
281 // Visitor:
282 [&]( BOARD_ITEM* other ) -> bool
283 {
284 checkAntiTrackKeepout( track, static_cast<ZONE*>( other ) );
285 return !m_drcEngine->IsCancelled();
286 },
288 }
289
290 checkDisallow( item );
291
292 if( item->HasHole() )
293 {
294 item->SetFlags( HOLE_PROXY );
295 checkDisallow( item );
296 item->ClearFlags( HOLE_PROXY );
297 }
298 }
299
300 if( !reportProgress( ii++, totalCount, progressDelta ) )
301 return false;
302
303 return true;
304 } );
305
306 return !m_drcEngine->IsCancelled();
307}
308
309
310namespace detail
311{
313}
constexpr int ARC_LOW_DEF
Definition base_units.h:128
BOX2< VECTOR2I > BOX2I
Definition box2.h:922
int GetDRCEpsilon() const
Return an epsilon which accounts for rounding errors, etc.
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition board_item.h:79
virtual PCB_LAYER_ID GetLayer() const
Return the primary layer this item is on.
Definition board_item.h:232
Information pertinent to a Pcbnew printed circuit board.
Definition board.h:317
int m_DRCMaxPhysicalClearance
Definition board.h:1383
int m_DRCMaxClearance
Definition board.h:1382
std::unordered_map< ZONE *, std::unique_ptr< DRC_RTREE > > m_CopperZoneRTreeCache
Definition board.h:1374
BOARD_DESIGN_SETTINGS & GetDesignSettings() const
Definition board.cpp:1040
std::shared_mutex m_CachesMutex
Definition board.h:1367
std::unordered_map< PTR_PTR_LAYER_CACHE_KEY, bool > m_IntersectsAreaCache
Definition board.h:1371
constexpr bool Intersects(const BOX2< Vec > &aRect) const
Definition box2.h:311
wxString GetName() const
Definition drc_rule.h:170
int m_DisallowFlags
Definition drc_rule.h:205
SEVERITY GetSeverity() const
Definition drc_rule.h:183
DRC_RULE * GetParentRule() const
Definition drc_rule.h:166
static std::shared_ptr< DRC_ITEM > Create(int aErrorCode)
Constructs a DRC_ITEM for the given error code.
Definition drc_item.cpp:381
Implement an R-tree for fast spatial and layer indexing of connectable items.
Definition drc_rtree.h:48
int QueryColliding(BOARD_ITEM *aRefItem, PCB_LAYER_ID aRefLayer, PCB_LAYER_ID aTargetLayer, std::function< bool(BOARD_ITEM *)> aFilter=nullptr, std::function< bool(BOARD_ITEM *)> aVisitor=nullptr, int aClearance=0) const
This is a fast test which essentially does bounding-box overlap given a worst-case clearance.
Definition drc_rtree.h:214
bool m_Implicit
Definition drc_rule.h:120
virtual ~DRC_TEST_PROVIDER_DISALLOW()=default
virtual const wxString GetName() const override
virtual bool Run() override
Run this provider against the given PCB with configured options (if any).
virtual bool reportPhase(const wxString &aStageName)
int forEachGeometryItem(const std::vector< KICAD_T > &aTypes, const LSET &aLayers, const std::function< bool(BOARD_ITEM *)> &aFunc)
virtual void reportViolation(std::shared_ptr< DRC_ITEM > &item, const VECTOR2I &aMarkerPos, int aMarkerLayer, const std::vector< PCB_SHAPE > &aShapes={})
virtual bool reportProgress(size_t aCount, size_t aSize, size_t aDelta=1)
PCB_LAYER_ID ExtractLayer() const
Find the first set PCB_LAYER_ID.
Definition lset.cpp:525
static const LSET & AllLayersMask()
Definition lset.cpp:624
virtual LSET GetLayerSet() const override
Return a std::bitset of all layers on which the item physically resides.
std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const override
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
Represent a set of closed polygons.
void Fracture()
Convert a set of polygons with holes to a single outline with "slits"/"fractures" connecting the oute...
void Deflate(int aAmount, CORNER_STRATEGY aCornerStrategy, int aMaxError)
SHAPE_POLY_SET CloneDropTriangulation() const
Handle a list of polygons defining a copper zone.
Definition zone.h:74
bool GetIsRuleArea() const
Accessors to parameters used in Rule Area zones:
Definition zone.h:704
const BOX2I GetBoundingBox() const override
Definition zone.cpp:621
bool GetDoNotAllowTracks() const
Definition zone.h:721
bool IsFilled() const
Definition zone.h:292
SHAPE_POLY_SET * Outline()
Definition zone.h:335
virtual LSET GetLayerSet() const override
Return a std::bitset of all layers on which the item physically resides.
Definition zone.h:136
bool GetDoNotAllowZoneFills() const
Definition zone.h:719
bool IsOnCopperLayer() const override
Definition zone.cpp:499
The common library.
@ ALLOW_ACUTE_CORNERS
just inflate the polygon. Acute angles create spikes
@ DRCE_TEXT_ON_EDGECUTS
Definition drc_item.h:42
@ DRCE_ALLOWED_ITEMS
Definition drc_item.h:41
@ DISALLOW_CONSTRAINT
Definition drc_rule.h:69
#define _(s)
#define HOLE_PROXY
Indicates the BOARD_ITEM is a proxy for its hole.
PCB_LAYER_ID
A quick note on layer IDs:
Definition layer_ids.h:60
@ Edge_Cuts
Definition layer_ids.h:112
@ UNDEFINED_LAYER
Definition layer_ids.h:61
static DRC_REGISTER_TEST_PROVIDER< DRC_TEST_PROVIDER_ANNULAR_WIDTH > dummy
@ RPT_SEVERITY_IGNORE
const double epsilon
thread_pool & GetKiCadThreadPool()
Get a reference to the current thread pool.
static thread_pool * tp
BS::thread_pool< 0 > thread_pool
Definition thread_pool.h:31
constexpr KICAD_T BaseType(const KICAD_T aType)
Return the underlying type of the given type.
Definition typeinfo.h:252
@ PCB_TEXTBOX_T
class PCB_TEXTBOX, wrapped text on a layer
Definition typeinfo.h:93
@ PCB_ZONE_T
class ZONE, a copper pour area
Definition typeinfo.h:107
@ PCB_TEXT_T
class PCB_TEXT, text on a layer
Definition typeinfo.h:92
@ PCB_FIELD_T
class PCB_FIELD, text associated with a footprint property
Definition typeinfo.h:90
@ PCB_ARC_T
class PCB_ARC, an arc track segment on a copper layer
Definition typeinfo.h:98
@ PCB_DIMENSION_T
class PCB_DIMENSION_BASE: abstract dimension meta-type
Definition typeinfo.h:100
@ PCB_TRACE_T
class PCB_TRACK, a track segment (segment on a copper layer)
Definition typeinfo.h:96
VECTOR2< int32_t > VECTOR2I
Definition vector2d.h:695