KiCad PCB EDA Suite
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drc_test_provider_via_diameter.cpp
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1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright The KiCad Developers.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <https://www.gnu.org/licenses/>.
18 */
19
20#include <pcb_track.h>
21#include <drc/drc_engine.h>
22#include <drc/drc_item.h>
23#include <drc/drc_rule.h>
25
26/*
27 Via diameter test.
28
29 Errors generated:
30 - DRCE_VIA_DIAMETER
31*/
32
34{
35public:
38
40
41 virtual bool Run() override;
42
43 virtual const wxString GetName() const override { return wxT( "diameter" ); };
44};
45
46
48{
49 if( m_drcEngine->IsErrorLimitExceeded( DRCE_VIA_DIAMETER ) )
50 {
51 REPORT_AUX( wxT( "Via diameter violations ignored. Tests not run." ) );
52 return true; // continue with other tests
53 }
54
55 if( !m_drcEngine->HasRulesForConstraintType( VIA_DIAMETER_CONSTRAINT ) )
56 {
57 REPORT_AUX( wxT( "No via diameter constraints found. Tests not run." ) );
58 return true; // continue with other tests
59 }
60
61 if( !reportPhase( _( "Checking via diameters..." ) ) )
62 return false; // DRC cancelled
63
64 auto checkViaDiameter =
65 [&]( BOARD_ITEM* item ) -> bool
66 {
67 if( m_drcEngine->IsErrorLimitExceeded( DRCE_VIA_DIAMETER ) )
68 return false;
69
70 if( item->Type() != PCB_VIA_T )
71 return true;
72
73 PCB_VIA* via = static_cast<PCB_VIA*>( item );
74
75 via->Padstack().ForEachUniqueLayer(
76 [&]( PCB_LAYER_ID aLayer )
77 {
78 if( via->IsGhostLayer( aLayer ) )
79 return;
80
81 DRC_CONSTRAINT constraint = m_drcEngine->EvalRules( VIA_DIAMETER_CONSTRAINT, item,
82 nullptr, aLayer );
83 bool fail_min = false;
84 bool fail_max = false;
85 int constraintDiameter = 0;
86 int actual = via->GetWidth( aLayer );
87
88 auto layerDesc =
89 [&]() -> wxString
90 {
91 if( aLayer == F_Cu )
92 return m_drcEngine->GetBoard()->GetLayerName( F_Cu );
93 else if( aLayer == B_Cu )
94 return m_drcEngine->GetBoard()->GetLayerName( B_Cu );
95 else if( via->Padstack().Mode() == PADSTACK::MODE::FRONT_INNER_BACK )
96 return _( "Inner Layers" );
97 else
98 return m_drcEngine->GetBoard()->GetLayerName( aLayer );
99 };
100
101 if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE )
102 {
103 if( constraint.Value().HasMin() && actual < constraint.Value().Min() )
104 {
105 fail_min = true;
106 constraintDiameter = constraint.Value().Min();
107 }
108
109 if( constraint.Value().HasMax() && actual > constraint.Value().Max() )
110 {
111 fail_max = true;
112 constraintDiameter = constraint.Value().Max();
113 }
114 }
115
116 if( fail_min || fail_max )
117 {
118 std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_VIA_DIAMETER );
119 wxString constraintName = constraint.GetName();
120 wxString msg;
121
122 if( fail_min )
123 {
124 if( constraint.m_ImplicitMin )
125 constraintName = _( "board setup constraints" );
126
127 if( via->Padstack().Mode() == PADSTACK::MODE::NORMAL )
128 {
129 msg = formatMsg( _( "(%s min diameter %s; actual %s)" ),
130 constraintName,
131 constraintDiameter,
132 actual );
133 }
134 else
135 {
136 msg = formatMsg( _( "(%s min diameter %s; actual %s on %s)" ),
137 constraintName,
138 constraintDiameter,
139 actual,
140 layerDesc() );
141 }
142 }
143 else if( fail_max )
144 {
145 if( via->Padstack().Mode() == PADSTACK::MODE::NORMAL )
146 {
147 msg = formatMsg( _( "(%s max diameter %s; actual %s)" ),
148 constraintName,
149 constraintDiameter,
150 actual );
151 }
152 else
153 {
154 msg = formatMsg( _( "(%s max diameter %s; actual %s on %s)" ),
155 constraintName,
156 constraintDiameter,
157 actual,
158 layerDesc() );
159 }
160 }
161
162 drcItem->SetErrorDetail( msg );
163 drcItem->SetItems( item );
164 drcItem->SetViolatingRule( constraint.GetParentRule() );
165
166 reportViolation( drcItem, via->GetPosition(), aLayer );
167 }
168 } );
169
170 return true;
171 };
172
173 const int progressDelta = 500;
174 int ii = 0;
175
176 for( PCB_TRACK* item : m_drcEngine->GetBoard()->Tracks() )
177 {
178 if( !reportProgress( ii++, m_drcEngine->GetBoard()->Tracks().size(), progressDelta ) )
179 break;
180
181 if( !checkViaDiameter( item ) )
182 break;
183 }
184
185 return !m_drcEngine->IsCancelled();
186}
187
188
189namespace detail
190{
192}
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition board_item.h:84
wxString GetName() const
Definition drc_rule.h:208
SEVERITY GetSeverity() const
Definition drc_rule.h:221
MINOPTMAX< int > & Value()
Definition drc_rule.h:201
DRC_RULE * GetParentRule() const
Definition drc_rule.h:204
bool m_ImplicitMin
Definition drc_rule.h:248
static std::shared_ptr< DRC_ITEM > Create(int aErrorCode)
Constructs a DRC_ITEM for the given error code.
Definition drc_item.cpp:444
virtual ~DRC_TEST_PROVIDER_VIA_DIAMETER()=default
virtual bool Run() override
Run this provider against the given PCB with configured options (if any).
virtual const wxString GetName() const override
virtual bool reportPhase(const wxString &aStageName)
void reportViolation(std::shared_ptr< DRC_ITEM > &item, const VECTOR2I &aMarkerPos, int aMarkerLayer, const std::function< void(PCB_MARKER *)> &aPathGenerator=[](PCB_MARKER *){})
wxString formatMsg(const wxString &aFormatString, const wxString &aSource, double aConstraint, double aActual, EDA_DATA_TYPE aDataType=EDA_DATA_TYPE::DISTANCE)
virtual bool reportProgress(size_t aCount, size_t aSize, size_t aDelta=1)
T Min() const
Definition minoptmax.h:29
bool HasMax() const
Definition minoptmax.h:35
bool HasMin() const
Definition minoptmax.h:34
T Max() const
Definition minoptmax.h:30
@ NORMAL
Shape is the same on all layers.
Definition padstack.h:170
@ FRONT_INNER_BACK
Up to three shapes can be defined (F_Cu, inner copper layers, B_Cu)
Definition padstack.h:171
@ DRCE_VIA_DIAMETER
Definition drc_item.h:59
@ VIA_DIAMETER_CONSTRAINT
Definition drc_rule.h:72
#define REPORT_AUX(s)
#define _(s)
PCB_LAYER_ID
A quick note on layer IDs:
Definition layer_ids.h:56
@ B_Cu
Definition layer_ids.h:61
@ F_Cu
Definition layer_ids.h:60
static DRC_REGISTER_TEST_PROVIDER< DRC_TEST_PROVIDER_ANNULAR_WIDTH > dummy
@ RPT_SEVERITY_IGNORE
int actual
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
Definition typeinfo.h:89