KiCad PCB EDA Suite
netinfo_item.cpp
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1
5/*
6 * This program source code file is part of KiCad, a free EDA CAD application.
7 *
8 * Copyright (C) 2012 Jean-Pierre Charras, [email protected]
9 * Copyright (C) 2012 SoftPLC Corporation, Dick Hollenbeck <[email protected]>
10 * Copyright (C) 1992-2021 KiCad Developers, see AUTHORS.txt for contributors.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, you may find one here:
24 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
25 * or you may search the http://www.gnu.org website for the version 2 license,
26 * or you may write to the Free Software Foundation, Inc.,
27 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
28 */
29
30#include <pcb_base_frame.h>
31#include <string_utils.h>
32#include <widgets/msgpanel.h>
33#include <base_units.h>
34#include <board.h>
37#include <footprint.h>
38#include <pcb_track.h>
39#include <pad.h>
40
41
42NETINFO_ITEM::NETINFO_ITEM( BOARD* aParent, const wxString& aNetName, int aNetCode ) :
43 BOARD_ITEM( aParent, PCB_NETINFO_T ),
44 m_netCode( aNetCode ),
45 m_netname( aNetName ),
46 m_shortNetname( m_netname.AfterLast( '/' ) ),
47 m_isCurrent( true )
48{
49 m_parent = aParent;
50
51 if( aParent )
52 m_netClass = aParent->GetDesignSettings().m_NetSettings->m_DefaultNetClass;
53 else
54 m_netClass = std::make_shared<NETCLASS>( wxT( "<invalid>" ) );
55}
56
57
59{
60 // m_NetClass is not owned by me.
61}
62
63
65{
66 m_netClass = m_parent->GetDesignSettings().m_NetSettings->m_DefaultNetClass;
67}
68
69
70void NETINFO_ITEM::SetNetClass( const std::shared_ptr<NETCLASS>& aNetClass )
71{
72 wxCHECK( m_parent, /* void */ );
73
74 if( aNetClass )
75 m_netClass = aNetClass;
76 else
77 m_netClass = m_parent->GetDesignSettings().m_NetSettings->m_DefaultNetClass;
78}
79
80
81void NETINFO_ITEM::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>& aList )
82{
83 wxString msg;
84
85 aList.emplace_back( _( "Net Name" ), UnescapeString( GetNetname() ) );
86
87 aList.emplace_back( _( "Net Code" ), wxString::Format( wxT( "%d" ), GetNetCode() ) );
88
89 // Warning: for netcode == NETINFO_LIST::ORPHANED, the parent or the board can be NULL
90 BOARD * board = m_parent ? m_parent->GetBoard() : nullptr;
91
92 if( board )
93 {
94 int count = 0;
95 PCB_TRACK* startTrack = nullptr;
96
97 for( FOOTPRINT* footprint : board->Footprints() )
98 {
99 for( PAD* pad : footprint->Pads() )
100 {
101 if( pad->GetNetCode() == GetNetCode() )
102 count++;
103 }
104 }
105
106 aList.emplace_back( _( "Pads" ), wxString::Format( wxT( "%d" ), count ) );
107
108 count = 0;
109
110 for( PCB_TRACK* track : board->Tracks() )
111 {
112 if( track->GetNetCode() == GetNetCode() )
113 {
114 if( track->Type() == PCB_VIA_T )
115 count++;
116 else if( !startTrack )
117 startTrack = track;
118 }
119 }
120
121 aList.emplace_back( _( "Vias" ), wxString::Format( wxT( "%d" ), count ) );
122
123 if( startTrack )
124 {
125 double lengthNet = 0.0; // This is the length of tracks on pcb
126 double lengthPadToDie = 0.0; // this is the length of internal ICs connections
127
128 std::tie( count, lengthNet, lengthPadToDie ) = board->GetTrackLength( *startTrack );
129
130 // Displays the full net length (tracks on pcb + internal ICs connections ):
131 aList.emplace_back( _( "Net Length" ),
132 aFrame->MessageTextFromValue( lengthNet + lengthPadToDie ) );
133
134 // Displays the net length of tracks only:
135 aList.emplace_back( _( "On Board" ), aFrame->MessageTextFromValue( lengthNet ) );
136
137 // Displays the net length of internal ICs connections (wires inside ICs):
138 aList.emplace_back( _( "In Package" ), aFrame->MessageTextFromValue( lengthPadToDie ) );
139 }
140 }
141}
142
143
144bool NETINFO_ITEM::Matches( const EDA_SEARCH_DATA& aSearchData, void* aAuxData ) const
145{
146 return BOARD_ITEM::Matches( GetNetname(), aSearchData );
147}
148
149
151{
152 std::shared_ptr<CONNECTIVITY_DATA> conn = GetBoard()->GetConnectivity();
153 BOX2I bbox;
154
155 for( BOARD_ITEM* item : conn->GetNetItems( m_netCode, { PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T,
156 PCB_ZONE_T, PCB_PAD_T } ) )
157 {
158 bbox.Merge( item->GetBoundingBox() );
159 }
160
161 return bbox;
162}
std::shared_ptr< NET_SETTINGS > m_NetSettings
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition: board_item.h:58
virtual const BOARD * GetBoard() const
Return the BOARD in which this BOARD_ITEM resides, or NULL if none.
Definition: board_item.cpp:43
Information pertinent to a Pcbnew printed circuit board.
Definition: board.h:265
FOOTPRINTS & Footprints()
Definition: board.h:307
TRACKS & Tracks()
Definition: board.h:304
std::tuple< int, double, double > GetTrackLength(const PCB_TRACK &aTrack) const
Return data on the length and number of track segments connected to a given track.
Definition: board.cpp:1719
BOARD_DESIGN_SETTINGS & GetDesignSettings() const
Definition: board.cpp:643
std::shared_ptr< CONNECTIVITY_DATA > GetConnectivity() const
Return a list of missing connections between components/tracks.
Definition: board.h:424
BOX2< Vec > & Merge(const BOX2< Vec > &aRect)
Modify the position and size of the rectangle in order to contain aRect.
Definition: box2.h:588
The base class for create windows for drawing purpose.
virtual bool Matches(const EDA_SEARCH_DATA &aSearchData, void *aAuxData) const
Compare the item against the search criteria in aSearchData.
Definition: eda_item.h:384
bool Matches(const EDA_SEARCH_DATA &aSearchData, void *aAuxData) const override
Compare the item against the search criteria in aSearchData.
NETINFO_ITEM(BOARD *aParent, const wxString &aNetName=wxEmptyString, int aNetCode=-1)
NETINFO_ITEM class, to handle info on nets: netnames, net constraints.
const wxString & GetNetname() const
Definition: netinfo.h:119
void Clear()
Set all fields to their default values.
int GetNetCode() const
Definition: netinfo.h:113
int m_netCode
A number equivalent to the net name.
Definition: netinfo.h:175
std::shared_ptr< NETCLASS > m_netClass
Definition: netinfo.h:179
void GetMsgPanelInfo(EDA_DRAW_FRAME *aFrame, std::vector< MSG_PANEL_ITEM > &aList) override
Return the information about the NETINFO_ITEM in aList to display in the message panel.
const BOX2I GetBoundingBox() const override
Return the orthogonal bounding box of this object for display purposes.
void SetNetClass(const std::shared_ptr< NETCLASS > &aNetClass)
BOARD * m_parent
The parent board the net belongs to.
Definition: netinfo.h:185
Definition: pad.h:59
wxString MessageTextFromValue(double aValue, bool aAddUnitLabel=true, EDA_DATA_TYPE aType=EDA_DATA_TYPE::DISTANCE)
A lower-precision version of StringFromValue().
#define _(s)
Message panel definition file.
void Format(OUTPUTFORMATTER *out, int aNestLevel, int aCtl, const CPTREE &aTree)
Output a PTREE into s-expression format via an OUTPUTFORMATTER derivative.
Definition: ptree.cpp:200
wxString UnescapeString(const wxString &aSource)
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
Definition: typeinfo.h:102
@ PCB_NETINFO_T
class NETINFO_ITEM, a description of a net
Definition: typeinfo.h:114