KiCad PCB EDA Suite
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netinfo_item.cpp
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1
4
5/*
6 * This program source code file is part of KiCad, a free EDA CAD application.
7 *
8 * Copyright (C) 2012 Jean-Pierre Charras, [email protected]
9 * Copyright (C) 2012 SoftPLC Corporation, Dick Hollenbeck <[email protected]>
10 * Copyright The KiCad Developers, see AUTHORS.txt for contributors.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, you may find one here:
24 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
25 * or you may search the http://www.gnu.org website for the version 2 license,
26 * or you may write to the Free Software Foundation, Inc.,
27 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
28 */
29
30#include "netinfo.h"
31
32#include <fmt/format.h>
33
34#include <pcb_base_frame.h>
35#include <string_utils.h>
36#include <widgets/msgpanel.h>
37#include <base_units.h>
38#include <board.h>
41#include <footprint.h>
42#include <pcb_track.h>
43#include <pad.h>
44
45
46NETINFO_ITEM::NETINFO_ITEM( BOARD* aParent, const wxString& aNetName, int aNetCode ) :
47 BOARD_ITEM( aParent, PCB_NETINFO_T ),
48 m_netCode( aNetCode ),
49 m_netname( aNetName ),
50 m_shortNetname( m_netname.AfterLast( '/' ) ),
52 m_isCurrent( true )
53{
54 m_parent = aParent;
55
56 if( aParent )
58 else
59 m_netClass = std::make_shared<NETCLASS>( wxT( "Default" ) );
60}
61
62
64{
65 // m_NetClass is not owned by me.
66}
67
68
70{
71 wxCHECK( m_parent, /* void */ );
72 m_netClass = m_parent->GetDesignSettings().m_NetSettings->GetDefaultNetclass();
73}
74
75
76void NETINFO_ITEM::SetNetClass( const std::shared_ptr<NETCLASS>& aNetClass )
77{
78 wxCHECK( m_parent, /* void */ );
79
80 if( aNetClass )
81 m_netClass = aNetClass;
82 else
83 m_netClass = m_parent->GetDesignSettings().m_NetSettings->GetDefaultNetclass();
84}
85
86
87void NETINFO_ITEM::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>& aList )
88{
89 aList.emplace_back( _( "Net Name" ), UnescapeString( GetNetname() ) );
90
91 aList.emplace_back( _( "Net Code" ), fmt::format( "{}", GetNetCode() ) );
92
93 // Warning: for netcode == NETINFO_LIST::ORPHANED, the parent or the board can be NULL
94 BOARD * board = m_parent ? m_parent->GetBoard() : nullptr;
95
96 if( board )
97 {
98 int count = 0;
99 PCB_TRACK* startTrack = nullptr;
100
101 for( FOOTPRINT* footprint : board->Footprints() )
102 {
103 for( PAD* pad : footprint->Pads() )
104 {
105 if( pad->GetNetCode() == GetNetCode() )
106 count++;
107 }
108 }
109
110 aList.emplace_back( _( "Pads" ), fmt::format( "{}", count ) );
111
112 count = 0;
113
114 for( PCB_TRACK* track : board->Tracks() )
115 {
116 if( track->GetNetCode() == GetNetCode() )
117 {
118 if( track->Type() == PCB_VIA_T )
119 count++;
120 else if( !startTrack )
121 startTrack = track;
122 }
123 }
124
125 aList.emplace_back( _( "Vias" ), fmt::format( "{}", count ) );
126
127 if( startTrack )
128 {
129 double lengthNet = 0.0; // This is the length of tracks / vias on the pcb
130 double lengthPadToDie = 0.0; // This is the length of internal IC connections
131 double delayNet = 0.0; // This is the delay of tracks / vias on the pcb
132 double delayPadToDie = 0.0; // This is the delay of internal IC connections
133
134 std::tie( count, lengthNet, lengthPadToDie, delayNet, delayPadToDie ) =
135 board->GetTrackLength( *startTrack );
136
137 if( delayNet == 0.0 )
138 {
139 // Displays the full net length (tracks on pcb + internal ICs connections ):
140 aList.emplace_back( _( "Net Length" ), aFrame->MessageTextFromValue( lengthNet + lengthPadToDie ) );
141
142 // Displays the net length of tracks only:
143 aList.emplace_back( _( "On Board" ), aFrame->MessageTextFromValue( lengthNet ) );
144
145 // Displays the net length of internal ICs connections (wires inside ICs):
146 aList.emplace_back( _( "In Package" ), aFrame->MessageTextFromValue( lengthPadToDie ) );
147 }
148 else
149 {
150 // Displays the full net length (tracks on pcb + internal ICs connections ):
151 aList.emplace_back( _( "Net Delay" ), aFrame->MessageTextFromValue( delayNet + delayPadToDie, true,
153
154 // Displays the net length of tracks only:
155 aList.emplace_back( _( "On Board" ),
156 aFrame->MessageTextFromValue( delayNet, true, EDA_DATA_TYPE::TIME ) );
157
158 // Displays the net length of internal ICs connections (wires inside ICs):
159 aList.emplace_back( _( "In Package" ),
160 aFrame->MessageTextFromValue( delayPadToDie, true, EDA_DATA_TYPE::TIME ) );
161 }
162 }
163 }
164}
165
166
167bool NETINFO_ITEM::Matches( const EDA_SEARCH_DATA& aSearchData, void* aAuxData ) const
168{
169 return BOARD_ITEM::Matches( GetNetname(), aSearchData );
170}
171
172
174{
175 static const std::vector<KICAD_T> netItemTypes = { PCB_TRACE_T,
176 PCB_ARC_T,
177 PCB_VIA_T,
179 PCB_PAD_T,
180 PCB_SHAPE_T };
181
182 std::shared_ptr<CONNECTIVITY_DATA> conn = GetBoard()->GetConnectivity();
183 BOX2I bbox;
184
185 for( BOARD_ITEM* item : conn->GetNetItems( m_netCode, netItemTypes ) )
186 bbox.Merge( item->GetBoundingBox() );
187
188 return bbox;
189}
190
191
193{
194 return m_shortNetname.StartsWith( wxT( "Net-(" ) )
195 || m_shortNetname.StartsWith( wxT( "unconnected-(" ) );
196}
197
198
199void NETINFO_ITEM::SetNetname( const wxString& aNewName )
200{
201 m_netname = aNewName;
202
203 if( aNewName.Contains( wxT( "/" ) ) )
204 m_shortNetname = aNewName.AfterLast( '/' );
205 else
206 m_shortNetname = aNewName;
207
209}
BOX2< VECTOR2I > BOX2I
Definition box2.h:922
std::shared_ptr< NET_SETTINGS > m_NetSettings
BOARD_ITEM(BOARD_ITEM *aParent, KICAD_T idtype, PCB_LAYER_ID aLayer=F_Cu)
Definition board_item.h:81
virtual const BOARD * GetBoard() const
Return the BOARD in which this BOARD_ITEM resides, or NULL if none.
Information pertinent to a Pcbnew printed circuit board.
Definition board.h:317
std::tuple< int, double, double, double, double > GetTrackLength(const PCB_TRACK &aTrack) const
Return data on the length and number of track segments connected to a given track.
Definition board.cpp:2523
const FOOTPRINTS & Footprints() const
Definition board.h:358
const TRACKS & Tracks() const
Definition board.h:356
BOARD_DESIGN_SETTINGS & GetDesignSettings() const
Definition board.cpp:1040
std::shared_ptr< CONNECTIVITY_DATA > GetConnectivity() const
Return a list of missing connections between components/tracks.
Definition board.h:521
constexpr BOX2< Vec > & Merge(const BOX2< Vec > &aRect)
Modify the position and size of the rectangle in order to contain aRect.
Definition box2.h:658
The base class for create windows for drawing purpose.
virtual bool Matches(const EDA_SEARCH_DATA &aSearchData, void *aAuxData) const
Compare the item against the search criteria in aSearchData.
Definition eda_item.h:401
bool Matches(const EDA_SEARCH_DATA &aSearchData, void *aAuxData) const override
Compare the item against the search criteria in aSearchData.
wxString m_shortNetname
Short net name, like vout from /sheet/subsheet/vout.
Definition netinfo.h:178
void SetNetname(const wxString &aNewName)
Set the long netname to aNetName, the short netname to the last token in the long netname's path,...
NETINFO_ITEM(BOARD *aParent, const wxString &aNetName=wxEmptyString, int aNetCode=-1)
NETINFO_ITEM class, to handle info on nets: netnames, net constraints.
wxString m_displayNetname
Unescaped netname for display.
Definition netinfo.h:180
const wxString & GetNetname() const
Definition netinfo.h:112
void Clear()
Set all fields to their default values.
int GetNetCode() const
Definition netinfo.h:106
int m_netCode
A number equivalent to the net name.
Definition netinfo.h:176
std::shared_ptr< NETCLASS > m_netClass
Definition netinfo.h:185
void GetMsgPanelInfo(EDA_DRAW_FRAME *aFrame, std::vector< MSG_PANEL_ITEM > &aList) override
Return the information about the NETINFO_ITEM in aList to display in the message panel.
bool HasAutoGeneratedNetname() const
wxString m_netname
Full net name like /sheet/subsheet/vout used by Eeschema.
Definition netinfo.h:177
const BOX2I GetBoundingBox() const override
Return the orthogonal bounding box of this object for display purposes.
bool m_isCurrent
Indicates the net is currently in use.
Definition netinfo.h:187
void SetNetClass(const std::shared_ptr< NETCLASS > &aNetClass)
BOARD * m_parent
The parent board the net belongs to.
Definition netinfo.h:191
std::shared_ptr< NETCLASS > GetDefaultNetclass()
Gets the default netclass for the project.
Definition pad.h:54
wxString MessageTextFromValue(double aValue, bool aAddUnitLabel=true, EDA_DATA_TYPE aType=EDA_DATA_TYPE::DISTANCE) const
A lower-precision version of StringFromValue().
#define _(s)
Message panel definition file.
wxString UnescapeString(const wxString &aSource)
@ PCB_SHAPE_T
class PCB_SHAPE, a segment not on copper layers
Definition typeinfo.h:88
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
Definition typeinfo.h:97
@ PCB_ZONE_T
class ZONE, a copper pour area
Definition typeinfo.h:107
@ PCB_PAD_T
class PAD, a pad in a footprint
Definition typeinfo.h:87
@ PCB_ARC_T
class PCB_ARC, an arc track segment on a copper layer
Definition typeinfo.h:98
@ PCB_NETINFO_T
class NETINFO_ITEM, a description of a net
Definition typeinfo.h:109
@ PCB_TRACE_T
class PCB_TRACK, a track segment (segment on a copper layer)
Definition typeinfo.h:96