KiCad PCB EDA Suite
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drc_test_provider_hole_size.cpp
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1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright The KiCad Developers.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, you may find one here:
18 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
19 * or you may search the http://www.gnu.org website for the version 2 license,
20 * or you may write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
22 */
23
25#include <footprint.h>
26#include <pad.h>
27#include <pcb_track.h>
29#include <drc/drc_engine.h>
30#include <drc/drc_item.h>
31#include <drc/drc_rule.h>
33
34/*
35 Drilled hole size test. scans vias/through-hole pads and checks for min drill sizes
36 Errors generated:
37 - DRCE_DRILL_OUT_OF_RANGE
38 - DRCE_MICROVIA_DRILL_OUT_OF_RANGE
39 - DRCE_PADSTACK
40*/
41
43{
44public:
46 {}
47
48 virtual ~DRC_TEST_PROVIDER_HOLE_SIZE() = default;
49
50 virtual bool Run() override;
51
52 virtual const wxString GetName() const override { return wxT( "hole_size" ); };
53
54private:
55 void checkViaHole( PCB_VIA* via, bool aExceedMicro, bool aExceedStd );
56 void checkPadHole( PAD* aPad );
57};
58
59
61{
63 {
64 if( !reportPhase( _( "Checking pad holes..." ) ) )
65 return false; // DRC cancelled
66
67 for( FOOTPRINT* footprint : m_drcEngine->GetBoard()->Footprints() )
68 {
69 for( PAD* pad : footprint->Pads() )
70 {
73 }
74 }
75 }
76
79 {
81 {
82 if( !reportPhase( _( "Checking via holes..." ) ) )
83 return false; // DRC cancelled
84 }
85 else
86 {
87 if( !reportPhase( _( "Checking micro-via holes..." ) ) )
88 return false; // DRC cancelled
89 }
90
91 for( PCB_TRACK* track : m_drcEngine->GetBoard()->Tracks() )
92 {
93 if( track->Type() == PCB_VIA_T )
94 {
97
98 if( exceedMicro && exceedStd )
99 break;
100
101 checkViaHole( static_cast<PCB_VIA*>( track ), exceedMicro, exceedStd );
102 }
103 }
104 }
105
106 return !m_drcEngine->IsCancelled();
107}
108
109
111{
112 int holeMinor = std::min( aPad->GetDrillSize().x, aPad->GetDrillSize().y );
113 int holeMajor = std::max( aPad->GetDrillSize().x, aPad->GetDrillSize().y );
114
115 if( holeMinor == 0 )
116 return;
117
118 auto constraint = m_drcEngine->EvalRules( HOLE_SIZE_CONSTRAINT, aPad, nullptr,
119 UNDEFINED_LAYER /* holes are not layer-specific */ );
120 bool fail_min = false;
121 bool fail_max = false;
122 int constraintValue = 0;
123
124 if( constraint.GetSeverity() == RPT_SEVERITY_IGNORE )
125 return;
126
127 if( constraint.Value().HasMin() && holeMinor < constraint.Value().Min() )
128 {
129 fail_min = true;
130 constraintValue = constraint.Value().Min();
131 }
132
133 if( constraint.Value().HasMax() && holeMajor > constraint.Value().Max() )
134 {
135 fail_max = true;
136 constraintValue = constraint.Value().Max();
137 }
138
139 if( fail_min || fail_max )
140 {
141 std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_DRILL_OUT_OF_RANGE );
142 wxString constraintName = constraint.GetName();
143 wxString msg;
144
145 if( fail_min )
146 {
147 if( constraint.GetParentRule() && constraint.GetParentRule()->m_Implicit )
148 constraintName = _( "board setup constraints" );
149
150 msg = formatMsg( _( "(%s min hole %s; actual %s)" ),
151 constraintName,
152 constraintValue,
153 holeMinor );
154 }
155 else
156 {
157 msg = formatMsg( _( "(%s max hole %s; actual %s)" ),
158 constraintName,
159 constraintValue,
160 holeMajor );
161 }
162
163 drcItem->SetErrorMessage( drcItem->GetErrorText() + wxS( " " ) + msg );
164 drcItem->SetItems( aPad );
165 drcItem->SetViolatingRule( constraint.GetParentRule() );
166
167 reportViolation( drcItem, aPad->GetPosition(), UNDEFINED_LAYER );
168 }
169}
170
171
172void DRC_TEST_PROVIDER_HOLE_SIZE::checkViaHole( PCB_VIA* via, bool aExceedMicro, bool aExceedStd )
173{
174 int errorCode;
175
176 if( via->GetViaType() == VIATYPE::MICROVIA )
177 {
178 if( aExceedMicro )
179 return;
180
182 }
183 else
184 {
185 if( aExceedStd )
186 return;
187
188 errorCode = DRCE_DRILL_OUT_OF_RANGE;
189 }
190
191 auto constraint = m_drcEngine->EvalRules( HOLE_SIZE_CONSTRAINT, via, nullptr,
192 UNDEFINED_LAYER /* holes are not layer-specific */ );
193 bool fail_min = false;
194 bool fail_max = false;
195 int constraintValue = 0;
196
197 if( constraint.GetSeverity() == RPT_SEVERITY_IGNORE )
198 return;
199
200 if( constraint.Value().HasMin() && via->GetDrillValue() < constraint.Value().Min() )
201 {
202 fail_min = true;
203 constraintValue = constraint.Value().Min();
204 }
205
206 if( constraint.Value().HasMax() && via->GetDrillValue() > constraint.Value().Max() )
207 {
208 fail_max = true;
209 constraintValue = constraint.Value().Max();
210 }
211
212 if( fail_min || fail_max )
213 {
214 std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( errorCode );
215 wxString constraintName = constraint.GetName();
216 wxString msg;
217
218 if( fail_min )
219 {
220 if( constraint.m_ImplicitMin )
221 constraintName = _( "board setup constraints" );
222
223 msg = formatMsg( _( "(%s min hole %s; actual %s)" ),
224 constraintName,
225 constraintValue,
226 via->GetDrillValue() );
227 }
228 else
229 {
230 msg = formatMsg( _( "(%s max hole %s; actual %s)" ),
231 constraintName,
232 constraintValue,
233 via->GetDrillValue() );
234 }
235
236 drcItem->SetErrorMessage( drcItem->GetErrorText() + wxS( " " ) + msg );
237 drcItem->SetItems( via );
238 drcItem->SetViolatingRule( constraint.GetParentRule() );
239
240 reportViolation( drcItem, via->GetPosition(), UNDEFINED_LAYER );
241 }
242}
243
244
245namespace detail
246{
248}
const FOOTPRINTS & Footprints() const
Definition: board.h:358
const TRACKS & Tracks() const
Definition: board.h:356
MINOPTMAX< int > & Value()
Definition: drc_rule.h:161
BOARD * GetBoard() const
Definition: drc_engine.h:100
bool IsErrorLimitExceeded(int error_code)
DRC_CONSTRAINT EvalRules(DRC_CONSTRAINT_T aConstraintType, const BOARD_ITEM *a, const BOARD_ITEM *b, PCB_LAYER_ID aLayer, REPORTER *aReporter=nullptr)
Definition: drc_engine.cpp:706
bool IsCancelled() const
static std::shared_ptr< DRC_ITEM > Create(int aErrorCode)
Constructs a DRC_ITEM for the given error code.
Definition: drc_item.cpp:393
virtual ~DRC_TEST_PROVIDER_HOLE_SIZE()=default
virtual bool Run() override
Run this provider against the given PCB with configured options (if any).
void checkViaHole(PCB_VIA *via, bool aExceedMicro, bool aExceedStd)
virtual const wxString GetName() const override
Represent a DRC "provider" which runs some DRC functions over a BOARD and spits out DRC_ITEM and posi...
virtual bool reportPhase(const wxString &aStageName)
virtual void reportViolation(std::shared_ptr< DRC_ITEM > &item, const VECTOR2I &aMarkerPos, int aMarkerLayer, DRC_CUSTOM_MARKER_HANDLER *aCustomHandler=nullptr)
DRC_ENGINE * m_drcEngine
wxString formatMsg(const wxString &aFormatString, const wxString &aSource, double aConstraint, double aActual, EDA_DATA_TYPE aDataType=EDA_DATA_TYPE::DISTANCE)
T Min() const
Definition: minoptmax.h:33
Definition: pad.h:54
const VECTOR2I & GetDrillSize() const
Definition: pad.h:305
VECTOR2I GetPosition() const override
Definition: pad.h:208
@ DRCE_DRILL_OUT_OF_RANGE
Definition: drc_item.h:60
@ DRCE_MICROVIA_DRILL_OUT_OF_RANGE
Definition: drc_item.h:64
@ HOLE_SIZE_CONSTRAINT
Definition: drc_rule.h:54
#define _(s)
@ UNDEFINED_LAYER
Definition: layer_ids.h:61
static DRC_REGISTER_TEST_PROVIDER< DRC_TEST_PROVIDER_ANNULAR_WIDTH > dummy
@ RPT_SEVERITY_IGNORE
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
Definition: typeinfo.h:97