52 virtual bool Run()
override;
54 virtual const wxString
GetName()
const override {
return wxT(
"connectivity" ); };
60 if( !
reportPhase(
_(
"Checking pad, via and zone connections..." ) ) )
64 std::shared_ptr<CONNECTIVITY_DATA> connectivity = board->
GetConnectivity();
66 int progressDelta = 250;
78 if( exceedV && exceedT )
80 else if( track->Type() ==
PCB_VIA_T && exceedV )
92 if( connectivity->TestTrackEndpointDangling( track,
true, &pos ) )
94 std::shared_ptr<DRC_ITEM> drcItem;
105 drcItem->SetViolatingRule( constraint.GetParentRule() );
112 drcItem->SetItems( track );
132 const std::list<CN_ITEM*>& items = connectivity->GetConnectivityAlgo()->ItemEntry( track ).GetItems();
137 CN_ITEM* citem = items.front();
139 if( !citem->
Valid() )
149 bool isPostMachined =
false;
154 isPostMachined =
pad->IsBackdrilledOrPostMachined( layer );
159 isPostMachined =
via->IsBackdrilledOrPostMachined( layer );
165 drcItem->SetItems( track, item );
167 VECTOR2I pos = ( track->GetStart() + track->GetEnd() ) / 2;
170 if( item->
HitTest( track->GetStart() ) )
171 pos = track->GetStart();
172 else if( item->
HitTest( track->GetEnd() ) )
173 pos = track->GetEnd();
191 for(
const auto& [ layer, layerIslands ] : zoneIslands )
193 for(
int polyIdx : layerIslands.m_IsolatedOutlines )
198 std::shared_ptr<SHAPE_POLY_SET> poly = zone->GetFilledPolysList( layer );
201 drcItem->SetItems( zone );
202 reportViolation( drcItem, poly->Outline( polyIdx ).CPoint( 0 ), layer );
210 if( !
reportPhase(
_(
"Checking net connections..." ) ) )
214 count = connectivity->GetUnconnectedCount(
false );
216 connectivity->RunOnUnconnectedEdges(
A base class derived from BOARD_ITEM for items that can be connected and have a net,...
Information pertinent to a Pcbnew printed circuit board.
std::map< ZONE *, std::map< PCB_LAYER_ID, ISOLATED_ISLANDS > > m_ZoneIsolatedIslandsMap
const TRACKS & Tracks() const
std::shared_ptr< CONNECTIVITY_DATA > GetConnectivity() const
Return a list of missing connections between components/tracks.
const VECTOR2I & Pos() const
BOARD_CONNECTED_ITEM * Parent() const
CN_EDGE represents a point-to-point connection, whether realized or unrealized (ie: tracks etc.
std::shared_ptr< const CN_ANCHOR > GetSourceNode() const
std::shared_ptr< const CN_ANCHOR > GetTargetNode() const
CN_ITEM represents a BOARD_CONNETED_ITEM in the connectivity system (ie: a pad, track/arc/via,...
const std::vector< CN_ITEM * > & ConnectedItems() const
static std::shared_ptr< DRC_ITEM > Create(int aErrorCode)
Constructs a DRC_ITEM for the given error code.
virtual bool Run() override
Run this provider against the given PCB with configured options (if any).
virtual ~DRC_TEST_PROVIDER_CONNECTIVITY()=default
virtual const wxString GetName() const override
DRC_TEST_PROVIDER_CONNECTIVITY()
virtual bool reportPhase(const wxString &aStageName)
void reportViolation(std::shared_ptr< DRC_ITEM > &item, const VECTOR2I &aMarkerPos, int aMarkerLayer, const std::function< void(PCB_MARKER *)> &aPathGenerator=[](PCB_MARKER *){})
virtual bool reportProgress(size_t aCount, size_t aSize, size_t aDelta=1)
KICAD_T Type() const
Returns the type of object.
virtual bool HitTest(const VECTOR2I &aPosition, int aAccuracy=0) const
Test if aPosition is inside or on the boundary of this item.
EDA_ITEM_FLAGS GetFlags() const
@ DRCE_TRACK_ON_POST_MACHINED_LAYER
@ VIA_DANGLING_CONSTRAINT
PCB_LAYER_ID
A quick note on layer IDs:
static DRC_REGISTER_TEST_PROVIDER< DRC_TEST_PROVIDER_ANNULAR_WIDTH > dummy
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
@ PCB_PAD_T
class PAD, a pad in a footprint
@ PCB_ARC_T
class PCB_ARC, an arc track segment on a copper layer
@ PCB_TRACE_T
class PCB_TRACK, a track segment (segment on a copper layer)
VECTOR2< int32_t > VECTOR2I