55 virtual bool Run()
override;
57 virtual const wxString
GetName()
const override
59 return wxT(
"connectivity" );
64 return wxT(
"Tests board connectivity" );
71 if( !
reportPhase(
_(
"Checking pad, via and zone connections..." ) ) )
75 std::shared_ptr<CONNECTIVITY_DATA> connectivity = board->
GetConnectivity();
77 int progressDelta = 250;
89 if( exceedV && exceedT )
91 else if( track->Type() ==
PCB_VIA_T && exceedV )
103 if( connectivity->TestTrackEndpointDangling( track,
true, &pos ) )
106 drcItem->SetItems( track );
120 for(
const auto& [ layer, layerIslands ] : zoneIslands )
122 for(
int polyIdx : layerIslands.m_IsolatedOutlines )
127 std::shared_ptr<SHAPE_POLY_SET> poly = zone->GetFilledPolysList( layer );
130 drcItem->SetItems( zone );
131 reportViolation( drcItem, poly->Outline( polyIdx ).CPoint( 0 ), layer );
139 if( !
reportPhase(
_(
"Checking net connections..." ) ) )
143 count = connectivity->GetUnconnectedCount(
false );
145 connectivity->RunOnUnconnectedEdges(
Information pertinent to a Pcbnew printed circuit board.
std::map< ZONE *, std::map< PCB_LAYER_ID, ISOLATED_ISLANDS > > m_ZoneIsolatedIslandsMap
const TRACKS & Tracks() const
std::shared_ptr< CONNECTIVITY_DATA > GetConnectivity() const
Return a list of missing connections between components/tracks.
CN_EDGE represents a point-to-point connection, whether realized or unrealized (ie: tracks etc.
std::shared_ptr< const CN_ANCHOR > GetSourceNode() const
std::shared_ptr< const CN_ANCHOR > GetTargetNode() const
bool IsErrorLimitExceeded(int error_code)
static std::shared_ptr< DRC_ITEM > Create(int aErrorCode)
Constructs a DRC_ITEM for the given error code.
virtual bool Run() override
Run this provider against the given PCB with configured options (if any).
virtual ~DRC_TEST_PROVIDER_CONNECTIVITY()
virtual const wxString GetName() const override
DRC_TEST_PROVIDER_CONNECTIVITY()
virtual const wxString GetDescription() const override
Represent a DRC "provider" which runs some DRC functions over a BOARD and spits out DRC_ITEM and posi...
virtual bool reportPhase(const wxString &aStageName)
virtual void reportViolation(std::shared_ptr< DRC_ITEM > &item, const VECTOR2I &aMarkerPos, int aMarkerLayer)
virtual void reportRuleStatistics()
virtual bool reportProgress(size_t aCount, size_t aSize, size_t aDelta=1)
static DRC_REGISTER_TEST_PROVIDER< DRC_TEST_PROVIDER_ANNULAR_WIDTH > dummy
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
@ PCB_TRACE_T
class PCB_TRACK, a track segment (segment on a copper layer)