KiCad PCB EDA Suite
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drc_test_provider_connectivity.cpp
Go to the documentation of this file.
1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright (C) 2004-2023 KiCad Developers.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, you may find one here:
18 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
19 * or you may search the http://www.gnu.org website for the version 2 license,
20 * or you may write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
22 */
23
24#include <board.h>
25#include <common.h>
26
29#include <zone.h>
30#include <drc/drc_engine.h>
31#include <drc/drc_item.h>
32#include <drc/drc_rule.h>
34
35
36/*
37 Connectivity test provider. Not rule-driven.
38 Errors generated:
39 - DRCE_DANGLING_TRACK
40 - DRCE_DANGLING_VIA
41 - DRCE_ISOLATED_COPPER
42*/
43
45{
46public:
48 {
49 }
50
52 {
53 }
54
55 virtual bool Run() override;
56
57 virtual const wxString GetName() const override
58 {
59 return wxT( "connectivity" );
60 };
61
62 virtual const wxString GetDescription() const override
63 {
64 return wxT( "Tests board connectivity" );
65 }
66};
67
68
70{
71 if( !reportPhase( _( "Checking pad, via and zone connections..." ) ) )
72 return false; // DRC cancelled
73
74 BOARD* board = m_drcEngine->GetBoard();
75 std::shared_ptr<CONNECTIVITY_DATA> connectivity = board->GetConnectivity();
76
77 int progressDelta = 250;
78 int ii = 0;
79 int count = board->Tracks().size() + board->m_ZoneIsolatedIslandsMap.size();
80
81 ii += count; // We gave half of this phase to CONNECTIVITY_DATA::Build()
82 count += count;
83
84 for( PCB_TRACK* track : board->Tracks() )
85 {
88
89 if( exceedV && exceedT )
90 break;
91 else if( track->Type() == PCB_VIA_T && exceedV )
92 continue;
93 else if( track->Type() == PCB_TRACE_T && exceedT )
94 continue;
95
96 if( !reportProgress( ii++, count, progressDelta ) )
97 return false; // DRC cancelled
98
99 // Test for dangling items
100 int code = track->Type() == PCB_VIA_T ? DRCE_DANGLING_VIA : DRCE_DANGLING_TRACK;
101 VECTOR2I pos;
102
103 if( connectivity->TestTrackEndpointDangling( track, true, &pos ) )
104 {
105 std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( code );
106 drcItem->SetItems( track );
107 reportViolation( drcItem, pos, track->GetLayer() );
108 }
109 }
110
111 /* test starved zones */
112 for( const auto& [ zone, zoneIslands ] : board->m_ZoneIsolatedIslandsMap )
113 {
115 break;
116
117 if( !reportProgress( ii++, count, progressDelta ) )
118 return false; // DRC cancelled
119
120 for( const auto& [ layer, layerIslands ] : zoneIslands )
121 {
122 for( int polyIdx : layerIslands.m_IsolatedOutlines )
123 {
125 break;
126
127 std::shared_ptr<SHAPE_POLY_SET> poly = zone->GetFilledPolysList( layer );
128
129 std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_ISOLATED_COPPER );
130 drcItem->SetItems( zone );
131 reportViolation( drcItem, poly->Outline( polyIdx ).CPoint( 0 ), layer );
132 }
133 }
134 }
135
137 return true; // continue with other tests
138
139 if( !reportPhase( _( "Checking net connections..." ) ) )
140 return false; // DRC cancelled
141
142 ii = 0;
143 count = connectivity->GetUnconnectedCount( false );
144
145 connectivity->RunOnUnconnectedEdges(
146 [&]( CN_EDGE& edge )
147 {
149 return false;
150
151 if( !reportProgress( ii++, count, progressDelta ) )
152 return false; // DRC cancelled
153
154 wxCHECK( edge.GetSourceNode() && !edge.GetSourceNode()->Dirty(), true );
155 wxCHECK( edge.GetTargetNode() && !edge.GetTargetNode()->Dirty(), true );
156
157 std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_UNCONNECTED_ITEMS );
158 drcItem->SetItems( edge.GetSourceNode()->Parent(), edge.GetTargetNode()->Parent() );
159 reportViolation( drcItem, edge.GetSourceNode()->Pos(), UNDEFINED_LAYER );
160
161 return true;
162 } );
163
165
166 return !m_drcEngine->IsCancelled();
167}
168
169
170namespace detail
171{
173}
Information pertinent to a Pcbnew printed circuit board.
Definition: board.h:290
std::map< ZONE *, std::map< PCB_LAYER_ID, ISOLATED_ISLANDS > > m_ZoneIsolatedIslandsMap
Definition: board.h:1309
const TRACKS & Tracks() const
Definition: board.h:329
std::shared_ptr< CONNECTIVITY_DATA > GetConnectivity() const
Return a list of missing connections between components/tracks.
Definition: board.h:475
CN_EDGE represents a point-to-point connection, whether realized or unrealized (ie: tracks etc.
std::shared_ptr< const CN_ANCHOR > GetSourceNode() const
std::shared_ptr< const CN_ANCHOR > GetTargetNode() const
BOARD * GetBoard() const
Definition: drc_engine.h:99
bool IsErrorLimitExceeded(int error_code)
bool IsCancelled() const
static std::shared_ptr< DRC_ITEM > Create(int aErrorCode)
Constructs a DRC_ITEM for the given error code.
Definition: drc_item.cpp:372
virtual bool Run() override
Run this provider against the given PCB with configured options (if any).
virtual const wxString GetName() const override
virtual const wxString GetDescription() const override
Represent a DRC "provider" which runs some DRC functions over a BOARD and spits out DRC_ITEM and posi...
virtual bool reportPhase(const wxString &aStageName)
virtual void reportViolation(std::shared_ptr< DRC_ITEM > &item, const VECTOR2I &aMarkerPos, int aMarkerLayer)
DRC_ENGINE * m_drcEngine
virtual void reportRuleStatistics()
virtual bool reportProgress(size_t aCount, size_t aSize, size_t aDelta=1)
The common library.
@ DRCE_UNCONNECTED_ITEMS
Definition: drc_item.h:39
@ DRCE_ISOLATED_COPPER
Definition: drc_item.h:48
@ DRCE_DANGLING_VIA
Definition: drc_item.h:50
@ DRCE_DANGLING_TRACK
Definition: drc_item.h:51
#define _(s)
@ UNDEFINED_LAYER
Definition: layer_ids.h:61
static DRC_REGISTER_TEST_PROVIDER< DRC_TEST_PROVIDER_ANNULAR_WIDTH > dummy
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
Definition: typeinfo.h:97
@ PCB_TRACE_T
class PCB_TRACK, a track segment (segment on a copper layer)
Definition: typeinfo.h:96