55 virtual bool Run()
override;
57 virtual const wxString
GetName()
const override 59 return wxT(
"connectivity" );
64 return wxT(
"Tests board connectivity" );
75 if( !
reportPhase(
_(
"Checking pad, via and zone connections..." ) ) )
80 std::shared_ptr<CONNECTIVITY_DATA> connectivity = board->
GetConnectivity();
83 connectivity->Clear();
88 int count = board->
Tracks().size() + board->
Zones().size();
98 if( exceedV && exceedT )
100 else if( track->Type() ==
PCB_VIA_T && exceedV )
112 if( connectivity->TestTrackEndpointDangling( track, &pos ) )
115 drcItem->SetItems( track );
126 if( !zone->IsOnCopperLayer() )
132 int netcode = zone->GetNetCode();
136 int pads_in_net = ( netcode > 0 ) ? connectivity->GetPadCount( netcode ) : 1;
138 if( ( netcode < 0 ) || pads_in_net == 0 )
141 drcItem->SetItems( zone );
149 if( !
reportPhase(
_(
"Checking net connections..." ) ) )
152 std::vector<CN_EDGE> edges;
153 connectivity->GetUnconnectedEdges( edges );
157 count = edges.size();
159 for(
const CN_EDGE& edge : edges )
168 drcItem->SetItems( edge.GetSourceNode()->Parent(), edge.GetTargetNode()->Parent() );
static std::shared_ptr< DRC_ITEM > Create(int aErrorCode)
Constructs a DRC_ITEM for the given error code.
virtual void reportViolation(std::shared_ptr< DRC_ITEM > &item, const wxPoint &aMarkerPos)
virtual ~DRC_TEST_PROVIDER_CONNECTIVITY()
bool IsErrorLimitExceeded(int error_code)
virtual bool reportProgress(int aCount, int aSize, int aDelta)
virtual const wxString GetName() const override
int GetNumPhases() const override
PROGRESS_REPORTER * GetProgressReporter() const
virtual void reportRuleStatistics()
class PCB_TRACK, a track segment (segment on a copper layer)
static DRC_REGISTER_TEST_PROVIDER< DRC_TEST_PROVIDER_ANNULAR_WIDTH > dummy
virtual bool Run() override
Run this provider against the given PCB with configured options (if any).
virtual bool reportPhase(const wxString &aStageName)
virtual const wxString GetDescription() const override
std::shared_ptr< CONNECTIVITY_DATA > GetConnectivity() const
Return a list of missing connections between components/tracks.
Handle a list of polygons defining a copper zone.
Represent a DRC "provider" which runs some DRC functions over a BOARD and spits out #DRC_ITEMs and po...
CN_EDGE represents a point-to-point connection, whether realized or unrealized (ie: tracks etc.
Information pertinent to a Pcbnew printed circuit board.
class PCB_VIA, a via (like a track segment on a copper layer)
DRC_TEST_PROVIDER_CONNECTIVITY()
virtual std::set< DRC_CONSTRAINT_T > GetConstraintTypes() const override