KiCad PCB EDA Suite
drc_test_provider_connectivity.cpp
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1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright (C) 2004-2022 KiCad Developers.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, you may find one here:
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20 * or you may write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
22 */
23
24#include <board.h>
25#include <common.h>
26
29
30#include <drc/drc_engine.h>
31#include <drc/drc_item.h>
32#include <drc/drc_rule.h>
34
35
36/*
37 Connectivity test provider. Not rule-driven.
38 Errors generated:
39 - DRCE_DANGLING_TRACK
40 - DRCE_DANGLING_VIA
41 - DRCE_ISOLATED_COPPER
42*/
43
45{
46public:
48 {
49 }
50
52 {
53 }
54
55 virtual bool Run() override;
56
57 virtual const wxString GetName() const override
58 {
59 return wxT( "connectivity" );
60 };
61
62 virtual const wxString GetDescription() const override
63 {
64 return wxT( "Tests board connectivity" );
65 }
66};
67
68
70{
71 if( !reportPhase( _( "Checking pad, via and zone connections..." ) ) )
72 return false; // DRC cancelled
73
74 BOARD* board = m_drcEngine->GetBoard();
75
76 std::shared_ptr<CONNECTIVITY_DATA> connectivity = board->GetConnectivity();
77 std::vector<CN_ZONE_ISOLATED_ISLAND_LIST> islandsList;
78
79 for( ZONE* zone : board->Zones() )
80 {
81 if( !zone->GetIsRuleArea() )
82 islandsList.emplace_back( CN_ZONE_ISOLATED_ISLAND_LIST( zone ) );
83 }
84
85 // Rebuild (from scratch, ignoring dirty flags) just in case. This really needs to be reliable.
86 connectivity->Clear();
87 connectivity->Build( board, m_drcEngine->GetProgressReporter() );
88 connectivity->FindIsolatedCopperIslands( islandsList, true );
89
90 int progressDelta = 250;
91 int ii = 0;
92 int count = board->Tracks().size() + islandsList.size();
93
94 ii += count; // We gave half of this phase to CONNECTIVITY_DATA::Build()
95 count += count;
96
97 for( PCB_TRACK* track : board->Tracks() )
98 {
101
102 if( exceedV && exceedT )
103 break;
104 else if( track->Type() == PCB_VIA_T && exceedV )
105 continue;
106 else if( track->Type() == PCB_TRACE_T && exceedT )
107 continue;
108
109 if( !reportProgress( ii++, count, progressDelta ) )
110 return false; // DRC cancelled
111
112 // Test for dangling items
113 int code = track->Type() == PCB_VIA_T ? DRCE_DANGLING_VIA : DRCE_DANGLING_TRACK;
114 VECTOR2I pos;
115
116 if( connectivity->TestTrackEndpointDangling( track, &pos ) )
117 {
118 std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( code );
119 drcItem->SetItems( track );
120 reportViolation( drcItem, pos, track->GetLayer() );
121 }
122 }
123
124 /* test starved zones */
125 for( CN_ZONE_ISOLATED_ISLAND_LIST& zone : islandsList )
126 {
128 break;
129
130 if( !reportProgress( ii++, count, progressDelta ) )
131 return false; // DRC cancelled
132
133 for( PCB_LAYER_ID layer : zone.m_zone->GetLayerSet().Seq() )
134 {
135 if( !zone.m_islands.count( layer ) )
136 continue;
137
138 std::shared_ptr<SHAPE_POLY_SET> poly = zone.m_zone->GetFilledPolysList( layer );
139
140 for( int idx : zone.m_islands.at( layer ) )
141 {
143 break;
144
145 std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_ISOLATED_COPPER );
146 drcItem->SetItems( zone.m_zone );
147 reportViolation( drcItem, poly->Outline( idx ).CPoint( 0 ), layer );
148 }
149 }
150 }
151
153 return true; // continue with other tests
154
155 if( !reportPhase( _( "Checking net connections..." ) ) )
156 return false; // DRC cancelled
157
158 ii = 0;
159 count = connectivity->GetUnconnectedCount( false );
160
161 connectivity->RunOnUnconnectedEdges(
162 [&]( CN_EDGE& edge )
163 {
165 return false;
166
167 if( !reportProgress( ii++, count, progressDelta ) )
168 return false; // DRC cancelled
169
170 std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_UNCONNECTED_ITEMS );
171 drcItem->SetItems( edge.GetSourceNode()->Parent(), edge.GetTargetNode()->Parent() );
172 reportViolation( drcItem, edge.GetSourceNode()->Pos(), UNDEFINED_LAYER );
173
174 return true;
175 } );
176
178
179 return !m_drcEngine->IsCancelled();
180}
181
182
183namespace detail
184{
186}
Information pertinent to a Pcbnew printed circuit board.
Definition: board.h:265
ZONES & Zones()
Definition: board.h:313
TRACKS & Tracks()
Definition: board.h:304
std::shared_ptr< CONNECTIVITY_DATA > GetConnectivity() const
Return a list of missing connections between components/tracks.
Definition: board.h:424
CN_EDGE represents a point-to-point connection, whether realized or unrealized (ie: tracks etc.
std::shared_ptr< CN_ANCHOR > GetTargetNode() const
std::shared_ptr< CN_ANCHOR > GetSourceNode() const
BOARD * GetBoard() const
Definition: drc_engine.h:89
bool IsErrorLimitExceeded(int error_code)
PROGRESS_REPORTER * GetProgressReporter() const
Definition: drc_engine.h:124
bool IsCancelled() const
static std::shared_ptr< DRC_ITEM > Create(int aErrorCode)
Constructs a DRC_ITEM for the given error code.
Definition: drc_item.cpp:325
virtual bool Run() override
Run this provider against the given PCB with configured options (if any).
virtual const wxString GetName() const override
virtual const wxString GetDescription() const override
Represent a DRC "provider" which runs some DRC functions over a BOARD and spits out #DRC_ITEMs and po...
virtual bool reportPhase(const wxString &aStageName)
virtual bool reportProgress(int aCount, int aSize, int aDelta)
virtual void reportViolation(std::shared_ptr< DRC_ITEM > &item, const VECTOR2I &aMarkerPos, int aMarkerLayer)
DRC_ENGINE * m_drcEngine
virtual void reportRuleStatistics()
Handle a list of polygons defining a copper zone.
Definition: zone.h:57
The common library.
@ DRCE_UNCONNECTED_ITEMS
Definition: drc_item.h:39
@ DRCE_ISOLATED_COPPER
Definition: drc_item.h:47
@ DRCE_DANGLING_VIA
Definition: drc_item.h:49
@ DRCE_DANGLING_TRACK
Definition: drc_item.h:50
#define _(s)
PCB_LAYER_ID
A quick note on layer IDs:
Definition: layer_ids.h:59
@ UNDEFINED_LAYER
Definition: layer_ids.h:60
static DRC_REGISTER_TEST_PROVIDER< DRC_TEST_PROVIDER_ANNULAR_WIDTH > dummy
A structure used for calculating isolated islands on a given zone across all its layers.
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
Definition: typeinfo.h:102
@ PCB_TRACE_T
class PCB_TRACK, a track segment (segment on a copper layer)
Definition: typeinfo.h:101