KiCad PCB EDA Suite
Loading...
Searching...
No Matches
drc_test_provider_connectivity.cpp
Go to the documentation of this file.
1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright The KiCad Developers.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, you may find one here:
18 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
19 * or you may search the http://www.gnu.org website for the version 2 license,
20 * or you may write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
22 */
23
24#include <board.h>
25#include <common.h>
26
29#include <zone.h>
30#include <drc/drc_item.h>
32
33
34/*
35 Connectivity test provider. Not rule-driven.
36 Errors generated:
37 - DRCE_DANGLING_TRACK
38 - DRCE_DANGLING_VIA
39 - DRCE_ISOLATED_COPPER
40*/
41
43{
44public:
47
49
50 virtual bool Run() override;
51
52 virtual const wxString GetName() const override { return wxT( "connectivity" ); };
53};
54
55
57{
58 if( !reportPhase( _( "Checking pad, via and zone connections..." ) ) )
59 return false; // DRC cancelled
60
61 BOARD* board = m_drcEngine->GetBoard();
62 std::shared_ptr<CONNECTIVITY_DATA> connectivity = board->GetConnectivity();
63
64 int progressDelta = 250;
65 int ii = 0;
66 int count = board->Tracks().size() + board->m_ZoneIsolatedIslandsMap.size();
67
68 ii += count; // We gave half of this phase to CONNECTIVITY_DATA::Build()
69 count += count;
70
71 for( PCB_TRACK* track : board->Tracks() )
72 {
73 bool exceedT = m_drcEngine->IsErrorLimitExceeded( DRCE_DANGLING_TRACK );
74 bool exceedV = m_drcEngine->IsErrorLimitExceeded( DRCE_DANGLING_VIA );
75
76 if( exceedV && exceedT )
77 break;
78 else if( track->Type() == PCB_VIA_T && exceedV )
79 continue;
80 else if( track->Type() == PCB_TRACE_T && exceedT )
81 continue;
82
83 if( !reportProgress( ii++, count, progressDelta ) )
84 return false; // DRC cancelled
85
86 // Test for dangling items
87 int code = track->Type() == PCB_VIA_T ? DRCE_DANGLING_VIA : DRCE_DANGLING_TRACK;
88 VECTOR2I pos;
89
90 if( connectivity->TestTrackEndpointDangling( track, true, &pos ) )
91 {
92 std::shared_ptr<DRC_ITEM> drcItem;
93
94 if( track->Type() == PCB_VIA_T )
95 {
96 auto constraint = m_drcEngine->EvalRules( VIA_DANGLING_CONSTRAINT, track, nullptr,
97 track->GetLayer() );
98
99 if( constraint.GetSeverity() == RPT_SEVERITY_IGNORE )
100 continue;
101
102 drcItem = DRC_ITEM::Create( code );
103 drcItem->SetViolatingRule( constraint.GetParentRule() );
104 }
105 else
106 {
107 drcItem = DRC_ITEM::Create( code );
108 }
109
110 drcItem->SetItems( track );
111 reportViolation( drcItem, pos, track->GetLayer() );
112 }
113 }
114
115 /* test starved zones */
116 for( const auto& [ zone, zoneIslands ] : board->m_ZoneIsolatedIslandsMap )
117 {
118 if( m_drcEngine->IsErrorLimitExceeded( DRCE_ISOLATED_COPPER ) )
119 break;
120
121 if( !reportProgress( ii++, count, progressDelta ) )
122 return false; // DRC cancelled
123
124 for( const auto& [ layer, layerIslands ] : zoneIslands )
125 {
126 for( int polyIdx : layerIslands.m_IsolatedOutlines )
127 {
128 if( m_drcEngine->IsErrorLimitExceeded( DRCE_ISOLATED_COPPER ) )
129 break;
130
131 std::shared_ptr<SHAPE_POLY_SET> poly = zone->GetFilledPolysList( layer );
132
133 std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_ISOLATED_COPPER );
134 drcItem->SetItems( zone );
135 reportViolation( drcItem, poly->Outline( polyIdx ).CPoint( 0 ), layer );
136 }
137 }
138 }
139
140 if( m_drcEngine->IsErrorLimitExceeded( DRCE_UNCONNECTED_ITEMS ) )
141 return true; // continue with other tests
142
143 if( !reportPhase( _( "Checking net connections..." ) ) )
144 return false; // DRC cancelled
145
146 ii = 0;
147 count = connectivity->GetUnconnectedCount( false );
148
149 connectivity->RunOnUnconnectedEdges(
150 [&]( CN_EDGE& edge )
151 {
152 if( m_drcEngine->IsErrorLimitExceeded( DRCE_UNCONNECTED_ITEMS ) )
153 return false;
154
155 if( !reportProgress( ii++, count, progressDelta ) )
156 return false; // DRC cancelled
157
158 wxCHECK( edge.GetSourceNode() && !edge.GetSourceNode()->Dirty(), true );
159 wxCHECK( edge.GetTargetNode() && !edge.GetTargetNode()->Dirty(), true );
160
161 std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_UNCONNECTED_ITEMS );
162 drcItem->SetItems( edge.GetSourceNode()->Parent(), edge.GetTargetNode()->Parent() );
163 reportViolation( drcItem, edge.GetSourceNode()->Pos(), UNDEFINED_LAYER );
164
165 return true;
166 } );
167
168 return !m_drcEngine->IsCancelled();
169}
170
171
172namespace detail
173{
175}
Information pertinent to a Pcbnew printed circuit board.
Definition board.h:317
std::map< ZONE *, std::map< PCB_LAYER_ID, ISOLATED_ISLANDS > > m_ZoneIsolatedIslandsMap
Definition board.h:1385
const TRACKS & Tracks() const
Definition board.h:356
std::shared_ptr< CONNECTIVITY_DATA > GetConnectivity() const
Return a list of missing connections between components/tracks.
Definition board.h:521
const VECTOR2I & Pos() const
bool Dirty() const
BOARD_CONNECTED_ITEM * Parent() const
CN_EDGE represents a point-to-point connection, whether realized or unrealized (ie: tracks etc.
std::shared_ptr< const CN_ANCHOR > GetSourceNode() const
std::shared_ptr< const CN_ANCHOR > GetTargetNode() const
static std::shared_ptr< DRC_ITEM > Create(int aErrorCode)
Constructs a DRC_ITEM for the given error code.
Definition drc_item.cpp:381
virtual bool Run() override
Run this provider against the given PCB with configured options (if any).
virtual ~DRC_TEST_PROVIDER_CONNECTIVITY()=default
virtual const wxString GetName() const override
virtual bool reportPhase(const wxString &aStageName)
virtual void reportViolation(std::shared_ptr< DRC_ITEM > &item, const VECTOR2I &aMarkerPos, int aMarkerLayer, const std::vector< PCB_SHAPE > &aShapes={})
virtual bool reportProgress(size_t aCount, size_t aSize, size_t aDelta=1)
The common library.
@ DRCE_UNCONNECTED_ITEMS
Definition drc_item.h:39
@ DRCE_ISOLATED_COPPER
Definition drc_item.h:48
@ DRCE_DANGLING_VIA
Definition drc_item.h:50
@ DRCE_DANGLING_TRACK
Definition drc_item.h:51
@ VIA_DANGLING_CONSTRAINT
Definition drc_rule.h:82
#define _(s)
@ UNDEFINED_LAYER
Definition layer_ids.h:61
static DRC_REGISTER_TEST_PROVIDER< DRC_TEST_PROVIDER_ANNULAR_WIDTH > dummy
@ RPT_SEVERITY_IGNORE
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
Definition typeinfo.h:97
@ PCB_TRACE_T
class PCB_TRACK, a track segment (segment on a copper layer)
Definition typeinfo.h:96
VECTOR2< int32_t > VECTOR2I
Definition vector2d.h:695