KiCad PCB EDA Suite
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drc_test_provider_silk_clearance.cpp
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1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright The KiCad Developers.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, you may find one here:
18 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
19 * or you may search the http://www.gnu.org website for the version 2 license,
20 * or you may write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
22 */
23
24#include <common.h>
25#include <board.h>
26#include <pcb_track.h>
28#include <geometry/seg.h>
29#include <drc/drc_engine.h>
30#include <drc/drc_item.h>
31#include <drc/drc_rule.h>
33#include <drc/drc_rtree.h>
34
35/*
36 Silk to silk clearance test. Check all silkscreen features against each other.
37 Errors generated:
38 - DRCE_OVERLAPPING_SILK
39
40*/
41
43{
44public:
46 m_board( nullptr ),
48 {}
49
51
52 virtual bool Run() override;
53
54 virtual const wxString GetName() const override { return wxT( "silk_clearance" ); };
55
56private:
57
60};
61
62
64{
65 const int progressDelta = 500;
66
68
69 // If the soldermask min width is greater than 0 then we must use a healing algorithm to generate
70 // a whole-board soldermask poly, and then test against that. However, that can't deal well with
71 // DRC exclusions (as any change anywhere on the board that affects the soldermask will null the
72 // associated exclusions), so we only use that when soldermask min width is > 0.
73 bool checkIndividualMaskItems = m_board->GetDesignSettings().m_SolderMaskMinWidth <= 0;
74
77 {
78 return true; // continue with other tests
79 }
80
81 DRC_CONSTRAINT worstClearanceConstraint;
83
84 if( m_drcEngine->QueryWorstConstraint( SILK_CLEARANCE_CONSTRAINT, worstClearanceConstraint ) )
85 m_largestClearance = worstClearanceConstraint.m_Value.Min();
86
87 if( !reportPhase( _( "Checking silkscreen for overlapping items..." ) ) )
88 return false; // DRC cancelled
89
90 DRC_RTREE silkTree;
91 DRC_RTREE targetTree;
92 int ii = 0;
93 int items = 0;
94 LSET silkLayers = LSET( { F_SilkS, B_SilkS } );
95 LSET targetLayers = LSET::FrontMask() | LSET::BackMask() | LSET( { Edge_Cuts, Margin } );
96
97 auto countItems =
98 [&]( BOARD_ITEM* item ) -> bool
99 {
100 ++items;
101 return true;
102 };
103
104 auto addToSilkTree =
105 [&]( BOARD_ITEM* item ) -> bool
106 {
107 if( !reportProgress( ii++, items, progressDelta ) )
108 return false;
109
110 for( PCB_LAYER_ID layer : { F_SilkS, B_SilkS } )
111 {
112 if( item->IsOnLayer( layer ) )
113 silkTree.Insert( item, layer );
114 }
115
116 return true;
117 };
118
119 auto addToTargetTree =
120 [&]( BOARD_ITEM* item ) -> bool
121 {
122 if( !reportProgress( ii++, items, progressDelta ) )
123 return false;
124
125 for( PCB_LAYER_ID layer : LSET( item->GetLayerSet() & targetLayers ) )
126 targetTree.Insert( item, layer );
127
128 return true;
129 };
130
131 forEachGeometryItem( s_allBasicItems, silkLayers, countItems );
132 forEachGeometryItem( s_allBasicItems, targetLayers, countItems );
133
134 forEachGeometryItem( s_allBasicItems, silkLayers, addToSilkTree );
135 forEachGeometryItem( s_allBasicItems, targetLayers, addToTargetTree );
136
137 REPORT_AUX( wxString::Format( wxT( "Testing %d silkscreen features against %d board items." ),
138 silkTree.size(),
139 targetTree.size() ) );
140
141 const std::vector<DRC_RTREE::LAYER_PAIR> layerPairs =
142 {
161 };
162
163 targetTree.QueryCollidingPairs( &silkTree, layerPairs,
164 [&]( const DRC_RTREE::LAYER_PAIR& aLayers, DRC_RTREE::ITEM_WITH_SHAPE* aRefItemShape,
165 DRC_RTREE::ITEM_WITH_SHAPE* aTestItemShape, bool* aCollisionDetected ) -> bool
166 {
167 BOARD_ITEM* refItem = aRefItemShape->parent;
168 const SHAPE* refShape = aRefItemShape->shape;
169 BOARD_ITEM* testItem = aTestItemShape->parent;
170 const SHAPE* testShape = aTestItemShape->shape;
171
172 std::shared_ptr<SHAPE> hole;
173
176 {
177 return false;
178 }
179
180 if( isInvisibleText( refItem ) || isInvisibleText( testItem ) )
181 return true;
182
183 if( testItem->IsTented( aLayers.first ) )
184 {
185 if( testItem->HasHole() )
186 {
187 hole = testItem->GetEffectiveHoleShape();
188 testShape = hole.get();
189 }
190 else
191 {
192 return true;
193 }
194 }
195
196 int errorCode = DRCE_OVERLAPPING_SILK;
198 refItem, testItem, aLayers.second );
199 int minClearance = -1;
200
201 if( !constraint.IsNull() && constraint.GetSeverity() != RPT_SEVERITY_IGNORE )
202 minClearance = constraint.GetValue().Min();
203
204 if( aLayers.second == F_Mask || aLayers.second == B_Mask )
205 {
206 if( checkIndividualMaskItems )
207 minClearance = std::max( minClearance, 0 );
208
209 errorCode = DRCE_SILK_MASK_CLEARANCE;
210 }
211
212 if( minClearance < 0 || m_drcEngine->IsErrorLimitExceeded( errorCode ) )
213 return true;
214
215 int actual;
216 VECTOR2I pos;
217
218 // Graphics are often compound shapes so ignore collisions between shapes in a
219 // single footprint or on the board (both parent footprints will be nullptr).
220 if( refItem->Type() == PCB_SHAPE_T && testItem->Type() == PCB_SHAPE_T
221 && refItem->GetParentFootprint() == testItem->GetParentFootprint() )
222 {
223 return true;
224 }
225
226 // Collide (and generate violations) based on a well-defined order so that
227 // exclusion checking against previously-generated violations will work.
228 if( aLayers.first == aLayers.second )
229 {
230 if( refItem->m_Uuid > testItem->m_Uuid )
231 {
232 std::swap( refItem, testItem );
233 std::swap( refShape, testShape );
234 }
235 }
236
237 if( refShape->Collide( testShape, minClearance, &actual, &pos ) )
238 {
239 std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( errorCode );
240
241 if( minClearance > 0 )
242 {
243 wxString msg = formatMsg( _( "(%s clearance %s; actual %s)" ),
244 constraint.GetParentRule()->m_Name,
245 minClearance,
246 actual );
247
248 drcItem->SetErrorMessage( drcItem->GetErrorText() + wxS( " " ) + msg );
249 }
250
251 drcItem->SetItems( refItem, testItem );
252 drcItem->SetViolatingRule( constraint.GetParentRule() );
253
254 reportViolation( drcItem, pos, aLayers.second );
255
256 *aCollisionDetected = true;
257 }
258
259 return true;
260 },
261 m_largestClearance,
262 [&]( int aCount, int aSize ) -> bool
263 {
264 return reportProgress( aCount, aSize, progressDelta );
265 } );
266
267 return !m_drcEngine->IsCancelled();
268}
269
270
271namespace detail
272{
274}
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition: board_item.h:79
virtual bool IsTented(PCB_LAYER_ID aLayer) const
Checks if the given object is tented (its copper shape is covered by solder mask) on a given side of ...
Definition: board_item.h:173
Information pertinent to a Pcbnew printed circuit board.
Definition: board.h:317
BOARD_DESIGN_SETTINGS & GetDesignSettings() const
Definition: board.cpp:1011
SEVERITY GetSeverity() const
Definition: drc_rule.h:181
const MINOPTMAX< int > & GetValue() const
Definition: drc_rule.h:160
MINOPTMAX< int > m_Value
Definition: drc_rule.h:202
bool IsNull() const
Definition: drc_rule.h:155
BOARD * GetBoard() const
Definition: drc_engine.h:95
bool IsErrorLimitExceeded(int error_code)
DRC_CONSTRAINT EvalRules(DRC_CONSTRAINT_T aConstraintType, const BOARD_ITEM *a, const BOARD_ITEM *b, PCB_LAYER_ID aLayer, REPORTER *aReporter=nullptr)
Definition: drc_engine.cpp:706
bool QueryWorstConstraint(DRC_CONSTRAINT_T aRuleId, DRC_CONSTRAINT &aConstraint)
Implement an R-tree for fast spatial and layer indexing of connectable items.
Definition: drc_rtree.h:48
void Insert(BOARD_ITEM *aItem, PCB_LAYER_ID aLayer, int aWorstClearance=0)
Insert an item into the tree on a particular layer with an optional worst clearance.
Definition: drc_rtree.h:104
size_t size() const
Return the number of items in the tree.
Definition: drc_rtree.h:535
std::pair< PCB_LAYER_ID, PCB_LAYER_ID > LAYER_PAIR
Definition: drc_rtree.h:440
int QueryCollidingPairs(DRC_RTREE *aRefTree, std::vector< LAYER_PAIR > aLayerPairs, std::function< bool(const LAYER_PAIR &, ITEM_WITH_SHAPE *, ITEM_WITH_SHAPE *, bool *aCollision)> aVisitor, int aMaxClearance, std::function< bool(int, int)> aProgressReporter) const
Definition: drc_rtree.h:455
virtual const wxString GetName() const override
virtual bool Run() override
Run this provider against the given PCB with configured options (if any).
virtual ~DRC_TEST_PROVIDER_SILK_CLEARANCE()=default
Represent a DRC "provider" which runs some DRC functions over a BOARD and spits out DRC_ITEM and posi...
virtual bool reportPhase(const wxString &aStageName)
int forEachGeometryItem(const std::vector< KICAD_T > &aTypes, const LSET &aLayers, const std::function< bool(BOARD_ITEM *)> &aFunc)
static std::vector< KICAD_T > s_allBasicItems
DRC_ENGINE * m_drcEngine
bool isInvisibleText(const BOARD_ITEM *aItem) const
virtual bool reportProgress(size_t aCount, size_t aSize, size_t aDelta=1)
LSET is a set of PCB_LAYER_IDs.
Definition: lset.h:37
static const LSET & FrontMask()
Return a mask holding all technical layers and the external CU layer on front side.
Definition: lset.cpp:705
static const LSET & BackMask()
Return a mask holding all technical layers and the external CU layer on back side.
Definition: lset.cpp:712
T Min() const
Definition: minoptmax.h:33
An abstract shape on 2D plane.
Definition: shape.h:126
The common library.
@ DRCE_SILK_MASK_CLEARANCE
Definition: drc_item.h:96
@ DRCE_OVERLAPPING_SILK
Definition: drc_item.h:101
@ SILK_CLEARANCE_CONSTRAINT
Definition: drc_rule.h:56
#define REPORT_AUX(s)
#define _(s)
PCB_LAYER_ID
A quick note on layer IDs:
Definition: layer_ids.h:60
@ F_CrtYd
Definition: layer_ids.h:116
@ B_Adhes
Definition: layer_ids.h:103
@ Edge_Cuts
Definition: layer_ids.h:112
@ F_Paste
Definition: layer_ids.h:104
@ F_Adhes
Definition: layer_ids.h:102
@ B_Mask
Definition: layer_ids.h:98
@ B_Cu
Definition: layer_ids.h:65
@ F_Mask
Definition: layer_ids.h:97
@ B_Paste
Definition: layer_ids.h:105
@ F_Fab
Definition: layer_ids.h:119
@ Margin
Definition: layer_ids.h:113
@ F_SilkS
Definition: layer_ids.h:100
@ B_CrtYd
Definition: layer_ids.h:115
@ B_SilkS
Definition: layer_ids.h:101
@ F_Cu
Definition: layer_ids.h:64
@ B_Fab
Definition: layer_ids.h:118
static DRC_REGISTER_TEST_PROVIDER< DRC_TEST_PROVIDER_ANNULAR_WIDTH > dummy
@ RPT_SEVERITY_IGNORE
int actual
@ PCB_SHAPE_T
class PCB_SHAPE, a segment not on copper layers
Definition: typeinfo.h:88