KiCad PCB EDA Suite
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drc_test_provider_silk_clearance.cpp
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1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright The KiCad Developers.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, you may find one here:
18 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
19 * or you may search the http://www.gnu.org website for the version 2 license,
20 * or you may write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
22 */
23
24#include <common.h>
25#include <board.h>
26#include <pcb_track.h>
28#include <geometry/seg.h>
29#include <drc/drc_engine.h>
30#include <drc/drc_item.h>
31#include <drc/drc_rule.h>
33#include <drc/drc_rtree.h>
34
35/*
36 Silk to silk clearance test. Check all silkscreen features against each other.
37 Errors generated:
38 - DRCE_OVERLAPPING_SILK
39
40*/
41
43{
44public:
46 m_board( nullptr ),
48 {
49 }
50
52 {
53 }
54
55 virtual bool Run() override;
56
57 virtual const wxString GetName() const override
58 {
59 return wxT( "silk_clearance" );
60 };
61
62 virtual const wxString GetDescription() const override
63 {
64 return wxT( "Tests for overlapping silkscreen features." );
65 }
66
67private:
68
71};
72
73
75{
76 const int progressDelta = 500;
77
79 {
80 reportAux( wxT( "Overlapping silk violations ignored. Tests not run." ) );
81 return true; // continue with other tests
82 }
83
85
86 DRC_CONSTRAINT worstClearanceConstraint;
88
89 if( m_drcEngine->QueryWorstConstraint( SILK_CLEARANCE_CONSTRAINT, worstClearanceConstraint ) )
90 m_largestClearance = worstClearanceConstraint.m_Value.Min();
91
92 reportAux( wxT( "Worst clearance : %d nm" ), m_largestClearance );
93
94 if( !reportPhase( _( "Checking silkscreen for overlapping items..." ) ) )
95 return false; // DRC cancelled
96
97 DRC_RTREE silkTree;
98 DRC_RTREE targetTree;
99 int ii = 0;
100 int items = 0;
101
102 auto countItems =
103 [&]( BOARD_ITEM* item ) -> bool
104 {
105 ++items;
106 return true;
107 };
108
109 auto addToSilkTree =
110 [&]( BOARD_ITEM* item ) -> bool
111 {
112 if( !reportProgress( ii++, items, progressDelta ) )
113 return false;
114
115 for( PCB_LAYER_ID layer : { F_SilkS, B_SilkS } )
116 {
117 if( item->IsOnLayer( layer ) )
118 silkTree.Insert( item, layer );
119 }
120
121 return true;
122 };
123
124 auto addToTargetTree =
125 [&]( BOARD_ITEM* item ) -> bool
126 {
127 if( !reportProgress( ii++, items, progressDelta ) )
128 return false;
129
130 for( PCB_LAYER_ID layer : item->GetLayerSet().Seq() )
131 targetTree.Insert( item, layer );
132
133 return true;
134 };
135
137
140 countItems );
141
142 forEachGeometryItem( s_allBasicItems, LSET( { F_SilkS, B_SilkS } ), addToSilkTree );
143
146 addToTargetTree );
147
148 reportAux( wxT( "Testing %d silkscreen features against %d board items." ),
149 silkTree.size(),
150 targetTree.size() );
151
152 const std::vector<DRC_RTREE::LAYER_PAIR> layerPairs =
153 {
172 };
173
174 targetTree.QueryCollidingPairs( &silkTree, layerPairs,
175 [&]( const DRC_RTREE::LAYER_PAIR& aLayers, DRC_RTREE::ITEM_WITH_SHAPE* aRefItemShape,
176 DRC_RTREE::ITEM_WITH_SHAPE* aTestItemShape, bool* aCollisionDetected ) -> bool
177 {
178 BOARD_ITEM* refItem = aRefItemShape->parent;
179 const SHAPE* refShape = aRefItemShape->shape;
180 BOARD_ITEM* testItem = aTestItemShape->parent;
181 const SHAPE* testShape = aTestItemShape->shape;
182
183 std::shared_ptr<SHAPE> hole;
184
186 return false;
187
188 if( isInvisibleText( refItem ) || isInvisibleText( testItem ) )
189 return true;
190
191 if( testItem->IsTented( aLayers.first ) )
192 {
193 if( testItem->HasHole() )
194 {
195 hole = testItem->GetEffectiveHoleShape();
196 testShape = hole.get();
197 }
198 else
199 {
200 return true;
201 }
202 }
203
205 refItem, testItem,
206 aLayers.second );
207
208 if( constraint.IsNull() || constraint.GetSeverity() == RPT_SEVERITY_IGNORE )
209 return true;
210
211 int minClearance = constraint.GetValue().Min();
212
213 if( minClearance < 0 )
214 return true;
215
216 int actual;
217 VECTOR2I pos;
218
219 // Graphics are often compound shapes so ignore collisions between shapes in a
220 // single footprint or on the board (both parent footprints will be nullptr).
221 if( refItem->Type() == PCB_SHAPE_T && testItem->Type() == PCB_SHAPE_T
222 && refItem->GetParentFootprint() == testItem->GetParentFootprint() )
223 {
224 return true;
225 }
226
227 // Collide (and generate violations) based on a well-defined order so that
228 // exclusion checking against previously-generated violations will work.
229 if( aLayers.first == aLayers.second )
230 {
231 if( refItem->m_Uuid > testItem->m_Uuid )
232 {
233 std::swap( refItem, testItem );
234 std::swap( refShape, testShape );
235 }
236 }
237
238 if( refShape->Collide( testShape, minClearance, &actual, &pos ) )
239 {
240 std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_OVERLAPPING_SILK );
241
242 if( minClearance > 0 )
243 {
244 wxString msg = formatMsg( _( "(%s clearance %s; actual %s)" ),
245 constraint.GetParentRule()->m_Name,
246 minClearance,
247 actual );
248
249 drcItem->SetErrorMessage( drcItem->GetErrorText() + wxS( " " ) + msg );
250 }
251
252 drcItem->SetItems( refItem, testItem );
253 drcItem->SetViolatingRule( constraint.GetParentRule() );
254
255 reportViolation( drcItem, pos, aLayers.second );
256
257 *aCollisionDetected = true;
258 }
259
260 return true;
261 },
262 m_largestClearance,
263 [&]( int aCount, int aSize ) -> bool
264 {
265 return reportProgress( aCount, aSize, progressDelta );
266 } );
267
268 reportRuleStatistics();
269
270 return !m_drcEngine->IsCancelled();
271}
272
273
274namespace detail
275{
277}
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition: board_item.h:79
virtual bool IsTented(PCB_LAYER_ID aLayer) const
Checks if the given object is tented (its copper shape is covered by solder mask) on a given side of ...
Definition: board_item.h:172
Information pertinent to a Pcbnew printed circuit board.
Definition: board.h:295
SEVERITY GetSeverity() const
Definition: drc_rule.h:173
const MINOPTMAX< int > & GetValue() const
Definition: drc_rule.h:152
MINOPTMAX< int > m_Value
Definition: drc_rule.h:190
bool IsNull() const
Definition: drc_rule.h:147
BOARD * GetBoard() const
Definition: drc_engine.h:96
bool IsErrorLimitExceeded(int error_code)
DRC_CONSTRAINT EvalRules(DRC_CONSTRAINT_T aConstraintType, const BOARD_ITEM *a, const BOARD_ITEM *b, PCB_LAYER_ID aLayer, REPORTER *aReporter=nullptr)
Definition: drc_engine.cpp:690
bool QueryWorstConstraint(DRC_CONSTRAINT_T aRuleId, DRC_CONSTRAINT &aConstraint)
Implement an R-tree for fast spatial and layer indexing of connectable items.
Definition: drc_rtree.h:48
void Insert(BOARD_ITEM *aItem, PCB_LAYER_ID aLayer, int aWorstClearance=0)
Insert an item into the tree on a particular layer with an optional worst clearance.
Definition: drc_rtree.h:104
size_t size() const
Return the number of items in the tree.
Definition: drc_rtree.h:538
std::pair< PCB_LAYER_ID, PCB_LAYER_ID > LAYER_PAIR
Definition: drc_rtree.h:443
int QueryCollidingPairs(DRC_RTREE *aRefTree, std::vector< LAYER_PAIR > aLayerPairs, std::function< bool(const LAYER_PAIR &, ITEM_WITH_SHAPE *, ITEM_WITH_SHAPE *, bool *aCollision)> aVisitor, int aMaxClearance, std::function< bool(int, int)> aProgressReporter) const
Definition: drc_rtree.h:458
virtual const wxString GetName() const override
virtual bool Run() override
Run this provider against the given PCB with configured options (if any).
virtual const wxString GetDescription() const override
Represent a DRC "provider" which runs some DRC functions over a BOARD and spits out DRC_ITEM and posi...
virtual bool reportPhase(const wxString &aStageName)
int forEachGeometryItem(const std::vector< KICAD_T > &aTypes, LSET aLayers, const std::function< bool(BOARD_ITEM *)> &aFunc)
static std::vector< KICAD_T > s_allBasicItems
DRC_ENGINE * m_drcEngine
bool isInvisibleText(const BOARD_ITEM *aItem) const
void reportAux(const wxString &aMsg)
virtual bool reportProgress(size_t aCount, size_t aSize, size_t aDelta=1)
LSET is a set of PCB_LAYER_IDs.
Definition: lset.h:37
static LSET FrontMask()
Return a mask holding all technical layers and the external CU layer on front side.
Definition: lset.cpp:660
static LSET BackMask()
Return a mask holding all technical layers and the external CU layer on back side.
Definition: lset.cpp:667
T Min() const
Definition: minoptmax.h:33
An abstract shape on 2D plane.
Definition: shape.h:126
The common library.
@ DRCE_OVERLAPPING_SILK
Definition: drc_item.h:101
@ SILK_CLEARANCE_CONSTRAINT
Definition: drc_rule.h:56
#define _(s)
PCB_LAYER_ID
A quick note on layer IDs:
Definition: layer_ids.h:60
@ F_CrtYd
Definition: layer_ids.h:116
@ B_Adhes
Definition: layer_ids.h:103
@ Edge_Cuts
Definition: layer_ids.h:112
@ F_Paste
Definition: layer_ids.h:104
@ F_Adhes
Definition: layer_ids.h:102
@ B_Mask
Definition: layer_ids.h:98
@ B_Cu
Definition: layer_ids.h:65
@ F_Mask
Definition: layer_ids.h:97
@ B_Paste
Definition: layer_ids.h:105
@ F_Fab
Definition: layer_ids.h:119
@ Margin
Definition: layer_ids.h:113
@ F_SilkS
Definition: layer_ids.h:100
@ B_CrtYd
Definition: layer_ids.h:115
@ B_SilkS
Definition: layer_ids.h:101
@ F_Cu
Definition: layer_ids.h:64
@ B_Fab
Definition: layer_ids.h:118
static DRC_REGISTER_TEST_PROVIDER< DRC_TEST_PROVIDER_ANNULAR_WIDTH > dummy
@ RPT_SEVERITY_IGNORE
@ PCB_SHAPE_T
class PCB_SHAPE, a segment not on copper layers
Definition: typeinfo.h:88