KiCad PCB EDA Suite
Loading...
Searching...
No Matches
drc_test_provider_silk_clearance.cpp
Go to the documentation of this file.
1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright (C) 2004-2023 KiCad Developers.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, you may find one here:
18 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
19 * or you may search the http://www.gnu.org website for the version 2 license,
20 * or you may write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
22 */
23
24#include <common.h>
25#include <board.h>
26#include <footprint.h>
27#include <pcb_shape.h>
28#include <pcb_track.h>
30#include <geometry/seg.h>
31#include <drc/drc_engine.h>
32#include <drc/drc_item.h>
33#include <drc/drc_rule.h>
35#include <drc/drc_rtree.h>
36
37/*
38 Silk to silk clearance test. Check all silkscreen features against each other.
39 Errors generated:
40 - DRCE_OVERLAPPING_SILK
41
42*/
43
45{
46public:
48 m_board( nullptr ),
50 {
51 }
52
54 {
55 }
56
57 virtual bool Run() override;
58
59 virtual const wxString GetName() const override
60 {
61 return wxT( "silk_clearance" );
62 };
63
64 virtual const wxString GetDescription() const override
65 {
66 return wxT( "Tests for overlapping silkscreen features." );
67 }
68
69private:
70
73};
74
75
77{
78 const int progressDelta = 500;
79
81 {
82 reportAux( wxT( "Overlapping silk violations ignored. Tests not run." ) );
83 return true; // continue with other tests
84 }
85
87
88 DRC_CONSTRAINT worstClearanceConstraint;
90
91 if( m_drcEngine->QueryWorstConstraint( SILK_CLEARANCE_CONSTRAINT, worstClearanceConstraint ) )
92 m_largestClearance = worstClearanceConstraint.m_Value.Min();
93
94 reportAux( wxT( "Worst clearance : %d nm" ), m_largestClearance );
95
96 if( !reportPhase( _( "Checking silkscreen for overlapping items..." ) ) )
97 return false; // DRC cancelled
98
99 DRC_RTREE silkTree;
100 DRC_RTREE targetTree;
101 int ii = 0;
102 int items = 0;
103
104 auto countItems =
105 [&]( BOARD_ITEM* item ) -> bool
106 {
107 ++items;
108 return true;
109 };
110
111 auto addToSilkTree =
112 [&]( BOARD_ITEM* item ) -> bool
113 {
114 if( !reportProgress( ii++, items, progressDelta ) )
115 return false;
116
117 for( PCB_LAYER_ID layer : { F_SilkS, B_SilkS } )
118 {
119 if( item->IsOnLayer( layer ) )
120 silkTree.Insert( item, layer );
121 }
122
123 return true;
124 };
125
126 auto addToTargetTree =
127 [&]( BOARD_ITEM* item ) -> bool
128 {
129 if( !reportProgress( ii++, items, progressDelta ) )
130 return false;
131
132 for( PCB_LAYER_ID layer : item->GetLayerSet().Seq() )
133 targetTree.Insert( item, layer );
134
135 return true;
136 };
137
139
142 countItems );
143
144 forEachGeometryItem( s_allBasicItems, LSET( 2, F_SilkS, B_SilkS ), addToSilkTree );
145
148 addToTargetTree );
149
150 reportAux( wxT( "Testing %d silkscreen features against %d board items." ),
151 silkTree.size(),
152 targetTree.size() );
153
154 const std::vector<DRC_RTREE::LAYER_PAIR> layerPairs =
155 {
174 };
175
176 targetTree.QueryCollidingPairs( &silkTree, layerPairs,
177 [&]( const DRC_RTREE::LAYER_PAIR& aLayers, DRC_RTREE::ITEM_WITH_SHAPE* aRefItemShape,
178 DRC_RTREE::ITEM_WITH_SHAPE* aTestItemShape, bool* aCollisionDetected ) -> bool
179 {
180 BOARD_ITEM* refItem = aRefItemShape->parent;
181 const SHAPE* refShape = aRefItemShape->shape;
182 BOARD_ITEM* testItem = aTestItemShape->parent;
183 const SHAPE* testShape = aTestItemShape->shape;
184
185 std::shared_ptr<SHAPE> hole;
186
188 return false;
189
190 if( isInvisibleText( refItem ) || isInvisibleText( testItem ) )
191 return true;
192
193 if( testItem->IsTented() )
194 {
195 if( testItem->HasHole() )
196 {
197 hole = testItem->GetEffectiveHoleShape();
198 testShape = hole.get();
199 }
200 else
201 {
202 return true;
203 }
204 }
205
207 refItem, testItem,
208 aLayers.second );
209
210 if( constraint.IsNull() || constraint.GetSeverity() == RPT_SEVERITY_IGNORE )
211 return true;
212
213 int minClearance = constraint.GetValue().Min();
214
215 if( minClearance < 0 )
216 return true;
217
218 int actual;
219 VECTOR2I pos;
220
221 // Graphics are often compound shapes so ignore collisions between shapes in a
222 // single footprint or on the board (both parent footprints will be nullptr).
223 if( refItem->Type() == PCB_SHAPE_T && testItem->Type() == PCB_SHAPE_T
224 && refItem->GetParentFootprint() == testItem->GetParentFootprint() )
225 {
226 return true;
227 }
228
229 if( refShape->Collide( testShape, minClearance, &actual, &pos ) )
230 {
231 std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_OVERLAPPING_SILK );
232
233 if( minClearance > 0 )
234 {
235 wxString msg = formatMsg( _( "(%s clearance %s; actual %s)" ),
236 constraint.GetParentRule()->m_Name,
237 minClearance,
238 actual );
239
240 drcItem->SetErrorMessage( drcItem->GetErrorText() + wxS( " " ) + msg );
241 }
242
243 drcItem->SetItems( refItem, testItem );
244 drcItem->SetViolatingRule( constraint.GetParentRule() );
245
246 reportViolation( drcItem, pos, aLayers.second );
247
248 *aCollisionDetected = true;
249 }
250
251 return true;
252 },
253 m_largestClearance,
254 [&]( int aCount, int aSize ) -> bool
255 {
256 return reportProgress( aCount, aSize, progressDelta );
257 } );
258
259 reportRuleStatistics();
260
261 return !m_drcEngine->IsCancelled();
262}
263
264
265namespace detail
266{
268}
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition: board_item.h:77
virtual bool IsTented() const
Definition: board_item.h:161
Information pertinent to a Pcbnew printed circuit board.
Definition: board.h:281
SEVERITY GetSeverity() const
Definition: drc_rule.h:162
const MINOPTMAX< int > & GetValue() const
Definition: drc_rule.h:141
MINOPTMAX< int > m_Value
Definition: drc_rule.h:172
DRC_RULE * GetParentRule() const
Definition: drc_rule.h:145
bool IsNull() const
Definition: drc_rule.h:136
BOARD * GetBoard() const
Definition: drc_engine.h:89
bool IsErrorLimitExceeded(int error_code)
DRC_CONSTRAINT EvalRules(DRC_CONSTRAINT_T aConstraintType, const BOARD_ITEM *a, const BOARD_ITEM *b, PCB_LAYER_ID aLayer, REPORTER *aReporter=nullptr)
Definition: drc_engine.cpp:675
bool QueryWorstConstraint(DRC_CONSTRAINT_T aRuleId, DRC_CONSTRAINT &aConstraint)
Implement an R-tree for fast spatial and layer indexing of connectable items.
Definition: drc_rtree.h:48
void Insert(BOARD_ITEM *aItem, PCB_LAYER_ID aLayer, int aWorstClearance=0)
Insert an item into the tree on a particular layer with an optional worst clearance.
Definition: drc_rtree.h:104
size_t size() const
Return the number of items in the tree.
Definition: drc_rtree.h:517
std::pair< PCB_LAYER_ID, PCB_LAYER_ID > LAYER_PAIR
Definition: drc_rtree.h:425
int QueryCollidingPairs(DRC_RTREE *aRefTree, std::vector< LAYER_PAIR > aLayerPairs, std::function< bool(const LAYER_PAIR &, ITEM_WITH_SHAPE *, ITEM_WITH_SHAPE *, bool *aCollision)> aVisitor, int aMaxClearance, std::function< bool(int, int)> aProgressReporter) const
Definition: drc_rtree.h:440
virtual const wxString GetName() const override
virtual bool Run() override
Run this provider against the given PCB with configured options (if any).
virtual const wxString GetDescription() const override
Represent a DRC "provider" which runs some DRC functions over a BOARD and spits out DRC_ITEM and posi...
virtual bool reportPhase(const wxString &aStageName)
int forEachGeometryItem(const std::vector< KICAD_T > &aTypes, LSET aLayers, const std::function< bool(BOARD_ITEM *)> &aFunc)
virtual void reportViolation(std::shared_ptr< DRC_ITEM > &item, const VECTOR2I &aMarkerPos, int aMarkerLayer)
static std::vector< KICAD_T > s_allBasicItems
DRC_ENGINE * m_drcEngine
bool isInvisibleText(const BOARD_ITEM *aItem) const
void reportAux(const wxString &aMsg)
virtual bool reportProgress(size_t aCount, size_t aSize, size_t aDelta=1)
LSET is a set of PCB_LAYER_IDs.
Definition: layer_ids.h:574
static LSET FrontMask()
Return a mask holding all technical layers and the external CU layer on front side.
Definition: lset.cpp:985
static LSET BackMask()
Return a mask holding all technical layers and the external CU layer on back side.
Definition: lset.cpp:992
T Min() const
Definition: minoptmax.h:33
An abstract shape on 2D plane.
Definition: shape.h:126
The common library.
@ DRCE_OVERLAPPING_SILK
Definition: drc_item.h:94
@ SILK_CLEARANCE_CONSTRAINT
Definition: drc_rule.h:53
#define _(s)
PCB_LAYER_ID
A quick note on layer IDs:
Definition: layer_ids.h:60
@ F_CrtYd
Definition: layer_ids.h:117
@ B_Adhes
Definition: layer_ids.h:97
@ Edge_Cuts
Definition: layer_ids.h:113
@ F_Paste
Definition: layer_ids.h:101
@ F_Adhes
Definition: layer_ids.h:98
@ B_Mask
Definition: layer_ids.h:106
@ B_Cu
Definition: layer_ids.h:95
@ F_Mask
Definition: layer_ids.h:107
@ B_Paste
Definition: layer_ids.h:100
@ F_Fab
Definition: layer_ids.h:120
@ Margin
Definition: layer_ids.h:114
@ F_SilkS
Definition: layer_ids.h:104
@ B_CrtYd
Definition: layer_ids.h:116
@ B_SilkS
Definition: layer_ids.h:103
@ F_Cu
Definition: layer_ids.h:64
@ B_Fab
Definition: layer_ids.h:119
static DRC_REGISTER_TEST_PROVIDER< DRC_TEST_PROVIDER_ANNULAR_WIDTH > dummy
@ RPT_SEVERITY_IGNORE
@ PCB_SHAPE_T
class PCB_SHAPE, a segment not on copper layers
Definition: typeinfo.h:88