KiCad PCB EDA Suite
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drc_test_provider_silk_clearance.cpp
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1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright The KiCad Developers.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, you may find one here:
18 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
19 * or you may search the http://www.gnu.org website for the version 2 license,
20 * or you may write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
22 */
23
24#include <common.h>
25#include <board.h>
26#include <pcb_board_outline.h>
27#include <pcb_track.h>
29#include <geometry/seg.h>
30#include <drc/drc_engine.h>
31#include <drc/drc_item.h>
32#include <drc/drc_rule.h>
34#include <drc/drc_rtree.h>
36
37/*
38 Silk to silk clearance test. Check all silkscreen features against each other.
39 Errors generated:
40 - DRCE_SILK_CLEARANCE
41
42*/
43
45{
46public:
51
53
54 virtual bool Run() override;
55
56 virtual const wxString GetName() const override { return wxT( "silk_clearance" ); };
57
58private:
59
62};
63
64
66{
67 const int progressDelta = 500;
68
69 m_board = m_drcEngine->GetBoard();
70
71 // If the soldermask min width is greater than 0 then we must use a healing algorithm to generate
72 // a whole-board soldermask poly, and then test against that. However, that can't deal well with
73 // DRC exclusions (as any change anywhere on the board that affects the soldermask will null the
74 // associated exclusions), so we only use that when soldermask min width is > 0.
75 bool checkIndividualMaskItems = m_board->GetDesignSettings().m_SolderMaskMinWidth <= 0;
76
77 if( m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_CLEARANCE )
78 && m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_MASK_CLEARANCE) )
79 {
80 return true; // continue with other tests
81 }
82
83 DRC_CONSTRAINT worstClearanceConstraint;
85
86 if( m_drcEngine->QueryWorstConstraint( SILK_CLEARANCE_CONSTRAINT, worstClearanceConstraint ) )
87 m_largestClearance = worstClearanceConstraint.m_Value.Min();
88
89 if( !reportPhase( _( "Checking silkscreen for overlapping items..." ) ) )
90 return false; // DRC cancelled
91
92 DRC_RTREE silkTree;
93 DRC_RTREE targetTree;
94 int ii = 0;
95 int items = 0;
96 LSET silkLayers = LSET( { F_SilkS, B_SilkS } );
97 LSET targetLayers = LSET::FrontMask() | LSET::BackMask() | LSET( { Edge_Cuts, Margin } );
98
99 auto countItems =
100 [&]( BOARD_ITEM* item ) -> bool
101 {
102 ++items;
103 return true;
104 };
105
106 auto addToSilkTree =
107 [&]( BOARD_ITEM* item ) -> bool
108 {
109 if( !reportProgress( ii++, items, progressDelta ) )
110 return false;
111
112 for( PCB_LAYER_ID layer : { F_SilkS, B_SilkS } )
113 {
114 if( item->IsOnLayer( layer ) )
115 silkTree.Insert( item, layer, 0, ATOMIC_TABLES );
116 }
117
118 return true;
119 };
120
121 auto addToTargetTree =
122 [&]( BOARD_ITEM* item ) -> bool
123 {
124 if( !reportProgress( ii++, items, progressDelta ) )
125 return false;
126
127 for( PCB_LAYER_ID layer : LSET( item->GetLayerSet() & targetLayers ) )
128 targetTree.Insert( item, layer, 0, ATOMIC_TABLES );
129
130 return true;
131 };
132
133 forEachGeometryItem( s_allBasicItems, silkLayers, countItems );
134 forEachGeometryItem( s_allBasicItems, targetLayers, countItems );
135
136 forEachGeometryItem( s_allBasicItems, silkLayers, addToSilkTree );
137 forEachGeometryItem( s_allBasicItems, targetLayers, addToTargetTree );
138
139 silkTree.Build();
140 targetTree.Build();
141
142 REPORT_AUX( wxString::Format( wxT( "Testing %d silkscreen features against %d board items." ),
143 silkTree.size(),
144 targetTree.size() ) );
145
146 const std::vector<DRC_RTREE::LAYER_PAIR> layerPairs =
147 {
166 };
167
168 targetTree.QueryCollidingPairs( &silkTree, layerPairs,
169 [&]( const DRC_RTREE::LAYER_PAIR& aLayers, DRC_RTREE::ITEM_WITH_SHAPE* aRefItemShape,
170 DRC_RTREE::ITEM_WITH_SHAPE* aTestItemShape, bool* aCollisionDetected ) -> bool
171 {
172 BOARD_ITEM* refItem = aRefItemShape->parent;
173 const SHAPE* refShape = aRefItemShape->shape;
174 BOARD_ITEM* testItem = aTestItemShape->parent;
175 const SHAPE* testShape = aTestItemShape->shape;
176
177 std::shared_ptr<SHAPE> hole;
178
179 if( m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_CLEARANCE )
180 && m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_MASK_CLEARANCE ) )
181 {
182 return false;
183 }
184
185 if( isInvisibleText( refItem ) || isInvisibleText( testItem ) )
186 return true;
187
188 if( testItem->IsTented( aLayers.first ) )
189 {
190 if( testItem->HasHole() )
191 {
192 hole = testItem->GetEffectiveHoleShape();
193 testShape = hole.get();
194 }
195 else
196 {
197 return true;
198 }
199 }
200
201 if( PCB_BOARD_OUTLINE* boardOutline = m_board->BoardOutline() )
202 {
203 if( !testItem->GetBoundingBox().Intersects( boardOutline->GetOutline().BBoxFromCaches() ) )
204 return true;
205
206 if( !testShape->Collide( &boardOutline->GetOutline() ) )
207 return true;
208 }
209
210 int errorCode = DRCE_SILK_CLEARANCE;
212 refItem, testItem, aLayers.second );
213 int minClearance = -1;
214
215 if( !constraint.IsNull() && constraint.GetSeverity() != RPT_SEVERITY_IGNORE )
216 minClearance = constraint.GetValue().Min();
217
218 if( aLayers.second == F_Mask || aLayers.second == B_Mask )
219 {
220 if( checkIndividualMaskItems )
221 minClearance = std::max( minClearance, 0 );
222
223 errorCode = DRCE_SILK_MASK_CLEARANCE;
224 }
225
226 if( minClearance < 0 || m_drcEngine->IsErrorLimitExceeded( errorCode ) )
227 return true;
228
229 int actual;
230 VECTOR2I pos;
231
232 // Graphics are often compound shapes so ignore collisions between shapes in a
233 // single footprint or on the board (both parent footprints will be nullptr).
234 if( refItem->Type() == PCB_SHAPE_T && testItem->Type() == PCB_SHAPE_T
235 && refItem->GetParentFootprint() == testItem->GetParentFootprint() )
236 {
237 return true;
238 }
239
240 // Collide (and generate violations) based on a well-defined order so that
241 // exclusion checking against previously-generated violations will work.
242 if( aLayers.first == aLayers.second )
243 {
244 if( refItem->m_Uuid > testItem->m_Uuid )
245 {
246 std::swap( refItem, testItem );
247 std::swap( refShape, testShape );
248 }
249 }
250
251 if( refShape->Collide( testShape, minClearance, &actual, &pos ) )
252 {
253 std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( errorCode );
254
255 if( minClearance > 0 )
256 {
257 drcItem->SetErrorDetail( formatMsg( _( "(%s clearance %s; actual %s)" ),
258 constraint.GetParentRule()->m_Name,
259 minClearance,
260 actual ) );
261 }
262
263 drcItem->SetItems( refItem, testItem );
264 drcItem->SetViolatingRule( constraint.GetParentRule() );
265 reportTwoShapeGeometry( drcItem, pos, refShape, testShape, aLayers.second, actual );
266 *aCollisionDetected = true;
267 }
268
269 return true;
270 },
272 [&]( int aCount, int aSize ) -> bool
273 {
274 return reportProgress( aCount, aSize, progressDelta );
275 } );
276
277 return !m_drcEngine->IsCancelled();
278}
279
280
281namespace detail
282{
284}
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition board_item.h:84
FOOTPRINT * GetParentFootprint() const
virtual bool IsTented(PCB_LAYER_ID aLayer) const
Checks if the given object is tented (its copper shape is covered by solder mask) on a given side of ...
Definition board_item.h:197
virtual std::shared_ptr< SHAPE_SEGMENT > GetEffectiveHoleShape() const
virtual bool HasHole() const
Definition board_item.h:180
Information pertinent to a Pcbnew printed circuit board.
Definition board.h:323
constexpr bool Intersects(const BOX2< Vec > &aRect) const
Definition box2.h:311
SEVERITY GetSeverity() const
Definition drc_rule.h:217
const MINOPTMAX< int > & GetValue() const
Definition drc_rule.h:196
MINOPTMAX< int > m_Value
Definition drc_rule.h:240
DRC_RULE * GetParentRule() const
Definition drc_rule.h:200
bool IsNull() const
Definition drc_rule.h:191
static std::shared_ptr< DRC_ITEM > Create(int aErrorCode)
Constructs a DRC_ITEM for the given error code.
Definition drc_item.cpp:407
Implement an R-tree for fast spatial and layer indexing of connectable items.
Definition drc_rtree.h:50
size_t size() const
Return the number of items in the tree.
Definition drc_rtree.h:554
std::pair< PCB_LAYER_ID, PCB_LAYER_ID > LAYER_PAIR
Definition drc_rtree.h:459
int QueryCollidingPairs(DRC_RTREE *aRefTree, std::vector< LAYER_PAIR > aLayerPairs, std::function< bool(const LAYER_PAIR &, ITEM_WITH_SHAPE *, ITEM_WITH_SHAPE *, bool *aCollision)> aVisitor, int aMaxClearance, std::function< bool(int, int)> aProgressReporter) const
Definition drc_rtree.h:474
void Build()
Finalize all pending inserts by bulk-building packed R-trees from the staged items.
Definition drc_rtree.h:168
void Insert(BOARD_ITEM *aItem, PCB_LAYER_ID aLayer, int aWorstClearance=0, bool aAtomicTables=false)
Insert an item into the tree on a particular layer with an optional worst clearance.
Definition drc_rtree.h:96
wxString m_Name
Definition drc_rule.h:153
virtual const wxString GetName() const override
virtual bool Run() override
Run this provider against the given PCB with configured options (if any).
virtual ~DRC_TEST_PROVIDER_SILK_CLEARANCE()=default
virtual bool reportPhase(const wxString &aStageName)
void reportTwoShapeGeometry(std::shared_ptr< DRC_ITEM > &aDrcItem, const VECTOR2I &aMarkerPos, const SHAPE *aShape1, const SHAPE *aShape2, PCB_LAYER_ID aLayer, int aDistance)
int forEachGeometryItem(const std::vector< KICAD_T > &aTypes, const LSET &aLayers, const std::function< bool(BOARD_ITEM *)> &aFunc)
static std::vector< KICAD_T > s_allBasicItems
bool isInvisibleText(const BOARD_ITEM *aItem) const
wxString formatMsg(const wxString &aFormatString, const wxString &aSource, double aConstraint, double aActual, EDA_DATA_TYPE aDataType=EDA_DATA_TYPE::DISTANCE)
virtual bool reportProgress(size_t aCount, size_t aSize, size_t aDelta=1)
virtual const BOX2I GetBoundingBox() const
Return the orthogonal bounding box of this object for display purposes.
Definition eda_item.cpp:120
const KIID m_Uuid
Definition eda_item.h:528
KICAD_T Type() const
Returns the type of object.
Definition eda_item.h:112
LSET is a set of PCB_LAYER_IDs.
Definition lset.h:37
static const LSET & FrontMask()
Return a mask holding all technical layers and the external CU layer on front side.
Definition lset.cpp:722
static const LSET & BackMask()
Return a mask holding all technical layers and the external CU layer on back side.
Definition lset.cpp:729
T Min() const
Definition minoptmax.h:33
An abstract shape on 2D plane.
Definition shape.h:126
virtual bool Collide(const VECTOR2I &aP, int aClearance=0, int *aActual=nullptr, VECTOR2I *aLocation=nullptr) const
Check if the boundary of shape (this) lies closer to the point aP than aClearance,...
Definition shape.h:181
The common library.
@ DRCE_SILK_MASK_CLEARANCE
Definition drc_item.h:97
@ DRCE_SILK_CLEARANCE
Definition drc_item.h:100
#define ATOMIC_TABLES
Definition drc_rtree.h:43
@ SILK_CLEARANCE_CONSTRAINT
Definition drc_rule.h:62
#define REPORT_AUX(s)
#define _(s)
PCB_LAYER_ID
A quick note on layer IDs:
Definition layer_ids.h:60
@ F_CrtYd
Definition layer_ids.h:116
@ B_Adhes
Definition layer_ids.h:103
@ Edge_Cuts
Definition layer_ids.h:112
@ F_Paste
Definition layer_ids.h:104
@ F_Adhes
Definition layer_ids.h:102
@ B_Mask
Definition layer_ids.h:98
@ B_Cu
Definition layer_ids.h:65
@ F_Mask
Definition layer_ids.h:97
@ B_Paste
Definition layer_ids.h:105
@ F_Fab
Definition layer_ids.h:119
@ Margin
Definition layer_ids.h:113
@ F_SilkS
Definition layer_ids.h:100
@ B_CrtYd
Definition layer_ids.h:115
@ B_SilkS
Definition layer_ids.h:101
@ F_Cu
Definition layer_ids.h:64
@ B_Fab
Definition layer_ids.h:118
static DRC_REGISTER_TEST_PROVIDER< DRC_TEST_PROVIDER_ANNULAR_WIDTH > dummy
@ RPT_SEVERITY_IGNORE
int actual
@ PCB_SHAPE_T
class PCB_SHAPE, a segment not on copper layers
Definition typeinfo.h:85
VECTOR2< int32_t > VECTOR2I
Definition vector2d.h:687