KiCad PCB EDA Suite
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drc_test_provider_silk_clearance.cpp
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1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright The KiCad Developers.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <https://www.gnu.org/licenses/>.
18 */
19
20#include <unordered_map>
21
22#include <common.h>
23#include <board.h>
24#include <pcb_board_outline.h>
25#include <pcb_track.h>
26#include <zone.h>
28#include <geometry/seg.h>
29#include <drc/drc_engine.h>
30#include <drc/drc_item.h>
31#include <drc/drc_rule.h>
33#include <drc/drc_rtree.h>
35
36/*
37 Silk to silk clearance test. Check all silkscreen features against each other.
38 Errors generated:
39 - DRCE_SILK_CLEARANCE
40
41*/
42
44{
45public:
50
52
53 virtual bool Run() override;
54
55 virtual const wxString GetName() const override { return wxT( "silk_clearance" ); };
56
57private:
58
61};
62
63
65{
66 const int progressDelta = 500;
67
68 m_board = m_drcEngine->GetBoard();
69
70 // If the soldermask min width is greater than 0 then we must use a healing algorithm to generate
71 // a whole-board soldermask poly, and then test against that. However, that can't deal well with
72 // DRC exclusions (as any change anywhere on the board that affects the soldermask will null the
73 // associated exclusions), so we only use that when soldermask min width is > 0.
74 bool checkIndividualMaskItems = m_board->GetDesignSettings().m_SolderMaskMinWidth <= 0;
75
76 if( m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_CLEARANCE )
77 && m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_MASK_CLEARANCE) )
78 {
79 return true; // continue with other tests
80 }
81
82 DRC_CONSTRAINT worstClearanceConstraint;
84
85 if( m_drcEngine->QueryWorstConstraint( SILK_CLEARANCE_CONSTRAINT, worstClearanceConstraint ) )
86 m_largestClearance = worstClearanceConstraint.m_Value.Min();
87
88 if( !reportPhase( _( "Checking silkscreen for overlapping items..." ) ) )
89 return false; // DRC cancelled
90
91 DRC_RTREE silkTree;
92 DRC_RTREE targetTree;
93 int ii = 0;
94 int items = 0;
95 LSET silkLayers = LSET( { F_SilkS, B_SilkS } );
96 LSET targetLayers = LSET::FrontMask() | LSET::BackMask() | LSET( { Edge_Cuts, Margin } );
97
98 auto countItems =
99 [&]( BOARD_ITEM* item ) -> bool
100 {
101 ++items;
102 return true;
103 };
104
105 // Rule areas are purely logical (no physical copper, mask, or silk) so they must never
106 // participate in silk-clearance collisions. Their effective shape now follows the
107 // outline (so disallow checks can collide against them), which would otherwise cause
108 // false silk-to-rule-area violations.
109 auto isRuleArea =
110 [&]( BOARD_ITEM* item ) -> bool
111 {
112 return item->Type() == PCB_ZONE_T && static_cast<ZONE*>( item )->GetIsRuleArea();
113 };
114
115 auto addToSilkTree =
116 [&]( BOARD_ITEM* item ) -> bool
117 {
118 if( !reportProgress( ii++, items, progressDelta ) )
119 return false;
120
121 if( isRuleArea( item ) )
122 return true;
123
124 for( PCB_LAYER_ID layer : { F_SilkS, B_SilkS } )
125 {
126 if( item->IsOnLayer( layer ) )
127 silkTree.Insert( item, layer, 0, ATOMIC_TABLES );
128 }
129
130 return true;
131 };
132
133 auto addToTargetTree =
134 [&]( BOARD_ITEM* item ) -> bool
135 {
136 if( !reportProgress( ii++, items, progressDelta ) )
137 return false;
138
139 if( isRuleArea( item ) )
140 return true;
141
142 for( PCB_LAYER_ID layer : LSET( item->GetLayerSet() & targetLayers ) )
143 targetTree.Insert( item, layer, 0, ATOMIC_TABLES );
144
145 return true;
146 };
147
148 forEachGeometryItem( s_allBasicItems, silkLayers, countItems );
149 forEachGeometryItem( s_allBasicItems, targetLayers, countItems );
150
151 forEachGeometryItem( s_allBasicItems, silkLayers, addToSilkTree );
152 forEachGeometryItem( s_allBasicItems, targetLayers, addToTargetTree );
153
154 silkTree.Build();
155 targetTree.Build();
156
157 REPORT_AUX( wxString::Format( wxT( "Testing %d silkscreen features against %d board items." ),
158 silkTree.size(),
159 targetTree.size() ) );
160
161 // Cache the board-outline bounding box and per-subshape collision results so that each
162 // subshape is only tested against the outline once during the visitor sweep. Without
163 // caching, QueryCollidingPairs invokes the visitor O(silk * target) times and the outline
164 // Collide (which walks the outline's triangulation) was dominating DRC runtime on boards
165 // with many silkscreen/mask polygons (see issue 24007).
166 PCB_BOARD_OUTLINE* boardOutline = m_board->BoardOutline();
167 BOX2I outlineBBox;
168
169 if( boardOutline && !boardOutline->HasOutline() )
170 boardOutline = nullptr;
171
172 if( boardOutline )
173 outlineBBox = boardOutline->GetOutline().BBoxFromCaches();
174
175 std::unordered_map<const SHAPE*, bool> outlineCollisionCache;
176
177 const std::vector<DRC_RTREE::LAYER_PAIR> layerPairs =
178 {
197 };
198
199 targetTree.QueryCollidingPairs( &silkTree, layerPairs,
200 [&]( const DRC_RTREE::LAYER_PAIR& aLayers, DRC_RTREE::ITEM_WITH_SHAPE* aRefItemShape,
201 DRC_RTREE::ITEM_WITH_SHAPE* aTestItemShape, bool* aCollisionDetected ) -> bool
202 {
203 BOARD_ITEM* refItem = aRefItemShape->parent;
204 const SHAPE* refShape = aRefItemShape->shape;
205 BOARD_ITEM* testItem = aTestItemShape->parent;
206 const SHAPE* testShape = aTestItemShape->shape;
207
208 std::shared_ptr<SHAPE> hole;
209
210 if( m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_CLEARANCE )
211 && m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_MASK_CLEARANCE ) )
212 {
213 return false;
214 }
215
216 if( isInvisibleText( refItem ) || isInvisibleText( testItem ) )
217 return true;
218
219 if( testItem->IsTented( aLayers.first ) )
220 {
221 if( testItem->HasHole() )
222 {
223 hole = testItem->GetEffectiveHoleShape();
224 testShape = hole.get();
225 }
226 else
227 {
228 return true;
229 }
230 }
231
232 if( boardOutline )
233 {
234 if( !testItem->GetBoundingBox().Intersects( outlineBBox ) )
235 return true;
236
237 // Only cache for shapes owned by the R-tree (stable pointers). Hole
238 // shapes are freshly created per visitor call via shared_ptr, so their
239 // raw addresses cannot be safely used as cache keys.
240 bool collidesOutline;
241
242 if( testShape == aTestItemShape->shape )
243 {
244 auto [it, inserted] = outlineCollisionCache.try_emplace( testShape, false );
245
246 if( inserted )
247 it->second = testShape->Collide( &boardOutline->GetOutline() );
248
249 collidesOutline = it->second;
250 }
251 else
252 {
253 collidesOutline = testShape->Collide( &boardOutline->GetOutline() );
254 }
255
256 if( !collidesOutline )
257 return true;
258 }
259
260 int errorCode = DRCE_SILK_CLEARANCE;
262 refItem, testItem, aLayers.second );
263 int minClearance = -1;
264
265 if( !constraint.IsNull() && constraint.GetSeverity() != RPT_SEVERITY_IGNORE )
266 minClearance = constraint.GetValue().Min();
267
268 if( aLayers.second == F_Mask || aLayers.second == B_Mask )
269 {
270 if( checkIndividualMaskItems )
271 minClearance = std::max( minClearance, 0 );
272
273 errorCode = DRCE_SILK_MASK_CLEARANCE;
274 }
275
276 if( minClearance < 0 || m_drcEngine->IsErrorLimitExceeded( errorCode ) )
277 return true;
278
279 int actual;
280 VECTOR2I pos;
281
282 // Graphics are often compound shapes so ignore collisions between shapes in a
283 // single footprint or on the board (both parent footprints will be nullptr).
284 if( refItem->Type() == PCB_SHAPE_T && testItem->Type() == PCB_SHAPE_T
285 && refItem->GetParentFootprint() == testItem->GetParentFootprint() )
286 {
287 return true;
288 }
289
290 // Collide (and generate violations) based on a well-defined order so that
291 // exclusion checking against previously-generated violations will work.
292 if( aLayers.first == aLayers.second )
293 {
294 if( refItem->m_Uuid > testItem->m_Uuid )
295 {
296 std::swap( refItem, testItem );
297 std::swap( refShape, testShape );
298 }
299 }
300
301 if( refShape->Collide( testShape, minClearance, &actual, &pos ) )
302 {
303 std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( errorCode );
304
305 if( minClearance > 0 )
306 {
307 drcItem->SetErrorDetail( formatMsg( _( "(%s clearance %s; actual %s)" ),
308 constraint.GetName(),
309 minClearance,
310 actual ) );
311 }
312
313 drcItem->SetItems( refItem, testItem );
314 drcItem->SetViolatingRule( constraint.GetParentRule() );
315 reportTwoShapeGeometry( drcItem, pos, refShape, testShape, aLayers.second, actual );
316 *aCollisionDetected = true;
317 }
318
319 return true;
320 },
322 [&]( int aCount, int aSize ) -> bool
323 {
324 return reportProgress( aCount, aSize, progressDelta );
325 } );
326
327 return !m_drcEngine->IsCancelled();
328}
329
330
331namespace detail
332{
334}
BOX2< VECTOR2I > BOX2I
Definition box2.h:918
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition board_item.h:80
FOOTPRINT * GetParentFootprint() const
virtual bool IsTented(PCB_LAYER_ID aLayer) const
Checks if the given object is tented (its copper shape is covered by solder mask) on a given side of ...
Definition board_item.h:193
virtual std::shared_ptr< SHAPE_SEGMENT > GetEffectiveHoleShape() const
virtual bool HasHole() const
Definition board_item.h:176
Information pertinent to a Pcbnew printed circuit board.
Definition board.h:320
constexpr bool Intersects(const BOX2< Vec > &aRect) const
Definition box2.h:307
wxString GetName() const
Definition drc_rule.h:204
SEVERITY GetSeverity() const
Definition drc_rule.h:217
const MINOPTMAX< int > & GetValue() const
Definition drc_rule.h:196
MINOPTMAX< int > m_Value
Definition drc_rule.h:240
DRC_RULE * GetParentRule() const
Definition drc_rule.h:200
bool IsNull() const
Definition drc_rule.h:191
static std::shared_ptr< DRC_ITEM > Create(int aErrorCode)
Constructs a DRC_ITEM for the given error code.
Definition drc_item.cpp:412
Implement an R-tree for fast spatial and layer indexing of connectable items.
Definition drc_rtree.h:45
size_t size() const
Return the number of items in the tree.
Definition drc_rtree.h:550
std::pair< PCB_LAYER_ID, PCB_LAYER_ID > LAYER_PAIR
Definition drc_rtree.h:455
int QueryCollidingPairs(DRC_RTREE *aRefTree, std::vector< LAYER_PAIR > aLayerPairs, std::function< bool(const LAYER_PAIR &, ITEM_WITH_SHAPE *, ITEM_WITH_SHAPE *, bool *aCollision)> aVisitor, int aMaxClearance, std::function< bool(int, int)> aProgressReporter) const
Definition drc_rtree.h:470
void Build()
Finalize all pending inserts by bulk-building packed R-trees from the staged items.
Definition drc_rtree.h:164
void Insert(BOARD_ITEM *aItem, PCB_LAYER_ID aLayer, int aWorstClearance=0, bool aAtomicTables=false)
Insert an item into the tree on a particular layer with an optional worst clearance.
Definition drc_rtree.h:91
virtual const wxString GetName() const override
virtual bool Run() override
Run this provider against the given PCB with configured options (if any).
virtual ~DRC_TEST_PROVIDER_SILK_CLEARANCE()=default
virtual bool reportPhase(const wxString &aStageName)
void reportTwoShapeGeometry(std::shared_ptr< DRC_ITEM > &aDrcItem, const VECTOR2I &aMarkerPos, const SHAPE *aShape1, const SHAPE *aShape2, PCB_LAYER_ID aLayer, int aDistance)
int forEachGeometryItem(const std::vector< KICAD_T > &aTypes, const LSET &aLayers, const std::function< bool(BOARD_ITEM *)> &aFunc)
static std::vector< KICAD_T > s_allBasicItems
bool isInvisibleText(const BOARD_ITEM *aItem) const
wxString formatMsg(const wxString &aFormatString, const wxString &aSource, double aConstraint, double aActual, EDA_DATA_TYPE aDataType=EDA_DATA_TYPE::DISTANCE)
virtual bool reportProgress(size_t aCount, size_t aSize, size_t aDelta=1)
virtual const BOX2I GetBoundingBox() const
Return the orthogonal bounding box of this object for display purposes.
Definition eda_item.cpp:135
const KIID m_Uuid
Definition eda_item.h:531
KICAD_T Type() const
Returns the type of object.
Definition eda_item.h:108
LSET is a set of PCB_LAYER_IDs.
Definition lset.h:37
static const LSET & FrontMask()
Return a mask holding all technical layers and the external CU layer on front side.
Definition lset.cpp:718
static const LSET & BackMask()
Return a mask holding all technical layers and the external CU layer on back side.
Definition lset.cpp:725
T Min() const
Definition minoptmax.h:29
bool HasOutline() const
const SHAPE_POLY_SET & GetOutline() const
const BOX2I BBoxFromCaches() const
An abstract shape on 2D plane.
Definition shape.h:124
virtual bool Collide(const VECTOR2I &aP, int aClearance=0, int *aActual=nullptr, VECTOR2I *aLocation=nullptr) const
Check if the boundary of shape (this) lies closer to the point aP than aClearance,...
Definition shape.h:179
Handle a list of polygons defining a copper zone.
Definition zone.h:70
The common library.
@ DRCE_SILK_MASK_CLEARANCE
Definition drc_item.h:93
@ DRCE_SILK_CLEARANCE
Definition drc_item.h:96
#define ATOMIC_TABLES
Definition drc_rtree.h:38
@ SILK_CLEARANCE_CONSTRAINT
Definition drc_rule.h:58
#define REPORT_AUX(s)
#define _(s)
PCB_LAYER_ID
A quick note on layer IDs:
Definition layer_ids.h:56
@ F_CrtYd
Definition layer_ids.h:112
@ B_Adhes
Definition layer_ids.h:99
@ Edge_Cuts
Definition layer_ids.h:108
@ F_Paste
Definition layer_ids.h:100
@ F_Adhes
Definition layer_ids.h:98
@ B_Mask
Definition layer_ids.h:94
@ B_Cu
Definition layer_ids.h:61
@ F_Mask
Definition layer_ids.h:93
@ B_Paste
Definition layer_ids.h:101
@ F_Fab
Definition layer_ids.h:115
@ Margin
Definition layer_ids.h:109
@ F_SilkS
Definition layer_ids.h:96
@ B_CrtYd
Definition layer_ids.h:111
@ B_SilkS
Definition layer_ids.h:97
@ F_Cu
Definition layer_ids.h:60
@ B_Fab
Definition layer_ids.h:114
static DRC_REGISTER_TEST_PROVIDER< DRC_TEST_PROVIDER_ANNULAR_WIDTH > dummy
@ RPT_SEVERITY_IGNORE
int actual
@ PCB_SHAPE_T
class PCB_SHAPE, a segment not on copper layers
Definition typeinfo.h:81
@ PCB_ZONE_T
class ZONE, a copper pour area
Definition typeinfo.h:101
VECTOR2< int32_t > VECTOR2I
Definition vector2d.h:683