57 virtual bool Run()
override;
59 virtual const wxString
GetName()
const override
61 return wxT(
"silk_clearance" );
66 return wxT(
"Tests for overlapping silkscreen features." );
78 const int progressDelta = 500;
82 reportAux( wxT(
"Overlapping silk violations ignored. Tests not run." ) );
96 if( !
reportPhase(
_(
"Checking silkscreen for overlapping items..." ) ) )
119 if( item->IsOnLayer( layer ) )
120 silkTree.
Insert( item, layer );
126 auto addToTargetTree =
133 targetTree.
Insert( item, layer );
150 reportAux( wxT(
"Testing %d silkscreen features against %d board items." ),
154 const std::vector<DRC_RTREE::LAYER_PAIR> layerPairs =
183 const SHAPE* testShape = aTestItemShape->
shape;
185 std::shared_ptr<SHAPE> hole;
193 if( testItem->
IsTented( aLayers.first ) )
195 if( testItem->HasHole() )
197 hole = testItem->GetEffectiveHoleShape();
198 testShape = hole.get();
215 if( minClearance < 0 )
224 && refItem->GetParentFootprint() == testItem->GetParentFootprint() )
229 if( refShape->Collide( testShape, minClearance, &actual, &pos ) )
231 std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_OVERLAPPING_SILK );
233 if( minClearance > 0 )
235 wxString msg = formatMsg( _(
"(%s clearance %s; actual %s)" ),
236 constraint.GetParentRule()->m_Name,
240 drcItem->SetErrorMessage( drcItem->GetErrorText() + wxS(
" " ) + msg );
243 drcItem->SetItems( refItem, testItem );
248 *aCollisionDetected =
true;
254 [&](
int aCount,
int aSize ) ->
bool
256 return reportProgress( aCount, aSize, progressDelta );
259 reportRuleStatistics();
261 return !m_drcEngine->IsCancelled();
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
virtual bool IsTented(PCB_LAYER_ID aLayer) const
Checks if the given object is tented (its copper shape is covered by solder mask) on a given side of ...
Information pertinent to a Pcbnew printed circuit board.
SEVERITY GetSeverity() const
const MINOPTMAX< int > & GetValue() const
DRC_RULE * GetParentRule() const
bool IsErrorLimitExceeded(int error_code)
DRC_CONSTRAINT EvalRules(DRC_CONSTRAINT_T aConstraintType, const BOARD_ITEM *a, const BOARD_ITEM *b, PCB_LAYER_ID aLayer, REPORTER *aReporter=nullptr)
bool QueryWorstConstraint(DRC_CONSTRAINT_T aRuleId, DRC_CONSTRAINT &aConstraint)
Implement an R-tree for fast spatial and layer indexing of connectable items.
void Insert(BOARD_ITEM *aItem, PCB_LAYER_ID aLayer, int aWorstClearance=0)
Insert an item into the tree on a particular layer with an optional worst clearance.
size_t size() const
Return the number of items in the tree.
std::pair< PCB_LAYER_ID, PCB_LAYER_ID > LAYER_PAIR
int QueryCollidingPairs(DRC_RTREE *aRefTree, std::vector< LAYER_PAIR > aLayerPairs, std::function< bool(const LAYER_PAIR &, ITEM_WITH_SHAPE *, ITEM_WITH_SHAPE *, bool *aCollision)> aVisitor, int aMaxClearance, std::function< bool(int, int)> aProgressReporter) const
virtual const wxString GetName() const override
virtual bool Run() override
Run this provider against the given PCB with configured options (if any).
virtual const wxString GetDescription() const override
DRC_TEST_PROVIDER_SILK_CLEARANCE()
virtual ~DRC_TEST_PROVIDER_SILK_CLEARANCE()
Represent a DRC "provider" which runs some DRC functions over a BOARD and spits out DRC_ITEM and posi...
virtual bool reportPhase(const wxString &aStageName)
int forEachGeometryItem(const std::vector< KICAD_T > &aTypes, LSET aLayers, const std::function< bool(BOARD_ITEM *)> &aFunc)
virtual void reportViolation(std::shared_ptr< DRC_ITEM > &item, const VECTOR2I &aMarkerPos, int aMarkerLayer)
static std::vector< KICAD_T > s_allBasicItems
bool isInvisibleText(const BOARD_ITEM *aItem) const
void reportAux(const wxString &aMsg)
virtual bool reportProgress(size_t aCount, size_t aSize, size_t aDelta=1)
LSET is a set of PCB_LAYER_IDs.
static LSET FrontMask()
Return a mask holding all technical layers and the external CU layer on front side.
static LSET BackMask()
Return a mask holding all technical layers and the external CU layer on back side.
An abstract shape on 2D plane.
@ SILK_CLEARANCE_CONSTRAINT
PCB_LAYER_ID
A quick note on layer IDs:
static DRC_REGISTER_TEST_PROVIDER< DRC_TEST_PROVIDER_ANNULAR_WIDTH > dummy
@ PCB_SHAPE_T
class PCB_SHAPE, a segment not on copper layers