KiCad PCB EDA Suite
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connectivity_data.cpp
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1/*
2 * This program source code file is part of KICAD, a free EDA CAD application.
3 *
4 * Copyright (C) 2017 CERN
5 * Copyright The KiCad Developers, see AUTHORS.txt for contributors.
6 * @author Tomasz Wlostowski <[email protected]>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <https://www.gnu.org/licenses/>.
20 */
21
22#ifdef PROFILE
23#include <core/profile.h>
24#endif
25
26#include <algorithm>
27#include <future>
28#include <initializer_list>
29
32#include <properties/property.h>
34#include <board_item.h>
39#include <footprint.h>
40#include <pad.h>
41#include <pcb_track.h>
43#include <progress_reporter.h>
44#include <thread_pool.h>
45#include <trigo.h>
46#include <drc/drc_rtree.h>
48
56
57
58CONNECTIVITY_DATA::CONNECTIVITY_DATA( std::shared_ptr<CONNECTIVITY_DATA> aGlobalConnectivity,
59 const std::vector<BOARD_ITEM*>& aLocalItems,
60 bool aSkipRatsnestUpdate ) :
61 m_skipRatsnestUpdate( aSkipRatsnestUpdate )
62{
63 Build( aGlobalConnectivity, aLocalItems );
64 m_progressReporter = nullptr;
65 m_fromToCache.reset( new FROM_TO_CACHE );
66}
67
68
70{
71 for( RN_NET* net : m_nets )
72 delete net;
73
74 m_nets.clear();
75}
76
77
79{
80 m_connAlgo->Add( aItem );
81 return true;
82}
83
84
86{
87 m_connAlgo->Remove( aItem );
88 return true;
89}
90
91
93{
94 m_connAlgo->Remove( aItem );
95 m_connAlgo->Add( aItem );
96 return true;
97}
98
99
101{
102 aBoard->CacheTriangulation( aReporter );
103
104 std::unique_lock<KISPINLOCK> lock( m_lock, std::try_to_lock );
105
106 if( !lock )
107 return false;
108
109 if( aReporter )
110 {
111 aReporter->Report( _( "Updating nets..." ) );
112 aReporter->KeepRefreshing( false );
113 }
114
115 for( RN_NET* net : m_nets )
116 delete net;
117
118 m_nets.clear();
119
120 m_connAlgo.reset( new CN_CONNECTIVITY_ALGO( this ) );
121 m_connAlgo->Build( aBoard, aReporter );
122
124
125 RefreshNetcodeMap( aBoard );
126
127 if( aReporter )
128 {
129 aReporter->SetCurrentProgress( 0.75 );
130 aReporter->KeepRefreshing( false );
131 }
132
134
135 if( aReporter )
136 {
137 aReporter->SetCurrentProgress( 1.0 );
138 aReporter->KeepRefreshing( false );
139 }
140
141 return true;
142}
143
144
146{
147 m_netcodeMap.clear();
148
149 for( NETINFO_ITEM* net : aBoard->GetNetInfo() )
150 m_netcodeMap[net->GetNetCode()] = net->GetNetname();
151}
152
153
154void CONNECTIVITY_DATA::Build( std::shared_ptr<CONNECTIVITY_DATA>& aGlobalConnectivity,
155 const std::vector<BOARD_ITEM*>& aLocalItems )
156{
157 std::unique_lock<KISPINLOCK> lock( m_lock, std::try_to_lock );
158
159 if( !lock )
160 return;
161
162 m_connAlgo.reset( new CN_CONNECTIVITY_ALGO( this ) );
163 m_connAlgo->LocalBuild( aGlobalConnectivity, aLocalItems );
164
166}
167
168
170{
171 m_connAlgo->ForEachAnchor( [&aDelta]( CN_ANCHOR& anchor )
172 {
173 anchor.Move( aDelta );
174 } );
175}
176
177
179{
180#ifdef PROFILE
181 PROF_TIMER rnUpdate( "update-ratsnest" );
182#endif
183
184 std::vector<RN_NET*> dirty_nets;
185
186 // Start with net 1 as net 0 is reserved for not-connected
187 // Nets without nodes are also ignored
188 std::copy_if( m_nets.begin() + 1, m_nets.end(), std::back_inserter( dirty_nets ),
189 [] ( RN_NET* aNet )
190 {
191 return aNet->IsDirty() && aNet->GetNodeCount() > 0;
192 } );
193
195
196 auto results = tp.submit_loop( 0, dirty_nets.size(),
197 [&]( const int ii )
198 {
199 dirty_nets[ii]->UpdateNet();
200 } );
201 results.wait();
202
203 auto results2 = tp.submit_loop( 0, dirty_nets.size(),
204 [&]( const int ii )
205 {
206 dirty_nets[ii]->OptimizeRNEdges();
207 } );
208 results2.wait();
209
210#ifdef PROFILE
211 rnUpdate.Show();
212#endif
213}
214
215
216void CONNECTIVITY_DATA::addRatsnestCluster( const std::shared_ptr<CN_CLUSTER>& aCluster )
217{
218 RN_NET* rnNet = m_nets[ aCluster->OriginNet() ];
219
220 rnNet->AddCluster( aCluster );
221}
222
223
225{
226
227 // We can take over the lock here if called in the same thread
228 // This is to prevent redraw during a RecalculateRatsnets process
229 std::unique_lock<KISPINLOCK> lock( m_lock );
230
232
233}
234
236{
237 m_connAlgo->PropagateNets( aCommit );
238
239 int lastNet = m_connAlgo->NetCount();
240
241 if( lastNet >= (int) m_nets.size() )
242 {
243 unsigned int prevSize = m_nets.size();
244 m_nets.resize( lastNet + 1 );
245
246 for( unsigned int i = prevSize; i < m_nets.size(); i++ )
247 m_nets[i] = new RN_NET;
248 }
249 else
250 {
251 for( size_t ii = lastNet; ii < m_nets.size(); ++ii )
252 m_nets[ii]->Clear();
253 }
254
255 const std::vector<std::shared_ptr<CN_CLUSTER>>& clusters = m_connAlgo->GetClusters();
256
257 for( int net = 0; net < lastNet; net++ )
258 {
259 if( m_connAlgo->IsNetDirty( net ) )
260 m_nets[net]->Clear();
261 }
262
263 for( const std::shared_ptr<CN_CLUSTER>& c : clusters )
264 {
265 int net = c->OriginNet();
266
267 // Don't add intentionally-kept zone islands to the ratsnest
268 if( c->IsOrphaned() && c->Size() == 1 )
269 {
270 if( dynamic_cast<CN_ZONE_LAYER*>( *c->begin() ) )
271 continue;
272 }
273
274 if( m_connAlgo->IsNetDirty( net ) )
276 }
277
278 m_connAlgo->ClearDirtyFlags();
279
282}
283
284
285void CONNECTIVITY_DATA::BlockRatsnestItems( const std::vector<BOARD_ITEM*>& aItems )
286{
287 std::vector<BOARD_CONNECTED_ITEM*> citems;
288
289 for( BOARD_ITEM* item : aItems )
290 {
291 if( item->Type() == PCB_FOOTPRINT_T )
292 {
293 for( PAD* pad : static_cast<FOOTPRINT*>(item)->Pads() )
294 citems.push_back( pad );
295 }
296 else
297 {
298 if( BOARD_CONNECTED_ITEM* citem = dynamic_cast<BOARD_CONNECTED_ITEM*>( item ) )
299 citems.push_back( citem );
300 }
301 }
302
303 for( const BOARD_CONNECTED_ITEM* item : citems )
304 {
305 if ( m_connAlgo->ItemExists( item ) )
306 {
307 CN_CONNECTIVITY_ALGO::ITEM_MAP_ENTRY& entry = m_connAlgo->ItemEntry( item );
308
309 for( CN_ITEM* cnItem : entry.GetItems() )
310 {
311 for( const std::shared_ptr<CN_ANCHOR>& anchor : cnItem->Anchors() )
312 anchor->SetNoLine( true );
313 }
314 }
315 }
316}
317
318
320{
321 return m_connAlgo->NetCount();
322}
323
324
325void CONNECTIVITY_DATA::FillIsolatedIslandsMap( std::map<ZONE*, std::map<PCB_LAYER_ID, ISOLATED_ISLANDS>>& aMap,
326 bool aConnectivityAlreadyRebuilt )
327{
328 m_connAlgo->FillIsolatedIslandsMap( aMap, aConnectivityAlreadyRebuilt );
329}
330
331
332void CONNECTIVITY_DATA::ComputeLocalRatsnest( const std::vector<BOARD_ITEM*>& aItems,
333 const CONNECTIVITY_DATA* aDynamicData,
334 VECTOR2I aInternalOffset )
335{
336 if( !aDynamicData )
337 return;
338
339 m_dynamicRatsnest.clear();
340 std::mutex dynamic_ratsnest_mutex;
341
342 // This gets connections between the stationary board and the
343 // moving selection
344
345 auto update_lambda = [&]( int nc )
346 {
347 RN_NET* dynamicNet = aDynamicData->m_nets[nc];
348 RN_NET* staticNet = m_nets[nc];
349
353 if( dynamicNet->GetNodeCount() != 0 && dynamicNet->GetNodeCount() != staticNet->GetNodeCount() )
354 {
355 VECTOR2I pos1, pos2;
356
357 if( staticNet->NearestBicoloredPair( dynamicNet, pos1, pos2 ) )
358 {
360 l.a = pos1;
361 l.b = pos2;
362 l.netCode = nc;
363
364 std::lock_guard<std::mutex> lock( dynamic_ratsnest_mutex );
365 m_dynamicRatsnest.push_back( l );
366 }
367 }
368 };
369
371 size_t num_nets = std::min( m_nets.size(), aDynamicData->m_nets.size() );
372
373 auto results = tp.submit_loop( 1, num_nets,
374 [&]( const int ii )
375 {
376 update_lambda( ii );
377 });
378 results.wait();
379
380 // This gets the ratsnest for internal connections in the moving set
381 const std::vector<CN_EDGE>& edges = GetRatsnestForItems( aItems );
382
383 for( const CN_EDGE& edge : edges )
384 {
385 const std::shared_ptr<const CN_ANCHOR>& nodeA = edge.GetSourceNode();
386 const std::shared_ptr<const CN_ANCHOR>& nodeB = edge.GetTargetNode();
387
388 if( !nodeA || nodeA->Dirty() || !nodeB || nodeB->Dirty() )
389 continue;
390
392
393 // Use the parents' positions
394 l.a = nodeA->Parent()->GetPosition() + aInternalOffset;
395 l.b = nodeB->Parent()->GetPosition() + aInternalOffset;
396 l.netCode = 0;
397 m_dynamicRatsnest.push_back( l );
398 }
399}
400
401
403{
404 m_connAlgo->ForEachAnchor( []( CN_ANCHOR& anchor )
405 {
406 anchor.SetNoLine( false );
407 } );
409}
410
411
416
417
419{
420 m_connAlgo->PropagateNets( aCommit );
421}
422
423
425 const std::initializer_list<KICAD_T>& aTypes ) const
426{
427 CN_CONNECTIVITY_ALGO::ITEM_MAP_ENTRY &entry = m_connAlgo->ItemEntry( aItem );
428
429 FOOTPRINT* parentFootprint = aItem->GetParentFootprint();
430
431 auto matchType =
432 [&]( KICAD_T aItemType )
433 {
434 if( aTypes.size() == 0 )
435 return true;
436
437 return alg::contains( aTypes, aItemType);
438 };
439
440 for( CN_ITEM* citem : entry.GetItems() )
441 {
442 for( CN_ITEM* connected : citem->ConnectedItems() )
443 {
444 CN_ZONE_LAYER* zoneLayer = dynamic_cast<CN_ZONE_LAYER*>( connected );
445
446 // lyIdx is compatible with StartLayer() and EndLayer() notation in CN_ITEM
447 // items, where B_Cu is set to INT_MAX (std::numeric_limits<int>::max())
448 int lyIdx = aLayer;
449
450 if( aLayer == B_Cu )
451 lyIdx = std::numeric_limits<int>::max();
452
453 if( connected->Valid()
454 && connected->StartLayer() <= lyIdx && connected->EndLayer() >= lyIdx
455 && matchType( connected->Parent()->Type() )
456 && connected->Net() == aItem->GetNetCode() )
457 {
458 BOARD_ITEM* connectedItem = connected->Parent();
459
460 if( connectedItem == aItem )
461 continue;
462
463 if( parentFootprint && connectedItem
464 && connectedItem->GetParentFootprint() == parentFootprint )
465 {
466 continue;
467 }
468
469 if( aItem->Type() == PCB_PAD_T && connectedItem
470 && connectedItem->Type() == PCB_PAD_T )
471 {
472 const PAD* thisPad = static_cast<const PAD*>( aItem );
473 const PAD* otherPad = static_cast<const PAD*>( connectedItem );
474
475 auto flashesConditionally = []( UNCONNECTED_LAYER_MODE aMode )
476 {
479 };
480
481 if( flashesConditionally( thisPad->Padstack().UnconnectedLayerMode() )
482 && flashesConditionally( otherPad->Padstack().UnconnectedLayerMode() ) )
483 {
484 continue;
485 }
486 }
487
488 if( aItem->Type() == PCB_PAD_T && zoneLayer )
489 {
490 const PAD* pad = static_cast<const PAD*>( aItem );
491 ZONE* zone = static_cast<ZONE*>( zoneLayer->Parent() );
492 int islandIdx = zoneLayer->SubpolyIndex();
493
494 if( zone->IsFilled() )
495 {
496 PCB_LAYER_ID pcbLayer = ToLAYER_ID( aLayer );
497 const SHAPE_POLY_SET* zoneFill = zone->GetFill( pcbLayer );
498 const SHAPE_LINE_CHAIN& padHull = pad->GetEffectivePolygon( pcbLayer,
499 ERROR_INSIDE )->Outline( 0 );
500
501 for( const VECTOR2I& pt : zoneFill->COutline( islandIdx ).CPoints() )
502 {
503 // If the entire island is inside the pad's flashing then the pad
504 // won't actually connect to anything else, so only return true if
505 // part of the island is *outside* the pad's flashing.
506
507 if( !padHull.PointInside( pt ) )
508 return true;
509 }
510 }
511
512 continue;
513 }
514 else if( aItem->Type() == PCB_VIA_T && zoneLayer )
515 {
516 const PCB_VIA* via = static_cast<const PCB_VIA*>( aItem );
517 ZONE* zone = static_cast<ZONE*>( zoneLayer->Parent() );
518 int islandIdx = zoneLayer->SubpolyIndex();
519
520 if( zone->IsFilled() )
521 {
522 PCB_LAYER_ID layer = ToLAYER_ID( aLayer );
523 const SHAPE_POLY_SET* zoneFill = zone->GetFill( layer );
524 SHAPE_CIRCLE viaHull( via->GetCenter(), via->GetWidth( layer ) / 2 );
525
526 for( const VECTOR2I& pt : zoneFill->COutline( islandIdx ).CPoints() )
527 {
528 // If the entire island is inside the via's flashing then the via
529 // won't actually connect to anything else, so only return true if
530 // part of the island is *outside* the via's flashing.
531
532 if( !viaHull.SHAPE::Collide( pt ) )
533 return true;
534 }
535 }
536
537 continue;
538 }
539
540 return true;
541 }
542 }
543 }
544
545 return false;
546}
547
548
549unsigned int CONNECTIVITY_DATA::GetUnconnectedCount( bool aVisibleOnly ) const
550{
551 unsigned int unconnected = 0;
552
553 for( RN_NET* net : m_nets )
554 {
555 if( !net )
556 continue;
557
558 for( const CN_EDGE& edge : net->GetEdges() )
559 {
560 if( edge.IsVisible() || !aVisibleOnly )
561 ++unconnected;
562 }
563 }
564
565 return unconnected;
566}
567
568
570{
571 for( RN_NET* net : m_nets )
572 net->Clear();
573}
574
575
576const std::vector<BOARD_CONNECTED_ITEM*>
578{
581
582 std::vector<BOARD_CONNECTED_ITEM*> rv;
583
584 auto clusters = m_connAlgo->SearchClusters( ( aFlags & IGNORE_NETS ) ? CSM_PROPAGATE : CSM_CONNECTIVITY_CHECK,
585 ( aFlags & EXCLUDE_ZONES ),
586 ( aFlags & IGNORE_NETS ) ? -1 : aItem->GetNetCode() );
587
588 for( const std::shared_ptr<CN_CLUSTER>& cl : clusters )
589 {
590 if( cl->Contains( aItem ) )
591 {
592 for( const CN_ITEM* item : *cl )
593 {
594 if( item->Valid() )
595 rv.push_back( item->Parent() );
596 }
597 }
598 }
599
600 return rv;
601}
602
603
604const std::vector<BOARD_CONNECTED_ITEM*>
605CONNECTIVITY_DATA::GetNetItems( int aNetCode, const std::vector<KICAD_T>& aTypes ) const
606{
607 std::vector<BOARD_CONNECTED_ITEM*> items;
608 items.reserve( 32 );
609
610 std::bitset<MAX_STRUCT_TYPE_ID> type_bits;
611
612 for( KICAD_T scanType : aTypes )
613 {
614 wxASSERT( scanType < MAX_STRUCT_TYPE_ID );
615 type_bits.set( scanType );
616 }
617
618 m_connAlgo->ForEachItem(
619 [&]( CN_ITEM& aItem )
620 {
621 if( aItem.Valid() && ( aItem.Net() == aNetCode ) && type_bits[aItem.Parent()->Type()] )
622 items.push_back( aItem.Parent() );
623 } );
624
625 std::sort( items.begin(), items.end() );
626 items.erase( std::unique( items.begin(), items.end() ), items.end() );
627 return items;
628}
629
630
631const std::vector<PCB_TRACK*>
633{
634 CN_CONNECTIVITY_ALGO::ITEM_MAP_ENTRY& entry = m_connAlgo->ItemEntry( aItem );
635
636 std::set<PCB_TRACK*> tracks;
637 std::vector<PCB_TRACK*> rv;
638
639 for( CN_ITEM* citem : entry.GetItems() )
640 {
641 for( CN_ITEM* connected : citem->ConnectedItems() )
642 {
643 if( connected->Valid() &&
644 ( connected->Parent()->Type() == PCB_TRACE_T ||
645 connected->Parent()->Type() == PCB_VIA_T ||
646 connected->Parent()->Type() == PCB_ARC_T ) )
647 {
648 tracks.insert( static_cast<PCB_TRACK*> ( connected->Parent() ) );
649 }
650 }
651 }
652
653 std::copy( tracks.begin(), tracks.end(), std::back_inserter( rv ) );
654 return rv;
655}
656
657
658void CONNECTIVITY_DATA::GetConnectedPads( const BOARD_CONNECTED_ITEM* aItem, std::set<PAD*>* pads ) const
659{
660 for( CN_ITEM* citem : m_connAlgo->ItemEntry( aItem ).GetItems() )
661 {
662 for( CN_ITEM* connected : citem->ConnectedItems() )
663 {
664 if( connected->Valid() && connected->Parent()->Type() == PCB_PAD_T )
665 pads->insert( static_cast<PAD*> ( connected->Parent() ) );
666 }
667 }
668}
669
670
671const std::vector<PAD*> CONNECTIVITY_DATA::GetConnectedPads( const BOARD_CONNECTED_ITEM* aItem )
672const
673{
674 std::set<PAD*> pads;
675 std::vector<PAD*> rv;
676
677 GetConnectedPads( aItem, &pads );
678
679 std::copy( pads.begin(), pads.end(), std::back_inserter( rv ) );
680 return rv;
681}
682
683
684void CONNECTIVITY_DATA::GetConnectedPadsAndVias( const BOARD_CONNECTED_ITEM* aItem, std::vector<PAD*>* pads,
685 std::vector<PCB_VIA*>* vias )
686{
687 for( CN_ITEM* citem : m_connAlgo->ItemEntry( aItem ).GetItems() )
688 {
689 for( CN_ITEM* connected : citem->ConnectedItems() )
690 {
691 if( connected->Valid() )
692 {
693 BOARD_CONNECTED_ITEM* parent = connected->Parent();
694
695 if( parent->Type() == PCB_PAD_T )
696 pads->push_back( static_cast<PAD*>( parent ) );
697 else if( parent->Type() == PCB_VIA_T )
698 vias->push_back( static_cast<PCB_VIA*>( parent ) );
699 }
700 }
701 }
702}
703
704
705unsigned int CONNECTIVITY_DATA::GetNodeCount( int aNet ) const
706{
707 int sum = 0;
708
709 if( aNet < 0 ) // Node count for all nets
710 {
711 for( const RN_NET* net : m_nets )
712 sum += net->GetNodeCount();
713 }
714 else if( aNet < (int) m_nets.size() )
715 {
716 sum = m_nets[aNet]->GetNodeCount();
717 }
718
719 return sum;
720}
721
722
723unsigned int CONNECTIVITY_DATA::GetPadCount( int aNet ) const
724{
725 int n = 0;
726
727 for( CN_ITEM* pad : m_connAlgo->ItemList() )
728 {
729 if( !pad->Valid() || pad->Parent()->Type() != PCB_PAD_T)
730 continue;
731
732 PAD* dpad = static_cast<PAD*>( pad->Parent() );
733
734 if( aNet < 0 || aNet == dpad->GetNetCode() )
735 n++;
736 }
737
738 return n;
739}
740
741
742void CONNECTIVITY_DATA::RunOnUnconnectedEdges( std::function<bool( CN_EDGE& )> aFunc )
743{
744 for( RN_NET* rnNet : m_nets )
745 {
746 if( rnNet )
747 {
748 for( CN_EDGE& edge : rnNet->GetEdges() )
749 {
750 if( !aFunc( edge ) )
751 return;
752 }
753 }
754 }
755}
756
757
758static int getMinDist( BOARD_CONNECTED_ITEM* aItem, const VECTOR2I& aPoint )
759{
760 switch( aItem->Type() )
761 {
762 case PCB_TRACE_T:
763 case PCB_ARC_T:
764 {
765 PCB_TRACK* track = static_cast<PCB_TRACK*>( aItem );
766
767 return std::min( track->GetStart().Distance(aPoint ), track->GetEnd().Distance( aPoint ) );
768 }
769
770 default:
771 return aItem->GetPosition().Distance( aPoint );
772 }
773}
774
775
776bool CONNECTIVITY_DATA::TestTrackEndpointDangling( PCB_TRACK* aTrack, bool aIgnoreTracksInPads,
777 VECTOR2I* aPos ) const
778{
779 const std::list<CN_ITEM*>& items = GetConnectivityAlgo()->ItemEntry( aTrack ).GetItems();
780
781 // Not in the connectivity system. This is a bug!
782 if( items.empty() )
783 {
784 wxFAIL_MSG( wxT( "track not in connectivity system" ) );
785 return false;
786 }
787
788 CN_ITEM* citem = items.front();
789
790 if( !citem->Valid() )
791 return false;
792
793 if( aTrack->Type() == PCB_TRACE_T || aTrack->Type() == PCB_ARC_T )
794 {
795 // Test if a segment is connected on each end.
796 //
797 // NB: be wary of short segments which can be connected to the *same* other item on
798 // each end. If that's their only connection then they're still dangling.
799
800 PCB_LAYER_ID layer = aTrack->GetLayer();
801 int accuracy = KiROUND( aTrack->GetWidth() / 2.0 );
802 int start_count = 0;
803 int end_count = 0;
804
805 for( CN_ITEM* connected : citem->ConnectedItems() )
806 {
807 BOARD_CONNECTED_ITEM* item = connected->Parent();
808 ZONE* zone = dynamic_cast<ZONE*>( item );
809 DRC_RTREE* rtree = nullptr;
810 bool hitStart = false;
811 bool hitEnd = false;
812
813 if( item->GetFlags() & IS_DELETED )
814 continue;
815
816 if( zone )
817 rtree = zone->GetBoard()->m_CopperZoneRTreeCache[ zone ].get();
818
819 if( rtree )
820 {
821 SHAPE_CIRCLE start( aTrack->GetStart(), accuracy );
822 SHAPE_CIRCLE end( aTrack->GetEnd(), accuracy );
823
824 hitStart = rtree->QueryColliding( start.BBox(), &start, layer );
825 hitEnd = rtree->QueryColliding( end.BBox(), &end, layer );
826 }
827 else
828 {
829 std::shared_ptr<SHAPE> shape = item->GetEffectiveShape( layer );
830
831 hitStart = shape->Collide( aTrack->GetStart(), accuracy );
832 hitEnd = shape->Collide( aTrack->GetEnd(), accuracy );
833 }
834
835 if( hitStart && hitEnd )
836 {
837 if( zone )
838 {
839 // Both start and end in a zone: track may be redundant, but it's not dangling
840 return false;
841 }
842 else if( item->Type() == PCB_PAD_T || item->Type() == PCB_VIA_T )
843 {
844 // Both start and end are under a pad: see what the caller wants us to do
845 if( aIgnoreTracksInPads )
846 return false;
847 }
848
849 if( getMinDist( item, aTrack->GetStart() ) < getMinDist( item, aTrack->GetEnd() ) )
850 start_count++;
851 else
852 end_count++;
853 }
854 else if( hitStart )
855 {
856 start_count++;
857 }
858 else if( hitEnd )
859 {
860 end_count++;
861 }
862
863 if( start_count > 0 && end_count > 0 )
864 return false;
865 }
866
867 if( aPos )
868 *aPos = (start_count == 0 ) ? aTrack->GetStart() : aTrack->GetEnd();
869
870 return true;
871 }
872 else if( aTrack->Type() == PCB_VIA_T )
873 {
874 // Test if a via is only connected on one layer
875
876 const std::vector<CN_ITEM*>& connected = citem->ConnectedItems();
877
878 if( connected.empty() )
879 {
880 // No connections AND no-net is not an error
881 if( aTrack->GetNetCode() <= 0 )
882 return false;
883
884 if( aPos )
885 *aPos = aTrack->GetPosition();
886
887 return true;
888 }
889
890 // Here, we check if the via is connected only to items on a single layer
891 int first_layer = UNDEFINED_LAYER;
892
893 for( CN_ITEM* item : connected )
894 {
895 if( item->Parent()->GetFlags() & IS_DELETED )
896 continue;
897
898 if( first_layer == UNDEFINED_LAYER )
899 first_layer = item->Layer();
900 else if( item->Layer() != first_layer )
901 return false;
902 }
903
904 if( aPos )
905 *aPos = aTrack->GetPosition();
906
907 return true;
908 }
909 else
910 {
911 wxFAIL_MSG( wxT( "CONNECTIVITY_DATA::TestTrackEndpointDangling: unknown track type" ) );
912 }
913
914 return false;
915}
916
917
918const std::vector<BOARD_CONNECTED_ITEM*>
920 const std::vector<KICAD_T>& aTypes, const int& aMaxError ) const
921{
922 CN_CONNECTIVITY_ALGO::ITEM_MAP_ENTRY& entry = m_connAlgo->ItemEntry( aItem );
923 std::vector<BOARD_CONNECTED_ITEM*> rv;
924 SEG::ecoord maxError_sq = (SEG::ecoord) aMaxError * aMaxError;
925
926 for( CN_ITEM* cnItem : entry.GetItems() )
927 {
928 for( CN_ITEM* connected : cnItem->ConnectedItems() )
929 {
930 for( const std::shared_ptr<CN_ANCHOR>& anchor : connected->Anchors() )
931 {
932 if( ( anchor->Pos() - aAnchor ).SquaredEuclideanNorm() <= maxError_sq )
933 {
934 for( KICAD_T type : aTypes )
935 {
936 if( connected->Valid() && connected->Parent()->Type() == type )
937 {
938 rv.push_back( connected->Parent() );
939 break;
940 }
941 }
942
943 break;
944 }
945 }
946 }
947 }
948
949 return rv;
950}
951
952
954{
955 if ( aNet < 0 || aNet >= (int) m_nets.size() )
956 return nullptr;
957
958 return m_nets[ aNet ];
959}
960
961
963{
964 if ( aItem->Type() == PCB_FOOTPRINT_T)
965 {
966 for( PAD* pad : static_cast<FOOTPRINT*>( aItem )->Pads() )
967 m_connAlgo->MarkNetAsDirty( pad->GetNetCode() );
968 }
969
970 if (aItem->IsConnected() )
971 m_connAlgo->MarkNetAsDirty( static_cast<BOARD_CONNECTED_ITEM*>( aItem )->GetNetCode() );
972}
973
974
976{
977 m_connAlgo->RemoveInvalidRefs();
978
979 for( RN_NET* rnNet : m_nets )
980 rnNet->RemoveInvalidRefs();
981}
982
983
985{
986 m_progressReporter = aReporter;
987 m_connAlgo->SetProgressReporter( m_progressReporter );
988}
989
990
991const std::vector<CN_EDGE>
992CONNECTIVITY_DATA::GetRatsnestForItems( const std::vector<BOARD_ITEM*>& aItems )
993{
994 std::set<int> nets;
995 std::vector<CN_EDGE> edges;
996 std::set<BOARD_CONNECTED_ITEM*> item_set;
997
998 for( BOARD_ITEM* item : aItems )
999 {
1000 if( item->Type() == PCB_FOOTPRINT_T )
1001 {
1002 FOOTPRINT* footprint = static_cast<FOOTPRINT*>( item );
1003
1004 for( PAD* pad : footprint->Pads() )
1005 {
1006 nets.insert( pad->GetNetCode() );
1007 item_set.insert( pad );
1008 }
1009 }
1010 else if( item->IsConnected() )
1011 {
1012 BOARD_CONNECTED_ITEM* conn_item = static_cast<BOARD_CONNECTED_ITEM*>( item );
1013
1014 item_set.insert( conn_item );
1015 nets.insert( conn_item->GetNetCode() );
1016 }
1017 }
1018
1019 for( int netcode : nets )
1020 {
1021 RN_NET* net = GetRatsnestForNet( netcode );
1022
1023 if( !net )
1024 continue;
1025
1026 for( const CN_EDGE& edge : net->GetEdges() )
1027 {
1028 std::shared_ptr<const CN_ANCHOR> srcNode = edge.GetSourceNode();
1029 std::shared_ptr<const CN_ANCHOR> dstNode = edge.GetTargetNode();
1030
1031 if( !srcNode || srcNode->Dirty() || !dstNode || dstNode->Dirty() )
1032 continue;
1033
1034 BOARD_CONNECTED_ITEM* srcParent = srcNode->Parent();
1035 BOARD_CONNECTED_ITEM* dstParent = dstNode->Parent();
1036
1037 bool srcFound = ( item_set.find( srcParent ) != item_set.end() );
1038 bool dstFound = ( item_set.find( dstParent ) != item_set.end() );
1039
1040 if ( srcFound && dstFound )
1041 edges.push_back( edge );
1042 }
1043 }
1044
1045 return edges;
1046}
1047
1048
1049const std::vector<CN_EDGE> CONNECTIVITY_DATA::GetRatsnestForPad( const PAD* aPad )
1050{
1051 std::vector<CN_EDGE> edges;
1052 RN_NET* net = GetRatsnestForNet( aPad->GetNetCode() );
1053
1054 if( !net )
1055 return edges;
1056
1057 for( const CN_EDGE& edge : net->GetEdges() )
1058 {
1059 if( !edge.GetSourceNode() || edge.GetSourceNode()->Dirty() )
1060 continue;
1061
1062 if( !edge.GetTargetNode() || edge.GetTargetNode()->Dirty() )
1063 continue;
1064
1065 if( edge.GetSourceNode()->Parent() == aPad || edge.GetTargetNode()->Parent() == aPad )
1066 edges.push_back( edge );
1067 }
1068
1069 return edges;
1070}
1071
1072
1073const std::vector<CN_EDGE> CONNECTIVITY_DATA::GetRatsnestForComponent( FOOTPRINT* aComponent,
1074 bool aSkipInternalConnections )
1075{
1076 std::set<int> nets;
1077 std::set<const PAD*> pads;
1078 std::vector<CN_EDGE> edges;
1079
1080 for( PAD* pad : aComponent->Pads() )
1081 {
1082 nets.insert( pad->GetNetCode() );
1083 pads.insert( pad );
1084 }
1085
1086 for( int netcode : nets )
1087 {
1088 RN_NET* net = GetRatsnestForNet( netcode );
1089
1090 if( !net )
1091 continue;
1092
1093 for( const CN_EDGE& edge : net->GetEdges() )
1094 {
1095 const std::shared_ptr<const CN_ANCHOR>& srcNode = edge.GetSourceNode();
1096 const std::shared_ptr<const CN_ANCHOR>& dstNode = edge.GetTargetNode();
1097
1098 if( !srcNode || srcNode->Dirty() || !dstNode || dstNode->Dirty() )
1099 continue;
1100
1101 const PAD* srcParent = static_cast<const PAD*>( srcNode->Parent() );
1102 const PAD* dstParent = static_cast<const PAD*>( dstNode->Parent() );
1103
1104 bool srcFound = ( pads.find(srcParent) != pads.end() );
1105 bool dstFound = ( pads.find(dstParent) != pads.end() );
1106
1107 if ( srcFound && dstFound && !aSkipInternalConnections )
1108 edges.push_back( edge );
1109 else if ( srcFound || dstFound )
1110 edges.push_back( edge );
1111 }
1112 }
1113
1114 return edges;
1115}
1116
1117
1119{
1120 if( std::shared_ptr<NET_SETTINGS> netSettings = m_netSettings.lock() )
1121 return netSettings.get();
1122 else
1123 return nullptr;
1124}
@ ERROR_INSIDE
constexpr BOX2I KiROUND(const BOX2D &aBoxD)
Definition box2.h:986
A base class derived from BOARD_ITEM for items that can be connected and have a net,...
PCB_LAYER_ID GetLayer() const override
Return the primary layer this item is on.
std::shared_ptr< NET_SETTINGS > m_NetSettings
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition board_item.h:81
virtual bool IsConnected() const
Returns information if the object is derived from BOARD_CONNECTED_ITEM.
Definition board_item.h:155
virtual std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
virtual const BOARD * GetBoard() const
Return the BOARD in which this BOARD_ITEM resides, or NULL if none.
FOOTPRINT * GetParentFootprint() const
Information pertinent to a Pcbnew printed circuit board.
Definition board.h:372
const NETINFO_LIST & GetNetInfo() const
Definition board.h:1086
std::unordered_map< ZONE *, std::unique_ptr< DRC_RTREE > > m_CopperZoneRTreeCache
Definition board.h:1675
BOARD_DESIGN_SETTINGS & GetDesignSettings() const
Definition board.cpp:1149
void CacheTriangulation(PROGRESS_REPORTER *aReporter=nullptr, const std::vector< ZONE * > &aZones={})
Definition board.cpp:1207
CN_ANCHOR represents a physical location that can be connected: a pad or a track/arc/via endpoint.
const std::list< CN_ITEM * > & GetItems() const
ITEM_MAP_ENTRY & ItemEntry(const BOARD_CONNECTED_ITEM *aItem)
CN_EDGE represents a point-to-point connection, whether realized or unrealized (ie: tracks etc.
CN_ITEM represents a BOARD_CONNETED_ITEM in the connectivity system (ie: a pad, track/arc/via,...
const std::vector< CN_ITEM * > & ConnectedItems() const
int Net() const
bool Valid() const
BOARD_CONNECTED_ITEM * Parent() const
int SubpolyIndex() const
void FillIsolatedIslandsMap(std::map< ZONE *, std::map< PCB_LAYER_ID, ISOLATED_ISLANDS > > &aMap, bool aConnectivityAlreadyRebuilt=false)
Fill the isolate islands list for each layer of each zone.
void RecalculateRatsnest(BOARD_COMMIT *aCommit=nullptr)
Function RecalculateRatsnest() Updates the ratsnest for the board.
void ClearLocalRatsnest()
Function ClearLocalRatsnest() Erases the temporary, selection-based ratsnest (i.e.
PROGRESS_REPORTER * m_progressReporter
unsigned int GetPadCount(int aNet=-1) const
void MarkItemNetAsDirty(BOARD_ITEM *aItem)
std::weak_ptr< NET_SETTINGS > m_netSettings
Used to get netclass data when drawing ratsnests.
const std::vector< BOARD_CONNECTED_ITEM * > GetConnectedItems(const BOARD_CONNECTED_ITEM *aItem, int aFlags=0) const
void PropagateNets(BOARD_COMMIT *aCommit=nullptr)
Propagates the net codes from the source pads to the tracks/vias.
void RunOnUnconnectedEdges(std::function< bool(CN_EDGE &)> aFunc)
std::vector< RN_DYNAMIC_LINE > m_dynamicRatsnest
bool m_skipRatsnestUpdate
Used to suppress ratsnest calculations on dynamic ratsnests.
const std::vector< CN_EDGE > GetRatsnestForPad(const PAD *aPad)
RN_NET * GetRatsnestForNet(int aNet)
Function GetRatsnestForNet() Returns the ratsnest, expressed as a set of graph edges for a given net.
const std::vector< BOARD_CONNECTED_ITEM * > GetConnectedItemsAtAnchor(const BOARD_CONNECTED_ITEM *aItem, const VECTOR2I &aAnchor, const std::vector< KICAD_T > &aTypes, const int &aMaxError=0) const
Function GetConnectedItemsAtAnchor() Returns a list of items connected to a source item aItem at posi...
void ClearRatsnest()
Function Clear() Erases the connectivity database.
bool Remove(BOARD_ITEM *aItem)
Function Remove() Removes an item from the connectivity data.
void GetConnectedPadsAndVias(const BOARD_CONNECTED_ITEM *aItem, std::vector< PAD * > *pads, std::vector< PCB_VIA * > *vias)
const NET_SETTINGS * GetNetSettings() const
void ComputeLocalRatsnest(const std::vector< BOARD_ITEM * > &aItems, const CONNECTIVITY_DATA *aDynamicData, VECTOR2I aInternalOffset={ 0, 0 })
Function ComputeLocalRatsnest() Calculates the temporary (usually selection-based) ratsnest for the s...
bool TestTrackEndpointDangling(PCB_TRACK *aTrack, bool aIgnoreTracksInPads, VECTOR2I *aPos=nullptr) const
unsigned int GetNodeCount(int aNet=-1) const
void SetProgressReporter(PROGRESS_REPORTER *aReporter)
void BlockRatsnestItems(const std::vector< BOARD_ITEM * > &aItems)
bool IsConnectedOnLayer(const BOARD_CONNECTED_ITEM *aItem, int aLayer, const std::initializer_list< KICAD_T > &aTypes={}) const
const std::vector< PCB_TRACK * > GetConnectedTracks(const BOARD_CONNECTED_ITEM *aItem) const
const std::vector< CN_EDGE > GetRatsnestForComponent(FOOTPRINT *aComponent, bool aSkipInternalConnections=false)
const std::vector< BOARD_CONNECTED_ITEM * > GetNetItems(int aNetCode, const std::vector< KICAD_T > &aTypes) const
Function GetNetItems() Returns the list of items that belong to a certain net.
bool Add(BOARD_ITEM *aItem)
Function Add() Adds an item to the connectivity data.
std::shared_ptr< CN_CONNECTIVITY_ALGO > m_connAlgo
bool Build(BOARD *aBoard, PROGRESS_REPORTER *aReporter=nullptr)
Function Build() Builds the connectivity database for the board aBoard.
std::shared_ptr< FROM_TO_CACHE > m_fromToCache
const std::vector< PAD * > GetConnectedPads(const BOARD_CONNECTED_ITEM *aItem) const
unsigned int GetUnconnectedCount(bool aVisibileOnly) const
std::map< int, wxString > m_netcodeMap
Used to map netcode to net name.
void internalRecalculateRatsnest(BOARD_COMMIT *aCommit=nullptr)
Updates the ratsnest for the board without locking the connectivity mutex.
void RefreshNetcodeMap(BOARD *aBoard)
Refresh the map of netcodes to net names.
void HideLocalRatsnest()
Hides the temporary, selection-based ratsnest lines.
const std::vector< CN_EDGE > GetRatsnestForItems(const std::vector< BOARD_ITEM * > &aItems)
void addRatsnestCluster(const std::shared_ptr< CN_CLUSTER > &aCluster)
std::vector< RN_NET * > m_nets
bool Update(BOARD_ITEM *aItem)
Function Update() Updates the connectivity data for an item.
void Move(const VECTOR2I &aDelta)
Moves the connectivity list anchors.
int GetNetCount() const
Function GetNetCount() Returns the total number of nets in the connectivity database.
std::shared_ptr< CN_CONNECTIVITY_ALGO > GetConnectivityAlgo() const
Implement an R-tree for fast spatial and layer indexing of connectable items.
Definition drc_rtree.h:45
int QueryColliding(BOARD_ITEM *aRefItem, PCB_LAYER_ID aRefLayer, PCB_LAYER_ID aTargetLayer, std::function< bool(BOARD_ITEM *)> aFilter=nullptr, std::function< bool(BOARD_ITEM *)> aVisitor=nullptr, int aClearance=0) const
This is a fast test which essentially does bounding-box overlap given a worst-case clearance.
Definition drc_rtree.h:225
virtual VECTOR2I GetPosition() const
Definition eda_item.h:282
KICAD_T Type() const
Returns the type of object.
Definition eda_item.h:108
EDA_ITEM_FLAGS GetFlags() const
Definition eda_item.h:155
std::deque< PAD * > & Pads()
Definition footprint.h:375
Handle the data for a net.
Definition netinfo.h:46
NET_SETTINGS stores various net-related settings in a project context.
UNCONNECTED_LAYER_MODE UnconnectedLayerMode() const
Definition padstack.h:366
Definition pad.h:61
const PADSTACK & Padstack() const
Definition pad.h:326
const VECTOR2I & GetStart() const
Definition pcb_track.h:93
VECTOR2I GetPosition() const override
Definition pcb_track.h:83
const VECTOR2I & GetEnd() const
Definition pcb_track.h:90
virtual int GetWidth() const
Definition pcb_track.h:87
A small class to help profiling.
Definition profile.h:46
void Show(std::ostream &aStream=std::cerr)
Print the elapsed time (in a suitable unit) to a stream.
Definition profile.h:103
A progress reporter interface for use in multi-threaded environments.
virtual bool KeepRefreshing(bool aWait=false)=0
Update the UI (if any).
virtual void Report(const wxString &aMessage)=0
Display aMessage in the progress bar dialog.
virtual void SetCurrentProgress(double aProgress)=0
Set the progress value to aProgress (0..1).
Describe ratsnest for a single net.
unsigned int GetNodeCount() const
const std::vector< CN_EDGE > & GetEdges() const
bool NearestBicoloredPair(RN_NET *aOtherNet, VECTOR2I &aPos1, VECTOR2I &aPos2) const
void AddCluster(std::shared_ptr< CN_CLUSTER > aCluster)
VECTOR2I::extended_type ecoord
Definition seg.h:40
const BOX2I BBox(int aClearance=0) const override
Compute a bounding box of the shape, with a margin of aClearance a collision.
Represent a polyline containing arcs as well as line segments: A chain of connected line and/or arc s...
bool PointInside(const VECTOR2I &aPt, int aAccuracy=0, bool aUseBBoxCache=false) const override
Check if point aP lies inside a closed shape.
const std::vector< VECTOR2I > & CPoints() const
Represent a set of closed polygons.
const SHAPE_LINE_CHAIN & COutline(int aIndex) const
double Distance(const VECTOR2< extended_type > &aVector) const
Compute the distance between two vectors.
Definition vector2d.h:549
Handle a list of polygons defining a copper zone.
Definition zone.h:70
bool IsFilled() const
Definition zone.h:306
SHAPE_POLY_SET * GetFill(PCB_LAYER_ID aLayer)
Definition zone.h:704
static int getMinDist(BOARD_CONNECTED_ITEM *aItem, const VECTOR2I &aPoint)
#define EXCLUDE_ZONES
#define IGNORE_NETS
Function GetConnectedItems() Returns a list of items connected to a source item aItem.
#define _(s)
#define IS_DELETED
PCB_LAYER_ID
A quick note on layer IDs:
Definition layer_ids.h:56
@ B_Cu
Definition layer_ids.h:61
@ UNDEFINED_LAYER
Definition layer_ids.h:57
PCB_LAYER_ID ToLAYER_ID(int aLayer)
Definition lset.cpp:750
bool contains(const _Container &__container, _Value __value)
Returns true if the container contains the given value.
Definition kicad_algo.h:96
UNCONNECTED_LAYER_MODE
Definition padstack.h:128
Class that computes missing connections on a PCB.
VECTOR2I end
const int accuracy
thread_pool & GetKiCadThreadPool()
Get a reference to the current thread pool.
static thread_pool * tp
BS::priority_thread_pool thread_pool
Definition thread_pool.h:27
KICAD_T
The set of class identification values stored in EDA_ITEM::m_structType.
Definition typeinfo.h:71
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
Definition typeinfo.h:90
@ MAX_STRUCT_TYPE_ID
Definition typeinfo.h:240
@ PCB_FOOTPRINT_T
class FOOTPRINT, a footprint
Definition typeinfo.h:79
@ PCB_PAD_T
class PAD, a pad in a footprint
Definition typeinfo.h:80
@ PCB_ARC_T
class PCB_ARC, an arc track segment on a copper layer
Definition typeinfo.h:91
@ PCB_TRACE_T
class PCB_TRACK, a track segment (segment on a copper layer)
Definition typeinfo.h:89
VECTOR2< int32_t > VECTOR2I
Definition vector2d.h:683