KiCad PCB EDA Suite
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connectivity_data.cpp
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1/*
2 * This program source code file is part of KICAD, a free EDA CAD application.
3 *
4 * Copyright (C) 2017 CERN
5 * Copyright (C) 2018-2023 KiCad Developers, see AUTHORS.txt for contributors.
6 * @author Tomasz Wlostowski <[email protected]>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, you may find one here:
20 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
21 * or you may search the http://www.gnu.org website for the version 2 license,
22 * or you may write to the Free Software Foundation, Inc.,
23 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
24 */
25
26#ifdef PROFILE
27#include <core/profile.h>
28#endif
29
30#include <algorithm>
31#include <future>
32#include <initializer_list>
33
42#include <progress_reporter.h>
43#include <core/thread_pool.h>
44#include <trigo.h>
45#include <drc/drc_rtree.h>
46
48 m_skipRatsnestUpdate( false )
49{
50 m_connAlgo.reset( new CN_CONNECTIVITY_ALGO( this ) );
51 m_progressReporter = nullptr;
52 m_fromToCache.reset( new FROM_TO_CACHE );
53}
54
55
56CONNECTIVITY_DATA::CONNECTIVITY_DATA( std::shared_ptr<CONNECTIVITY_DATA> aGlobalConnectivity,
57 const std::vector<BOARD_ITEM*>& aLocalItems,
58 bool aSkipRatsnestUpdate ) :
59 m_skipRatsnestUpdate( aSkipRatsnestUpdate )
60{
61 Build( aGlobalConnectivity, aLocalItems );
62 m_progressReporter = nullptr;
63 m_fromToCache.reset( new FROM_TO_CACHE );
64}
65
66
68{
69 for( RN_NET* net : m_nets )
70 delete net;
71
72 m_nets.clear();
73}
74
75
77{
78 m_connAlgo->Add( aItem );
79 return true;
80}
81
82
84{
85 m_connAlgo->Remove( aItem );
86 return true;
87}
88
89
91{
92 m_connAlgo->Remove( aItem );
93 m_connAlgo->Add( aItem );
94 return true;
95}
96
97
99{
100 aBoard->CacheTriangulation( aReporter );
101
102 std::unique_lock<KISPINLOCK> lock( m_lock, std::try_to_lock );
103
104 if( !lock )
105 return false;
106
107 if( aReporter )
108 {
109 aReporter->Report( _( "Updating nets..." ) );
110 aReporter->KeepRefreshing( false );
111 }
112
113 std::shared_ptr<NET_SETTINGS>& netSettings = aBoard->GetDesignSettings().m_NetSettings;
114
115 m_connAlgo.reset( new CN_CONNECTIVITY_ALGO( this ) );
116 m_connAlgo->Build( aBoard, aReporter );
117
118 m_netclassMap.clear();
119
120 for( NETINFO_ITEM* net : aBoard->GetNetInfo() )
121 {
122 net->SetNetClass( netSettings->GetEffectiveNetClass( net->GetNetname() ) );
123
124 if( net->GetNetClass()->GetName() != NETCLASS::Default )
125 m_netclassMap[ net->GetNetCode() ] = net->GetNetClass()->GetName();
126 }
127
128 if( aReporter )
129 {
130 aReporter->SetCurrentProgress( 0.75 );
131 aReporter->KeepRefreshing( false );
132 }
133
135
136 if( aReporter )
137 {
138 aReporter->SetCurrentProgress( 1.0 );
139 aReporter->KeepRefreshing( false );
140 }
141
142 return true;
143}
144
145
146void CONNECTIVITY_DATA::Build( std::shared_ptr<CONNECTIVITY_DATA>& aGlobalConnectivity,
147 const std::vector<BOARD_ITEM*>& aLocalItems )
148{
149 std::unique_lock<KISPINLOCK> lock( m_lock, std::try_to_lock );
150
151 if( !lock )
152 return;
153
154 m_connAlgo.reset( new CN_CONNECTIVITY_ALGO( this ) );
155 m_connAlgo->LocalBuild( aGlobalConnectivity, aLocalItems );
156
158}
159
160
162{
163 m_connAlgo->ForEachAnchor( [&aDelta]( CN_ANCHOR& anchor )
164 {
165 anchor.Move( aDelta );
166 } );
167}
168
169
171{
172#ifdef PROFILE
173 PROF_TIMER rnUpdate( "update-ratsnest" );
174#endif
175
176 std::vector<RN_NET*> dirty_nets;
177
178 // Start with net 1 as net 0 is reserved for not-connected
179 // Nets without nodes are also ignored
180 std::copy_if( m_nets.begin() + 1, m_nets.end(), std::back_inserter( dirty_nets ),
181 [] ( RN_NET* aNet )
182 {
183 return aNet->IsDirty() && aNet->GetNodeCount() > 0;
184 } );
185
187
188 tp.push_loop( dirty_nets.size(),
189 [&]( const int a, const int b )
190 {
191 for( int ii = a; ii < b; ++ii )
192 dirty_nets[ii]->UpdateNet();
193 } );
194 tp.wait_for_tasks();
195
196 tp.push_loop( dirty_nets.size(),
197 [&]( const int a, const int b )
198 {
199 for( int ii = a; ii < b; ++ii )
200 dirty_nets[ii]->OptimizeRNEdges();
201 } );
202 tp.wait_for_tasks();
203
204#ifdef PROFILE
205 rnUpdate.Show();
206#endif
207}
208
209
210void CONNECTIVITY_DATA::addRatsnestCluster( const std::shared_ptr<CN_CLUSTER>& aCluster )
211{
212 RN_NET* rnNet = m_nets[ aCluster->OriginNet() ];
213
214 rnNet->AddCluster( aCluster );
215}
216
217
219{
220
221 // We can take over the lock here if called in the same thread
222 // This is to prevent redraw during a RecalculateRatsnets process
223 std::unique_lock<KISPINLOCK> lock( m_lock );
224
226
227}
228
230{
231 m_connAlgo->PropagateNets( aCommit );
232
233 int lastNet = m_connAlgo->NetCount();
234
235 if( lastNet >= (int) m_nets.size() )
236 {
237 unsigned int prevSize = m_nets.size();
238 m_nets.resize( lastNet + 1 );
239
240 for( unsigned int i = prevSize; i < m_nets.size(); i++ )
241 m_nets[i] = new RN_NET;
242 }
243 else
244 {
245 for( size_t ii = lastNet; ii < m_nets.size(); ++ii )
246 m_nets[ii]->Clear();
247 }
248
249 const std::vector<std::shared_ptr<CN_CLUSTER>>& clusters = m_connAlgo->GetClusters();
250
251 for( int net = 0; net < lastNet; net++ )
252 {
253 if( m_connAlgo->IsNetDirty( net ) )
254 {
255 m_nets[net]->Clear();
256 }
257 }
258
259 for( const std::shared_ptr<CN_CLUSTER>& c : clusters )
260 {
261 int net = c->OriginNet();
262
263 // Don't add intentionally-kept zone islands to the ratsnest
264 if( c->IsOrphaned() && c->Size() == 1 )
265 {
266 if( dynamic_cast<CN_ZONE_LAYER*>( *c->begin() ) )
267 continue;
268 }
269
270 if( m_connAlgo->IsNetDirty( net ) )
272 }
273
274 m_connAlgo->ClearDirtyFlags();
275
278}
279
280
281void CONNECTIVITY_DATA::BlockRatsnestItems( const std::vector<BOARD_ITEM*>& aItems )
282{
283 std::vector<BOARD_CONNECTED_ITEM*> citems;
284
285 for( BOARD_ITEM* item : aItems )
286 {
287 if( item->Type() == PCB_FOOTPRINT_T )
288 {
289 for( PAD* pad : static_cast<FOOTPRINT*>(item)->Pads() )
290 citems.push_back( pad );
291 }
292 else
293 {
294 if( BOARD_CONNECTED_ITEM* citem = dynamic_cast<BOARD_CONNECTED_ITEM*>( item ) )
295 citems.push_back( citem );
296 }
297 }
298
299 for( const BOARD_CONNECTED_ITEM* item : citems )
300 {
301 if ( m_connAlgo->ItemExists( item ) )
302 {
303 CN_CONNECTIVITY_ALGO::ITEM_MAP_ENTRY& entry = m_connAlgo->ItemEntry( item );
304
305 for( CN_ITEM* cnItem : entry.GetItems() )
306 {
307 for( const std::shared_ptr<CN_ANCHOR>& anchor : cnItem->Anchors() )
308 anchor->SetNoLine( true );
309 }
310 }
311 }
312}
313
314
316{
317 return m_connAlgo->NetCount();
318}
319
320
321void CONNECTIVITY_DATA::FillIsolatedIslandsMap( std::map<ZONE*, std::map<PCB_LAYER_ID, ISOLATED_ISLANDS>>& aMap,
322 bool aConnectivityAlreadyRebuilt )
323{
324 m_connAlgo->FillIsolatedIslandsMap( aMap, aConnectivityAlreadyRebuilt );
325}
326
327
328void CONNECTIVITY_DATA::ComputeLocalRatsnest( const std::vector<BOARD_ITEM*>& aItems,
329 const CONNECTIVITY_DATA* aDynamicData,
330 VECTOR2I aInternalOffset )
331{
332 if( !aDynamicData )
333 return;
334
335 m_dynamicRatsnest.clear();
336 std::mutex dynamic_ratsnest_mutex;
337
338 // This gets connections between the stationary board and the
339 // moving selection
340
341 auto update_lambda = [&]( int nc )
342 {
343 RN_NET* dynamicNet = aDynamicData->m_nets[nc];
344 RN_NET* staticNet = m_nets[nc];
345
349 if( dynamicNet->GetNodeCount() != 0
350 && dynamicNet->GetNodeCount() != staticNet->GetNodeCount() )
351 {
352 VECTOR2I pos1, pos2;
353
354 if( staticNet->NearestBicoloredPair( dynamicNet, pos1, pos2 ) )
355 {
357 l.a = pos1;
358 l.b = pos2;
359 l.netCode = nc;
360
361 std::lock_guard<std::mutex> lock( dynamic_ratsnest_mutex );
362 m_dynamicRatsnest.push_back( l );
363 }
364 }
365 };
366
368 size_t num_nets = std::min( m_nets.size(), aDynamicData->m_nets.size() );
369
370 tp.push_loop( 1, num_nets,
371 [&]( const int a, const int b)
372 {
373 for( int ii = a; ii < b; ++ii )
374 update_lambda( ii );
375 });
376 tp.wait_for_tasks();
377
378 // This gets the ratsnest for internal connections in the moving set
379 const std::vector<CN_EDGE>& edges = GetRatsnestForItems( aItems );
380
381 for( const CN_EDGE& edge : edges )
382 {
383 const std::shared_ptr<const CN_ANCHOR>& nodeA = edge.GetSourceNode();
384 const std::shared_ptr<const CN_ANCHOR>& nodeB = edge.GetTargetNode();
385
386 if( !nodeA || nodeA->Dirty() || !nodeB || nodeB->Dirty() )
387 continue;
388
390
391 // Use the parents' positions
392 l.a = nodeA->Parent()->GetPosition() + aInternalOffset;
393 l.b = nodeB->Parent()->GetPosition() + aInternalOffset;
394 l.netCode = 0;
395 m_dynamicRatsnest.push_back( l );
396 }
397}
398
399
401{
402 m_connAlgo->ForEachAnchor( []( CN_ANCHOR& anchor )
403 {
404 anchor.SetNoLine( false );
405 } );
407}
408
409
411{
412 m_dynamicRatsnest.clear();
413}
414
415
417{
418 m_connAlgo->PropagateNets( aCommit );
419}
420
421
423 const std::initializer_list<KICAD_T>& aTypes ) const
424{
425 CN_CONNECTIVITY_ALGO::ITEM_MAP_ENTRY &entry = m_connAlgo->ItemEntry( aItem );
426
427 auto matchType =
428 [&]( KICAD_T aItemType )
429 {
430 if( aTypes.size() == 0 )
431 return true;
432
433 return alg::contains( aTypes, aItemType);
434 };
435
436 for( CN_ITEM* citem : entry.GetItems() )
437 {
438 for( CN_ITEM* connected : citem->ConnectedItems() )
439 {
440 CN_ZONE_LAYER* zoneLayer = dynamic_cast<CN_ZONE_LAYER*>( connected );
441
442 if( connected->Valid()
443 && connected->Layers().Overlaps( aLayer )
444 && matchType( connected->Parent()->Type() )
445 && connected->Net() == aItem->GetNetCode() )
446 {
447 if( aItem->Type() == PCB_PAD_T && zoneLayer )
448 {
449 const PAD* pad = static_cast<const PAD*>( aItem );
450 ZONE* zone = static_cast<ZONE*>( zoneLayer->Parent() );
451 int islandIdx = zoneLayer->SubpolyIndex();
452
453 if( zone->IsFilled() )
454 {
455 const SHAPE_POLY_SET* zoneFill = zone->GetFill( ToLAYER_ID( aLayer ) );
456 const SHAPE_LINE_CHAIN& padHull = pad->GetEffectivePolygon( ERROR_INSIDE )->Outline( 0 );
457
458 for( const VECTOR2I& pt : zoneFill->COutline( islandIdx ).CPoints() )
459 {
460 // If the entire island is inside the pad's flashing then the pad
461 // won't actually connect to anything else, so only return true if
462 // part of the island is *outside* the pad's flashing.
463
464 if( !padHull.PointInside( pt ) )
465 return true;
466 }
467 }
468
469 continue;
470 }
471 else if( aItem->Type() == PCB_VIA_T && zoneLayer )
472 {
473 const PCB_VIA* via = static_cast<const PCB_VIA*>( aItem );
474 ZONE* zone = static_cast<ZONE*>( zoneLayer->Parent() );
475 int islandIdx = zoneLayer->SubpolyIndex();
476
477 if( zone->IsFilled() )
478 {
479 const SHAPE_POLY_SET* zoneFill = zone->GetFill( ToLAYER_ID( aLayer ) );
480 SHAPE_CIRCLE viaHull( via->GetCenter(), via->GetWidth() / 2 );
481
482 for( const VECTOR2I& pt : zoneFill->COutline( islandIdx ).CPoints() )
483 {
484 // If the entire island is inside the via's flashing then the via
485 // won't actually connect to anything else, so only return true if
486 // part of the island is *outside* the via's flashing.
487
488 if( !viaHull.SHAPE::Collide( pt ) )
489 return true;
490 }
491 }
492
493 continue;
494 }
495
496 return true;
497 }
498 }
499 }
500
501 return false;
502}
503
504
505unsigned int CONNECTIVITY_DATA::GetUnconnectedCount( bool aVisibleOnly ) const
506{
507 unsigned int unconnected = 0;
508
509 for( RN_NET* net : m_nets )
510 {
511 if( !net )
512 continue;
513
514 for( const CN_EDGE& edge : net->GetEdges() )
515 {
516 if( edge.IsVisible() || !aVisibleOnly )
517 ++unconnected;
518 }
519 }
520
521 return unconnected;
522}
523
524
526{
527 for( RN_NET* net : m_nets )
528 net->Clear();
529}
530
531
532const std::vector<BOARD_CONNECTED_ITEM*>
534 const std::vector<KICAD_T>& aTypes,
535 bool aIgnoreNetcodes ) const
536{
537 std::vector<BOARD_CONNECTED_ITEM*> rv;
539
540 if( aIgnoreNetcodes )
542 else
544
545 const auto clusters = m_connAlgo->SearchClusters( searchMode, aTypes,
546 aIgnoreNetcodes ? -1 : aItem->GetNetCode() );
547
548 for( const std::shared_ptr<CN_CLUSTER>& cl : clusters )
549 {
550 if( cl->Contains( aItem ) )
551 {
552 for( const CN_ITEM* item : *cl )
553 {
554 if( item->Valid() )
555 rv.push_back( item->Parent() );
556 }
557 }
558 }
559
560 return rv;
561}
562
563
564const std::vector<BOARD_CONNECTED_ITEM*>
565CONNECTIVITY_DATA::GetNetItems( int aNetCode, const std::vector<KICAD_T>& aTypes ) const
566{
567 std::vector<BOARD_CONNECTED_ITEM*> items;
568 items.reserve( 32 );
569
570 std::bitset<MAX_STRUCT_TYPE_ID> type_bits;
571
572 for( KICAD_T scanType : aTypes )
573 {
574 wxASSERT( scanType < MAX_STRUCT_TYPE_ID );
575 type_bits.set( scanType );
576 }
577
578 m_connAlgo->ForEachItem(
579 [&]( CN_ITEM& aItem )
580 {
581 if( aItem.Valid() && ( aItem.Net() == aNetCode ) && type_bits[aItem.Parent()->Type()] )
582 items.push_back( aItem.Parent() );
583 } );
584
585 std::sort( items.begin(), items.end() );
586 items.erase( std::unique( items.begin(), items.end() ), items.end() );
587 return items;
588}
589
590
591const std::vector<PCB_TRACK*>
593{
594 CN_CONNECTIVITY_ALGO::ITEM_MAP_ENTRY& entry = m_connAlgo->ItemEntry( aItem );
595
596 std::set<PCB_TRACK*> tracks;
597 std::vector<PCB_TRACK*> rv;
598
599 for( CN_ITEM* citem : entry.GetItems() )
600 {
601 for( CN_ITEM* connected : citem->ConnectedItems() )
602 {
603 if( connected->Valid() &&
604 ( connected->Parent()->Type() == PCB_TRACE_T ||
605 connected->Parent()->Type() == PCB_VIA_T ||
606 connected->Parent()->Type() == PCB_ARC_T ) )
607 {
608 tracks.insert( static_cast<PCB_TRACK*> ( connected->Parent() ) );
609 }
610 }
611 }
612
613 std::copy( tracks.begin(), tracks.end(), std::back_inserter( rv ) );
614 return rv;
615}
616
617
619 std::set<PAD*>* pads ) const
620{
621 for( CN_ITEM* citem : m_connAlgo->ItemEntry( aItem ).GetItems() )
622 {
623 for( CN_ITEM* connected : citem->ConnectedItems() )
624 {
625 if( connected->Valid() && connected->Parent()->Type() == PCB_PAD_T )
626 pads->insert( static_cast<PAD*> ( connected->Parent() ) );
627 }
628 }
629}
630
631
632const std::vector<PAD*> CONNECTIVITY_DATA::GetConnectedPads( const BOARD_CONNECTED_ITEM* aItem )
633const
634{
635 std::set<PAD*> pads;
636 std::vector<PAD*> rv;
637
638 GetConnectedPads( aItem, &pads );
639
640 std::copy( pads.begin(), pads.end(), std::back_inserter( rv ) );
641 return rv;
642}
643
644
646 std::vector<PAD*>* pads,
647 std::vector<PCB_VIA*>* vias )
648{
649 for( CN_ITEM* citem : m_connAlgo->ItemEntry( aItem ).GetItems() )
650 {
651 for( CN_ITEM* connected : citem->ConnectedItems() )
652 {
653 if( connected->Valid() )
654 {
655 BOARD_CONNECTED_ITEM* parent = connected->Parent();
656
657 if( parent->Type() == PCB_PAD_T )
658 pads->push_back( static_cast<PAD*>( parent ) );
659 else if( parent->Type() == PCB_VIA_T )
660 vias->push_back( static_cast<PCB_VIA*>( parent ) );
661 }
662 }
663 }
664}
665
666
667unsigned int CONNECTIVITY_DATA::GetNodeCount( int aNet ) const
668{
669 int sum = 0;
670
671 if( aNet < 0 ) // Node count for all nets
672 {
673 for( const RN_NET* net : m_nets )
674 sum += net->GetNodeCount();
675 }
676 else if( aNet < (int) m_nets.size() )
677 {
678 sum = m_nets[aNet]->GetNodeCount();
679 }
680
681 return sum;
682}
683
684
685unsigned int CONNECTIVITY_DATA::GetPadCount( int aNet ) const
686{
687 int n = 0;
688
689 for( CN_ITEM* pad : m_connAlgo->ItemList() )
690 {
691 if( !pad->Valid() || pad->Parent()->Type() != PCB_PAD_T)
692 continue;
693
694 PAD* dpad = static_cast<PAD*>( pad->Parent() );
695
696 if( aNet < 0 || aNet == dpad->GetNetCode() )
697 n++;
698 }
699
700 return n;
701}
702
703
704void CONNECTIVITY_DATA::RunOnUnconnectedEdges( std::function<bool( CN_EDGE& )> aFunc )
705{
706 for( RN_NET* rnNet : m_nets )
707 {
708 if( rnNet )
709 {
710 for( CN_EDGE& edge : rnNet->GetEdges() )
711 {
712 if( !aFunc( edge ) )
713 return;
714 }
715 }
716 }
717}
718
719
720static int getMinDist( BOARD_CONNECTED_ITEM* aItem, const VECTOR2I& aPoint )
721{
722 switch( aItem->Type() )
723 {
724 case PCB_TRACE_T:
725 case PCB_ARC_T:
726 {
727 PCB_TRACK* track = static_cast<PCB_TRACK*>( aItem );
728
729 return std::min( track->GetStart().Distance(aPoint ),
730 track->GetEnd().Distance( aPoint ) );
731 }
732
733 default:
734 return aItem->GetPosition().Distance( aPoint );
735 }
736}
737
738
739bool CONNECTIVITY_DATA::TestTrackEndpointDangling( PCB_TRACK* aTrack, bool aIgnoreTracksInPads,
740 VECTOR2I* aPos ) const
741{
742 const std::list<CN_ITEM*>& items = GetConnectivityAlgo()->ItemEntry( aTrack ).GetItems();
743
744 // Not in the connectivity system. This is a bug!
745 if( items.empty() )
746 {
747 wxFAIL_MSG( wxT( "track not in connectivity system" ) );
748 return false;
749 }
750
751 CN_ITEM* citem = items.front();
752
753 if( !citem->Valid() )
754 return false;
755
756 if( aTrack->Type() == PCB_TRACE_T || aTrack->Type() == PCB_ARC_T )
757 {
758 // Test if a segment is connected on each end.
759 //
760 // NB: be wary of short segments which can be connected to the *same* other item on
761 // each end. If that's their only connection then they're still dangling.
762
763 PCB_LAYER_ID layer = aTrack->GetLayer();
764 int accuracy = KiROUND( aTrack->GetWidth() / 2 );
765 int start_count = 0;
766 int end_count = 0;
767
768 for( CN_ITEM* connected : citem->ConnectedItems() )
769 {
770 BOARD_CONNECTED_ITEM* item = connected->Parent();
771 ZONE* zone = dynamic_cast<ZONE*>( item );
772 DRC_RTREE* rtree = nullptr;
773 bool hitStart = false;
774 bool hitEnd = false;
775
776 if( item->GetFlags() & IS_DELETED )
777 continue;
778
779 if( zone )
780 rtree = zone->GetBoard()->m_CopperZoneRTreeCache[ zone ].get();
781
782 if( rtree )
783 {
784 SHAPE_CIRCLE start( aTrack->GetStart(), accuracy );
785 SHAPE_CIRCLE end( aTrack->GetEnd(), accuracy );
786
787 hitStart = rtree->QueryColliding( start.BBox(), &start, layer );
788 hitEnd = rtree->QueryColliding( end.BBox(), &end, layer );
789 }
790 else
791 {
792 std::shared_ptr<SHAPE> shape = item->GetEffectiveShape( layer );
793
794 hitStart = shape->Collide( aTrack->GetStart(), accuracy );
795 hitEnd = shape->Collide( aTrack->GetEnd(), accuracy );
796 }
797
798 if( hitStart && hitEnd )
799 {
800 if( zone )
801 {
802 // Both start and end in a zone: track may be redundant, but it's not dangling
803 return false;
804 }
805 else if( item->Type() == PCB_PAD_T || item->Type() == PCB_VIA_T )
806 {
807 // Both start and end are under a pad: see what the caller wants us to do
808 if( aIgnoreTracksInPads )
809 return false;
810 }
811
812 if( getMinDist( item, aTrack->GetStart() ) < getMinDist( item, aTrack->GetEnd() ) )
813 start_count++;
814 else
815 end_count++;
816 }
817 else if( hitStart )
818 {
819 start_count++;
820 }
821 else if( hitEnd )
822 {
823 end_count++;
824 }
825
826 if( start_count > 0 && end_count > 0 )
827 return false;
828 }
829
830 if( aPos )
831 *aPos = (start_count == 0 ) ? aTrack->GetStart() : aTrack->GetEnd();
832
833 return true;
834 }
835 else if( aTrack->Type() == PCB_VIA_T )
836 {
837 // Test if a via is only connected on one layer
838
839 const std::vector<CN_ITEM*>& connected = citem->ConnectedItems();
840
841 if( connected.empty() )
842 {
843 if( aPos )
844 *aPos = aTrack->GetPosition();
845
846 return true;
847 }
848
849 // Here, we check if the via is connected only to items on a single layer
850 int first_layer = UNDEFINED_LAYER;
851
852 for( CN_ITEM* item : connected )
853 {
854 if( item->Parent()->GetFlags() & IS_DELETED )
855 continue;
856
857 if( first_layer == UNDEFINED_LAYER )
858 first_layer = item->Layer();
859 else if( item->Layer() != first_layer )
860 return false;
861 }
862
863 if( aPos )
864 *aPos = aTrack->GetPosition();
865
866 return true;
867 }
868 else
869 {
870 wxFAIL_MSG( wxT( "CONNECTIVITY_DATA::TestTrackEndpointDangling: unknown track type" ) );
871 }
872
873 return false;
874}
875
876
877const std::vector<BOARD_CONNECTED_ITEM*>
879 const VECTOR2I& aAnchor,
880 const std::vector<KICAD_T>& aTypes,
881 const int& aMaxError ) const
882{
883 CN_CONNECTIVITY_ALGO::ITEM_MAP_ENTRY& entry = m_connAlgo->ItemEntry( aItem );
884 std::vector<BOARD_CONNECTED_ITEM*> rv;
885 SEG::ecoord maxError_sq = (SEG::ecoord) aMaxError * aMaxError;
886
887 for( CN_ITEM* cnItem : entry.GetItems() )
888 {
889 for( CN_ITEM* connected : cnItem->ConnectedItems() )
890 {
891 for( const std::shared_ptr<CN_ANCHOR>& anchor : connected->Anchors() )
892 {
893 if( ( anchor->Pos() - aAnchor ).SquaredEuclideanNorm() <= maxError_sq )
894 {
895 for( KICAD_T type : aTypes )
896 {
897 if( connected->Valid() && connected->Parent()->Type() == type )
898 {
899 rv.push_back( connected->Parent() );
900 break;
901 }
902 }
903
904 break;
905 }
906 }
907 }
908 }
909
910 return rv;
911}
912
913
915{
916 if ( aNet < 0 || aNet >= (int) m_nets.size() )
917 return nullptr;
918
919 return m_nets[ aNet ];
920}
921
922
924{
925 if ( aItem->Type() == PCB_FOOTPRINT_T)
926 {
927 for( PAD* pad : static_cast<FOOTPRINT*>( aItem )->Pads() )
928 m_connAlgo->MarkNetAsDirty( pad->GetNetCode() );
929 }
930
931 if (aItem->IsConnected() )
932 m_connAlgo->MarkNetAsDirty( static_cast<BOARD_CONNECTED_ITEM*>( aItem )->GetNetCode() );
933}
934
935
937{
938 m_connAlgo->RemoveInvalidRefs();
939
940 for( RN_NET* rnNet : m_nets )
941 rnNet->RemoveInvalidRefs();
942}
943
944
946{
947 m_progressReporter = aReporter;
948 m_connAlgo->SetProgressReporter( m_progressReporter );
949}
950
951
952const std::vector<CN_EDGE>
953CONNECTIVITY_DATA::GetRatsnestForItems( const std::vector<BOARD_ITEM*>& aItems )
954{
955 std::set<int> nets;
956 std::vector<CN_EDGE> edges;
957 std::set<BOARD_CONNECTED_ITEM*> item_set;
958
959 for( BOARD_ITEM* item : aItems )
960 {
961 if( item->Type() == PCB_FOOTPRINT_T )
962 {
963 FOOTPRINT* footprint = static_cast<FOOTPRINT*>( item );
964
965 for( PAD* pad : footprint->Pads() )
966 {
967 nets.insert( pad->GetNetCode() );
968 item_set.insert( pad );
969 }
970 }
971 else if( item->IsConnected() )
972 {
973 BOARD_CONNECTED_ITEM* conn_item = static_cast<BOARD_CONNECTED_ITEM*>( item );
974
975 item_set.insert( conn_item );
976 nets.insert( conn_item->GetNetCode() );
977 }
978 }
979
980 for( int netcode : nets )
981 {
982 RN_NET* net = GetRatsnestForNet( netcode );
983
984 if( !net )
985 continue;
986
987 for( const CN_EDGE& edge : net->GetEdges() )
988 {
989 std::shared_ptr<const CN_ANCHOR> srcNode = edge.GetSourceNode();
990 std::shared_ptr<const CN_ANCHOR> dstNode = edge.GetTargetNode();
991
992 if( !srcNode || srcNode->Dirty() || !dstNode || dstNode->Dirty() )
993 continue;
994
995 BOARD_CONNECTED_ITEM* srcParent = srcNode->Parent();
996 BOARD_CONNECTED_ITEM* dstParent = dstNode->Parent();
997
998 bool srcFound = ( item_set.find( srcParent ) != item_set.end() );
999 bool dstFound = ( item_set.find( dstParent ) != item_set.end() );
1000
1001 if ( srcFound && dstFound )
1002 edges.push_back( edge );
1003 }
1004 }
1005
1006 return edges;
1007}
1008
1009
1010const std::vector<CN_EDGE> CONNECTIVITY_DATA::GetRatsnestForPad( const PAD* aPad )
1011{
1012 std::vector<CN_EDGE> edges;
1013 RN_NET* net = GetRatsnestForNet( aPad->GetNetCode() );
1014
1015 if( !net )
1016 return edges;
1017
1018 for( const CN_EDGE& edge : net->GetEdges() )
1019 {
1020 if( !edge.GetSourceNode() || edge.GetSourceNode()->Dirty() )
1021 continue;
1022
1023 if( !edge.GetTargetNode() || edge.GetTargetNode()->Dirty() )
1024 continue;
1025
1026 if( edge.GetSourceNode()->Parent() == aPad || edge.GetTargetNode()->Parent() == aPad )
1027 edges.push_back( edge );
1028 }
1029
1030 return edges;
1031}
1032
1033
1034const std::vector<CN_EDGE> CONNECTIVITY_DATA::GetRatsnestForComponent( FOOTPRINT* aComponent,
1035 bool aSkipInternalConnections )
1036{
1037 std::set<int> nets;
1038 std::set<const PAD*> pads;
1039 std::vector<CN_EDGE> edges;
1040
1041 for( PAD* pad : aComponent->Pads() )
1042 {
1043 nets.insert( pad->GetNetCode() );
1044 pads.insert( pad );
1045 }
1046
1047 for( int netcode : nets )
1048 {
1049 RN_NET* net = GetRatsnestForNet( netcode );
1050
1051 if( !net )
1052 continue;
1053
1054 for( const CN_EDGE& edge : net->GetEdges() )
1055 {
1056 const std::shared_ptr<const CN_ANCHOR>& srcNode = edge.GetSourceNode();
1057 const std::shared_ptr<const CN_ANCHOR>& dstNode = edge.GetTargetNode();
1058
1059 if( !srcNode || srcNode->Dirty() || !dstNode || dstNode->Dirty() )
1060 continue;
1061
1062 const PAD* srcParent = static_cast<const PAD*>( srcNode->Parent() );
1063 const PAD* dstParent = static_cast<const PAD*>( dstNode->Parent() );
1064
1065 bool srcFound = ( pads.find(srcParent) != pads.end() );
1066 bool dstFound = ( pads.find(dstParent) != pads.end() );
1067
1068 if ( srcFound && dstFound && !aSkipInternalConnections )
1069 edges.push_back( edge );
1070 else if ( srcFound || dstFound )
1071 edges.push_back( edge );
1072 }
1073 }
1074
1075 return edges;
1076}
1077
1078
A base class derived from BOARD_ITEM for items that can be connected and have a net,...
std::shared_ptr< NET_SETTINGS > m_NetSettings
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition: board_item.h:79
virtual PCB_LAYER_ID GetLayer() const
Return the primary layer this item is on.
Definition: board_item.h:240
virtual bool IsConnected() const
Returns information if the object is derived from BOARD_CONNECTED_ITEM.
Definition: board_item.h:136
virtual std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
Definition: board_item.cpp:246
virtual const BOARD * GetBoard() const
Return the BOARD in which this BOARD_ITEM resides, or NULL if none.
Definition: board_item.cpp:47
Information pertinent to a Pcbnew printed circuit board.
Definition: board.h:289
const NETINFO_LIST & GetNetInfo() const
Definition: board.h:864
std::unordered_map< ZONE *, std::unique_ptr< DRC_RTREE > > m_CopperZoneRTreeCache
Definition: board.h:1286
BOARD_DESIGN_SETTINGS & GetDesignSettings() const
Definition: board.cpp:875
void CacheTriangulation(PROGRESS_REPORTER *aReporter=nullptr, const std::vector< ZONE * > &aZones={})
Definition: board.cpp:913
CN_ANCHOR represents a physical location that can be connected: a pad or a track/arc/via endpoint.
const std::list< CN_ITEM * > & GetItems() const
CN_EDGE represents a point-to-point connection, whether realized or unrealized (ie: tracks etc.
CN_ITEM represents a BOARD_CONNETED_ITEM in the connectivity system (ie: a pad, track/arc/via,...
const std::vector< CN_ITEM * > & ConnectedItems() const
int Net() const
bool Valid() const
BOARD_CONNECTED_ITEM * Parent() const
int SubpolyIndex() const
void FillIsolatedIslandsMap(std::map< ZONE *, std::map< PCB_LAYER_ID, ISOLATED_ISLANDS > > &aMap, bool aConnectivityAlreadyRebuilt=false)
Fill the isolate islands list for each layer of each zone.
void RecalculateRatsnest(BOARD_COMMIT *aCommit=nullptr)
Function RecalculateRatsnest() Updates the ratsnest for the board.
void ClearLocalRatsnest()
Function ClearLocalRatsnest() Erases the temporary, selection-based ratsnest (i.e.
PROGRESS_REPORTER * m_progressReporter
unsigned int GetPadCount(int aNet=-1) const
void MarkItemNetAsDirty(BOARD_ITEM *aItem)
void PropagateNets(BOARD_COMMIT *aCommit=nullptr)
Propagates the net codes from the source pads to the tracks/vias.
void RunOnUnconnectedEdges(std::function< bool(CN_EDGE &)> aFunc)
std::vector< RN_DYNAMIC_LINE > m_dynamicRatsnest
bool m_skipRatsnestUpdate
Used to suppress ratsnest calculations on dynamic ratsnests.
const std::vector< CN_EDGE > GetRatsnestForPad(const PAD *aPad)
RN_NET * GetRatsnestForNet(int aNet)
Function GetRatsnestForNet() Returns the ratsnest, expressed as a set of graph edges for a given net.
const std::vector< BOARD_CONNECTED_ITEM * > GetConnectedItemsAtAnchor(const BOARD_CONNECTED_ITEM *aItem, const VECTOR2I &aAnchor, const std::vector< KICAD_T > &aTypes, const int &aMaxError=0) const
Function GetConnectedItemsAtAnchor() Returns a list of items connected to a source item aItem at posi...
void ClearRatsnest()
Function Clear() Erases the connectivity database.
bool Remove(BOARD_ITEM *aItem)
Function Remove() Removes an item from the connectivity data.
void GetConnectedPadsAndVias(const BOARD_CONNECTED_ITEM *aItem, std::vector< PAD * > *pads, std::vector< PCB_VIA * > *vias)
void ComputeLocalRatsnest(const std::vector< BOARD_ITEM * > &aItems, const CONNECTIVITY_DATA *aDynamicData, VECTOR2I aInternalOffset={ 0, 0 })
Function ComputeLocalRatsnest() Calculates the temporary (usually selection-based) ratsnest for the s...
bool TestTrackEndpointDangling(PCB_TRACK *aTrack, bool aIgnoreTracksInPads, VECTOR2I *aPos=nullptr) const
unsigned int GetNodeCount(int aNet=-1) const
void SetProgressReporter(PROGRESS_REPORTER *aReporter)
void BlockRatsnestItems(const std::vector< BOARD_ITEM * > &aItems)
bool IsConnectedOnLayer(const BOARD_CONNECTED_ITEM *aItem, int aLayer, const std::initializer_list< KICAD_T > &aTypes={}) const
const std::vector< PCB_TRACK * > GetConnectedTracks(const BOARD_CONNECTED_ITEM *aItem) const
std::map< int, wxString > m_netclassMap
Map of netcode -> netclass the net is a member of; used for ratsnest painting.
const std::vector< CN_EDGE > GetRatsnestForComponent(FOOTPRINT *aComponent, bool aSkipInternalConnections=false)
const std::vector< BOARD_CONNECTED_ITEM * > GetNetItems(int aNetCode, const std::vector< KICAD_T > &aTypes) const
Function GetNetItems() Returns the list of items that belong to a certain net.
bool Add(BOARD_ITEM *aItem)
Function Add() Adds an item to the connectivity data.
std::shared_ptr< CN_CONNECTIVITY_ALGO > m_connAlgo
bool Build(BOARD *aBoard, PROGRESS_REPORTER *aReporter=nullptr)
Function Build() Builds the connectivity database for the board aBoard.
const std::vector< BOARD_CONNECTED_ITEM * > GetConnectedItems(const BOARD_CONNECTED_ITEM *aItem, const std::vector< KICAD_T > &aTypes, bool aIgnoreNetcodes=false) const
Function GetConnectedItems() Returns a list of items connected to a source item aItem.
std::shared_ptr< FROM_TO_CACHE > m_fromToCache
const std::vector< PAD * > GetConnectedPads(const BOARD_CONNECTED_ITEM *aItem) const
unsigned int GetUnconnectedCount(bool aVisibileOnly) const
void internalRecalculateRatsnest(BOARD_COMMIT *aCommit=nullptr)
Updates the ratsnest for the board without locking the connectivity mutex.
void HideLocalRatsnest()
Hides the temporary, selection-based ratsnest lines.
const std::vector< CN_EDGE > GetRatsnestForItems(const std::vector< BOARD_ITEM * > &aItems)
void addRatsnestCluster(const std::shared_ptr< CN_CLUSTER > &aCluster)
std::vector< RN_NET * > m_nets
bool Update(BOARD_ITEM *aItem)
Function Update() Updates the connectivity data for an item.
void Move(const VECTOR2I &aDelta)
Moves the connectivity list anchors.
int GetNetCount() const
Function GetNetCount() Returns the total number of nets in the connectivity database.
std::shared_ptr< CN_CONNECTIVITY_ALGO > GetConnectivityAlgo() const
Implement an R-tree for fast spatial and layer indexing of connectable items.
Definition: drc_rtree.h:48
int QueryColliding(BOARD_ITEM *aRefItem, PCB_LAYER_ID aRefLayer, PCB_LAYER_ID aTargetLayer, std::function< bool(BOARD_ITEM *)> aFilter=nullptr, std::function< bool(BOARD_ITEM *)> aVisitor=nullptr, int aClearance=0) const
This is a fast test which essentially does bounding-box overlap given a worst-case clearance.
Definition: drc_rtree.h:213
virtual VECTOR2I GetPosition() const
Definition: eda_item.h:243
KICAD_T Type() const
Returns the type of object.
Definition: eda_item.h:101
EDA_ITEM_FLAGS GetFlags() const
Definition: eda_item.h:130
std::deque< PAD * > & Pads()
Definition: footprint.h:205
static const char Default[]
the name of the default NETCLASS
Definition: netclass.h:46
Handle the data for a net.
Definition: netinfo.h:56
Definition: pad.h:54
const VECTOR2I & GetStart() const
Definition: pcb_track.h:122
VECTOR2I GetPosition() const override
Definition: pcb_track.h:112
const VECTOR2I & GetEnd() const
Definition: pcb_track.h:119
virtual int GetWidth() const
Definition: pcb_track.h:116
A small class to help profiling.
Definition: profile.h:49
void Show(std::ostream &aStream=std::cerr)
Print the elapsed time (in a suitable unit) to a stream.
Definition: profile.h:105
A progress reporter interface for use in multi-threaded environments.
virtual bool KeepRefreshing(bool aWait=false)=0
Update the UI (if any).
virtual void Report(const wxString &aMessage)=0
Display aMessage in the progress bar dialog.
virtual void SetCurrentProgress(double aProgress)=0
Set the progress value to aProgress (0..1).
Describe ratsnest for a single net.
Definition: ratsnest_data.h:63
unsigned int GetNodeCount() const
Definition: ratsnest_data.h:94
const std::vector< CN_EDGE > & GetEdges() const
Definition: ratsnest_data.h:96
bool NearestBicoloredPair(RN_NET *aOtherNet, VECTOR2I &aPos1, VECTOR2I &aPos2) const
void AddCluster(std::shared_ptr< CN_CLUSTER > aCluster)
VECTOR2I::extended_type ecoord
Definition: seg.h:44
const BOX2I BBox(int aClearance=0) const override
Compute a bounding box of the shape, with a margin of aClearance a collision.
Definition: shape_circle.h:70
bool PointInside(const VECTOR2I &aPt, int aAccuracy=0, bool aUseBBoxCache=false) const override
Check if point aP lies inside a closed shape.
Represent a polyline containing arcs as well as line segments: A chain of connected line and/or arc s...
const std::vector< VECTOR2I > & CPoints() const
Represent a set of closed polygons.
const SHAPE_LINE_CHAIN & COutline(int aIndex) const
double Distance(const VECTOR2< extended_type > &aVector) const
Compute the distance between two vectors.
Definition: vector2d.h:550
Handle a list of polygons defining a copper zone.
Definition: zone.h:73
bool IsFilled() const
Definition: zone.h:261
SHAPE_POLY_SET * GetFill(PCB_LAYER_ID aLayer)
Definition: zone.h:622
static int getMinDist(BOARD_CONNECTED_ITEM *aItem, const VECTOR2I &aPoint)
#define _(s)
#define IS_DELETED
@ ERROR_INSIDE
PCB_LAYER_ID
A quick note on layer IDs:
Definition: layer_ids.h:60
@ UNDEFINED_LAYER
Definition: layer_ids.h:61
PCB_LAYER_ID ToLAYER_ID(int aLayer)
Definition: lset.cpp:876
bool contains(const _Container &__container, _Value __value)
Returns true if the container contains the given value.
Definition: kicad_algo.h:100
Class that computes missing connections on a PCB.
static thread_pool * tp
Definition: thread_pool.cpp:30
BS::thread_pool thread_pool
Definition: thread_pool.h:30
thread_pool & GetKiCadThreadPool()
Get a reference to the current thread pool.
Definition: thread_pool.cpp:32
KICAD_T
The set of class identification values stored in EDA_ITEM::m_structType.
Definition: typeinfo.h:78
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
Definition: typeinfo.h:97
@ MAX_STRUCT_TYPE_ID
Definition: typeinfo.h:236
@ PCB_FOOTPRINT_T
class FOOTPRINT, a footprint
Definition: typeinfo.h:86
@ PCB_PAD_T
class PAD, a pad in a footprint
Definition: typeinfo.h:87
@ PCB_ARC_T
class PCB_ARC, an arc track segment on a copper layer
Definition: typeinfo.h:98
@ PCB_TRACE_T
class PCB_TRACK, a track segment (segment on a copper layer)
Definition: typeinfo.h:96
constexpr ret_type KiROUND(fp_type v)
Round a floating point number to an integer using "round halfway cases away from zero".
Definition: util.h:121