KiCad PCB EDA Suite
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connectivity_data.cpp
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1/*
2 * This program source code file is part of KICAD, a free EDA CAD application.
3 *
4 * Copyright (C) 2017 CERN
5 * Copyright (C) 2018-2023 KiCad Developers, see AUTHORS.txt for contributors.
6 * @author Tomasz Wlostowski <[email protected]>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, you may find one here:
20 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
21 * or you may search the http://www.gnu.org website for the version 2 license,
22 * or you may write to the Free Software Foundation, Inc.,
23 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
24 */
25
26#ifdef PROFILE
27#include <core/profile.h>
28#endif
29
30#include <algorithm>
31#include <future>
32#include <initializer_list>
33
42#include <progress_reporter.h>
43#include <core/thread_pool.h>
44#include <trigo.h>
45#include <drc/drc_rtree.h>
46
48{
50 m_progressReporter = nullptr;
51 m_fromToCache.reset( new FROM_TO_CACHE );
52}
53
54
55CONNECTIVITY_DATA::CONNECTIVITY_DATA( const std::vector<BOARD_ITEM*>& aItems, bool aSkipRatsnest )
56 : m_skipRatsnest( aSkipRatsnest )
57{
58 Build( aItems );
59 m_progressReporter = nullptr;
60 m_fromToCache.reset( new FROM_TO_CACHE );
61}
62
63
65{
66 for( RN_NET* net : m_nets )
67 delete net;
68
69 m_nets.clear();
70}
71
72
74{
75 m_connAlgo->Add( aItem );
76 return true;
77}
78
79
81{
82 m_connAlgo->Remove( aItem );
83 return true;
84}
85
86
88{
89 m_connAlgo->Remove( aItem );
90 m_connAlgo->Add( aItem );
91 return true;
92}
93
94
96{
97 aBoard->CacheTriangulation( aReporter );
98
99 std::unique_lock<KISPINLOCK> lock( m_lock, std::try_to_lock );
100
101 if( !lock )
102 return false;
103
104 if( aReporter )
105 {
106 aReporter->Report( _( "Updating nets..." ) );
107 aReporter->KeepRefreshing( false );
108 }
109
110 std::shared_ptr<NET_SETTINGS>& netSettings = aBoard->GetDesignSettings().m_NetSettings;
111
112 m_connAlgo.reset( new CN_CONNECTIVITY_ALGO );
113 m_connAlgo->Build( aBoard, aReporter );
114
115 m_netclassMap.clear();
116
117 for( NETINFO_ITEM* net : aBoard->GetNetInfo() )
118 {
119 net->SetNetClass( netSettings->GetEffectiveNetClass( net->GetNetname() ) );
120
121 if( net->GetNetClass()->GetName() != NETCLASS::Default )
122 m_netclassMap[ net->GetNetCode() ] = net->GetNetClass()->GetName();
123 }
124
125 if( aReporter )
126 {
127 aReporter->SetCurrentProgress( 0.75 );
128 aReporter->KeepRefreshing( false );
129 }
130
132
133 if( aReporter )
134 {
135 aReporter->SetCurrentProgress( 1.0 );
136 aReporter->KeepRefreshing( false );
137 }
138
139 return true;
140}
141
142
143void CONNECTIVITY_DATA::Build( const std::vector<BOARD_ITEM*>& aItems )
144{
145 std::unique_lock<KISPINLOCK> lock( m_lock, std::try_to_lock );
146
147 if( !lock )
148 return;
149
150 m_connAlgo.reset( new CN_CONNECTIVITY_ALGO );
151 m_connAlgo->LocalBuild( aItems );
152
154}
155
156
158{
159 m_connAlgo->ForEachAnchor( [&aDelta]( CN_ANCHOR& anchor )
160 {
161 anchor.Move( aDelta );
162 } );
163}
164
165
167{
168#ifdef PROFILE
169 PROF_TIMER rnUpdate( "update-ratsnest" );
170#endif
171
172 std::vector<RN_NET*> dirty_nets;
173
174 // Start with net 1 as net 0 is reserved for not-connected
175 // Nets without nodes are also ignored
176 std::copy_if( m_nets.begin() + 1, m_nets.end(), std::back_inserter( dirty_nets ),
177 [] ( RN_NET* aNet )
178 {
179 return aNet->IsDirty() && aNet->GetNodeCount() > 0;
180 } );
181
183
184 tp.push_loop( dirty_nets.size(),
185 [&]( const int a, const int b )
186 {
187 for( int ii = a; ii < b; ++ii )
188 dirty_nets[ii]->UpdateNet();
189 } );
190 tp.wait_for_tasks();
191
192 tp.push_loop( dirty_nets.size(),
193 [&]( const int a, const int b )
194 {
195 for( int ii = a; ii < b; ++ii )
196 dirty_nets[ii]->OptimizeRNEdges();
197 } );
198 tp.wait_for_tasks();
199
200#ifdef PROFILE
201 rnUpdate.Show();
202#endif
203}
204
205
206void CONNECTIVITY_DATA::addRatsnestCluster( const std::shared_ptr<CN_CLUSTER>& aCluster )
207{
208 RN_NET* rnNet = m_nets[ aCluster->OriginNet() ];
209
210 rnNet->AddCluster( aCluster );
211}
212
213
215{
216
217 // We can take over the lock here if called in the same thread
218 // This is to prevent redraw during a RecalculateRatsnets process
219 std::unique_lock<KISPINLOCK> lock( m_lock );
220
222
223}
224
226{
227 m_connAlgo->PropagateNets( aCommit );
228
229 int lastNet = m_connAlgo->NetCount();
230
231 if( lastNet >= (int) m_nets.size() )
232 {
233 unsigned int prevSize = m_nets.size();
234 m_nets.resize( lastNet + 1 );
235
236 for( unsigned int i = prevSize; i < m_nets.size(); i++ )
237 m_nets[i] = new RN_NET;
238 }
239 else
240 {
241 for( size_t ii = lastNet; ii < m_nets.size(); ++ii )
242 m_nets[ii]->Clear();
243 }
244
245 const std::vector<std::shared_ptr<CN_CLUSTER>>& clusters = m_connAlgo->GetClusters();
246
247 int dirtyNets = 0;
248
249 for( int net = 0; net < lastNet; net++ )
250 {
251 if( m_connAlgo->IsNetDirty( net ) )
252 {
253 m_nets[net]->Clear();
254 dirtyNets++;
255 }
256 }
257
258 for( const std::shared_ptr<CN_CLUSTER>& c : clusters )
259 {
260 int net = c->OriginNet();
261
262 // Don't add intentionally-kept zone islands to the ratsnest
263 if( c->IsOrphaned() && c->Size() == 1 )
264 {
265 if( dynamic_cast<CN_ZONE_LAYER*>( *c->begin() ) )
266 continue;
267 }
268
269 if( m_connAlgo->IsNetDirty( net ) )
271 }
272
273 m_connAlgo->ClearDirtyFlags();
274
275 if( !m_skipRatsnest )
277}
278
279
280void CONNECTIVITY_DATA::BlockRatsnestItems( const std::vector<BOARD_ITEM*>& aItems )
281{
282 std::vector<BOARD_CONNECTED_ITEM*> citems;
283
284 for( BOARD_ITEM* item : aItems )
285 {
286 if( item->Type() == PCB_FOOTPRINT_T )
287 {
288 for( PAD* pad : static_cast<FOOTPRINT*>(item)->Pads() )
289 citems.push_back( pad );
290 }
291 else
292 {
293 if( BOARD_CONNECTED_ITEM* citem = dynamic_cast<BOARD_CONNECTED_ITEM*>( item ) )
294 citems.push_back( citem );
295 }
296 }
297
298 for( const BOARD_CONNECTED_ITEM* item : citems )
299 {
300 if ( m_connAlgo->ItemExists( item ) )
301 {
302 CN_CONNECTIVITY_ALGO::ITEM_MAP_ENTRY& entry = m_connAlgo->ItemEntry( item );
303
304 for( CN_ITEM* cnItem : entry.GetItems() )
305 {
306 for( const std::shared_ptr<CN_ANCHOR>& anchor : cnItem->Anchors() )
307 anchor->SetNoLine( true );
308 }
309 }
310 }
311}
312
313
315{
316 return m_connAlgo->NetCount();
317}
318
319
320void CONNECTIVITY_DATA::FillIsolatedIslandsMap( std::map<ZONE*, std::map<PCB_LAYER_ID, ISOLATED_ISLANDS>>& aMap,
321 bool aConnectivityAlreadyRebuilt )
322{
323 m_connAlgo->FillIsolatedIslandsMap( aMap, aConnectivityAlreadyRebuilt );
324}
325
326
327void CONNECTIVITY_DATA::ComputeLocalRatsnest( const std::vector<BOARD_ITEM*>& aItems,
328 const CONNECTIVITY_DATA* aDynamicData,
329 VECTOR2I aInternalOffset )
330{
331 if( !aDynamicData )
332 return;
333
334 m_dynamicRatsnest.clear();
335 std::mutex dynamic_ratsnest_mutex;
336
337 // This gets connections between the stationary board and the
338 // moving selection
339
340 auto update_lambda = [&]( int nc )
341 {
342 RN_NET* dynamicNet = aDynamicData->m_nets[nc];
343 RN_NET* staticNet = m_nets[nc];
344
348 if( dynamicNet->GetNodeCount() != 0
349 && dynamicNet->GetNodeCount() != staticNet->GetNodeCount() )
350 {
351 VECTOR2I pos1, pos2;
352
353 if( staticNet->NearestBicoloredPair( dynamicNet, pos1, pos2 ) )
354 {
356 l.a = pos1;
357 l.b = pos2;
358 l.netCode = nc;
359
360 std::lock_guard<std::mutex> lock( dynamic_ratsnest_mutex );
361 m_dynamicRatsnest.push_back( l );
362 }
363 }
364 };
365
367 size_t num_nets = std::min( m_nets.size(), aDynamicData->m_nets.size() );
368
369 tp.push_loop( 1, num_nets,
370 [&]( const int a, const int b)
371 {
372 for( int ii = a; ii < b; ++ii )
373 update_lambda( ii );
374 });
375 tp.wait_for_tasks();
376
377 // This gets the ratsnest for internal connections in the moving set
378 const std::vector<CN_EDGE>& edges = GetRatsnestForItems( aItems );
379
380 for( const CN_EDGE& edge : edges )
381 {
382 const std::shared_ptr<const CN_ANCHOR>& nodeA = edge.GetSourceNode();
383 const std::shared_ptr<const CN_ANCHOR>& nodeB = edge.GetTargetNode();
385
386 // Use the parents' positions
387 l.a = nodeA->Parent()->GetPosition() + aInternalOffset;
388 l.b = nodeB->Parent()->GetPosition() + aInternalOffset;
389 l.netCode = 0;
390 m_dynamicRatsnest.push_back( l );
391 }
392}
393
394
396{
397 m_connAlgo->ForEachAnchor( []( CN_ANCHOR& anchor )
398 {
399 anchor.SetNoLine( false );
400 } );
402}
403
404
406{
407 m_dynamicRatsnest.clear();
408}
409
410
412{
413 m_connAlgo->PropagateNets( aCommit );
414}
415
416
418 const std::initializer_list<KICAD_T>& aTypes ) const
419{
420 CN_CONNECTIVITY_ALGO::ITEM_MAP_ENTRY &entry = m_connAlgo->ItemEntry( aItem );
421
422 auto matchType =
423 [&]( KICAD_T aItemType )
424 {
425 if( aTypes.size() == 0 )
426 return true;
427
428 return alg::contains( aTypes, aItemType);
429 };
430
431 for( CN_ITEM* citem : entry.GetItems() )
432 {
433 for( CN_ITEM* connected : citem->ConnectedItems() )
434 {
435 CN_ZONE_LAYER* zoneLayer = dynamic_cast<CN_ZONE_LAYER*>( connected );
436
437 if( connected->Valid()
438 && connected->Layers().Overlaps( aLayer )
439 && matchType( connected->Parent()->Type() )
440 && connected->Net() == aItem->GetNetCode() )
441 {
442 if( aItem->Type() == PCB_PAD_T && zoneLayer )
443 {
444 const PAD* pad = static_cast<const PAD*>( aItem );
445 ZONE* zone = static_cast<ZONE*>( zoneLayer->Parent() );
446 int islandIdx = zoneLayer->SubpolyIndex();
447
448 if( zone->IsFilled() )
449 {
450 const SHAPE_POLY_SET* zoneFill = zone->GetFill( ToLAYER_ID( aLayer ) );
451 const SHAPE_LINE_CHAIN& padHull = pad->GetEffectivePolygon()->Outline( 0 );
452
453 for( const VECTOR2I& pt : zoneFill->COutline( islandIdx ).CPoints() )
454 {
455 // If the entire island is inside the pad's flashing then the pad
456 // won't actually connect to anything else, so only return true if
457 // part of the island is *outside* the pad's flashing.
458
459 if( !padHull.PointInside( pt ) )
460 return true;
461 }
462 }
463
464 continue;
465 }
466 else if( aItem->Type() == PCB_VIA_T && zoneLayer )
467 {
468 const PCB_VIA* via = static_cast<const PCB_VIA*>( aItem );
469 ZONE* zone = static_cast<ZONE*>( zoneLayer->Parent() );
470 int islandIdx = zoneLayer->SubpolyIndex();
471
472 if( zone->IsFilled() )
473 {
474 const SHAPE_POLY_SET* zoneFill = zone->GetFill( ToLAYER_ID( aLayer ) );
475 SHAPE_CIRCLE viaHull( via->GetCenter(), via->GetWidth() / 2 );
476
477 for( const VECTOR2I& pt : zoneFill->COutline( islandIdx ).CPoints() )
478 {
479 // If the entire island is inside the via's flashing then the via
480 // won't actually connect to anything else, so only return true if
481 // part of the island is *outside* the via's flashing.
482
483 if( !viaHull.SHAPE::Collide( pt ) )
484 return true;
485 }
486 }
487
488 continue;
489 }
490
491 return true;
492 }
493 }
494 }
495
496 return false;
497}
498
499
500unsigned int CONNECTIVITY_DATA::GetUnconnectedCount( bool aVisibleOnly ) const
501{
502 unsigned int unconnected = 0;
503
504 for( RN_NET* net : m_nets )
505 {
506 if( !net )
507 continue;
508
509 for( const CN_EDGE& edge : net->GetEdges() )
510 {
511 if( edge.IsVisible() || !aVisibleOnly )
512 ++unconnected;
513 }
514 }
515
516 return unconnected;
517}
518
519
521{
522 for( RN_NET* net : m_nets )
523 net->Clear();
524}
525
526
527const std::vector<BOARD_CONNECTED_ITEM*>
529 const std::initializer_list<KICAD_T>& aTypes,
530 bool aIgnoreNetcodes ) const
531{
532 std::vector<BOARD_CONNECTED_ITEM*> rv;
534
535 if( aIgnoreNetcodes )
537 else
539
540 const auto clusters = m_connAlgo->SearchClusters( searchMode, aTypes,
541 aIgnoreNetcodes ? -1 : aItem->GetNetCode() );
542
543 for( const std::shared_ptr<CN_CLUSTER>& cl : clusters )
544 {
545 if( cl->Contains( aItem ) )
546 {
547 for( const CN_ITEM* item : *cl )
548 {
549 if( item->Valid() )
550 rv.push_back( item->Parent() );
551 }
552 }
553 }
554
555 return rv;
556}
557
558
559const std::vector<BOARD_CONNECTED_ITEM*>
560CONNECTIVITY_DATA::GetNetItems( int aNetCode, const std::initializer_list<KICAD_T>& aTypes ) const
561{
562 std::vector<BOARD_CONNECTED_ITEM*> items;
563 items.reserve( 32 );
564
565 std::bitset<MAX_STRUCT_TYPE_ID> type_bits;
566
567 for( KICAD_T scanType : aTypes )
568 {
569 wxASSERT( scanType < MAX_STRUCT_TYPE_ID );
570 type_bits.set( scanType );
571 }
572
573 m_connAlgo->ForEachItem(
574 [&]( CN_ITEM& aItem )
575 {
576 if( aItem.Valid() && ( aItem.Net() == aNetCode ) && type_bits[aItem.Parent()->Type()] )
577 items.push_back( aItem.Parent() );
578 } );
579
580 std::sort( items.begin(), items.end() );
581 items.erase( std::unique( items.begin(), items.end() ), items.end() );
582 return items;
583}
584
585
586const std::vector<PCB_TRACK*>
588{
589 CN_CONNECTIVITY_ALGO::ITEM_MAP_ENTRY& entry = m_connAlgo->ItemEntry( aItem );
590
591 std::set<PCB_TRACK*> tracks;
592 std::vector<PCB_TRACK*> rv;
593
594 for( CN_ITEM* citem : entry.GetItems() )
595 {
596 for( CN_ITEM* connected : citem->ConnectedItems() )
597 {
598 if( connected->Valid() &&
599 ( connected->Parent()->Type() == PCB_TRACE_T ||
600 connected->Parent()->Type() == PCB_VIA_T ||
601 connected->Parent()->Type() == PCB_ARC_T ) )
602 {
603 tracks.insert( static_cast<PCB_TRACK*> ( connected->Parent() ) );
604 }
605 }
606 }
607
608 std::copy( tracks.begin(), tracks.end(), std::back_inserter( rv ) );
609 return rv;
610}
611
612
614 std::set<PAD*>* pads ) const
615{
616 for( CN_ITEM* citem : m_connAlgo->ItemEntry( aItem ).GetItems() )
617 {
618 for( CN_ITEM* connected : citem->ConnectedItems() )
619 {
620 if( connected->Valid() && connected->Parent()->Type() == PCB_PAD_T )
621 pads->insert( static_cast<PAD*> ( connected->Parent() ) );
622 }
623 }
624}
625
626
627const std::vector<PAD*> CONNECTIVITY_DATA::GetConnectedPads( const BOARD_CONNECTED_ITEM* aItem )
628const
629{
630 std::set<PAD*> pads;
631 std::vector<PAD*> rv;
632
633 GetConnectedPads( aItem, &pads );
634
635 std::copy( pads.begin(), pads.end(), std::back_inserter( rv ) );
636 return rv;
637}
638
639
641 std::vector<PAD*>* pads,
642 std::vector<PCB_VIA*>* vias )
643{
644 for( CN_ITEM* citem : m_connAlgo->ItemEntry( aItem ).GetItems() )
645 {
646 for( CN_ITEM* connected : citem->ConnectedItems() )
647 {
648 if( connected->Valid() )
649 {
650 BOARD_CONNECTED_ITEM* parent = connected->Parent();
651
652 if( parent->Type() == PCB_PAD_T )
653 pads->push_back( static_cast<PAD*>( parent ) );
654 else if( parent->Type() == PCB_VIA_T )
655 vias->push_back( static_cast<PCB_VIA*>( parent ) );
656 }
657 }
658 }
659}
660
661
662unsigned int CONNECTIVITY_DATA::GetNodeCount( int aNet ) const
663{
664 int sum = 0;
665
666 if( aNet < 0 ) // Node count for all nets
667 {
668 for( const RN_NET* net : m_nets )
669 sum += net->GetNodeCount();
670 }
671 else if( aNet < (int) m_nets.size() )
672 {
673 sum = m_nets[aNet]->GetNodeCount();
674 }
675
676 return sum;
677}
678
679
680unsigned int CONNECTIVITY_DATA::GetPadCount( int aNet ) const
681{
682 int n = 0;
683
684 for( CN_ITEM* pad : m_connAlgo->ItemList() )
685 {
686 if( !pad->Valid() || pad->Parent()->Type() != PCB_PAD_T)
687 continue;
688
689 PAD* dpad = static_cast<PAD*>( pad->Parent() );
690
691 if( aNet < 0 || aNet == dpad->GetNetCode() )
692 n++;
693 }
694
695 return n;
696}
697
698
699void CONNECTIVITY_DATA::RunOnUnconnectedEdges( std::function<bool( CN_EDGE& )> aFunc )
700{
701 for( RN_NET* rnNet : m_nets )
702 {
703 if( rnNet )
704 {
705 for( CN_EDGE& edge : rnNet->GetEdges() )
706 {
707 if( !aFunc( edge ) )
708 return;
709 }
710 }
711 }
712}
713
714
715static int getMinDist( BOARD_CONNECTED_ITEM* aItem, const VECTOR2I& aPoint )
716{
717 switch( aItem->Type() )
718 {
719 case PCB_TRACE_T:
720 case PCB_ARC_T:
721 {
722 PCB_TRACK* track = static_cast<PCB_TRACK*>( aItem );
723
724 return std::min( GetLineLength( track->GetStart(), aPoint ),
725 GetLineLength( track->GetEnd(), aPoint ) );
726 }
727
728 default:
729 return GetLineLength( aItem->GetPosition(), aPoint );
730 }
731}
732
733
734bool CONNECTIVITY_DATA::TestTrackEndpointDangling( PCB_TRACK* aTrack, bool aIgnoreTracksInPads,
735 VECTOR2I* aPos ) const
736{
737 const std::list<CN_ITEM*>& items = GetConnectivityAlgo()->ItemEntry( aTrack ).GetItems();
738
739 // Not in the connectivity system. This is a bug!
740 if( items.empty() )
741 {
742 wxFAIL_MSG( wxT( "track not in connectivity system" ) );
743 return false;
744 }
745
746 CN_ITEM* citem = items.front();
747
748 if( !citem->Valid() )
749 return false;
750
751 if( aTrack->Type() == PCB_TRACE_T || aTrack->Type() == PCB_ARC_T )
752 {
753 // Test if a segment is connected on each end.
754 //
755 // NB: be wary of short segments which can be connected to the *same* other item on
756 // each end. If that's their only connection then they're still dangling.
757
758 PCB_LAYER_ID layer = aTrack->GetLayer();
759 int accuracy = KiROUND( aTrack->GetWidth() / 2 );
760 int start_count = 0;
761 int end_count = 0;
762
763 for( CN_ITEM* connected : citem->ConnectedItems() )
764 {
765 BOARD_CONNECTED_ITEM* item = connected->Parent();
766 ZONE* zone = dynamic_cast<ZONE*>( item );
767 DRC_RTREE* rtree = nullptr;
768 bool hitStart = false;
769 bool hitEnd = false;
770
771 if( item->GetFlags() & IS_DELETED )
772 continue;
773
774 if( zone )
775 rtree = zone->GetBoard()->m_CopperZoneRTreeCache[ zone ].get();
776
777 if( rtree )
778 {
779 SHAPE_CIRCLE start( aTrack->GetStart(), accuracy );
780 SHAPE_CIRCLE end( aTrack->GetEnd(), accuracy );
781
782 hitStart = rtree->QueryColliding( start.BBox(), &start, layer );
783 hitEnd = rtree->QueryColliding( end.BBox(), &end, layer );
784 }
785 else
786 {
787 std::shared_ptr<SHAPE> shape = item->GetEffectiveShape( layer );
788
789 hitStart = shape->Collide( aTrack->GetStart(), accuracy );
790 hitEnd = shape->Collide( aTrack->GetEnd(), accuracy );
791 }
792
793 if( hitStart && hitEnd )
794 {
795 if( zone )
796 {
797 // Both start and end in a zone: track may be redundant, but it's not dangling
798 return false;
799 }
800 else if( item->Type() == PCB_PAD_T || item->Type() == PCB_VIA_T )
801 {
802 // Both start and end are under a pad: see what the caller wants us to do
803 if( aIgnoreTracksInPads )
804 return false;
805 }
806
807 if( getMinDist( item, aTrack->GetStart() ) < getMinDist( item, aTrack->GetEnd() ) )
808 start_count++;
809 else
810 end_count++;
811 }
812 else if( hitStart )
813 {
814 start_count++;
815 }
816 else if( hitEnd )
817 {
818 end_count++;
819 }
820
821 if( start_count > 0 && end_count > 0 )
822 return false;
823 }
824
825 if( aPos )
826 *aPos = (start_count == 0 ) ? aTrack->GetStart() : aTrack->GetEnd();
827
828 return true;
829 }
830 else if( aTrack->Type() == PCB_VIA_T )
831 {
832 // Test if a via is only connected on one layer
833
834 const std::vector<CN_ITEM*>& connected = citem->ConnectedItems();
835
836 if( connected.empty() )
837 {
838 if( aPos )
839 *aPos = aTrack->GetPosition();
840
841 return true;
842 }
843
844 // Here, we check if the via is connected only to items on a single layer
845 int first_layer = UNDEFINED_LAYER;
846
847 for( CN_ITEM* item : connected )
848 {
849 if( item->Parent()->GetFlags() & IS_DELETED )
850 continue;
851
852 if( first_layer == UNDEFINED_LAYER )
853 first_layer = item->Layer();
854 else if( item->Layer() != first_layer )
855 return false;
856 }
857
858 if( aPos )
859 *aPos = aTrack->GetPosition();
860
861 return true;
862 }
863 else
864 {
865 wxFAIL_MSG( wxT( "CONNECTIVITY_DATA::TestTrackEndpointDangling: unknown track type" ) );
866 }
867
868 return false;
869}
870
871
872const std::vector<BOARD_CONNECTED_ITEM*>
874 const VECTOR2I& aAnchor,
875 const std::initializer_list<KICAD_T>& aTypes,
876 const int& aMaxError ) const
877{
878 CN_CONNECTIVITY_ALGO::ITEM_MAP_ENTRY& entry = m_connAlgo->ItemEntry( aItem );
879 std::vector<BOARD_CONNECTED_ITEM*> rv;
880 SEG::ecoord maxError_sq = (SEG::ecoord) aMaxError * aMaxError;
881
882 for( CN_ITEM* cnItem : entry.GetItems() )
883 {
884 for( CN_ITEM* connected : cnItem->ConnectedItems() )
885 {
886 for( const std::shared_ptr<CN_ANCHOR>& anchor : connected->Anchors() )
887 {
888 if( ( anchor->Pos() - aAnchor ).SquaredEuclideanNorm() <= maxError_sq )
889 {
890 for( KICAD_T type : aTypes )
891 {
892 if( connected->Valid() && connected->Parent()->Type() == type )
893 {
894 rv.push_back( connected->Parent() );
895 break;
896 }
897 }
898
899 break;
900 }
901 }
902 }
903 }
904
905 return rv;
906}
907
908
910{
911 if ( aNet < 0 || aNet >= (int) m_nets.size() )
912 return nullptr;
913
914 return m_nets[ aNet ];
915}
916
917
919{
920 if ( aItem->Type() == PCB_FOOTPRINT_T)
921 {
922 for( PAD* pad : static_cast<FOOTPRINT*>( aItem )->Pads() )
923 m_connAlgo->MarkNetAsDirty( pad->GetNetCode() );
924 }
925
926 if (aItem->IsConnected() )
927 m_connAlgo->MarkNetAsDirty( static_cast<BOARD_CONNECTED_ITEM*>( aItem )->GetNetCode() );
928}
929
930
932{
933 m_progressReporter = aReporter;
934 m_connAlgo->SetProgressReporter( m_progressReporter );
935}
936
937
938const std::vector<CN_EDGE>
939CONNECTIVITY_DATA::GetRatsnestForItems( const std::vector<BOARD_ITEM*>& aItems )
940{
941 std::set<int> nets;
942 std::vector<CN_EDGE> edges;
943 std::set<BOARD_CONNECTED_ITEM*> item_set;
944
945 for( BOARD_ITEM* item : aItems )
946 {
947 if( item->Type() == PCB_FOOTPRINT_T )
948 {
949 FOOTPRINT* footprint = static_cast<FOOTPRINT*>( item );
950
951 for( PAD* pad : footprint->Pads() )
952 {
953 nets.insert( pad->GetNetCode() );
954 item_set.insert( pad );
955 }
956 }
957 else if( item->IsConnected() )
958 {
959 BOARD_CONNECTED_ITEM* conn_item = static_cast<BOARD_CONNECTED_ITEM*>( item );
960
961 item_set.insert( conn_item );
962 nets.insert( conn_item->GetNetCode() );
963 }
964 }
965
966 for( int netcode : nets )
967 {
968 RN_NET* net = GetRatsnestForNet( netcode );
969
970 if( !net )
971 continue;
972
973 for( const CN_EDGE& edge : net->GetEdges() )
974 {
975 std::shared_ptr<const CN_ANCHOR> srcNode = edge.GetSourceNode();
976 std::shared_ptr<const CN_ANCHOR> dstNode = edge.GetTargetNode();
977
978 BOARD_CONNECTED_ITEM* srcParent = srcNode->Parent();
979 BOARD_CONNECTED_ITEM* dstParent = dstNode->Parent();
980
981 bool srcFound = ( item_set.find( srcParent ) != item_set.end() );
982 bool dstFound = ( item_set.find( dstParent ) != item_set.end() );
983
984 if ( srcFound && dstFound )
985 edges.push_back( edge );
986 }
987 }
988
989 return edges;
990}
991
992
993const std::vector<CN_EDGE> CONNECTIVITY_DATA::GetRatsnestForPad( const PAD* aPad )
994{
995 std::vector<CN_EDGE> edges;
996 RN_NET* net = GetRatsnestForNet( aPad->GetNetCode() );
997
998 if( !net )
999 return edges;
1000
1001 for( const CN_EDGE& edge : net->GetEdges() )
1002 {
1003 if( edge.GetSourceNode()->Parent() == aPad || edge.GetTargetNode()->Parent() == aPad )
1004 edges.push_back( edge );
1005 }
1006
1007 return edges;
1008}
1009
1010
1011const std::vector<CN_EDGE> CONNECTIVITY_DATA::GetRatsnestForComponent( FOOTPRINT* aComponent,
1012 bool aSkipInternalConnections )
1013{
1014 std::set<int> nets;
1015 std::set<const PAD*> pads;
1016 std::vector<CN_EDGE> edges;
1017
1018 for( PAD* pad : aComponent->Pads() )
1019 {
1020 nets.insert( pad->GetNetCode() );
1021 pads.insert( pad );
1022 }
1023
1024 for( int netcode : nets )
1025 {
1026 RN_NET* net = GetRatsnestForNet( netcode );
1027
1028 if( !net )
1029 continue;
1030
1031 for( const CN_EDGE& edge : net->GetEdges() )
1032 {
1033 const std::shared_ptr<const CN_ANCHOR>& srcNode = edge.GetSourceNode();
1034 const std::shared_ptr<const CN_ANCHOR>& dstNode = edge.GetTargetNode();
1035
1036 const PAD* srcParent = static_cast<const PAD*>( srcNode->Parent() );
1037 const PAD* dstParent = static_cast<const PAD*>( dstNode->Parent() );
1038
1039 bool srcFound = ( pads.find(srcParent) != pads.end() );
1040 bool dstFound = ( pads.find(dstParent) != pads.end() );
1041
1042 if ( srcFound && dstFound && !aSkipInternalConnections )
1043 edges.push_back( edge );
1044 else if ( srcFound || dstFound )
1045 edges.push_back( edge );
1046 }
1047 }
1048
1049 return edges;
1050}
1051
1052
A base class derived from BOARD_ITEM for items that can be connected and have a net,...
std::shared_ptr< NET_SETTINGS > m_NetSettings
A base class for any item which can be embedded within the BOARD container class, and therefore insta...
Definition: board_item.h:77
virtual PCB_LAYER_ID GetLayer() const
Return the primary layer this item is on.
Definition: board_item.h:204
virtual bool IsConnected() const
Returns information if the object is derived from BOARD_CONNECTED_ITEM.
Definition: board_item.h:134
virtual std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
Definition: board_item.cpp:227
virtual const BOARD * GetBoard() const
Return the BOARD in which this BOARD_ITEM resides, or NULL if none.
Definition: board_item.cpp:45
Information pertinent to a Pcbnew printed circuit board.
Definition: board.h:271
const NETINFO_LIST & GetNetInfo() const
Definition: board.h:803
std::unordered_map< ZONE *, std::unique_ptr< DRC_RTREE > > m_CopperZoneRTreeCache
Definition: board.h:1198
BOARD_DESIGN_SETTINGS & GetDesignSettings() const
Definition: board.cpp:731
void CacheTriangulation(PROGRESS_REPORTER *aReporter=nullptr, const std::vector< ZONE * > &aZones={})
Definition: board.cpp:770
CN_ANCHOR represents a physical location that can be connected: a pad or a track/arc/via endpoint.
const std::list< CN_ITEM * > & GetItems() const
CN_EDGE represents a point-to-point connection, whether realized or unrealized (ie: tracks etc.
CN_ITEM represents a BOARD_CONNETED_ITEM in the connectivity system (ie: a pad, track/arc/via,...
const std::vector< CN_ITEM * > & ConnectedItems() const
int Net() const
bool Valid() const
BOARD_CONNECTED_ITEM * Parent() const
int SubpolyIndex() const
void FillIsolatedIslandsMap(std::map< ZONE *, std::map< PCB_LAYER_ID, ISOLATED_ISLANDS > > &aMap, bool aConnectivityAlreadyRebuilt=false)
Fill the isolate islands list for each layer of each zone.
void RecalculateRatsnest(BOARD_COMMIT *aCommit=nullptr)
Function RecalculateRatsnest() Updates the ratsnest for the board.
void ClearLocalRatsnest()
Function ClearLocalRatsnest() Erases the temporary, selection-based ratsnest (i.e.
PROGRESS_REPORTER * m_progressReporter
bool m_skipRatsnest
Used to suppress ratsnest calculations on dynamic ratsnests.
unsigned int GetPadCount(int aNet=-1) const
const std::vector< BOARD_CONNECTED_ITEM * > GetConnectedItemsAtAnchor(const BOARD_CONNECTED_ITEM *aItem, const VECTOR2I &aAnchor, const std::initializer_list< KICAD_T > &aTypes, const int &aMaxError=0) const
Function GetConnectedItemsAtAnchor() Returns a list of items connected to a source item aItem at posi...
void MarkItemNetAsDirty(BOARD_ITEM *aItem)
void PropagateNets(BOARD_COMMIT *aCommit=nullptr)
Propagates the net codes from the source pads to the tracks/vias.
void RunOnUnconnectedEdges(std::function< bool(CN_EDGE &)> aFunc)
std::vector< RN_DYNAMIC_LINE > m_dynamicRatsnest
const std::vector< CN_EDGE > GetRatsnestForPad(const PAD *aPad)
RN_NET * GetRatsnestForNet(int aNet)
Function GetRatsnestForNet() Returns the ratsnest, expressed as a set of graph edges for a given net.
void ClearRatsnest()
Function Clear() Erases the connectivity database.
bool Remove(BOARD_ITEM *aItem)
Function Remove() Removes an item from the connectivity data.
void GetConnectedPadsAndVias(const BOARD_CONNECTED_ITEM *aItem, std::vector< PAD * > *pads, std::vector< PCB_VIA * > *vias)
void ComputeLocalRatsnest(const std::vector< BOARD_ITEM * > &aItems, const CONNECTIVITY_DATA *aDynamicData, VECTOR2I aInternalOffset={ 0, 0 })
Function ComputeLocalRatsnest() Calculates the temporary (usually selection-based) ratsnest for the s...
bool TestTrackEndpointDangling(PCB_TRACK *aTrack, bool aIgnoreTracksInPads, VECTOR2I *aPos=nullptr) const
unsigned int GetNodeCount(int aNet=-1) const
void SetProgressReporter(PROGRESS_REPORTER *aReporter)
void BlockRatsnestItems(const std::vector< BOARD_ITEM * > &aItems)
bool IsConnectedOnLayer(const BOARD_CONNECTED_ITEM *aItem, int aLayer, const std::initializer_list< KICAD_T > &aTypes={}) const
const std::vector< PCB_TRACK * > GetConnectedTracks(const BOARD_CONNECTED_ITEM *aItem) const
std::map< int, wxString > m_netclassMap
Map of netcode -> netclass the net is a member of; used for ratsnest painting.
const std::vector< CN_EDGE > GetRatsnestForComponent(FOOTPRINT *aComponent, bool aSkipInternalConnections=false)
bool Add(BOARD_ITEM *aItem)
Function Add() Adds an item to the connectivity data.
const std::vector< BOARD_CONNECTED_ITEM * > GetConnectedItems(const BOARD_CONNECTED_ITEM *aItem, const std::initializer_list< KICAD_T > &aTypes, bool aIgnoreNetcodes=false) const
Function GetConnectedItems() Returns a list of items connected to a source item aItem.
std::shared_ptr< CN_CONNECTIVITY_ALGO > m_connAlgo
bool Build(BOARD *aBoard, PROGRESS_REPORTER *aReporter=nullptr)
Function Build() Builds the connectivity database for the board aBoard.
std::shared_ptr< FROM_TO_CACHE > m_fromToCache
const std::vector< PAD * > GetConnectedPads(const BOARD_CONNECTED_ITEM *aItem) const
const std::vector< BOARD_CONNECTED_ITEM * > GetNetItems(int aNetCode, const std::initializer_list< KICAD_T > &aTypes) const
Function GetNetItems() Returns the list of items that belong to a certain net.
unsigned int GetUnconnectedCount(bool aVisibileOnly) const
void internalRecalculateRatsnest(BOARD_COMMIT *aCommit=nullptr)
Updates the ratsnest for the board without locking the connectivity mutex.
void HideLocalRatsnest()
Hides the temporary, selection-based ratsnest lines.
const std::vector< CN_EDGE > GetRatsnestForItems(const std::vector< BOARD_ITEM * > &aItems)
void addRatsnestCluster(const std::shared_ptr< CN_CLUSTER > &aCluster)
std::vector< RN_NET * > m_nets
bool Update(BOARD_ITEM *aItem)
Function Update() Updates the connectivity data for an item.
void Move(const VECTOR2I &aDelta)
Moves the connectivity list anchors.
int GetNetCount() const
Function GetNetCount() Returns the total number of nets in the connectivity database.
std::shared_ptr< CN_CONNECTIVITY_ALGO > GetConnectivityAlgo() const
Implement an R-tree for fast spatial and layer indexing of connectable items.
Definition: drc_rtree.h:48
int QueryColliding(BOARD_ITEM *aRefItem, PCB_LAYER_ID aRefLayer, PCB_LAYER_ID aTargetLayer, std::function< bool(BOARD_ITEM *)> aFilter=nullptr, std::function< bool(BOARD_ITEM *)> aVisitor=nullptr, int aClearance=0) const
This is a fast test which essentially does bounding-box overlap given a worst-case clearance.
Definition: drc_rtree.h:214
virtual VECTOR2I GetPosition() const
Definition: eda_item.h:239
KICAD_T Type() const
Returns the type of object.
Definition: eda_item.h:97
EDA_ITEM_FLAGS GetFlags() const
Definition: eda_item.h:126
PADS & Pads()
Definition: footprint.h:188
static const char Default[]
the name of the default NETCLASS
Definition: netclass.h:49
Handle the data for a net.
Definition: netinfo.h:67
Definition: pad.h:58
int GetWidth() const
Definition: pcb_track.h:107
const VECTOR2I & GetStart() const
Definition: pcb_track.h:113
VECTOR2I GetPosition() const override
Definition: pcb_track.h:103
const VECTOR2I & GetEnd() const
Definition: pcb_track.h:110
A small class to help profiling.
Definition: profile.h:47
void Show(std::ostream &aStream=std::cerr)
Print the elapsed time (in a suitable unit) to a stream.
Definition: profile.h:103
A progress reporter interface for use in multi-threaded environments.
virtual bool KeepRefreshing(bool aWait=false)=0
Update the UI (if any).
virtual void Report(const wxString &aMessage)=0
Display aMessage in the progress bar dialog.
virtual void SetCurrentProgress(double aProgress)=0
Set the progress value to aProgress (0..1).
Describe ratsnest for a single net.
Definition: ratsnest_data.h:63
unsigned int GetNodeCount() const
Definition: ratsnest_data.h:92
const std::vector< CN_EDGE > & GetEdges() const
Definition: ratsnest_data.h:94
bool NearestBicoloredPair(RN_NET *aOtherNet, VECTOR2I &aPos1, VECTOR2I &aPos2) const
void AddCluster(std::shared_ptr< CN_CLUSTER > aCluster)
VECTOR2I::extended_type ecoord
Definition: seg.h:44
const BOX2I BBox(int aClearance=0) const override
Compute a bounding box of the shape, with a margin of aClearance a collision.
Definition: shape_circle.h:70
bool PointInside(const VECTOR2I &aPt, int aAccuracy=0, bool aUseBBoxCache=false) const override
Check if point aP lies inside a closed shape.
Represent a polyline containing arcs as well as line segments: A chain of connected line and/or arc s...
const std::vector< VECTOR2I > & CPoints() const
Represent a set of closed polygons.
const SHAPE_LINE_CHAIN & COutline(int aIndex) const
Handle a list of polygons defining a copper zone.
Definition: zone.h:72
bool IsFilled() const
Definition: zone.h:249
SHAPE_POLY_SET * GetFill(PCB_LAYER_ID aLayer)
Definition: zone.h:621
static int getMinDist(BOARD_CONNECTED_ITEM *aItem, const VECTOR2I &aPoint)
#define _(s)
#define IS_DELETED
PCB_LAYER_ID
A quick note on layer IDs:
Definition: layer_ids.h:60
@ UNDEFINED_LAYER
Definition: layer_ids.h:61
PCB_LAYER_ID ToLAYER_ID(int aLayer)
Definition: lset.cpp:932
bool contains(const _Container &__container, _Value __value)
Returns true if the container contains the given value.
Definition: kicad_algo.h:99
Class that computes missing connections on a PCB.
static thread_pool * tp
Definition: thread_pool.cpp:30
BS::thread_pool thread_pool
Definition: thread_pool.h:30
thread_pool & GetKiCadThreadPool()
Get a reference to the current thread pool.
Definition: thread_pool.cpp:32
double GetLineLength(const VECTOR2I &aPointA, const VECTOR2I &aPointB)
Return the length of a line segment defined by aPointA and aPointB.
Definition: trigo.h:188
KICAD_T
The set of class identification values stored in EDA_ITEM::m_structType.
Definition: typeinfo.h:78
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
Definition: typeinfo.h:94
@ MAX_STRUCT_TYPE_ID
Definition: typeinfo.h:240
@ PCB_FOOTPRINT_T
class FOOTPRINT, a footprint
Definition: typeinfo.h:86
@ PCB_PAD_T
class PAD, a pad in a footprint
Definition: typeinfo.h:87
@ PCB_ARC_T
class PCB_ARC, an arc track segment on a copper layer
Definition: typeinfo.h:95
@ PCB_TRACE_T
class PCB_TRACK, a track segment (segment on a copper layer)
Definition: typeinfo.h:93
constexpr ret_type KiROUND(fp_type v)
Round a floating point number to an integer using "round halfway cases away from zero".
Definition: util.h:85