39 const std::shared_ptr<SHAPE_POLY_SET>& aPadShape,
43 int64_t bestDistSq = std::numeric_limits<int64_t>::max();
45 for(
int i = 0; i < aPadShape->OutlineCount(); i++ )
52 std::vector<VECTOR2I> intersections;
57 for(
const VECTOR2I& pt : intersections )
62 int64_t distSq = ( pt - aInsidePoint ).SquaredEuclideanNorm();
64 if( distSq < bestDistSq )
83 const int start = aForward ? 0 : aLine.
PointCount() - 1;
84 const int delta = aForward ? 1 : -1;
89 int firstOutside = -1;
91 bool hasIntersection =
false;
93 for(
int vertex = start +
delta; aForward ? vertex < aLine.
PointCount() : vertex >= 0; vertex +=
delta )
95 if( !shape->Contains( aLine.
GetPoint( vertex ) ) )
97 firstOutside = vertex;
98 int prevVertex = vertex -
delta;
101 ssize_t arcIdx = aLine.
ArcIndex( prevVertex );
103 if( arcIdx >= 0 && aLine.
ArcIndex( vertex ) == arcIdx )
110 if( !hasIntersection )
115 if( shape->Collide( seg, 0,
nullptr, &loc ) )
117 intersectionPt = loc;
118 hasIntersection =
true;
126 if( firstOutside < 0 )
136 if( hasIntersection )
137 newChain.
Append( intersectionPt );
138 newChain.
Append( aLine.
Slice( firstOutside, -1 ) );
144 if( hasIntersection )
145 newChain.
Append( intersectionPt );
154 std::vector<LENGTH_DELAY_CALCULATION_ITEM>& aItems,
const PATH_OPTIMISATIONS aOptimisations,
158 const bool doTrace = wxLog::IsAllowedTraceMask( wxT(
"PNS_TUNE" ) );
162 wxLogTrace( wxT(
"PNS_TUNE" ), wxT(
"" ) );
163 wxLogTrace( wxT(
"PNS_TUNE" ), wxT(
"========== CalculateLengthDetails START ==========" ) );
164 wxLogTrace( wxT(
"PNS_TUNE" ), wxT(
"CalculateLengthDetails: input has %zu items" ), aItems.size() );
165 wxLogTrace( wxT(
"PNS_TUNE" ), wxT(
"CalculateLengthDetails: optimisations - OptimiseVias=%d, MergeTracks=%d, OptimiseTracesInPads=%d, InferViaInPad=%d" ),
170 int initialPads = 0, initialVias = 0, initialLines = 0, initialUnknown = 0;
174 switch( item.Type() )
176 case LENGTH_DELAY_CALCULATION_ITEM::TYPE::PAD: initialPads++;
break;
177 case LENGTH_DELAY_CALCULATION_ITEM::TYPE::VIA: initialVias++;
break;
178 case LENGTH_DELAY_CALCULATION_ITEM::TYPE::LINE: initialLines++;
break;
179 default: initialUnknown++;
break;
183 wxLogTrace( wxT(
"PNS_TUNE" ), wxT(
"CalculateLengthDetails: initial items - PADs=%d, VIAs=%d, LINEs=%d, UNKNOWN=%d" ),
184 initialPads, initialVias, initialLines, initialUnknown );
191 wxLogTrace( wxT(
"PNS_TUNE" ), wxT(
"CalculateLengthDetails: performing optimisations..." ) );
193 std::vector<LENGTH_DELAY_CALCULATION_ITEM*> pads;
194 std::vector<LENGTH_DELAY_CALCULATION_ITEM*> lines;
195 std::vector<LENGTH_DELAY_CALCULATION_ITEM*> vias;
198 std::map<VECTOR2I, std::unordered_set<LENGTH_DELAY_CALCULATION_ITEM*>> linesPositionMap;
201 std::map<VECTOR2I, std::unordered_set<LENGTH_DELAY_CALCULATION_ITEM*>> padsPositionMap;
205 if( item.Type() == LENGTH_DELAY_CALCULATION_ITEM::TYPE::PAD )
207 pads.emplace_back( &item );
208 padsPositionMap[item.GetPad()->GetPosition()].insert( &item );
210 else if( item.Type() == LENGTH_DELAY_CALCULATION_ITEM::TYPE::VIA )
212 vias.emplace_back( &item );
214 else if( item.Type() == LENGTH_DELAY_CALCULATION_ITEM::TYPE::LINE )
216 lines.emplace_back( &item );
217 linesPositionMap[item.GetLine().CPoint( 0 )].insert( &item );
218 linesPositionMap[item.GetLine().CLastPoint()].insert( &item );
225 wxLogTrace( wxT(
"PNS_TUNE" ), wxT(
"CalculateLengthDetails: optimising via layers (%zu vias)" ), vias.size() );
227 optimiseVias( vias, lines, linesPositionMap, padsPositionMap );
233 wxLogTrace( wxT(
"PNS_TUNE" ), wxT(
"CalculateLengthDetails: merging tracks (%zu lines)" ), lines.size() );
260 wxLogTrace( wxT(
"PNS_TUNE" ), wxT(
"CalculateLengthDetails: optimising traces in pads" ) );
272 wxLogTrace( wxT(
"PNS_TUNE" ), wxT(
"CalculateLengthDetails: creating layer detail maps" ) );
274 details.
LayerLengths = std::make_unique<std::map<PCB_LAYER_ID, int64_t>>();
277 details.
LayerDelays = std::make_unique<std::map<PCB_LAYER_ID, int64_t>>();
280 const bool useHeight =
m_board->GetDesignSettings().m_UseHeightForLengthCalcs;
283 wxLogTrace( wxT(
"PNS_TUNE" ), wxT(
"CalculateLengthDetails: useHeight=%d" ), useHeight );
291 wxLogTrace( wxT(
"PNS_TUNE" ), wxT(
"CalculateLengthDetails: inferring vias in pads" ) );
293 std::pair<int64_t, int64_t> inferredStartPadViaDetails{ 0, 0 };
294 std::pair<int64_t, int64_t> inferredEndPadViaDetails{ 0, 0 };
297 inferViaInPad( aStartPad, aItems.front(), details, inferredStartPadViaDetails, withDelay );
298 inferViaInPad( aEndPad, aItems.back(), details, inferredEndPadViaDetails, withDelay );
300 if( aPerItemLengthDelays )
310 int processedPads = 0, processedVias = 0, processedLines = 0;
311 int mergedRetired = 0, unknownType = 0;
314 if( aPerItemLengthDelays )
320 auto setPerItemLengthDetail = [aPerItemLengthDelays](
const size_t idx,
const int64_t value )
322 if( !aPerItemLengthDelays )
328 auto setPerItemDelayDetail = [aPerItemLengthDelays](
const size_t idx,
const int64_t value )
330 if( !aPerItemLengthDelays )
337 wxLogTrace( wxT(
"PNS_TUNE" ), wxT(
"CalculateLengthDetails: processing %zu items..." ), aItems.size() );
339 for(
size_t i = 0; i < aItems.size(); ++i )
345 || item.
Type() == LENGTH_DELAY_CALCULATION_ITEM::TYPE::UNKNOWN )
355 if( item.
Type() == LENGTH_DELAY_CALCULATION_ITEM::TYPE::LINE )
359 setPerItemLengthDetail( i, length );
366 else if( item.
Type() == LENGTH_DELAY_CALCULATION_ITEM::TYPE::VIA && useHeight )
368 const auto [layerStart, layerEnd] = item.
GetLayers();
370 setPerItemLengthDetail( i, viaHeight );
371 details.
ViaLength +=
static_cast<int>( viaHeight );
376 wxLogTrace( wxT(
"PNS_TUNE" ), wxT(
"CalculateLengthDetails: via from layer %d to %d, height=%lld" ),
377 layerStart, layerEnd, viaHeight );
379 else if( item.
Type() == LENGTH_DELAY_CALCULATION_ITEM::TYPE::PAD )
382 setPerItemLengthDetail( i, padToDie );
387 if( doTrace && padToDie > 0 )
388 wxLogTrace( wxT(
"PNS_TUNE" ), wxT(
"CalculateLengthDetails: pad with pad-to-die length=%lld" ), padToDie );
394 wxLogTrace( wxT(
"PNS_TUNE" ), wxT(
"CalculateLengthDetails: processed items - PADs=%d, VIAs=%d, LINEs=%d" ),
395 processedPads, processedVias, processedLines );
396 wxLogTrace( wxT(
"PNS_TUNE" ), wxT(
"CalculateLengthDetails: skipped items - merged/retired=%d, unknown=%d" ),
397 mergedRetired, unknownType );
404 wxLogTrace( wxT(
"PNS_TUNE" ), wxT(
"CalculateLengthDetails: calculating time domain statistics" ) );
408 ctx.
NetClass = aItems.front().GetEffectiveNetClass();
412 wxASSERT( itemDelays.size() == aItems.size() );
414 for(
size_t i = 0; i < aItems.size(); ++i )
419 || item.
Type() == LENGTH_DELAY_CALCULATION_ITEM::TYPE::UNKNOWN )
424 setPerItemDelayDetail( i, itemDelays[i] );
426 if( item.
Type() == LENGTH_DELAY_CALCULATION_ITEM::TYPE::LINE )
433 else if( item.
Type() == LENGTH_DELAY_CALCULATION_ITEM::TYPE::VIA && useHeight )
437 else if( item.
Type() == LENGTH_DELAY_CALCULATION_ITEM::TYPE::PAD )
444 wxLogTrace( wxT(
"PNS_TUNE" ), wxT(
"CalculateLengthDetails: total delays - Track=%lld, Via=%lld, PadToDie=%lld" ),
450 wxLogTrace( wxT(
"PNS_TUNE" ), wxT(
"CalculateLengthDetails: RESULTS:" ) );
451 wxLogTrace( wxT(
"PNS_TUNE" ), wxT(
" Track length: %lld" ), details.
TrackLength );
452 wxLogTrace( wxT(
"PNS_TUNE" ), wxT(
" Via length: %d (from %d vias)" ), details.
ViaLength, details.
NumVias );
453 wxLogTrace( wxT(
"PNS_TUNE" ), wxT(
" Pad-to-die length: %d (from %d pads)" ), details.
PadToDieLength, details.
NumPads );
454 wxLogTrace( wxT(
"PNS_TUNE" ), wxT(
" TOTAL LENGTH: %lld" ), details.
TotalLength() );
455 wxLogTrace( wxT(
"PNS_TUNE" ), wxT(
"========== CalculateLengthDetails END ==========" ) );
456 wxLogTrace( wxT(
"PNS_TUNE" ), wxT(
"" ) );
465 std::pair<int64_t, int64_t>& aInferredViaLengthDelay,
466 const bool aWithDelayDetail )
const
468 if( aPad && aItem.
Type() == LENGTH_DELAY_CALCULATION_ITEM::TYPE::LINE )
473 if( !padLayers.
Contains( startBottomLayer ) )
479 const int64_t height =
StackupHeight( startBottomLayer, padLayer );
481 aInferredViaLengthDelay.first = height;
484 if( aWithDelayDetail )
491 aInferredViaLengthDelay.second = delay;
500 const PAD* aEndPad )
const
508 const PAD* aEndPad )
const
518 if( !
m_board || !
m_board->GetDesignSettings().m_UseHeightForLengthCalcs )
521 if(
m_board->GetDesignSettings().m_HasStackup )
536 std::vector<LENGTH_DELAY_CALCULATION_ITEM*>& aLines,
537 std::map<
VECTOR2I, std::unordered_set<LENGTH_DELAY_CALCULATION_ITEM*>>& aLinesPositionMap )
540 std::vector<LENGTH_DELAY_CALCULATION_ITEM*> pads;
544 aLinesPositionMap[line->GetLine().CPoint( 0 )].erase( line );
545 aLinesPositionMap[line->GetLine().CLastPoint()].erase( line );
549 auto tryMerge = [&removeFromPositionMap, &aLinesPositionMap](
const MERGE_POINT aMergePoint,
554 const auto startItr = aLinesPositionMap.find( aMergePos );
556 if( startItr == aLinesPositionMap.end() )
559 std::unordered_set<LENGTH_DELAY_CALCULATION_ITEM*>& startItems = startItr->second;
561 if( startItems.size() != 1 )
571 if( aPrimaryItem->GetStartLayer() != lineToMerge->
GetStartLayer() )
577 removeFromPositionMap( lineToMerge );
589 removeFromPositionMap( primaryItem );
595 bool mergeComplete =
false;
597 while( !mergeComplete )
599 bool startMerged =
false;
600 bool endMerged =
false;
608 mergeComplete = !startMerged && !endMerged;
621 for(
auto itr = aSecondary.
CPoints().begin() + 1; itr != aSecondary.
CPoints().end(); ++itr )
622 aPrimary.
Insert( 0, *itr );
628 for(
auto itr = aSecondary.
CPoints().rbegin() + 1; itr != aSecondary.
CPoints().rend(); ++itr )
629 aPrimary.
Insert( 0, *itr );
636 for(
auto itr = aSecondary.
CPoints().begin() + 1; itr != aSecondary.
CPoints().end(); ++itr )
643 for(
auto itr = aSecondary.
CPoints().rbegin() + 1; itr != aSecondary.
CPoints().rend(); ++itr )
651 const std::vector<LENGTH_DELAY_CALCULATION_ITEM*>& aLines )
655 const PAD*
pad = padItem->GetPad();
663 const PCB_LAYER_ID pcbLayer = lineItem->GetStartLayer();
673 const std::vector<LENGTH_DELAY_CALCULATION_ITEM*>& aVias, std::vector<LENGTH_DELAY_CALCULATION_ITEM*>& aLines,
674 std::map<
VECTOR2I, std::unordered_set<LENGTH_DELAY_CALCULATION_ITEM*>>& aLinesPositionMap,
675 const std::map<
VECTOR2I, std::unordered_set<LENGTH_DELAY_CALCULATION_ITEM*>>& aPadsPositionMap )
const
681 std::unordered_set<LENGTH_DELAY_CALCULATION_ITEM*> connectedLines;
685 auto exactMatch = aLinesPositionMap.find( viaPos );
687 if( exactMatch != aLinesPositionMap.end() )
688 connectedLines.insert( exactMatch->second.begin(), exactMatch->second.end() );
695 maxRadius = std::max( maxRadius, pcbVia->
GetWidth( layer ) / 2 );
698 const int64_t maxRadiusSq =
static_cast<int64_t
>( maxRadius ) * maxRadius;
700 for(
const auto& [pos, lineSet] : aLinesPositionMap )
705 if( ( pos - viaPos ).SquaredEuclideanNorm() > maxRadiusSq )
713 if( shape && shape->Collide( pos, 0 ) )
714 connectedLines.insert( lineItem );
718 const PAD* coincidentPad =
nullptr;
720 for(
PAD*
pad :
m_board->GetConnectivity()->GetConnectedPads( pcbVia ) )
729 spanLayers.
set( lineItem->GetStartLayer() );
744 spanLayers.
set( padSideLayer );
747 wxLogTrace( wxT(
"PNS_TUNE" ),
748 wxT(
"optimiseVias: via@(%d,%d) connectedLines=%zu coincidentPad=%d "
749 "spanLayerCount=%d" ),
750 viaPos.
x, viaPos.
y, connectedLines.size(), coincidentPad ? 1 : 0,
751 static_cast<int>( spanLayers.count() ) );
755 if( cuStack.empty() )
760 else if( cuStack.size() == 1 )
763 via->SetLayers( cuStack.front(), cuStack.front() );
768 via->SetLayers( cuStack.front(), cuStack.back() );
786 if( shape->Contains( aLine.
CPoint( 0 ) ) )
788 else if( shape->Contains( aLine.
CLastPoint() ) )
798 const int start = aForward ? 0 : aLine.
PointCount() - 1;
799 const int delta = aForward ? 1 : -1;
812 int firstOutside = -1;
814 bool hasIntersection =
false;
816 for(
int vertex = start +
delta; aForward ? vertex < aLine.
PointCount() : vertex >= 0; vertex +=
delta )
818 if( !viaShape->Collide( aLine.
GetPoint( vertex ), 0 ) )
820 firstOutside = vertex;
821 int prevVertex = vertex -
delta;
827 std::vector<VECTOR2I> pts =
circle.Intersect( seg );
833 intersectionPt = pts[0];
835 for(
size_t i = 1; i < pts.size(); i++ )
837 if( ( pts[i] - outside ).SquaredEuclideanNorm()
838 < ( intersectionPt - outside ).SquaredEuclideanNorm() )
840 intersectionPt = pts[i];
844 hasIntersection =
true;
851 if( firstOutside < 0 )
861 if( hasIntersection )
862 newChain.
Append( intersectionPt );
864 newChain.
Append( aLine.
Slice( firstOutside, -1 ) );
871 if( hasIntersection )
872 newChain.
Append( intersectionPt );
888 if( viaShape->Collide( aLine.
CPoint( 0 ), 0 ) )
890 else if( viaShape->Collide( aLine.
CLastPoint(), 0 ) )
898 return shape && shape->Collide( aPoint, 0 );
936 std::vector<VECTOR2I> points{ track->GetStart(), track->GetEnd() };
947 else if(
const PAD*
pad =
dynamic_cast<const PAD*
>( aBoardItem ) )
952 const LSET& layers =
pad->Padstack().LayerSet();
964 item.
SetLayers( firstLayer, secondLayer );
975 std::unique_ptr<TUNING_PROFILE_PARAMETERS_IFACE>&& aProvider )
BASE_SET & set(size_t pos)
A base class derived from BOARD_ITEM for items that can be connected and have a net,...
virtual NETCLASS * GetEffectiveNetClass() const
Return the NETCLASS for this item.
FOOTPRINT * GetParentFootprint() const
Manage layers needed to make a physical board.
void BuildDefaultStackupList(const BOARD_DESIGN_SETTINGS *aSettings, int aActiveCopperLayersCount=0)
Create a default stackup, according to the current BOARD_DESIGN_SETTINGS settings.
int GetLayerDistance(PCB_LAYER_ID aFirstLayer, PCB_LAYER_ID aSecondLayer) const
Calculate the distance (height) between the two given copper layers.
Represent basic circle geometry with utility geometry functions.
Lightweight class which holds a pad, via, or a routed trace outline.
MERGE_STATUS GetMergeStatus() const
Gets the MERGE_STATUS of this item.
void SetLine(const SHAPE_LINE_CHAIN &aLine)
Sets the source SHAPE_LINE_CHAIN of this item.
void SetVia(const PCB_VIA *aVia)
Sets the VIA associated with this item.
TYPE Type() const
Gets the routing item type.
std::tuple< PCB_LAYER_ID, PCB_LAYER_ID > GetLayers() const
Gets the upper and lower layers for the proxied item.
void SetPad(const PAD *aPad)
Sets the parent PAD associated with this item.
void SetMergeStatus(const MERGE_STATUS aStatus)
Sets the MERGE_STATUS of this item.
const NETCLASS * GetEffectiveNetClass() const
Returns the effective net class for the item.
SHAPE_LINE_CHAIN & GetLine() const
Gets the SHAPE_LINE_CHAIN associated with this item.
const PAD * GetPad() const
Gets the parent PAD associated with this item.
PCB_LAYER_ID GetStartLayer() const
Gets the start board layer for the proxied item.
void SetEffectiveNetClass(const NETCLASS *aNetClass)
Sets the effective net class for the item.
void CalculateViaLayers(const BOARD *aBoard)
Calculates active via payers for a proxied VIA object.
void SetLayers(const PCB_LAYER_ID aStart, const PCB_LAYER_ID aEnd=PCB_LAYER_ID::UNDEFINED_LAYER)
Sets the first and last layers associated with this item.
std::unique_ptr< TUNING_PROFILE_PARAMETERS_IFACE > m_tuningProfileParameters
The active provider of tuning profile parameters.
int64_t CalculateLengthForDelay(int64_t aDesiredDelay, const TUNING_PROFILE_GEOMETRY_CONTEXT &aCtx) const
Calculates the length of track required for the given delay in a specific geometry context.
void inferViaInPad(const PAD *aPad, const LENGTH_DELAY_CALCULATION_ITEM &aItem, LENGTH_DELAY_STATS &aDetails, std::pair< int64_t, int64_t > &aInferredViaLengthDelay, bool aWithDelayDetail) const
Infers if there is a via in the given pad.
int64_t CalculatePropagationDelayForShapeLineChain(const SHAPE_LINE_CHAIN &aShape, const TUNING_PROFILE_GEOMETRY_CONTEXT &aCtx) const
Gets the propagation delay for the given shape line chain.
static void clipLineToPad(SHAPE_LINE_CHAIN &aLine, const PAD *aPad, PCB_LAYER_ID aLayer, bool aForward=true)
Clips the given line to the minimal direct electrical length within the pad.
MERGE_POINT
Enum to describe whether track merging is attempted from the start or end of a track segment.
static void optimiseTracesInPads(const std::vector< LENGTH_DELAY_CALCULATION_ITEM * > &aPads, const std::vector< LENGTH_DELAY_CALCULATION_ITEM * > &aLines)
Optimises the given set of items to minimise the electrical path length.
static void mergeLines(std::vector< LENGTH_DELAY_CALCULATION_ITEM * > &aLines, std::map< VECTOR2I, std::unordered_set< LENGTH_DELAY_CALCULATION_ITEM * > > &aLinesPositionMap)
Merges any lines (traces) that are contiguous, on one layer, and with no junctions.
int64_t CalculateDelay(std::vector< LENGTH_DELAY_CALCULATION_ITEM > &aItems, PATH_OPTIMISATIONS aOptimisations, const PAD *aStartPad=nullptr, const PAD *aEndPad=nullptr) const
Calculates the electrical propagation delay of the given items.
int64_t CalculateLength(std::vector< LENGTH_DELAY_CALCULATION_ITEM > &aItems, PATH_OPTIMISATIONS aOptimisations, const PAD *aStartPad=nullptr, const PAD *aEndPad=nullptr) const
Calculates the electrical length of the given items.
int StackupHeight(PCB_LAYER_ID aFirstLayer, PCB_LAYER_ID aSecondLayer) const
Returns the stackup distance between the two given layers.
void SynchronizeTuningProfileProperties() const
Ensure time domain properties provider is synced with board / project settings if required.
LENGTH_DELAY_STATS CalculateLengthDetails(std::vector< LENGTH_DELAY_CALCULATION_ITEM > &aItems, PATH_OPTIMISATIONS aOptimisations, const PAD *aStartPad=nullptr, const PAD *aEndPad=nullptr, LENGTH_DELAY_LAYER_OPT aLayerOpt=LENGTH_DELAY_LAYER_OPT::NO_LAYER_DETAIL, LENGTH_DELAY_DOMAIN_OPT aDomain=LENGTH_DELAY_DOMAIN_OPT::NO_DELAY_DETAIL, LENGTH_DELAY_ITEM_DETAILS *aPerItemLengthDelays=nullptr) const
Calculates the electrical length of the given items.
static void OptimiseTraceInVia(SHAPE_LINE_CHAIN &aLine, const PCB_VIA *aVia, PCB_LAYER_ID aLayer)
Clips trace portions inside a VIA pad and replaces them with a straight-line segment from the VIA edg...
static void clipLineToVia(SHAPE_LINE_CHAIN &aLine, const PCB_VIA *aVia, PCB_LAYER_ID aLayer, bool aForward)
Clips the given line to the minimal direct electrical length within the via.
BOARD * m_board
The parent board for all items.
LENGTH_DELAY_CALCULATION_ITEM GetLengthCalculationItem(const BOARD_CONNECTED_ITEM *aBoardItem) const
Return a LENGTH_CALCULATION_ITEM constructed from the given BOARD_CONNECTED_ITEM.
void SetTuningProfileParametersProvider(std::unique_ptr< TUNING_PROFILE_PARAMETERS_IFACE > &&aProvider)
Sets the provider for tuning profile parameter resolution.
static void mergeShapeLineChains(SHAPE_LINE_CHAIN &aPrimary, const SHAPE_LINE_CHAIN &aSecondary, MERGE_POINT aMergePoint)
Merges two SHAPE_LINE_CHAINs where there is a shared endpoing.
static bool findArcPadIntersection(const SHAPE_ARC &aArc, const std::shared_ptr< SHAPE_POLY_SET > &aPadShape, const VECTOR2I &aInsidePoint, VECTOR2I &aIntersection)
Finds the intersection point between an arc and a pad shape.
void optimiseVias(const std::vector< LENGTH_DELAY_CALCULATION_ITEM * > &aVias, std::vector< LENGTH_DELAY_CALCULATION_ITEM * > &aLines, std::map< VECTOR2I, std::unordered_set< LENGTH_DELAY_CALCULATION_ITEM * > > &aLinesPositionMap, const std::map< VECTOR2I, std::unordered_set< LENGTH_DELAY_CALCULATION_ITEM * > > &aPadsPositionMap) const
Optimises the via layers.
static bool IsPointInsideViaPad(const PCB_VIA *aVia, const VECTOR2I &aPoint, PCB_LAYER_ID aLayer)
Returns true if the given point falls inside VIA pad shape on the given layer.
static void OptimiseTraceInPad(SHAPE_LINE_CHAIN &aLine, const PAD *aPad, PCB_LAYER_ID aPcbLayer)
Optimises the given trace / line to minimise the electrical path length within the given pad.
LSEQ is a sequence (and therefore also a set) of PCB_LAYER_IDs.
LSET is a set of PCB_LAYER_IDs.
copper_layers_iterator copper_layers_end() const
LSEQ CuStack() const
Return a sequence of copper layers in starting from the front/top and extending to the back/bottom.
copper_layers_iterator copper_layers_begin() const
bool Contains(PCB_LAYER_ID aLayer) const
See if the layer set contains a PCB layer.
void ForEachUniqueLayer(const std::function< void(PCB_LAYER_ID)> &aMethod) const
Runs the given callable for each active unique copper layer in this padstack, meaning F_Cu for MODE::...
const LSET & LayerSet() const
bool FlashLayer(int aLayer, bool aOnlyCheckIfPermitted=false) const
Check to see whether the pad should be flashed on the specific layer.
PAD_ATTRIB GetAttribute() const
VECTOR2I GetPosition() const override
const PADSTACK & Padstack() const
const std::shared_ptr< SHAPE_POLY_SET > & GetEffectivePolygon(PCB_LAYER_ID aLayer, ERROR_LOC aErrorLoc=ERROR_INSIDE) const
int GetPadToDieLength() const
const VECTOR2I & GetMid() const
const VECTOR2I & GetStart() const
const VECTOR2I & GetEnd() const
virtual int GetWidth() const
VECTOR2I GetPosition() const override
std::shared_ptr< SHAPE > GetEffectiveShape(PCB_LAYER_ID aLayer=UNDEFINED_LAYER, FLASHING aFlash=FLASHING::DEFAULT) const override
Some pad shapes can be complex (rounded/chamfered rectangle), even without considering custom shapes.
const PADSTACK & Padstack() const
PCB_LAYER_ID GetLayer() const override
Return the primary layer this item is on.
int GetWidth() const override
bool Contains(const SEG &aSeg) const
int IntersectLine(const SEG &aSeg, std::vector< VECTOR2I > *aIpsBuffer) const
Find intersection points between this arc and aSeg, treating aSeg as an infinite line.
const VECTOR2I GetCenter() const
Represent a polyline containing arcs as well as line segments: A chain of connected line and/or arc s...
const SHAPE_ARC & Arc(size_t aArc) const
virtual const VECTOR2I GetPoint(int aIndex) const override
int PointCount() const
Return the number of points (vertices) in this line chain.
ssize_t ArcIndex(size_t aSegment) const
Return the arc index for the given segment index.
const std::vector< SHAPE_ARC > & CArcs() const
void Append(int aX, int aY, bool aAllowDuplication=false)
Append a new point at the end of the line chain.
const VECTOR2I & CPoint(int aIndex) const
Return a reference to a given point in the line chain.
const SHAPE_LINE_CHAIN Slice(int aStartIndex, int aEndIndex) const
Return a subset of this line chain containing the [start_index, end_index] range of points.
int SegmentCount() const
Return the number of segments in this line chain.
const VECTOR2I & CLastPoint() const
Return the last point in the line chain.
const SEG CSegment(int aIndex) const
Return a constant copy of the aIndex segment in the line chain.
void Insert(size_t aVertex, const VECTOR2I &aP)
long long int Length() const
Return length of the line chain in Euclidean metric.
const std::vector< VECTOR2I > & CPoints() const
a few functions useful in geometry calculations.
@ ALWAYS_FLASHED
Always flashed for connectivity.
PCB_LAYER_ID
A quick note on layer IDs:
LENGTH_DELAY_DOMAIN_OPT
Enum which controls the calculation domain of the length / delay calculation methods.
LENGTH_DELAY_LAYER_OPT
Enum which controls the level of detail returned by the length / delay calculation methods.
@ SMD
Smd pad, appears on the solder paste layer (default)
@ CONN
Like smd, does not appear on the solder paste layer (default) Note: also has a special attribute in G...
Used to represent the results of a call to CalculateLengthDetails, including inferred via-in-pad deta...
int64_t InferredEndViaLength
The length of an inferred end via-in-pad.
int64_t InferredStartViaLength
The length of an inferred start via-in-pad.
int64_t InferredEndViaDelay
The delay of an inferred end via-in-pad.
std::vector< std::pair< int64_t, int64_t > > LengthsAndDelays
Per-item lengths and delays.
int64_t InferredStartViaDelay
The delay of an inferred start via-in-pad.
Holds length measurement result details and statistics.
std::unique_ptr< std::map< PCB_LAYER_ID, int64_t > > LayerDelays
int64_t TotalLength() const
Calculates the total electrical length for this set of statistics.
std::unique_ptr< std::map< PCB_LAYER_ID, int64_t > > LayerLengths
int64_t TotalDelay() const
Calculates the total electrical propagation delay for this set of statistics.
Struct to control which optimisations the length calculation code runs on the given path objects.
bool InferViaInPad
Determines if there is a via-in-pad present on the board but not in the item set.
bool OptimiseVias
Optimise vias for electrical length calculations, including effective via span and trace clipping ins...
bool MergeTracks
Merges all contiguous (end-to-end, same layer) tracks.
bool OptimiseTracesInPads
Optimises the electrical length of tracks within pads.
A data structure to contain basic geometry data which can affect signal propagation calculations.
const NETCLASS * NetClass
The net class this track belongs to.
SHAPE_CIRCLE circle(c.m_circle_center, c.m_circle_radius)
@ PCB_VIA_T
class PCB_VIA, a via (like a track segment on a copper layer)
@ PCB_ARC_T
class PCB_ARC, an arc track segment on a copper layer
@ PCB_TRACE_T
class PCB_TRACK, a track segment (segment on a copper layer)
VECTOR2< int32_t > VECTOR2I