KiCad PCB EDA Suite
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pcb_io_solidworks.cpp
Go to the documentation of this file.
1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright The KiCad Developers, see AUTHORS.txt for contributors.
5 *
6 * This program is free software: you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation, either version 3 of the License, or (at your
9 * option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <https://www.gnu.org/licenses/>.
18 */
19
20#include <wx/string.h>
21
22#include <font/fontconfig.h>
23#include <pcb_io_solidworks.h>
25#include <altium_pcb.h>
26#include <pcb_io/pcb_io.h>
27#include <reporter.h>
28
34
35
39
40
41bool PCB_IO_SOLIDWORKS::CanReadBoard( const wxString& aFileName ) const
42{
43 if( !PCB_IO::CanReadBoard( aFileName ) )
44 return false;
45
47}
48
49
50void PCB_IO_SOLIDWORKS::loadBoard( const wxString& aFileName, BOARD& aBoard, bool aIsNewLoad,
51 const std::map<std::string, UTF8>* aProperties, PROJECT* aProject )
52{
53 m_props = aProperties;
54 m_board = &aBoard;
55
56 // Collect the font substitution warnings (RAII - automatically reset on scope exit)
58
59 // clang-format off
60 const std::map<ALTIUM_PCB_DIR, std::string> mapping = {
61 { ALTIUM_PCB_DIR::FILE_HEADER, "FileHeader" },
62 { ALTIUM_PCB_DIR::ARCS6, "D2864697BB2D411B857EBD69D74447" },
63 { ALTIUM_PCB_DIR::BOARD6, "21CE7E3D9BFF41679BACA1184CAF54" },
64 { ALTIUM_PCB_DIR::BOARDREGIONS, "67075A4119214CE4AB174F9B1A9A41" },
65 { ALTIUM_PCB_DIR::CLASSES6, "1122D4F14A924F9CA5C2060AF370E0" },
66 { ALTIUM_PCB_DIR::COMPONENTS6, "208CAE8E44BD43D5B3CCA426D9331B" },
67 { ALTIUM_PCB_DIR::COMPONENTBODIES6, "6DDF94E6CB364893BED31C189F9AF3" },
68 { ALTIUM_PCB_DIR::DIMENSIONS6, "6148AE8C77B042798B46830E96BB24" },
69 { ALTIUM_PCB_DIR::FILLS6, "5944DE0E258C41E2B0B382AC964048" },
70 { ALTIUM_PCB_DIR::MODELS, "874F98A7E25A48EDAD394EB891E503" },
71 { ALTIUM_PCB_DIR::NETS6, "0201837ACD434D55B34BBC68B75BAB" },
72 { ALTIUM_PCB_DIR::PADS6, "E4D0C33E25824886ABC7FEEAE7B521" },
73 { ALTIUM_PCB_DIR::POLYGONS6, "7ABD4252549749DD8DB16804819AC3" },
74 { ALTIUM_PCB_DIR::REGIONS6, "6B3892541AB94CD999291D590B5C86" }, // probably wrong; in as a placeholder
75 { ALTIUM_PCB_DIR::RULES6, "7009830ADF65423FA6CCB73A77E710" },
76 { ALTIUM_PCB_DIR::SHAPEBASEDREGIONS6, "91241C66300E4490965070BA56F6F7" },
77 { ALTIUM_PCB_DIR::TEXTS6, "4AF3D139533041489C2A57BBF9890D" },
78 { ALTIUM_PCB_DIR::TRACKS6, "5D0C6E18E16A4BBFAA256C24B79EAE" },
79 { ALTIUM_PCB_DIR::VIAS6, "2AF5387F097242D3A1095B6FAC3397" },
80 { ALTIUM_PCB_DIR::WIDESTRINGS6, "9B378679AF85466C8673A41EE46393" }
81
82 /*
83 * Understood but not needed:
84 * 04A8F96E0E4C478C813AE57CACCD0F - Legacy text storage
85 * 01F1BD1AA06E4D6A9D1ABF0BBFF4A4 - Fwd/Back compatibility messages
86 *
87 * Not yet used by KiCad:
88 * 7C01505E39124E67BCCAB1883B8FB7 - Design Rule Checker Options6
89 * 63B31A3709B54882BFA96424906BE8 - EmbeddedFonts6
90 * 8B83C7E94C1D419B9B2D5505479820 - Pin Swap Options6
91 * F78C10230A794F5C93ACB50AC693B2 - Advanced Placer Options6
92 *
93 * No data yet on:
94 * 1C0DB1ED572645BEB65D029D20406C
95 * 2AA5C1C72BF14315A47DD931B84A79
96 * 6468C28D32CC4867AB374091CC8431
97 * 6B3892541AB94CD999291D590B5C86
98 * 8675F4105E444E6D9B2BEE6273769D
99 * B983FCC2B6DE46E0B94006B6393235
100 * D6551D22B6DB44659C3F32F7E1949D
101 *
102 * Not yet identified:
103 * D06DD2E4A51C4A3EA96D9ED8C8F3F3
104 * F9C465994DE840579ED19E820C19C2
105 *
106 * Region-like objects that don't map cleanly (maybe Solidworks sketches?)
107 * 84958494F3F54075975C4E199DB8EB
108 * 2E731D36D1F049428744F0661F3E44
109 */
110 };
111 // clang-format on
112
113 LoadAltiumBoard( aFileName, m_board, mapping, m_props, aProject,
115}
Information pertinent to a Pcbnew printed circuit board.
Definition board.h:410
RAII class to set and restore the fontconfig reporter.
Definition reporter.h:385
REPORTER * m_reporter
Reporter to log errors/warnings to, may be nullptr.
Definition io_base.h:238
PROGRESS_REPORTER * m_progressReporter
Progress reporter to track the progress of the operation, may be nullptr.
Definition io_base.h:241
virtual void RegisterCallback(LAYER_MAPPING_HANDLER aLayerMappingHandler)
Register a different handler to be called when mapping of input layers to KiCad layers occurs.
LAYER_MAPPING_HANDLER m_layer_mapping_handler
Callback to get layer mapping.
static LOAD_INFO_REPORTER & GetInstance()
Definition reporter.cpp:351
static bool checkFileHeader(const wxString &aFileName)
static std::map< wxString, PCB_LAYER_ID > DefaultLayerMappingCallback(const std::vector< INPUT_LAYER_DESC > &aInputLayerDescriptionVector)
Return the automapped layers.
void loadBoard(const wxString &aFileName, BOARD &aBoard, bool aIsNewLoad, const std::map< std::string, UTF8 > *aProperties, PROJECT *aProject=nullptr) override
Parse aFileName into aBoard.
bool CanReadBoard(const wxString &aFileName) const override
BOARD * m_board
The board BOARD being worked on, no ownership here.
Definition pcb_io.h:393
virtual bool CanReadBoard(const wxString &aFileName) const
Definition pcb_io.cpp:40
PCB_IO(const wxString &aName)
Definition pcb_io.h:372
const std::map< std::string, UTF8 > * m_props
Properties passed via Save() or Load(), no ownership, may be NULL.
Definition pcb_io.h:396
Container for project specific data.
Definition project.h:63
void LoadAltiumBoard(const wxString &aFileName, BOARD *aBoard, const std::map< ALTIUM_PCB_DIR, std::string > &aMapping, const std::map< std::string, UTF8 > *aProperties, PROJECT *aProject, PROGRESS_REPORTER *aProgressReporter, LAYER_MAPPING_HANDLER &aLayerMappingHandler, REPORTER *aReporter)