KiCad PCB EDA Suite
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test_issue18119_bus_hierarchy.cpp
Go to the documentation of this file.
1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright The KiCad Developers, see AUTHORS.TXT for contributors.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 3
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, you may find one here:
18 * https://www.gnu.org/licenses/gpl-3.0.en.html
19 * or you may search the http://www.gnu.org website for the version 32 license,
20 * or you may write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
22 */
23
45
48
49#include <connection_graph.h>
50#include <schematic.h>
51#include <sch_sheet.h>
52#include <sch_screen.h>
53#include <sch_symbol.h>
54#include <sch_pin.h>
56#include <locale_io.h>
57
59{
62
64 std::unique_ptr<SCHEMATIC> m_schematic;
65};
66
67
81{
83
84 KI_TEST::LoadSchematic( m_settingsManager, "issue18119/issue18119", m_schematic );
85
86 SCH_SHEET_LIST sheets = m_schematic->BuildSheetListSortedByPageNumbers();
87 CONNECTION_GRAPH* graph = m_schematic->ConnectionGraph();
88
89 // Find connectors and power symbols and their net codes
90 std::map<wxString, int> connectorNetCodes; // Reference -> net code
91 std::map<wxString, int> resistorPinNetCodes; // R1.1, R1.2 -> net code
92
93 for( const auto& [key, subgraphs] : graph->GetNetMap() )
94 {
95 for( CONNECTION_SUBGRAPH* subgraph : subgraphs )
96 {
97 for( SCH_ITEM* item : subgraph->GetItems() )
98 {
99 if( item->Type() == SCH_PIN_T )
100 {
101 SCH_PIN* pin = static_cast<SCH_PIN*>( item );
102 SCH_SYMBOL* symbol = dynamic_cast<SCH_SYMBOL*>( pin->GetParentSymbol() );
103
104 if( symbol )
105 {
106 wxString ref = symbol->GetRef( &subgraph->GetSheet() );
107
108 // Track connectors J1-J4 and power symbols
109 if( ref == "J1" || ref == "J2" || ref == "J3" || ref == "J4" ||
110 ref == "#PWR01" || ref == "#PWR02" || ref == "#PWR03" || ref == "#PWR04" )
111 {
112 connectorNetCodes[ref] = key.Netcode;
113 }
114
115 // Track R1 pins
116 if( ref == "R1" )
117 {
118 wxString pinKey = ref + "." + pin->GetNumber();
119 resistorPinNetCodes[pinKey] = key.Netcode;
120 }
121 }
122 }
123 }
124 }
125 }
126
127 // Verify we found all expected components
128 BOOST_REQUIRE_MESSAGE( connectorNetCodes.count( "J1" ), "J1 (VCC connector) should be found" );
129 BOOST_REQUIRE_MESSAGE( connectorNetCodes.count( "J2" ), "J2 (GND connector) should be found" );
130 BOOST_REQUIRE_MESSAGE( connectorNetCodes.count( "J3" ), "J3 (BUS0) should be found" );
131 BOOST_REQUIRE_MESSAGE( connectorNetCodes.count( "J4" ), "J4 (BUS1) should be found" );
132 BOOST_REQUIRE_MESSAGE( connectorNetCodes.count( "#PWR02" ), "GND power symbol should be found" );
133
134 // J1 should be on VCC net (through direct wire connection)
135 BOOST_REQUIRE_MESSAGE( connectorNetCodes.count( "#PWR01" ), "VCC power symbol should be found" );
136 BOOST_CHECK_MESSAGE( connectorNetCodes["J1"] == connectorNetCodes["#PWR01"],
137 "J1 should be on the same net as VCC" );
138
139 // J2 should be on GND net (through direct wire connection)
140 BOOST_CHECK_MESSAGE( connectorNetCodes["J2"] == connectorNetCodes["#PWR02"],
141 "J2 should be on the same net as GND" );
142
143 // J3 (BUS0) should be on the same net as R1 pin 1 (through OUT_0)
144 // Note: R1 separates the OUT_0 net from the VCC net, so J3 is NOT on VCC net
145 BOOST_REQUIRE_MESSAGE( resistorPinNetCodes.count( "R1.1" ), "R1 pin 1 should be found" );
146 BOOST_CHECK_MESSAGE( connectorNetCodes["J3"] == resistorPinNetCodes["R1.1"],
147 "J3 (BUS0) should be on the same net as R1.1 (via OUT_0)" );
148
149 // J4 (BUS1) should be on GND net (through OUT_1 -> GND)
150 // This tests that BUS1 properly connects through BUS[0..1] -> SUB_BUS[0..1] -> SUB_BUS1 -> OUT_1
151 // This is the main bug - BUS1 does not connect to GND
152 BOOST_CHECK_MESSAGE( connectorNetCodes["J4"] == connectorNetCodes["#PWR02"],
153 "J4 (BUS1) should be on the same net as GND (via OUT_1)" );
154}
Calculate the connectivity of a schematic and generates netlists.
const NET_MAP & GetNetMap() const
A subgraph is a set of items that are electrically connected on a single sheet.
Instantiate the current locale within a scope in which you are expecting exceptions to be thrown.
Definition locale_io.h:41
Base class for any item which can be embedded within the SCHEMATIC container class,...
Definition sch_item.h:167
A container for handling SCH_SHEET_PATH objects in a flattened hierarchy.
Schematic symbol object.
Definition sch_symbol.h:76
const wxString GetRef(const SCH_SHEET_PATH *aSheet, bool aIncludeUnit=false) const override
void LoadSchematic(SETTINGS_MANAGER &aSettingsManager, const wxString &aRelPath, std::unique_ptr< SCHEMATIC > &aSchematic)
std::vector< FAB_LAYER_COLOR > dummy
std::unique_ptr< SCHEMATIC > m_schematic
BOOST_FIXTURE_TEST_CASE(Issue18119BusHierarchy, ISSUE18119_FIXTURE)
Test that bus member connections propagate correctly through hierarchy when wire names differ on each...
KIBIS_PIN * pin
@ SCH_PIN_T
Definition typeinfo.h:157