test_issue18119_bus_hierarchy.cpp File Reference

Test for issue #18119: Bus net connections not propagating correctly through hierarchy when bus member wire names differ from parent bus wire names. More...

#include <qa_utils/wx_utils/unit_test_utils.h>
#include <schematic_utils/schematic_file_util.h>
#include <connection_graph.h>
#include <schematic.h>
#include <sch_sheet.h>
#include <sch_screen.h>
#include <sch_symbol.h>
#include <sch_pin.h>
#include <settings/settings_manager.h>
#include <locale_io.h>

Go to the source code of this file.

Classes
struct	ISSUE18119_FIXTURE

Functions
	BOOST_FIXTURE_TEST_CASE (Issue18119BusHierarchy, ISSUE18119_FIXTURE)
	Test that bus member connections propagate correctly through hierarchy when wire names differ on each side of the hierarchy.

Detailed Description

Test for issue #18119: Bus net connections not propagating correctly through hierarchy when bus member wire names differ from parent bus wire names.

The schematic has:

• Main sheet with BUS0, BUS1 labels connected via bus entries to bus BUS[0..1]
• Bus BUS[0..1] connected to sheet pin SUB_BUS[0..1]
• Sub sheet with hierarchical label SUB_BUS[0..1] broken out to SUB_BUS0 and SUB_BUS1
• SUB_BUS0 connected to hierarchical label OUT_0
• SUB_BUS1 connected to hierarchical label OUT_1
• On main sheet: OUT_0 -> R1 -> VCC, OUT_1 -> GND

Expected: BUS0 should be connected to VCC (through OUT_0), BUS1 should be connected to GND (through OUT_1).

The bug: BUS1 does not connect to GND because the net name propagation through the bus hierarchy doesn't work correctly when wire names (BUS0/BUS1) differ from bus member names (SUB_BUS0/SUB_BUS1).

Definition in file test_issue18119_bus_hierarchy.cpp.

Function Documentation

BOOST_FIXTURE_TEST_CASE()

BOOST_FIXTURE_TEST_CASE	(	Issue18119BusHierarchy	,
		ISSUE18119_FIXTURE	)

Test that bus member connections propagate correctly through hierarchy when wire names differ on each side of the hierarchy.

Expected connectivity:

• J4 (BUS1) should be on the same net as GND (via OUT_1) - this is the main bug
• J3 (BUS0) should be on the same net as R1.1 (via OUT_0) - different net from VCC due to R1

Note: R1 is between OUT_0 and VCC, creating two separate nets:

• Net 1: OUT_0 side (includes J3/BUS0/SUB_BUS0/OUT_0/R1.1)
• Net 2: VCC side (includes R1.2/VCC)

Definition at line 80 of file test_issue18119_bus_hierarchy.cpp.

References dummy, CONNECTION_GRAPH::GetNetMap(), SCH_SYMBOL::GetRef(), KI_TEST::LoadSchematic(), pin, and SCH_PIN_T.