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KiCad PCB EDA Suite
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#include <qa_utils/wx_utils/unit_test_utils.h>#include <schematic_utils/schematic_file_util.h>#include <connection_graph.h>#include <schematic.h>#include <sch_sheet.h>#include <sch_screen.h>#include <sch_symbol.h>#include <sch_pin.h>#include <settings/settings_manager.h>#include <locale_io.h>Go to the source code of this file.
Classes | |
| struct | CONNECTIVITY_TEST_FIXTURE |
Functions | |
| BOOST_FIXTURE_TEST_CASE (CheckNetCounts, CONNECTIVITY_TEST_FIXTURE) | |
| BOOST_FIXTURE_TEST_CASE (Issue17771, CONNECTIVITY_TEST_FIXTURE) | |
| Test for issue #17771: Bus implicit connection not working across hierarchy. | |
| BOOST_FIXTURE_TEST_CASE | ( | CheckNetCounts | , |
| CONNECTIVITY_TEST_FIXTURE | ) |
Definition at line 46 of file test_connectivity_algo.cpp.
References dummy, CONNECTION_GRAPH::GetNetMap(), KI_TEST::LoadSchematic(), and name.
| BOOST_FIXTURE_TEST_CASE | ( | Issue17771 | , |
| CONNECTIVITY_TEST_FIXTURE | ) |
Test for issue #17771: Bus implicit connection not working across hierarchy.
The schematic has a hierarchy where bus members should connect through implicit bus connections. The bug was that V.Z1 connects through to the root but V.Z2 does not, because the intermediate net W.X.Y.Z1 is explicitly labeled on the "sub" sheet while W.X.Y.Z2 relies on implicit bus member expansion.
Expected: Both nets should connect properly:
Definition at line 79 of file test_connectivity_algo.cpp.
References dummy, CONNECTION_GRAPH::GetNetMap(), SCH_SYMBOL::GetRef(), KI_TEST::LoadSchematic(), pin, and SCH_PIN_T.