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KiCad PCB EDA Suite
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#include <qa_utils/wx_utils/unit_test_utils.h>#include <schematic_utils/schematic_file_util.h>#include <connection_graph.h>#include <schematic.h>#include <sch_pin.h>#include <sch_screen.h>#include <sch_sheet.h>#include <sch_symbol.h>#include <settings/settings_manager.h>#include <locale_io.h>Go to the source code of this file.
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| struct | ISSUE_23719_FIXTURE |
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| BOOST_FIXTURE_TEST_CASE (Issue23719, ISSUE_23719_FIXTURE) | |
| Test for issue #23719 – global labels not combining nets across more than two sheets. | |
| BOOST_FIXTURE_TEST_CASE | ( | Issue23719 | , |
| ISSUE_23719_FIXTURE | ) |
Test for issue #23719 – global labels not combining nets across more than two sheets.
Schematic structure (3 sub-sheets, all globals).
Sheet 1 – Connector J1 with two of its pins driven by two different global labels. one pin -> "P5V_IF_Rtn_Sense" one pin -> "P5V_IF_Rtn"
Sheet 2 – TestPoint TP1 with two wires meeting at a junction; the junction is connected to both of these global labels. "P5V_IF_Rtn_Sense" "P5V_IF_Rtn"
Sheet 3 – A single wire connecting two global labels. "P5V_IF_Rtn" "P4"
Through transitivity, all four global names refer to the same logical net.
P5V_IF_Rtn_Sense <-- shared via Sheet 2 --> P5V_IF_Rtn P5V_IF_Rtn <-- shared via Sheet 3 --> P4
Therefore both wired J1 pins and TP1's pin must all end up on the same net.
The bug. When one of the multi-driver subgraphs (Sheet 3) gets an alphabetically-lower primary name (here "P4"), the cross-sheet promotion pass walked candidates by their original driver text instead of by their already-promoted name. As a result, the J1 "P5V_IF_Rtn_Sense" subgraph, which had been promoted to "P5V_IF_Rtn" by Sheet 2, was never re-promoted to "P4" by Sheet 3 and ended up isolated on a stale net name.
Definition at line 80 of file test_issue23719_global_label_chain.cpp.
References BOOST_CHECK_MESSAGE(), dummy, CONNECTION_GRAPH::GetNetMap(), SCH_SYMBOL::GetRef(), KI_TEST::LoadSchematic(), name, pin, and SCH_PIN_T.