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KiCad PCB EDA Suite
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Creepage DRC test with HV/GND netclass constraints. More...
#include <qa_utils/file_utils.h>#include <qa_utils/wx_utils/unit_test_utils.h>#include <pcbnew_utils/board_test_utils.h>#include <board.h>#include <board_design_settings.h>#include <drc/drc_item.h>#include <drc/drc_engine.h>#include <settings/settings_manager.h>#include <widgets/report_severity.h>#include <base_units.h>#include <netinfo.h>#include <pcb_shape.h>#include <pcb_track.h>#include <zone.h>#include <filesystem>#include <fstream>Go to the source code of this file.
Classes | |
| struct | DRC_CREEPAGE_TEST_FIXTURE |
Functions | |
| BOOST_FIXTURE_TEST_CASE (CreepageHVvsGND, DRC_CREEPAGE_TEST_FIXTURE) | |
| BOOST_FIXTURE_TEST_CASE (CreepageMalformedEdge, DRC_CREEPAGE_TEST_FIXTURE) | |
| Regression test for https://gitlab.com/kicad/code/kicad/-/issues/23653. | |
| BOOST_FIXTURE_TEST_CASE (CreepageIgnoresRuleAreas, DRC_CREEPAGE_TEST_FIXTURE) | |
| Regression test for https://gitlab.com/kicad/code/kicad/-/issues/25165. | |
Creepage DRC test with HV/GND netclass constraints.
The board has an HV trace running near a GND trace. The custom rule requires 8mm creepage between HV and GND netclasses, but the actual surface distance is ~3.25mm.
Definition in file test_drc_creepage.cpp.
| BOOST_FIXTURE_TEST_CASE | ( | CreepageHVvsGND | , |
| DRC_CREEPAGE_TEST_FIXTURE | ) |
Definition at line 69 of file test_drc_creepage.cpp.
References BOOST_TEST_MESSAGE(), DRC_ENGINE::ClearViolationHandler(), DRCE_CREEPAGE, DRCE_FIRST, DRCE_LAST, BOARD_DESIGN_SETTINGS::GetSeverity(), KI_TEST::LoadBoard(), BOARD_DESIGN_SETTINGS::m_DRCEngine, BOARD_DESIGN_SETTINGS::m_DRCSeverities, MM, RPT_SEVERITY_ERROR, RPT_SEVERITY_IGNORE, DRC_ENGINE::RunTests(), and DRC_ENGINE::SetViolationHandler().
| BOOST_FIXTURE_TEST_CASE | ( | CreepageIgnoresRuleAreas | , |
| DRC_CREEPAGE_TEST_FIXTURE | ) |
Regression test for https://gitlab.com/kicad/code/kicad/-/issues/25165.
A rule area has no net, so it lands on netcode 0 and used to be collected as copper. The netless corner tracks give netcode 0 a bounding box wide enough to get past the early reject in testCreepage. They sit too far from the HV track to violate anything.
Definition at line 162 of file test_drc_creepage.cpp.
References ZONE::AppendCorner(), B_Cu, BOOST_TEST_MESSAGE(), DRC_ENGINE::ClearViolationHandler(), DRCE_CREEPAGE, DRCE_FIRST, DRCE_LAST, Edge_Cuts, F_Cu, ZONE::GetIsRuleArea(), DRC_ENGINE::InitEngine(), BOARD_DESIGN_SETTINGS::m_DRCEngine, BOARD_DESIGN_SETTINGS::m_DRCSeverities, MM, KI_TEST::SCOPED_TEMP_DIR::Path(), PCB_ZONE_T, pcbIUScale, RECTANGLE, RPT_SEVERITY_ERROR, RPT_SEVERITY_IGNORE, DRC_ENGINE::RunTests(), ZONE::SetDoNotAllowFootprints(), ZONE::SetDoNotAllowPads(), ZONE::SetDoNotAllowTracks(), ZONE::SetDoNotAllowVias(), ZONE::SetDoNotAllowZoneFills(), PCB_SHAPE::SetEnd(), PCB_TRACK::SetEnd(), ZONE::SetIsRuleArea(), BOARD_CONNECTED_ITEM::SetLayer(), PCB_SHAPE::SetLayer(), ZONE::SetLayerSet(), BOARD_CONNECTED_ITEM::SetNet(), PCB_SHAPE::SetStart(), PCB_TRACK::SetStart(), DRC_ENGINE::SetViolationHandler(), PCB_TRACK::SetWidth(), and EDA_ITEM::Type().
| BOOST_FIXTURE_TEST_CASE | ( | CreepageMalformedEdge | , |
| DRC_CREEPAGE_TEST_FIXTURE | ) |
Regression test for https://gitlab.com/kicad/code/kicad/-/issues/23653.
A board with an extra line on Edge.Cuts that prevents GetBoardPolygonOutlines from forming a valid polygon should still produce creepage violations. Previously the creepage test bailed out entirely when the outline was malformed.
Definition at line 115 of file test_drc_creepage.cpp.
References BOOST_TEST_MESSAGE(), DRC_ENGINE::ClearViolationHandler(), DRCE_CREEPAGE, DRCE_FIRST, DRCE_LAST, BOARD_DESIGN_SETTINGS::GetSeverity(), KI_TEST::LoadBoard(), BOARD_DESIGN_SETTINGS::m_DRCEngine, BOARD_DESIGN_SETTINGS::m_DRCSeverities, MM, RPT_SEVERITY_ERROR, RPT_SEVERITY_IGNORE, DRC_ENGINE::RunTests(), and DRC_ENGINE::SetViolationHandler().