38 std::set<wxString> names;
40 for(
const auto& [key, subgraphs] :
m_schematic.ConnectionGraph()->GetNetMap() )
42 if( !key.Name.IsEmpty() )
43 names.insert( key.Name );
46 return { names.begin(), names.end() };
53 std::set<wxString> names;
60 if(
const auto name = seed->GetConnectionName( &aSheet );
name && !
name->IsEmpty() )
61 names.insert( *
name );
64 std::unordered_set<SCH_ITEM*> items;
66 for(
const wxString&
name : names )
69 return { items.begin(), items.end() };
78 std::set<wxString> names;
82 const SCH_CONNECTION* connection = subgraph->GetDriverConnection();
87 if( connection->
IsNet() )
88 names.insert( connection->
Name() );
90 for(
const auto& member : connection->
AllMembers() )
92 if( member && member->IsNet() )
93 names.insert( member->Name() );
97 names.erase( wxString() );
98 return { names.begin(), names.end() };
103 bool aIncludeBusParents,
104 bool aIncludeBusMembers )
const
109 const auto& graph = *
m_schematic.ConnectionGraph();
110 std::set<const CONNECTION_SUBGRAPH*> subgraphs;
111 std::vector<const CONNECTION_SUBGRAPH*> pending;
112 auto add = [&](
const wxString&
name )
116 if( subgraph && subgraphs.insert( subgraph ).second )
117 pending.push_back( subgraph );
122 if( aIncludeBusMembers )
124 for(
const wxString& member :
SignalNames( aName ) )
128 if( aIncludeBusParents )
130 for(
const wxString&
equivalent : graph.GetEquivalentBusNames( aName ) )
133 for(
size_t i = 0; i < pending.size(); ++i )
135 for(
const auto& [member, parents] : pending[i]->GetBusParents() )
140 add( parent->GetNetName() );
146 std::erase_if( subgraphs,
164 std::set<KIID_PATH> sheets;
167 sheets.insert( subgraph->GetSheet().PathRef() );
174 bool aIncludeBusMembers )
const
180 auto& items =
result[subgraph->GetSheet()];
181 items.insert( items.end(), subgraph->GetItems().begin(), subgraph->GetItems().end() );
187 items.erase( std::unique( items.begin(), items.end() ), items.end() );
195 std::unordered_set<SCH_ITEM*>& aItems,
bool aIncludeBusParents,
196 bool aIncludeBusMembers )
const
200 if( subgraph->GetSheet() == aSheet )
201 aItems.insert( subgraph->GetItems().begin(), subgraph->GetItems().end() );
A subgraph is a set of items that are electrically connected on a single sheet.
const std::set< SCH_ITEM * > & GetItems() const
Provide a read-only reference to the items in the subgraph.
const SCH_SHEET_PATH & GetSheet() const
Holds all the data relating to one schematic.
Each graphical item can have a SCH_CONNECTION describing its logical connection (to a bus or net).
const std::vector< std::shared_ptr< SCH_CONNECTION > > AllMembers() const
wxString Name(bool aIgnoreSheet=false) const
void CollectNetItems(const wxString &aName, const SCH_SHEET_PATH &aSheet, std::unordered_set< SCH_ITEM * > &aItems, bool aIncludeBusParents=false, bool aIncludeBusMembers=false) const
Add the items of a net on one sheet to aItems without building other sheets.
bool HasNet(const wxString &aName) const
std::vector< wxString > SignalNames(const wxString &aName) const
Signal itself or leaf signals of a bus, suitable for PCB cross-probing.
std::set< const CONNECTION_SUBGRAPH * > netSubgraphs(const wxString &aName, bool aIncludeBusParents, bool aIncludeBusMembers) const
NET_ITEMS_BY_SHEET NetItems(const wxString &aName, bool aIncludeBusParents, bool aIncludeBusMembers=false) const
const SCHEMATIC & m_schematic
NAVIGATION_QUERY(const SCHEMATIC &aSchematic)
std::vector< SCH_ITEM * > WholeNetItems(const std::vector< SCH_ITEM * > &aSeeds, const SCH_SHEET_PATH &aSheet) const
Whole nets containing the seeds on this instance; excludes bus parents and members.
std::set< KIID_PATH > NetSheets(const wxString &aName) const
std::vector< wxString > NetNames() const
Base class for any item which can be embedded within the SCHEMATIC container class,...
Handle access to a stack of flattened SCH_SHEET objects by way of a path for creating a flattened sch...
SCH_SCREEN * LastScreen()
bool equivalent(SIM_MODEL::DEVICE_T a, SIM_MODEL::DEVICE_T b)
std::map< SCH_SHEET_PATH, std::vector< SCH_ITEM * >, SHEET_PATH_CMP > NET_ITEMS_BY_SHEET
wxString result
Test unit parsing edge cases and error handling.