KiCad PCB EDA Suite
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test_ngspice_helpers.cpp
Go to the documentation of this file.
1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright (C) 2020 S.Kocjan <[email protected]>
5 * Copyright (C) 2020 KiCad Developers, see AUTHORS.TXT for contributors.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, you may find one here:
19 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
20 * or you may search the http://www.gnu.org website for the version 2 license,
21 * or you may write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
23 */
24
30#include <string.h>
32#include <vector>
33#include <wx/string.h>
34
35// Code under test
36#include <project.h>
37#include <schematic.h>
40
42{
43public:
45 m_manager( true ),
46 m_schematic( nullptr ),
48 {
51 }
52
54 {
56 }
57
59
61
63};
64
65
69BOOST_FIXTURE_TEST_SUITE( NgspiceCircuitModel, TEST_NGSPICE_HELPERS )
70
71
72
75BOOST_AUTO_TEST_CASE( CommandToSimType )
76{
77 struct TEST_DATA
78 {
79 wxString command;
80 SIM_TYPE type;
81 };
82
83 std::vector<struct TEST_DATA> testData = {
84 { ".op", ST_OP },
85 { ".option TEMP=27", ST_UNKNOWN },
86 { ".tran 0 1 0.1", ST_TRAN },
87 { ".tran 0 1 0.1 UIC", ST_TRAN },
88 { ".ac dec 10 1 10K", ST_AC },
89 { ".ac dec 10 1K 100MEG", ST_AC },
90 { ".ac lin 100 1 100HZ", ST_AC },
91 { ".dc VIN 0.25 5.0 0.25", ST_DC },
92 { ".dc VDS 0 10 .5 VGS 0 5 1", ST_DC },
93 { ".dc VCE 0 10 .25 IB 0 10u 1u", ST_DC },
94 { ".dc RLoad 1k 2k 100", ST_DC },
95 { ".dc TEMP -15 75 5", ST_DC },
96 { ".disto dec 10 1kHz 100MEG", ST_DISTO },
97 { ".disto dec 10 1kHz 100MEG 0.9", ST_DISTO },
98 { ".noise v(5) VIN dec 10 1kHz 100MEG", ST_NOISE },
99 { ".noise v(5,3) V1 oct 8 1.0 1.0e6 1", ST_NOISE },
100 { ".pz 1 0 3 0 cur pol", ST_PZ },
101 { ".pz 2 3 5 0 vol zer", ST_PZ },
102 { ".pz 4 1 4 1 cur pz", ST_PZ },
103 { ".SENS V(1,OUT)", ST_SENS },
104 { ".SENS V(OUT) AC DEC 10 100 100k", ST_SENS },
105 { ".SENS I(VTEST)", ST_SENS },
106 { ".tf v(5, 3) VIN", ST_TF },
107 { ".tf i(VLOAD) VIN", ST_TF },
108 };
109
110 for( auto& step : testData )
111 {
112 SIM_TYPE result = SPICE_CIRCUIT_MODEL::CommandToSimType( step.command );
113
114 BOOST_CHECK_EQUAL( result, step.type );
115 }
116
117 for( auto& step : testData )
118 {
119 step.command.Append( "\n" );
120 SIM_TYPE result = SPICE_CIRCUIT_MODEL::CommandToSimType( step.command );
121
122 BOOST_CHECK_EQUAL( result, step.type );
123 }
124}
125
126
130BOOST_AUTO_TEST_CASE( VectorToSignal )
131{
132 struct TEST_DATA
133 {
134 std::string vector;
135 wxString signal;
136 SIM_TRACE_TYPE type;
137 };
138
139 std::vector<struct TEST_DATA> testData = {
140 { "@c3[i]", "I(C3)", SPT_CURRENT },
141 { "@r12[i]", "I(R12)", SPT_CURRENT },
142 { "@r7[i]", "I(R7)", SPT_CURRENT },
143 { "@l2[i]", "I(L2)", SPT_CURRENT },
144 { "@c2[i]", "I(C2)", SPT_CURRENT },
145 { "@r6[i]", "I(R6)", SPT_CURRENT },
146 { "@r5[i]", "I(R5)", SPT_CURRENT },
147 { "@r10[i]", "I(R10)", SPT_CURRENT },
148 { "@q3[ie]", "Ie(Q3)", SPT_CURRENT },
149 { "@q3[ic]", "Ic(Q3)", SPT_CURRENT },
150 { "@q3[ib]", "Ib(Q3)", SPT_CURRENT },
151 { "@r11[i]", "I(R11)", SPT_CURRENT },
152 { "@r8[i]", "I(R8)", SPT_CURRENT },
153 { "@q1[ie]", "Ie(Q1)", SPT_CURRENT },
154 { "@q1[ic]", "Ic(Q1)", SPT_CURRENT },
155 { "@q1[ib]", "Ib(Q1)", SPT_CURRENT },
156 { "@r1[i]", "I(R1)", SPT_CURRENT },
157 { "@l1[i]", "I(L1)", SPT_CURRENT },
158 { "@c4[i]", "I(C4)", SPT_CURRENT },
159 { "@r2[i]", "I(R2)", SPT_CURRENT },
160 { "@q2[ig]", "Ig(Q2)", SPT_CURRENT },
161 { "@q2[id]", "Id(Q2)", SPT_CURRENT },
162 { "@q2[is]", "Is(Q2)", SPT_CURRENT },
163 { "@v2[i]", "I(V2)", SPT_CURRENT },
164 { "@r9[i]", "I(R9)", SPT_CURRENT },
165 { "@c1[i]", "I(C1)", SPT_CURRENT },
166 { "@v1[i]", "I(V1)", SPT_CURRENT },
167 { "@r3[i]", "I(R3)", SPT_CURRENT },
168 { "@r4[i]", "I(R4)", SPT_CURRENT },
169 { "vout", "V(vout)", SPT_VOLTAGE },
170 { "net-_q3-pad2_", "V(net-_q3-pad2_)", SPT_VOLTAGE },
171 { "net-_q2-pad3_", "V(net-_q2-pad3_)", SPT_VOLTAGE },
172 { "net-_q2-pad1_", "V(net-_q2-pad1_)", SPT_VOLTAGE },
173 { "net-_q1-pad3_", "V(net-_q1-pad3_)", SPT_VOLTAGE },
174 { "net-_l2-pad1_", "V(net-_l2-pad1_)", SPT_VOLTAGE },
175 { "net-_c4-pad2_", "V(net-_c4-pad2_)", SPT_VOLTAGE },
176 { "net-_c3-pad1_", "V(net-_c3-pad1_)", SPT_VOLTAGE },
177 { "net-_c1-pad2_", "V(net-_c1-pad2_)", SPT_VOLTAGE },
178 { "/vin", "V(/vin)", SPT_VOLTAGE },
179 { "/vbase", "V(/vbase)", SPT_VOLTAGE },
180 { "+12v", "V(+12v)", SPT_VOLTAGE },
181 { "@m1[cgs]", "", SPT_UNKNOWN },
182 { "@d1[g11]", "", SPT_UNKNOWN },
183 { "@d1[c12]", "", SPT_UNKNOWN },
184 { "@d1[y21]", "", SPT_UNKNOWN },
185 { "@n1[vth0]", "", SPT_UNKNOWN },
186 { "@mn1[gm]", "", SPT_UNKNOWN },
187 { "@m.xmos1.xmos2.m1[vdsat]", "", SPT_UNKNOWN }
188 };
189
190 for( auto& step : testData )
191 {
192 wxString outputSignalName;
193 SIM_TRACE_TYPE retVal;
194
195 retVal = m_exporter.VectorToSignal( step.vector, outputSignalName );
196
197 BOOST_CHECK_EQUAL( retVal, step.type );
198 BOOST_CHECK_EQUAL( outputSignalName.Cmp( step.signal ), 0 );
199 }
200}
201
202
203BOOST_AUTO_TEST_SUITE_END()
Holds all the data relating to one schematic.
Definition: schematic.h:75
void Reset()
Initialize this schematic to a blank one, unloading anything existing.
Definition: schematic.cpp:128
void SetProject(PROJECT *aPrj)
Definition: schematic.cpp:154
bool LoadProject(const wxString &aFullPath, bool aSetActive=true)
Loads a project or sets up a new project with a specified path.
PROJECT & Prj() const
A helper while we are not MDI-capable – return the one and only project.
Special netlist exporter flavor that allows one to override simulation commands.
static SIM_TYPE CommandToSimType(const wxString &aCmd)
Return simulation type basing on a simulation command directive.
SPICE_CIRCUIT_MODEL m_exporter
SIM_TRACE_TYPE
Definition: sim_types.h:50
@ SPT_UNKNOWN
Definition: sim_types.h:67
@ SPT_VOLTAGE
Definition: sim_types.h:52
@ SPT_CURRENT
Definition: sim_types.h:53
SIM_TYPE
< Possible simulation types
Definition: sim_types.h:32
@ ST_TRAN
Definition: sim_types.h:42
@ ST_UNKNOWN
Definition: sim_types.h:33
@ ST_NOISE
Definition: sim_types.h:37
@ ST_AC
Definition: sim_types.h:34
@ ST_DISTO
Definition: sim_types.h:36
@ ST_TF
Definition: sim_types.h:41
@ ST_SENS
Definition: sim_types.h:40
@ ST_DC
Definition: sim_types.h:35
@ ST_OP
Definition: sim_types.h:38
@ ST_PZ
Definition: sim_types.h:39
BOOST_AUTO_TEST_CASE(CommandToSimType)
Declare the test suite.