KiCad PCB EDA Suite
Loading...
Searching...
No Matches
pads_sch_schematic_builder.h
Go to the documentation of this file.
1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright (C) 2025 KiCad Developers, see AUTHORS.txt for contributors.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 3
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <https://www.gnu.org/licenses/>.
18 */
19
20#ifndef PADS_SCH_SCHEMATIC_BUILDER_H_
21#define PADS_SCH_SCHEMATIC_BUILDER_H_
22
24#include <sch_label.h>
25#include <map>
26#include <set>
27#include <vector>
28#include <memory>
29#include <wx/string.h>
30
31class SCH_SCREEN;
32class SCH_SHEET;
33class SCH_SHEET_PATH;
34class SCH_SHEET_PIN;
35class SCH_HIERLABEL;
36class SCH_GLOBALLABEL;
37class SCH_LINE;
38class SCH_JUNCTION;
39class SCH_LABEL;
41class SCH_SYMBOL;
42class SCHEMATIC;
43
44namespace PADS_SCH
45{
46
54{
55public:
56 PADS_SCH_SCHEMATIC_BUILDER( const PARAMETERS& aParams, SCHEMATIC* aSchematic );
58
66 int CreateWires( const std::vector<SCH_SIGNAL>& aSignals, SCH_SCREEN* aScreen );
67
74 SCH_LINE* CreateWire( const WIRE_SEGMENT& aWire );
75
83 int CreateJunctions( const std::vector<SCH_SIGNAL>& aSignals, SCH_SCREEN* aScreen );
84
98 int CreateNetLabels( const std::vector<SCH_SIGNAL>& aSignals, SCH_SCREEN* aScreen,
99 const std::set<std::string>& aSignalOpcIds,
100 const std::set<std::string>& aSkipSignals = {},
101 const std::map<std::string, NETNAME_LABEL>& aNetNameLabels = {} );
102
111 static SPIN_STYLE SpinFromNetNameLabel( const NETNAME_LABEL& aLabel );
112
124 SCH_GLOBALLABEL* CreateNetLabel( const SCH_SIGNAL& aSignal, const VECTOR2I& aPosition,
125 SPIN_STYLE aOrientation = SPIN_STYLE::RIGHT );
126
134 int CreateBusWires( const std::vector<SCH_SIGNAL>& aSignals, SCH_SCREEN* aScreen );
135
142 SCH_LINE* CreateBusWire( const WIRE_SEGMENT& aWire );
143
150 static bool IsBusSignal( const std::string& aName );
151
161 void ApplyPartAttributes( SCH_SYMBOL* aSymbol, const PART_PLACEMENT& aPlacement );
162
169 void ApplyFieldSettings( SCH_SYMBOL* aSymbol, const PART_PLACEMENT& aPlacement );
170
182 int CreateCustomFields( SCH_SYMBOL* aSymbol, const PART_PLACEMENT& aPlacement );
183
193 void CreateTitleBlock( SCH_SCREEN* aScreen );
194
208 SCH_SHEET* CreateHierarchicalSheet( int aSheetNumber, int aTotalSheets,
209 SCH_SHEET* aParentSheet,
210 const wxString& aBaseFilename );
211
218
228 VECTOR2I CalculateSheetPosition( int aSheetIndex, int aTotalSheets ) const;
229
240 SCH_SHEET_PIN* CreateSheetPin( SCH_SHEET* aSheet, const std::string& aSignalName,
241 int aPinIndex );
242
253 SCH_HIERLABEL* CreateHierLabel( const std::string& aSignalName, const VECTOR2I& aPosition,
254 SCH_SCREEN* aScreen );
255
266 static bool IsGlobalSignal( const std::string& aSignalName,
267 const std::set<int>& aSheetNumbers );
268
269private:
273 int toKiCadUnits( double aPadsValue ) const;
274
278 int toKiCadY( double aPadsY ) const;
279
283 std::vector<VECTOR2I> findJunctionPoints( const std::vector<SCH_SIGNAL>& aSignals );
284
288 VECTOR2I chooseLabelPosition( const SCH_SIGNAL& aSignal );
289
295 const VECTOR2I& aAdjacentPos );
296
301 wxString convertNetName( const std::string& aName ) const;
302
306};
307
308} // namespace PADS_SCH
309
310#endif // PADS_SCH_SCHEMATIC_BUILDER_H_
SCH_LINE * CreateWire(const WIRE_SEGMENT &aWire)
Create a single wire segment.
std::vector< VECTOR2I > findJunctionPoints(const std::vector< SCH_SIGNAL > &aSignals)
Find junction points where 3+ wire segments meet.
static SPIN_STYLE SpinFromNetNameLabel(const NETNAME_LABEL &aLabel)
Map a PADS NETNAMES label entry to a KiCad global-label spin style.
int toKiCadY(double aPadsY) const
Convert PADS Y coordinate to KiCad Y, accounting for Y-axis inversion and page offset.
SCH_SHEET_PIN * CreateSheetPin(SCH_SHEET *aSheet, const std::string &aSignalName, int aPinIndex)
Create hierarchical sheet pin on a sheet symbol.
int CreateJunctions(const std::vector< SCH_SIGNAL > &aSignals, SCH_SCREEN *aScreen)
Create junctions at wire intersection points.
void ApplyPartAttributes(SCH_SYMBOL *aSymbol, const PART_PLACEMENT &aPlacement)
Apply part attributes to a symbol instance.
PADS_SCH_SCHEMATIC_BUILDER(const PARAMETERS &aParams, SCHEMATIC *aSchematic)
void CreateTitleBlock(SCH_SCREEN *aScreen)
Create title block from parsed PADS parameters.
VECTOR2I CalculateSheetPosition(int aSheetIndex, int aTotalSheets) const
Calculate position for a sheet symbol on the parent sheet.
SPIN_STYLE computeLabelOrientation(const VECTOR2I &aLabelPos, const VECTOR2I &aAdjacentPos)
Compute label orientation from the wire direction at the label position.
int toKiCadUnits(double aPadsValue) const
Convert PADS coordinate to KiCad internal units.
int CreateCustomFields(SCH_SYMBOL *aSymbol, const PART_PLACEMENT &aPlacement)
Create custom fields from non-standard PADS attributes.
VECTOR2I chooseLabelPosition(const SCH_SIGNAL &aSignal)
Choose best position for net label on a signal's wires.
SCH_LINE * CreateBusWire(const WIRE_SEGMENT &aWire)
Create a single bus wire segment.
SCH_HIERLABEL * CreateHierLabel(const std::string &aSignalName, const VECTOR2I &aPosition, SCH_SCREEN *aScreen)
Create hierarchical label in a sub-schematic.
void ApplyFieldSettings(SCH_SYMBOL *aSymbol, const PART_PLACEMENT &aPlacement)
Apply field visibility and position from PADS attribute settings.
int CreateWires(const std::vector< SCH_SIGNAL > &aSignals, SCH_SCREEN *aScreen)
Create wire segments from signal definitions and add to screen.
SCH_GLOBALLABEL * CreateNetLabel(const SCH_SIGNAL &aSignal, const VECTOR2I &aPosition, SPIN_STYLE aOrientation=SPIN_STYLE::RIGHT)
Create a global net label for a signal.
static bool IsGlobalSignal(const std::string &aSignalName, const std::set< int > &aSheetNumbers)
Check if a signal name represents a global signal.
int CreateBusWires(const std::vector< SCH_SIGNAL > &aSignals, SCH_SCREEN *aScreen)
Create bus wires and entries for bus signals.
wxString convertNetName(const std::string &aName) const
Convert a PADS net name for use as a KiCad label.
SCH_SHEET * CreateHierarchicalSheet(int aSheetNumber, int aTotalSheets, SCH_SHEET *aParentSheet, const wxString &aBaseFilename)
Create hierarchical sheet for a sub-schematic page.
VECTOR2I GetDefaultSheetSize() const
Get standard sheet size for a given sheet number.
int CreateNetLabels(const std::vector< SCH_SIGNAL > &aSignals, SCH_SCREEN *aScreen, const std::set< std::string > &aSignalOpcIds, const std::set< std::string > &aSkipSignals={}, const std::map< std::string, NETNAME_LABEL > &aNetNameLabels={})
Create net labels for named signals.
static bool IsBusSignal(const std::string &aName)
Check if a signal name indicates a bus.
Holds all the data relating to one schematic.
Definition schematic.h:90
Class for a wire to bus entry.
Segment description base class to describe items which have 2 end points (track, wire,...
Definition sch_line.h:38
Handle access to a stack of flattened SCH_SHEET objects by way of a path for creating a flattened sch...
Define a sheet pin (label) used in sheets to create hierarchical schematics.
Sheet symbol placed in a schematic, and is the entry point for a sub schematic.
Definition sch_sheet.h:44
Schematic symbol object.
Definition sch_symbol.h:69
Net name label from NETNAMES section.
General schematic parameters from SCH and FIELDS sections.
Part instance from PART section.
Signal (net) definition from CONNECTION and SIGNAL sections.
Wire segment connecting two endpoints through coordinate vertices.
VECTOR2< int32_t > VECTOR2I
Definition vector2d.h:683