KiCad PCB EDA Suite
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drc_test_provider_via_stitch.cpp
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1/*
2 * This program source code file is part of KiCad, a free EDA CAD application.
3 *
4 * Copyright The KiCad Developers.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, you may find one here:
18 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
19 */
20
21#include <board.h>
22#include <drc/drc_engine.h>
23#include <drc/drc_item.h>
27
28/*
29 Same-net via-stitch zone overlap test.
30
31 Generated errors:
32 - DRCE_VIA_STITCH_OVERLAP
33*/
34
36{
37public:
39
40 virtual ~DRC_TEST_PROVIDER_VIA_STITCH() = default;
41
42 virtual bool Run() override;
43
44 virtual const wxString GetName() const override { return wxT( "via_stitch_overlap" ); }
45};
46
47
49{
50 if( m_drcEngine->IsErrorLimitExceeded( DRCE_VIA_STITCH_OVERLAP ) )
51 {
52 REPORT_AUX( wxT( "Via-stitch overlap tests not run." ) );
53 return true; // continue with other tests
54 }
55
56 if( !reportPhase( _( "Checking via-stitch zone overlaps..." ) ) )
57 return false; // DRC cancelled
58
59 // Collect the stitch generators present on the board.
60 std::vector<PCB_VIA_STITCH*> stitches;
61
62 for( PCB_GENERATOR* gen : m_drcEngine->GetBoard()->Generators() )
63 {
64 if( PCB_VIA_STITCH* stitch = dynamic_cast<PCB_VIA_STITCH*>( gen ) )
65 stitches.push_back( stitch );
66 }
67
68 for( size_t i = 0; i < stitches.size(); ++i )
69 {
70 if( m_drcEngine->IsErrorLimitExceeded( DRCE_VIA_STITCH_OVERLAP ) )
71 break;
72
73 PCB_VIA_STITCH* a = stitches[i];
74
75 if( a->GetNetCode() == 0 )
76 continue;
77
78 for( size_t j = i + 1; j < stitches.size(); ++j )
79 {
80 PCB_VIA_STITCH* b = stitches[j];
81
82 if( b->GetNetCode() != a->GetNetCode() )
83 continue;
84
85 SHAPE_POLY_SET intersection = a->Outline();
86 intersection.BooleanIntersection( b->Outline() );
87
88 if( intersection.OutlineCount() == 0 )
89 continue;
90
91 std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_VIA_STITCH_OVERLAP );
92 drcItem->SetItems( a, b );
93
94 // Report at the center of intersection
95 VECTOR2I pos = intersection.BBox().Centre();
96 reportViolation( drcItem, pos, a->GetLayer() );
97 }
98 }
99
100 return !m_drcEngine->IsCancelled();
101}
102
103
104namespace detail
105{
107}
constexpr Vec Centre() const
Definition box2.h:94
static std::shared_ptr< DRC_ITEM > Create(int aErrorCode)
Constructs a DRC_ITEM for the given error code.
Definition drc_item.cpp:444
virtual bool Run() override
Run this provider against the given PCB with configured options (if any).
virtual const wxString GetName() const override
virtual ~DRC_TEST_PROVIDER_VIA_STITCH()=default
virtual bool reportPhase(const wxString &aStageName)
void reportViolation(std::shared_ptr< DRC_ITEM > &item, const VECTOR2I &aMarkerPos, int aMarkerLayer, const std::function< void(PCB_MARKER *)> &aPathGenerator=[](PCB_MARKER *){})
const SHAPE_POLY_SET & Outline() const
PCB_LAYER_ID GetLayer() const override
Return the primary layer this item is on.
int GetNetCode() const
Represent a set of closed polygons.
void BooleanIntersection(const SHAPE_POLY_SET &b)
Perform boolean polyset intersection.
int OutlineCount() const
Return the number of outlines in the set.
const BOX2I BBox(int aClearance=0) const override
Compute a bounding box of the shape, with a margin of aClearance a collision.
@ DRCE_VIA_STITCH_OVERLAP
Definition drc_item.h:128
#define REPORT_AUX(s)
#define _(s)
static DRC_REGISTER_TEST_PROVIDER< DRC_TEST_PROVIDER_ANNULAR_WIDTH > dummy
VECTOR2< int32_t > VECTOR2I
Definition vector2d.h:683