KiCad PCB EDA Suite
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common/transline_calculations/stripline.h
Go to the documentation of this file.
1/*
2 * Copyright (C) 2001 Gopal Narayanan <[email protected]>
3 * Copyright (C) 2002 Claudio Girardi <[email protected]>
4 * Copyright (C) 2005, 2006 Stefan Jahn <[email protected]>
5 * Modified for Kicad: 2018 Jean-Pierre Charras <jp.charras at wanadoo.fr>
6 * Copyright The KiCad Developers, see AUTHORS.txt for contributors.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this package; see the file COPYING. If not, write to
20 * the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor,
21 * Boston, MA 02110-1301, USA.
22 */
23
24#ifndef TRANSLINE_CALCULATIONS_STRIPLINE_H
25#define TRANSLINE_CALCULATIONS_STRIPLINE_H
26
27
29
30
32{
34
35public:
37 TRANSLINE_CALCULATION_BASE( { TCP::SKIN_DEPTH, TCP::EPSILON_EFF, TCP::EPSILONR, TCP::T, TCP::STRIPLINE_A,
38 TCP::H, TCP::Z0, TCP::LOSS_CONDUCTOR, TCP::PHYS_LEN, TCP::LOSS_DIELECTRIC,
39 TCP::FREQUENCY, TCP::TAND, TCP::PHYS_WIDTH, TCP::UNIT_PROP_DELAY, TCP::ANG_L,
40 TCP::SIGMA, TCP::MURC } ),
41 unit_prop_delay( 0.0 )
42 {
43 }
44
46 void Analyse() override;
47
49 bool Synthesize( SYNTHESIZE_OPTS aOpts ) override;
50
51private:
53 void SetAnalysisResults() override;
54
56 void SetSynthesisResults() override;
57
59 double lineImpedance( double aHeight, double& aAc ) const;
60
62};
63
64
65#endif //TRANSLINE_CALCULATIONS_STRIPLINE_H
bool Synthesize(SYNTHESIZE_OPTS aOpts) override
Synthesis track geometry parameters to match given Z0.
void SetAnalysisResults() override
Sets the output values and status following analysis.
void SetSynthesisResults() override
Sets the output values and status following synthesis.
double lineImpedance(double aHeight, double &aAc) const
Calculate characteristic impedance and conductor loss (in db/meter)
void Analyse() override
Analyse track geometry parameters to output Z0 and Ang_L.
The base class for all transmission line calculations.
SYNTHESIZE_OPTS
Options for specifying synthesis inputs, targets, or strategies.
TRANSLINE_PARAMETERS
All possible parameters used (as inputs or outputs) by the transmission line calculations.