| __init__(self, *args) | pcbnew.BOARD_DESIGN_SETTINGS | |
| CloneFrom(self, "BOARD_DESIGN_SETTINGS" aOther) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetAuxOrigin(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetBiggestClearanceValue(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetBoardThickness(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetCopperLayerCount(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetCurrentDiffPairGap(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetCurrentDiffPairViaGap(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetCurrentDiffPairWidth(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetCurrentMicroViaDrill(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetCurrentMicroViaSize(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetCurrentNetClassName(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetCurrentTrackWidth(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetCurrentViaDrill(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetCurrentViaSize(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetCustomDiffPairGap(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetCustomDiffPairViaGap(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetCustomDiffPairWidth(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetCustomTrackWidth(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetCustomViaDrill(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetCustomViaSize(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetDefault(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetDefaultZoneSettings(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetDiffPairIndex(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetDRCEpsilon(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetEnabledLayers(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetGridOrigin(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetHolePlatingThickness(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetLayerClass(self, "PCB_LAYER_ID" aLayer) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetLineThickness(self, "PCB_LAYER_ID" aLayer) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetNetClasses(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetSeverity(self, "int" aDRCErrorCode) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetSmallestClearanceValue(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetStackupDescriptor(self, *args) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetTextItalic(self, "PCB_LAYER_ID" aLayer) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetTextSize(self, "PCB_LAYER_ID" aLayer) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetTextThickness(self, "PCB_LAYER_ID" aLayer) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetTextUpright(self, "PCB_LAYER_ID" aLayer) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetTrackWidthIndex(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| GetViaSizeIndex(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| Ignore(self, "int" aDRCErrorCode) | pcbnew.BOARD_DESIGN_SETTINGS | |
| IsLayerEnabled(self, "PCB_LAYER_ID" aLayerId) | pcbnew.BOARD_DESIGN_SETTINGS | |
| LoadFromFile(self, *args) | pcbnew.BOARD_DESIGN_SETTINGS | |
| m_BlindBuriedViaAllowed | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_CopperEdgeClearance | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_CurrentViaType | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_DefaultFPTextItems | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_DiffPairDimensionsList | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_DimensionArrowLength | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_DimensionExtensionOffset | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_DimensionKeepTextAligned | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_DimensionPrecision | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_DimensionSuppressZeroes | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_DimensionTextPosition | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_DimensionUnitsFormat | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_DimensionUnitsMode | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_DrcExclusions | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_DRCSeverities | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_HasStackup | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_HoleClearance | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_HoleToHoleMin | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_LineThickness | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_MaxError | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_MicroViasAllowed | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_MicroViasMinDrill | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_MicroViasMinSize | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_MinClearance | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_MinThroughDrill | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_SilkClearance | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_SolderMaskMargin | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_SolderMaskMinWidth | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_SolderPasteMargin | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_SolderPasteMarginRatio | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_TempOverrideTrackWidth | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_TextItalic | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_TextSize | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_TextThickness | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_TextUpright | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_TrackMinWidth | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_TrackWidthList | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_UseConnectedTrackWidth | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_UseHeightForLengthCalcs | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_ViasDimensionsList | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_ViasMinAnnularWidth | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_ViasMinSize | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_ZoneFillVersion | pcbnew.BOARD_DESIGN_SETTINGS | static |
| m_ZoneKeepExternalFillets | pcbnew.BOARD_DESIGN_SETTINGS | static |
| SetAuxOrigin(self, "wxPoint" aOrigin) | pcbnew.BOARD_DESIGN_SETTINGS | |
| SetBoardThickness(self, "int" aThickness) | pcbnew.BOARD_DESIGN_SETTINGS | |
| SetCopperEdgeClearance(self, "int" aDistance) | pcbnew.BOARD_DESIGN_SETTINGS | |
| SetCopperLayerCount(self, "int" aNewLayerCount) | pcbnew.BOARD_DESIGN_SETTINGS | |
| SetCustomDiffPairGap(self, "int" aGap) | pcbnew.BOARD_DESIGN_SETTINGS | |
| SetCustomDiffPairViaGap(self, "int" aGap) | pcbnew.BOARD_DESIGN_SETTINGS | |
| SetCustomDiffPairWidth(self, "int" aWidth) | pcbnew.BOARD_DESIGN_SETTINGS | |
| SetCustomTrackWidth(self, "int" aWidth) | pcbnew.BOARD_DESIGN_SETTINGS | |
| SetCustomViaDrill(self, "int" aDrill) | pcbnew.BOARD_DESIGN_SETTINGS | |
| SetCustomViaSize(self, "int" aSize) | pcbnew.BOARD_DESIGN_SETTINGS | |
| SetDefaultZoneSettings(self, "ZONE_SETTINGS" aSettings) | pcbnew.BOARD_DESIGN_SETTINGS | |
| SetDiffPairIndex(self, "unsigned int" aIndex) | pcbnew.BOARD_DESIGN_SETTINGS | |
| SetEnabledLayers(self, "LSET" aMask) | pcbnew.BOARD_DESIGN_SETTINGS | |
| SetGridOrigin(self, "wxPoint" aOrigin) | pcbnew.BOARD_DESIGN_SETTINGS | |
| SetMinHoleSeparation(self, "int" aDistance) | pcbnew.BOARD_DESIGN_SETTINGS | |
| SetNetClasses(self, "NETCLASSES" aNetClasses) | pcbnew.BOARD_DESIGN_SETTINGS | |
| SetSilkClearance(self, "int" aDistance) | pcbnew.BOARD_DESIGN_SETTINGS | |
| SetTrackWidthIndex(self, "unsigned int" aIndex) | pcbnew.BOARD_DESIGN_SETTINGS | |
| SetViaSizeIndex(self, "unsigned int" aIndex) | pcbnew.BOARD_DESIGN_SETTINGS | |
| thisown | pcbnew.BOARD_DESIGN_SETTINGS | static |
| UseCustomDiffPairDimensions(self, *args) | pcbnew.BOARD_DESIGN_SETTINGS | |
| UseCustomTrackViaSize(self, *args) | pcbnew.BOARD_DESIGN_SETTINGS | |
| UseNetClassDiffPair(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| UseNetClassTrack(self) | pcbnew.BOARD_DESIGN_SETTINGS | |
| UseNetClassVia(self) | pcbnew.BOARD_DESIGN_SETTINGS | |